PRELIMINARY
3.3V 1K/4K/16K x36 Unidirectional
Synchronous FIFO w/ Bus Matching
CY7C43643AV
CY7C43663AV
CY7C43683AV
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-06024 Rev. ** Revised March 30, 2001
3663AV
Features
• High-speed, low-power, unidirectional, First-In First-
Out (FIFO) memories w/ bus matching capabilities
• 1K x 36 (CY7C43643AV)
• 4K x 36 (CY7C43663AV)
• 16K x 36 ( CY7C43683AV)
• 0.25-micron CMOS for optimum speed/power
• High-speed 133-MHz operation (7.5-ns read/write cycle
times)
• Low power
—ICC = 60 mA
—ISB = 10 mA
• Fully asynchronous and simultaneous read and write
operation permitted
• Mailbox bypass register for each FIFO
• Parallel and Serial Programmable Almost Full and
Almost Empty flags
• Retransmit function
• Standard or FWFT user selectable mode
• Partial Rese t
• Big or Little Endian format for word or byte bus sizes
• 128-Pin TQFP packaging
• Easily expandable in width and depth
Logic Block Diagram
Port A
Control
Logic Port B
Control
Logic
Mail1
Register
Input
Register
Output
Register
Write
Pointer Read
Pointer
Status
Flag Logic
Programmable
Flag Offset Timing
Mode
1K/4K/16K
x36
Dual Ported
Memory
Mail2
Register
FIFO,
Mail1
CLKA
CSA
W/RA
ENA
MBA
RT
MRS1
PRS
FF/IR
AF
SPM
FS0/SD
FS1/SEN
A0–35
MBF2
BE/FWFT
B0–35
CLKB
CSB
W/RB
ENB
MBB
BE
BM
SIZE
EF/OR
AE
MBF1
Mail2
Reset
Logic
Bus Matching
36
36
MRS2
Registers
CY7C43643AV
CY7C43663AV
CY7C43683AV
PRELIMINARY
Document #: 38-06024 Rev. ** Page 2 of 29
Pin Configurati o n[1]
Note:
1. Pin-compatible to IDT723623/33/43 family.
CY7C43643AV
CY7C43663AV
CY7C43683AV
TQFP
Top View
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
FS0/SD
MRS2
FS1/SEN
GND
NC
MRS1
MBA
MBF2
NC
AF
V
CC
PRS
FF/IR
CSA
ENB
W/RB
CSB
GND
NC
EF/OR
NC
AE
V
CC
MBF1
MBB
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
B30
B26
B27
B28
B29
B31
NC
GND
B32
B33
B34
B35
VCC
NC
CLKB
GND
SIZE
B16
B17
B18
B19
B20
B21
B22
B23
GND
BM
B24
B25
RT
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
A
2
B
0
GND
A
0
A
1
V
CC
SPM
A
3
A
4
A
5
GND
A
6
A
7
A
8
A
9
B
9
B
8
B
7
V
CC
B
6
GND
B
5
B
4
B
3
B
2
B
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
VCC
A29
GND
A30
A31
A32
A34
A35
GND
CLKA
ENA
W/RA
A12
A20
GND
A18
A19
A21
VCC
A22
GND
FWFT/STAN
A23
A24
A25
A26
A27
A28
A33
72
71
70
69
68
67
66
65
B12
B10
B11
GND
B13
B14
B15
VCC
30
31
32
33
34
35
36
37
38
NC
A10
A11
GND
A13
A14
A15
A16
A17
NC
CY7C43643AV
CY7C43663AV
CY7C43683AV
PRELIMINARY
Document #: 38-06024 Rev. ** Page 3 of 29
Functional Description
The CY7C436X3AV is a monolithic, high-speed, low-power,
CMOS Unidirectional Synchronous FIFO memory which sup-
ports clock frequencies up to 133 MHz and has read access
times as fast as 6 ns.
The CY7C436X3AV is a synchronous (clocked) FIFO, mean-
ing eac h port emp loys a sy nchronous interface . All data trans-
fers thro ugh a port a re gated to the LOW -to-HIGH tr ansition of
a port clock by enable signals. The clocks for each port are
independent of one another and can be asynchronous or co-
incident. The enables for each port are arranged to provide a
simple unidirectional interface between microprocessors and/
or buses with synchronous control.
Comm unicatio n betwee n each port may bypa ss the FIF Os via
two mailbox registers. The mailbox registers’ width matches
the selected Port B bus width. Each mailbox register has a fla g
(MBF1 and MBF2) to signal when new mail has been stored.
T wo kinds of reset are available on the CY7C436X3A V : Master
Reset and Pa rtial R eset . Mas ter Rese t initi alize s the read and
write pointers to the first location of the memory array, config-
ures the FIFO for Big or Little Endian byte arrangement, and
select s s eri al fl ag programming, para ll el flag program mi ng , or
one of the three possible default flag offset settings, 8, 16, or
64. The FIFO also has two Master Reset pins, MRS1 and
MRS2.
Partial Reset also sets the read and write pointers to the first
locatio n o f th e m em ory. Unli ke Master Res et, any setti ngs e x-
isting prior to Partial Reset (i.e., programming method and par-
tial flag default offsets) are retained. Partial Reset is useful
since it permits fl ushing of the FIFO mem ory withou t changin g
any con fig uration settin gs. The FIF O has its own i ndepe ndent
Partial Reset pin, PRS.
The CY7C436X3AV have two modes of operation: In the CY
Standard M ode , the first word w ritt en to an em pty FIFO is de-
posited in to th e m em ory array. A read operation is re qui red to
access that word (along with all other words residing in
memory). In the First-Word Fall-Through Mode (FWFT), the
first long -word (36-bi t wide ) written to a n empty FIFO appear s
automat ically o n the outpu ts, no read operation re quired (nev -
ertheless, accessing subsequent words does necessitate a
formal read request). The state of the FWFT/STAN pin during
FIFO operation determines the mode in use.
The FIFO has a combined Empty/Output Ready flag (EF/OR)
and a combined Full/Input Ready flag (FF/IR). The EF and FF
function s are selec ted in the C Y Stand ard M ode. EF ind icates
whether the memory is empty or not. FF indicates whether the
memory is full. The IR and OR functions are selected in the
First- Word Fall-Thro ugh Mode. IR indicates whether or no t the
FIFO has av ailabl e memo ry locati ons. O R shows whether the
FIFO has data available for reading or not. It marks the pres-
ence of valid data on the outputs.
The FIFO has a programmable Almost Empty flag (AE) and a
programmable Almost Full flag (AF). AE indicates when a se-
lected number of words written to FIFO memory achieve a
predetermined “almost empty state.” AF indicates when a se-
lected number of words written to the memory achieve a pre-
determined “almost full state.”[2]
FF/IR and AF are synchronized to the port clock that writes
data i nto i ts array. EF/OR and AE are synchr onized to th e port
clock that reads data from its array. Programmable offset for
AE and AF are loaded in parallel using Port A or in serial via
the SD input. Three default offset settings are also provided.
The AE threshold can be se t at 8, 16 , or 64 lo ca tion s from th e
empty boundary and AF threshold can be set at 8, 16, or 64
locations from the full boundary. All these choices are made
using the FS0 and FS1 inputs during Master Reset.
Two or more devices may be used in parallel to create wider
data paths.
The CY7C436X3AV are characterized for operation from 0°C
to 70°C commercial and from –40°C to 85°C industrial. Input
ESD protec tion is greater than 2001 V , and latch-up is pre vent-
ed by the use of guard rings.
Selection Guide
CY7C43643/63/83AV
-7 CY7C43643/63/83AV
-10 CY7C43643/63/83AV
-15
Maximu m Frequency (MHz ) 133 100 66.7
Maximum Access Time (ns) 6 8 10
Minimum Cycle Time (ns) 7.5 10 15
Minimum Data or Enable Set-Up (ns) 3 4 5
Minimum Data or Enable Hold (ns) 0 0 0
Maximum Flag Delay (ns) 6 8 10
Active Power Supply
Current (ICC1) (mA) Commercial 60 60 60
Industrial 60
CY7C43643AV CY7C43663AV CY7C43683AV
Density 1K x 36 4K x 36 16K x 36
Package 128 TQFP 128 TQFP 128 TQFP
Note:
2. When FIFO is operated at the almost empty/full boundary, there may be an uncertainty of up to 2 clock cycles for flag deassertion, but the flag will always be
asserted exactly when the FIFO content reaches the programmed value. Use the assertion edge for trigger if flag accuracy is required. Refer to “Designing
with CY7C436xx Synchronous FIFOs” application note for more details on flag uncertainties.
CY7C43643AV
CY7C43663AV
CY7C43683AV
PRELIMINARY
Document #: 38-06024 Rev. ** Page 4 of 29
Pin Definitions
Signal Name Description I/O Function
A0–35 Port A Data I 36-bit unidirectional data port for side A.
AE Almost Empty
Flag (Por t B) O Program mable Almost Empty flag sy nchroniz ed to CLKB. It is LO W when the num ber
of words in the FIFO is less than or equal to the value in the Almost Empty offset
register, X.[2]
AF Almost Fu ll Flag O Prog ramma ble Almos t Full fl ag sy nchron ized to CLKA. It is LOW whe n the num ber of
empty lo ca tio ns i n th e FIFO is les s than or e qua l to the va lue in the Alm os t Ful l o f fs et
register, Y.[2]
B0–35 Port B Data O 36-bit unidirectional data port for side B.
BE/FWFT Big Endian/
First-Word Fall-
Through Select
I This is a dual-pu rpose pin. Du ring Master R ese t, a HI GH on BE will selec t Big En dian
operation. In this case, depending on the bus size, th e most signific ant byte or word on
Port A is transfe rred to Port B first. A LOW on BE will select Little Endian operation. In
this ca se, the least signi ficant b yte or word o n Port A is transferre d to Port B first. Aft er
Master Reset, this pin selects the timing mode. A HIGH on FWF T sele cts CY Standard
Mode, a LO W selects Fi rst-Wo rd Fall-Through M ode. Once the ti ming mode ha s been
selected, the level on FWFT must be static throughout device operation.
BM Bus Match
Select (Port B) I A HIGH on this pin ena bles either byte or word bus wid th on Port B, dependin g on the
state of SIZE. A LOW selects long-word operation. BM works with SIZE and BE to
select the bus size and end ian arrangem ent for Port B. The lev el of BM must b e static
throughout device operation.
CLKA Port A Clock I CLKA is a continuous clock that synchronizes all data transfers through Port A and can
be asynchronous or coincident to CLKB. FF/IR and AF are all synchronized to the LOW-
to-HIGH transition of CLKA.
CLKB Port B Clock I CLKB is a continuous clock that synchronizes all data transfers through Port B and can
be asynchronous or coincident to CLKA. EF/OR and AE are synchronized to the LOW-
to-HIGH transition of CLKB.
CSA Port A Chip
Select ICSA must be LOW to enable a LOW-to HIGH transition of CLKA to read (from Mail2
register) or write on Port A. The A0–35 outputs are in the high-impedance state when
CSA is HIGH.
CSB Port B Chip
Select ICSB must be LO W to enab le a LOW -t o HIGH t ransiti on of CLKB to re ad or wri te (into
Mail2 register) on Port B. The B0–35 outputs are in the high-impedance state when CSB
is HIGH.
EF/OR Empty/Output
Ready Flag
(Port B)
O This is a dual-function pin. In the CY Standard Mode, the EF function is selected. EF
indicates whether or not the FIFO memory is empty . In the FWF T mode, the OR function
is selected. OR indicates the presence of valid data on B0–35 outputs, available for
reading. EF/OR is synchronized to the LOW-to-HIGH transition of CLKB.
ENA Port A Enable I ENA must be HIG H to e nab le a LO W -to-HIGH tran si tio n of CL KA to re ad (from Mail2
register ) or write data on Port A.
ENB Port B Enable I ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write (to
Mail2 register) data on Port B.
FF/IR Port B Full/Input
Ready Flag O This is a dual-function pin. In the CY Standard Mode, the FF function is selected. FF
indicates whether or not the FIFO memory is full. In the FWFT mode, the IR function
is selec ted. IR indic ates whether o r not there is s pace availab le for writi ng to the FIFO
memory. FF/IR is synchronized to the LOW-to-HIGH transition of CLKA.
FS1/SEN Flag Offset
Select 1/Serial
Enable
I FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register program-
ming. D uring Master Reset, FS1/SEN and FS0/SD, t ogether w ith SPM, selec t the flag
offset programming method. Three offset register programming methods are available:
automati ca lly loa d one of thre e pre se t val ues (8, 16 , or 64 ), para lle l lo ad fro m Por t A,
and ser ial load. When se rial load is s elected for fl ag offs et register pro gramming, FS1/
SEN is used as an enable synchronous to the LOW-to-HIGH transition of CLKA. When
FS1/SEN is LOW, a rising edge on CLKA loads the bit present on FS0/SD into the X
and Y r egisters. The numb er of bit wr ites require d to pr ogram the of fse t registers i s 20
for the CY7C43643AV, 24 for the CY7C43663AV, and 28 for the CY7C43683AV. The
first bit writ e stores the Y-register MSB and the last bit write stor es the X-reg ister LSB.
FS0/ SD Flag Offset
Select 0/Serial
Data
I
CY7C43643AV
CY7C43663AV
CY7C43683AV
PRELIMINARY
Document #: 38-06024 Rev. ** Page 5 of 29
MBA Port A Mailbox
Select I A HIGH leve l on M BA cho os es a mailbo x register for a Port A read or wri te op erat ion
When a write ope ration is performed on Port A, a HIGH on MBA will wri te the data into
Mail1 register, a low on MBA will write the data into the FIFO memory.
MBB Port B Mailbox
Select I A HIGH level o n MBB ch ooses a m ailbox register fo r a Port B read o r write operati on.
When a read operation is performed on Port B, a HIGH le vel on MBB selects data from
the Mail1 register for output and a LOW level selects FIFO output register data for
output. Data can only be written into Mail2 register through Port B (MBB HIGH) and
not into the FIFO memory.
MBF1 Mail1 Register
Flag OMBF1 is set LOW by a LOW -to-HIGH trans iti on of CLKA that writ es da ta to the Ma il1
register. Writes to the Mail1 register are inhibited while MBF1 is LOW. MBF1 is set
HIGH by a LOW -to -HIGH transi tion o f CL KB when a Port B read is s elect ed and MBB
is HIGH. MBF1 is set HIGH following either a Master or Partial Reset.
MBF2 Mail2 Register
Flag OMBF2 is set LOW by a LOW -to-HIGH trans iti on of CLKB that writ es da ta to the Ma il2
register. Writes to the Mail2 register are inhibited while MBF2 is LOW. MBF2 is set
HIGH by a LOW -to -HIGH transi tion o f CL KA when a Port A read is s elect ed and MBA
is HIGH. MBF2 is set HIGH following either a Master or Partial Reset.
MRS1 Master Reset I A LOW on this pin initializes the FIFO read and write pointers to the first location of
memory and sets the Port B output register to all zeroes. A LOW pulse on MRS1 selects
the programming method (serial or parallel) and one of three programmable flag default
offsets. It also configures Port B for bus size and endian arrangement. Four LOW-to-
HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while
MRS1 is LOW.
MRS2 Master Reset I A LOW on this pin initializes the Mail2 Register.
PRS Partial Reset I A LOW on this pin initializes the FIFO read and write pointers to the first location of
memory and sets the Port B output register to all zeroes. During Partial Reset, the
currently selected bus size, endian arrangement, programming method (serial or par-
allel), and programmable flag settings are all retained.
RT Retransmit I A LOW strobe on this pin will retransmit the data in the FIFO. This is achieved by
bringing the re ad po inter back to l ocatio n ze ro. The user wil l sti ll ne ed to prefor m read
operations to retransmit the data. Retransmit function applies to CY standard mode
only.
SIZE Bus Size Select I A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW
on this pin when BM is HIGH selects word (18-bit) bus size. SIZE works with BM and
BE to select the bus size and endian arrangement for Port B. The level of SIZE must
be static throughout device operation.
SPM Serial
Programming I A LOW on this pin selects serial programming of partial flag offse ts. A HIGH on this pin
selects parallel programming or default offsets (8, 16, or 64).
W/RA Port A Write/
Read Select I A HIGH se le cts a wri t e ope rati on a nd a LO W se lec ts a re ad o pe r atio n o n Po rt A fo r a
LOW -to-HIG H tra nsiti on o f CLKA. The A0–35 outputs a re i n th e high-imped ance sta te
when W/RA is HIGH.
W/RB Port B Write/
Read Select I A LOW sel ec ts a wr it e op era tio n and a HIG H se lec ts a re ad o peration o n Po rt B fo r a
LOW -to-HIG H tra nsiti on o f CLKB. The B0–35 outputs a re i n th e high-imped ance sta te
when W/RB is LOW.
Pin Definitions (continued)
Signal Name Description I/O Function
CY7C43643AV
CY7C43663AV
CY7C43683AV
PRELIMINARY
Document #: 38-06024 Rev. ** Page 6 of 29
Maximum Ratings[3]
(Above w hi ch the useful life may be impaired. For user g uid e-
lines, not tes ted .)
Storage Temperature ...................................–65°C to +150°C
Ambient Temperature with
Power Applied...............................................–55°C to +125°C
Supply Voltage to Ground Potential............... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State[4]......................................–0.5V to VCC+0.5V
DC Input Voltage[4] ..................................–0.5V to VCC+0.5V
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage...........................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Operating Range
Range Ambient
Temperature VCC[5]
Commercial 0°C to +70°C 3.3V ± 10%
Industrial –40°C to + 85°C 3.3V ± 10%
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions
CY7C43643/63/83AV
UnitMin. Max.
VOH Output HIGH Voltage VCC = 3.0 V,
IOH = –2.0 mA 2.4 V
VOL Output LOW Voltage VCC = 3.0 V,
IOL = 8.0 mA 0.5 V
VIH Input HIGH Voltage 2.0 VCC V
VIL Input LOW Vo ltage –0.5 0.8 V
IIX Input Leakage Current VCC = Max. –10 +10 µA
IOZL
IOZH Output OFF, High Z
Current VSS < VO< VCC –10 +10 µA
ICC1[6] Active Power Supply
Current Com’l60 mA
Ind 60 mA
ISB[7] Average Standby
Current Com’l10 mA
Ind 10 mA
Capacitance[8]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 2 5°C, f = 1 MHz,
VCC = 3.3V 4pF
COUT Output Capacitance 8pF
Notes:
3. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
4. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
5. Operating V CC Range for -7 speed is 3.3V ± 5%.
6. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10 MHz. Outputs
are unloaded.
7. All inputs = VCC – 0.2V, except CLKA and CLKB (which are at frequency = 0 MHz). All outputs are unloaded.
8. Tested initially and after any design or process changes that may affect these parameters.
CY7C43643AV
CY7C43663AV
CY7C43683AV
PRELIMINARY
Document #: 38-06024 Rev. ** Page 7 of 29
AC Test Loads and Waveforms (-10, -15)
AC Test Loads and Waveforms (-7)
Switching Characteristics Over the Operating Range
Parameter Description
CY7C43643/63/
83AV
-7
CY7C43643/
63/83AV
-10
CY7C43643/
63/83AV
-15
UnitMin. Max. Min. Max. Min. Max.
fSClock Frequency, CLKA or CLKB 133 100 67 MHz
tCLK Clock Cycle Time, CLKA or CLKB 7.5 10 15 ns
tCLKH Pulse Duration, CLKA or CLKB HIGH 3.5 4 6 ns
tCLKL Pulse Duration, CLKA or CLKB LOW 3.5 4 6 ns
tDS Set-Up T ime, A 0–35 before CLKA ↑ and B0–35 before
CLKB↑3 4 5 ns
tENS Set-Up T im e, CSA, W/RA , ENA, and MBA before
CLKA↑; CSB, W/RB, ENB, and MBB before CLKB↑3 4 5 ns
tRSTS Set-Up T ime, M RS1/MRS2, PRS, RT LOW before
CLKA↑ or CLKB↑[10] 2.5 4 5 ns
tFSS Set-Up Time, FS0 and FS1 before MRS1/MRS2
HIGH 5 7 7.5 ns
tBES Set-Up Ti me, BE/FWFT before MRS1/MRS2 HIGH 5 7 7.5 ns
tSPMS Set-Up T im e, SPM before MRS1/MRS2 HIGH 5 7 7.5 ns
tSDS Set-Up Ti me, FS0/SD before CLKA↑3 4 5 ns
tSENS Set-Up Time, FS1/SEN before CLKA↑3 4 5 ns
tFWS Set-Up Time, FWFT before CLKA↑0 0 0 ns
tDH Hold Time, A0–35 after CLKA↑ and B0–35 after
CLKB↑0 0 0 ns
tENH Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑;
CSB, W/RB, ENB, and MBB after CLKB↑0 0 0 ns
Note:
9. CL = 5 pF for tDIS.
10. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3.0V
3.3V
OUTPUT
R2=680Ω
CL =30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
≤3ns ≤3ns
ALL INPUT PULSES
R1=330Ω
[9]
3.0V
GND
90%
10%
90%
10%
≤3ns ≤3ns
ALL INPUT PULSES
I/O
50Ω
V
CC
/2
Z0=50Ω
CY7C43643AV
CY7C43663AV
CY7C43683AV
PRELIMINARY
Document #: 38-06024 Rev. ** Page 8 of 29
tRSTH Hol d Time, MRS1/MRS2, PRS, RT LOW after
CLKA↑ or CLKB↑[10] 1 2 2 ns
tFSH Hold Time, FS0 and FS1 after MRS1/MRS2 HIGH 1 1 2 ns
tBEH Hold Ti me, BE/FWFT after MRS1/MRS2 HIGH 1 1 2 ns
tSPMH Hold Time, SPM after MRS1/MRS2 HIGH 1 1 2 ns
tSDH Hold Ti me, FS0/SD after CLKA↑0 0 0 ns
tSENH Hold Time, FS1/SEN after CLKA↑0 0 0 ns
tSPH Hold T ime, F S1/SEN HIGH a fter MRS1/MRS2 HIGH 1 1 2 ns
tSKEW1[11] Skew Time between CLKA↑ and CLKB↑ fo r EF/OR
and FF/IR 5 5 7.5 ns
tSKEW2[11] Skew Time between CLKA↑ and CLKB↑ for AE and
AF 7 8 12 ns
tAAccess Time, CLK A↑ to A0–35 and CLKB↑ to B0–35 1 6 1 8 3 10 ns
tWFF Propagation Delay Time, CLKA↑ to FF/IR 1 6 1 8 2 10 ns
tREF Propagation Delay Time, CLKB↑ to EF/OR 1 6 1 8 2 10 ns
tPAE Propagation Delay Time, CLKB↑ to AE 1 6 1 8 1 10 ns
tPAF Propagation Delay Time, CLKA↑ to AF 1 6 1 8 1 10 ns
tPMF Propagation Delay Time, CLKA↑ to MBF1 LOW or
MBF2 HIGH and CLKB↑ to MBF2 LOW or MBF1
HIGH
0 6 0 8 0 12 ns
tPMR Propagation Delay Time, CLKA↑ to B0–35[12] and
CLKB↑ to A0–35[13] 1 7 2 11 312 ns
tMDV Propagation Delay Time, MBA to A0–35 Valid and
MBB to B0–35 Valid 1 6 2 9 3 11 ns
tRSF Propagation Delay T ime, MRS1/MRS2 or PRS LOW
to AE LOW , AF HIGH,FF/ IR LOW, EF/ OR LOW and
MBF1/MBF2 HIGH
1 6 1 10 115 ns
tEN Enable Time, CSA or W/RA LOW to A0–35 Active and
CSB LOW and W/RB HIGH to B0–35 Active 1 6 2 8 2 10 ns
tDIS Disable Time, CSA or W/RA HIGH to A0–35 at High
Impedance and CSB HIGH or W/RB LOW to B0–35
at High Impedance
1 5 1 6 1 8 ns
tRTR Retransmit R ec overy Time 90 90 90 ns
Notes:
1 1. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between the CLKA cycle and the CLKB
cycle.
12. Writing data to the Mail1 register when the B0–35 outputs are active and MBB is HIGH.
13. Writing data to the Mail2 register when the A0–35 outputs are active and MBA is HIGH.
Switching Characteristics Over the Operating Range (continued)
Parameter Description
CY7C43643/63/
83AV
-7
CY7C43643/
63/83AV
-10
CY7C43643/
63/83AV
-15
UnitMin. Max. Min. Max. Min. Max.
CY7C43643AV
CY7C43663AV
CY7C43683AV
PRELIMINARY
Document #: 38-06024 Rev. ** Page 9 of 29
Switching Waveforms
Note:
14. PRS must be HIGH during Master Reset.
Master Reset Loading X and Y with a Preset Value of Eight
CLKA
tRSF
tRSF
tRSF
tWFF
tFSS tFSH
tSPMS tSPMH
tBES tBEH
tRSTH
tRSTS
tFWS
CLKB
MRS1,
MRS2
BE/FWFT
SPM
FS1/SEN,
FS0/SD
FF/IR
EF/OR
AE
AF
MBF1
[14]
tRSF
tRSF
CY7C43643AV
CY7C43663AV
CY7C43683AV
PRELIMINARY
Document #: 38-06024 Rev. ** Page 10 of 29
Notes:
15. MRS1/MRS2 must be HIGH during Partial Reset.
16. CSA=LOW , W/RA=HIGH, MBA=LOW. It is not necessary to program offset register on consecutive clock cycles. FIFO can only be programmed in parallel
when FF/IR is HIGH.
17. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKB for FF/IR to transition HIGH in the next cycle. If the time between the rising
edge of CLKA and rising edge of CLKB is less than tSKEW1, then FF/IR may transition HIGH one cycle later than shown.
Switching Waveforms (continued)
Partial Reset (CY Standard and FWFT Modes)
tRSF
tRSF
tRSF
tRSTS tRSTH
CLKA
CLKB
PRS
FF/IR
EF/OR
AE
AF
MBF1
[15]
tWFF
tRSF
tRSF
Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset
(CY Standard and FWFT Modes)
tWFF
tFSS
tDS
tFSS tFSH
tFSH
tENS tENH
tDH
tSKEW1[17]
AF Offset (Y) First Word to FIFO
CLKA
MRS1,
MRS2
SPM
FS1/SEN,
FS0/SD
FF/IR
ENA
A0−35
[16]
AE Offset (X)
CY7C43643AV
CY7C43663AV
CY7C43683AV
PRELIMINARY
Document #: 38-06024 Rev. ** Page 1 1 of 29
Notes:
18. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts into the memory are ignored until FF/IR is set HIGH.
19. Pr ogr am ma ble offsets are w ritte n serial ly to the SD i npu t in the order AF offset (Y) then AE offset (X).
20. Read From FIFO.
21. If W/RB switches from read to write before the assertion of CSB, tENS=tDIS+tENS.
Switching Waveforms (continued)
Serial Programming of the Almost-Full Flag and Almost-Empty Flag
Offset Values (CY Standard and FWFT Modes)
tFSS tSPH tSENS tSENH tSENH
tSENS
tSDH
tSDS tSDH
tSDS
tWFF
AF Offset (Y) MSB
tFSS tFSH
CLKA
MRS1,
MRS2
SPM
FF/IR
FS1/SEN
[18, 19]
FS0/SD [19]
AE Offset (X) LSB
tFSS tFSH
OR
tCLKH tCLKL
tENS
tDIS
tENS tEN
tCLK
tDIS
tENH
tENS tENH
tA
tA
tA
tA
tEN
tEN
tMDV
tMDV
W1[20] W2[20]
W1[20] W2[20]
W3[20]
Previous Data
No Operation
CLKB
EF/OR
CSB
W/RB
MBB
ENB
B0–35
(Standard Mode)
B0–35
(FWFT Mode)
Port B Long-Word Read Cycle Timing for FIFO (CY Standard and FWFT Modes)
HIGH
[21]
CY7C43643AV
CY7C43663AV
CY7C43683AV
PRELIMINARY
Document #: 38-06024 Rev. ** Page 12 of 29
Notes:
22. Unused bytes B18–35 contains all zeroes for word-size reads.
23. Unused bytes B9–17, B18–26, and B27–35 co ntain all zeroes for byte-size reads.
Switching Waveforms (continued)
OR
OR
tDIS
tENS tENH
tA
tA
tA
tA
tEN
tEN
tMDV
tMDV tDIS
Previous Data
Read 1
Read 1
Read 2
Read 2
Read 3
No Operation
CLKB
EF/OR
CSB
W/RB
MBB
ENB
B0–17
(Standard Mode)
B0–17
(FWFT Mode)
Port B Word Read Cycle Timing for FIFO (CY Standard and FWFT Modes)[22]
HIGH
[21]
tDIS
tENStENH
tA
tA
tA
tA
tEN
tEN
tMDV
tMDV tDIS
tA
tA
tA
tA
Previous Data
Read 1
Read 1
Read 2
Read 2
Read 3
Read 3
Read 4
Read 4
Read 5
No Operation
HIGH
CLKB
EF/OR
CSB
W/RB
MBB
ENB
B0–8
(Standard Mode)
B0–8
(FWFT Mode)
Port B Byte Read Cycle Timing for FIFO (CY Standard and FWFT Modes) [23]
OR
[21]
CY7C43643AV
CY7C43663AV
CY7C43683AV
PRELIMINARY
Document #: 38-06024 Rev. ** Page 13 of 29
Notes:
24. If Port B size is word or byte, EF is set LOW by the last word or byte read from the FIFO, respectively.
25. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for OR to transition HIGH and to clock the next word to the FIFO outp ut
register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of OR HIGH and load
of the first word to the output register may occur one CLKB cycle later than shown.
Switching Waveforms (continued)
tCLKH tCLKL
tENS
tCLK
tEN
tENS
tEN
tA
tDS
W1
LOW
tDH
HIGH
HIGH
FIFO Em pty
LOW
HIGH
LOW
Old Data in FIFO Output Register W1
tENS tENH
tREF tREF
tCLKH tCLKL
tCLK
tSKEW1[25]
CLKA
CSA
W/RA
MBA
ENA
FF/IR
A0–35
CLKB
EF/OR
CSB
W/RB
MBB
ENB
B0–35
OR Flag Timing and First Data Word Fall Through when FIFO is Empty (FWFT Mode) [24]
CY7C43643AV
CY7C43663AV
CY7C43683AV
PRELIMINARY
Document #: 38-06024 Rev. ** Page 14 of 29
Note:
26. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EF to transition HIGH in the next CLKB cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transiti on of EF HIGH may occur one CLKB cycle later than shown.
Switching Waveforms (continued)
tCLKH tCLKL
tENS
tENH
tENS
tENH
tA
tDS
W1
LOW
tDH
HIGH
HIGH
FIFO Empty
LOW
HIGH
LOW
W1
tENStENH
tREF tREF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[26]
CLKA
CSA
W/RA
MBA
ENA
FF/IR
A0–35
CLKB
EF/OR
CSB
W/RB
MBB
ENB
B0–35
EF Flag Timing and First Data Read Fall Through when FIFO is Empty (CY Standard Mode)
[24]
CY7C43643AV
CY7C43663AV
CY7C43683AV
PRELIMINARY
Document #: 38-06024 Rev. ** Page 15 of 29
Notes:
27. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that reads the last word or byte write of the long-word, respectively.
28. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition HIGH in the next CLKA cycle. If the time between the
rising CLKB edge and rising CLKA edge is less than tSKEW1, then IR may transition HIGH one CLKA cycle later than shown.
Switching Waveforms (continued)
tCLKH tCLKL
tENStENH
tA
LOW
HIGH
HIGH
FIFO Full
LOW
HIGH
tENStENH
tWFF tWFF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[28]
tDH
tDS
tENH
tENS
Previous Word in FIFO Output Register N ex t Wo rd Fro m FI FO
To FIFO
CLKB
CSB
W/RB
MBB
ENB
EF/OR
B0–35
CLKA
FF/IR
CSA
W/RA
MBA
ENA
A0–35
IR Flag Timing and First Available Write when FIFO is Full (FWFT Mode) [27]
LOW
CY7C43643AV
CY7C43663AV
CY7C43683AV
PRELIMINARY
Document #: 38-06024 Rev. ** Page 16 of 29
Note:
29. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FF to transition HIGH in the next CLKA cycle. If the time between the
rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transiti on of FF HIGH may occur one CLKA cycle later than shown.
Switching Waveforms (continued)
tCLKH tCLKL
tENStENH
tA
LOW
HIGH
HIGH
FIFO Fu ll
LOW
HIGH
tENStENH
tWFF tWFF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[29]
tDH
tDS
tENH
tENS
Previous Word in FIFO Output Register Nex t Wor d Fro m FIF O
CLKB
CSB
W/RB
MBB
ENB
EF/OR
B0–35
CLKA
FF/IR
CSA
W/RA
MBA
ENA
A0−35
FF Flag Timing and First Available Write when FIFO is Full (CY Standard Mode) [27]
LOW
CY7C43643AV
CY7C43663AV
CY7C43683AV
PRELIMINARY
Document #: 38-06024 Rev. ** Page 17 of 29
Notes:
30. P ort A Wri te ( CSA = L OW, W/RA = HIGH, MBA = LOW), Port B read (CSB = LOW , W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been
read from the FIFO.
31. D = Maximum FIFO Depth = 1K for the CY7C43643AV, 4K for the 43663AV, and 16K for the CY7C43683AV.
32. If Port B size is word or byte, tSKEW2 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
33. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition HIGH in the next CLKA cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than tSKEW2, then AF may transition HIGH one CLKB cycle later than shown.
34. P ort A Wri te ( CSA = L OW, W/RA = HIGH, MBA = LOW), Port B read (CSB = LOW , W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been
read from the FIFO.
35. If Port B size is word or byte, AE is set LOW by the last word or byte read from FIFO, respectively.
36. tSKEW2 i s the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition HIGH in the next CLKB cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than tSKEW2, then AE may transition HIGH one CLKB cycle later than shown.
Switching Waveforms (continued)
Tim ing for AF when FIFO is Almost Full (CY Standard and FWFT Modes)
tENH
tENS
tPAF
tENS tENH
[D–(Y+1)] Words in FIFO (D–Y)Words in FIFO
CLKA
ENA
AF
CLKB
ENB
[2, 30, 31, 32]
[D-(Y+2)] words in FIFO
tSKEW2[33]
tPAF
tENS tENH
CLKA
ENA
CLKB
AE
ENB
Timing for AE when FIFO is Almost Empty (CY Standard and FWFT Modes)[ 2, 34, 35]
tENS tENH
X Word in FIFO
tENH
tENS
tSKEW2[36]
tPAE
tPAE
tENS tENH
(X+2)W or ds in FIFO
tENH
tENS
X Words in FIFO
(X+1) Words in FIFO (X+2) Words in FIFO
CY7C43643AV
CY7C43663AV
CY7C43683AV
PRELIMINARY
Document #: 38-06024 Rev. ** Page 18 of 29
Note:
37. If Port B is configured for word size, data can be written to the Mail1 register using A0–17 (A18–35 are “Don’t Care” inputs). In this first case B0–17 will have
valid data (B18–35 will be indeterminate). If Port B is configured for byte size, data can be written to the Mail1 Register using A0–8 (A9–35 are “Don’t Care”
inputs). In this second case, B0–8 will have valid data (B9–35 will be indeterminate).
38. If W/RA switches from read to write before the assertion of CSA, tENS = tDIS+tENS.
Switching Waveforms (continued)
tENH
tENS
tENH
tENS
tENH
tENS
tENH
tENS
tDH
tDS
W1
tPMF tPMF
tEN tMDV tPMR
tENS tENH
tDIS
FIFO Output Register W1 (Remains valid in Mail1 Register after read)
CLKA
CSA
W/RA
MBA
ENA
A0–35
CLKB
MBF1
CSB
W/RB
MBB
ENB
Timing for Mail1 Register and MBF1 Flag (CY Standard and FWFT Modes)[37]
B0−35
[38]
[21]
CY7C43643AV
CY7C43663AV
CY7C43683AV
PRELIMINARY
Document #: 38-06024 Rev. ** Page 19 of 29
Notes:
39. If Port B is co nfig ure d for wo rd si ze, data c an b e wr itt en t o the M ail 2 r egis ter usin g B 0–17 (B18–35 are don’t care inputs). In this first case A0–17 will have valid
data (A 18–35 will be indeterminate). If Port B is configured for byte size, data can be written to the Mail2 Register using B0–8 (B9–35 are “Don’t Care” inputs).
In this second case, A0–8 will have valid data (A9–35 will be indeterminate).
40. Clocks are free-running in this case. CY standard mode only. Write operation should be prohibited one write clock cycle before the falling edge of RT, and
during the retransmit operation, i.e, when R T is LOW and tRTR after the RT rising edge.
41. The Empty and Full flags may change state during Retransmit as a result of the offset of the read and write pointers, but the Empty and Full flags will be
valid at tRTR.
42. For the AE and AF flags, two clock cycles are necessary after tRTR to update these flags.
Switching Waveforms (continued)
tENH
tENS
tENH
tENS
tENH
tENS
tENH
tENS
tDH
tDS
W1
tPMF tPMF
tEN tMDV tPMR
tENS tENH
tDIS
FIFO2 Output Register W1 (Remains valid in Mail2 Register after read)
CLKB
CSB
W/RB
MBB
ENB
B0–35
CLKA
MBF2
CSA
W/RA
MBA
ENA
A0−35
Timing for Mail2 Register and MBF2 Flag (CY Standard and FWFT Modes)[39]
[21]
[38]
FIFO Retransmit Timing
ENB
RT
t
RTR
EFB/FFA
[39, 40, 41, 42]
tRSTS tRSTH
CLKA
CLKB
CY7C43643AV
CY7C43663AV
CY7C43683AV
PRELIMINARY
Document #: 38-06024 Rev. ** Page 20 of 29
Signal Descript ion
Master Reset (MRS1, MRS2)
The FIFO memory of the CY7C436X3AV undergoes a com-
plete reset by taking its associated Master Reset (MRS1,
MRS2) input LOW for at least four Port A clock (CLKA) and
four Port B clock (CLKB) LOW-to-HIGH transitions. The Mas-
ter Reset input can switch asynchronously to the clocks. A
Master Reset initializes the internal read and write pointers
and forces the Full /In put R ea dy fla g (FF/IR) LO W, the Empty/
Output Re ady fla g (EF/O R) LO W, the Almo st Em pty fla g (AE)
LOW , and the Almost Full flag (AF) HIGH. A Master Reset also
forces the Mailbox flag (MBF1, MBF2) of the parallel mailbox
register HIGH. After a Master Reset, the FIFO’s Full/Input
Ready flag is set HIGH after two clock cycles to begin normal
operation. A Master Reset must be performed on the FIFO
after power up, before data is written to its memory.
A LOW-to-HIGH transition on a FIFO Master Reset (MRS1,
MRS2) input latches the value of the Big Endian (BE) input,
determining the order by which bytes are transferred through
Port B.
A LOW-to-HIGH transition on a FIFO reset (MRS1, MRS2)
input latches the values of the Flag Select (FS0, FS1) and
Serial Programming Mode (SPM) inputs for choosing the Al-
most Full and Almost Empty offset programming method (see
Almost Empty and Almost Full flag offset programming below).
Partial Reset (PRS)
The FIFO memory of the CY7C436X3AV undergoes a limited
reset by t aki ng its as so ci at ed Pa rt ia l Rese t (PRS ) input LOW
for at least four Port A clock (CLKA) and four Port B clock
(CLKB) LOW-to-HIGH transitions. The Partial Reset inputs
can switch asynchronously to the clocks. A Partial Reset ini-
tialize s the internal rea d and write pointers and fo rces the Full/
Input Ready flag (FF/IR) LOW, the Em pty/Outp ut Ready f lag
(EF/OR) LOW, the Almost Empty flag (AE) LOW, and the Al-
most Full flag (AF) HIGH. A Partial Reset al so forces the Mail-
box flag (MBF1, MBF2) of the parallel mailbox register HIGH.
After a Partial Reset, the FIFO’s Full/Input Ready flag is set
HIGH after two clock cycles to begin normal operation.
What ever fl ag offsets, program ming met hod (pa rallel or seri-
al), and timing mode (FWFT or CY Standard mode) are cur-
rently selected at the time a Partial Reset is initiated, those
settings will remain unchanged upon completion of the reset
operation. A Partial Reset may be useful in the case where
reprogramming a FIFO following a Master Reset would be in-
convenient.
Big Endian/First-Word Fall-Through (BE/FWFT)
This is a dual-purpo se pin. At the time of Mast er Reset, the BE
select function is active, permitting a choice of Big or Little
Endian byte arrangement for data written to or read from
Port B. This selection determines the order by which bytes (or
words) of data are tran sferred through thi s port. For the follow-
ing illustrations, assume that a byte (or word) bus size has
been selected for Port B.
A HIGH on the BE/FWF T input when the Master Reset (MRS1,
MRS2) inputs go from LOW to HIGH will select a Big Endian
arrangement. When data is moving in the direction from Port
A to Port B, the most significant byte (word) of the long-word
written to Port A will be transferred to Port B first; the least
signifi cant byte (word) of the long-word writt en to Port A will b e
transferred to Port B last.
A LOW on th e BE/FWF T in put when the Mas ter Reset (M RS1,
MRS2) inputs go from L OW to HIGH will se le ct a L ittle En dian
arrangement. When data is moving in the direction from Port
A to Port B, the least significant byte (word) of the long-word
written to Port A will be transferred to Port B first; the most
signifi cant byte (word) of the long-word writt en to Port A will b e
transferred to Port B last.
After Mast er Reset, the F WF T selec t function is active, permi t-
ting a choice between two possible timing modes: CY Stan-
dard Mode or First-Word Fall-Through (FWFT) Mode. Once
the Ma ster Reset (MRS1, MRS2) input i s HIGH, a HIGH on the
BE/FWFT input at the second LOW-to-HIGH transition of
CLKA will select CY Standard Mode. This mode uses the Emp-
ty Flag function (EF) to indicate whether or not there are any
words p res ent in the FIFO me mory. It uses th e Ful l Fl ag func -
tion (FF) to in dic ate whe ther or not th e FI FO me mo ry h as an y
free spa ce for wr itin g. In CY Stand ard Mo de , ev ery word rea d
from the FIFO, including the first, must be requested using a
formal read operation.
Once the Master Reset (MRS1, MRS2) input is HIGH, a LO W
on the BE/FWFT input of the second LOW-to-HIGH transition
of CLKA will select FWFT Mode. This mode uses the Output
Ready function (OR) to indicate whether or not there is valid
data at the data outputs (B0–35). It also uses the Input Ready
function (IR) to indicate whether or not the FIFO memory has
any free space for writing. In the FWFT mode, the first word
written to an empty FIFO goes directly to data outputs, no read
request necessary. Subsequent words must be accessed by
performing a formal read operation.
Following Master Reset, the level applied to the BE/FWFT in-
put to choose the desired timing mode must remain static
throughout the FIFO operation.
Programming the Almost Empty and Almost Full Flags
T wo re gisters in the C Y7C436X3AV are used to hold the offset
values for the Almost Em pty a nd Alm ost Full fla gs. The Po rt B
Almost Empty fla g (AE) offs et register is la beled X. The Port A
Almost Full flag (AF) offset register is labeled Y. The index of
each register name corresponds with preset values during the
reset of a FIFO, programmed in parallel using the FIFO’s Port
A data inputs, or programmed in serial using the Serial Data
(SD) input (see Table 1).
To load a FIFO’s Almost Empt y flag and Alm ost Full fla g offs et
registers with one of the three preset values listed in Ta bl e 1 ,
the Serial Program Mode (SPM) and at least one of the flag-
select inputs must be HIGH during the LOW-to-HIGH transition
of its Mas ter Reset input (MRS1, MRS2). For example, to load
the p r es et v al ue o f 64 i nt o X an d Y, SP M, FS0 and FS1 must
be HIGH when the FIFO reset (MRS1, MRS2) returns HIGH.
When using one of the preset values for the flag offsets, the
FIFO can be reset simultaneously or at different times.
To program the X a nd Y regist ers from Port A, pe rform a Mas -
ter Reset on both FIFOs simultaneously with SPM HIGH and
FS0 and FS1 LOW during the LOW-to-HIGH transition of
MRS1, MRS2. After this reset is complete, the first two writes
to the FIF O do n ot stor e data in RAM but l oad the of fset re gis-
ters in the order Y and X. The Port A data inputs used by the
offset registers are (A0–9), (A0–11), or (A0–13), for the
CY7C436X3AV, respectively. The highest numbered input is
used as the most significant bit of the binary number in each
CY7C43643AV
CY7C43663AV
CY7C43683AV
PRELIMINARY
Document #: 38-06024 Rev. ** Page 21 of 29
case. Valid program ming value s for the registe rs range from 0
to 1023 for the CY7C43643AV; 0 to 4095 for the
CY7C43663AV; 0 to 16383 for the CY7C43683AV.[2] Before
programming the offset registers, FF/IR is set HIGH. FIFOs
begin normal operation after programming is complete.
To program the X and Y registers serially, initiate a Master
Reset with SPM LOW , FS0/SD LOW , and FS1/SEN HIGH dur-
ing the LOW-to-HIGH transition of MRS1, MRS2. After this
reset is complete, the X and Y register values are loaded bit-
wise through the FS0/SD input on each LOW-to-HIGH transi-
tion of CLKA that the FS1/SEN input is LOW. Twenty, twenty-
four , o r twe nty-eight bit writ es are needed to complete the pro-
grammi ng f or the CY7C 436X3 AV, respec tively. The two regi s-
ters are written in the order Y then finally X. The first-bit write
stores the most significant bit of the Y register and the last-bit
write st ores the leas t significant bi t of the X register. Each reg-
ister value can be programmed from 0 to 1023
(CY7C43643AV), 0 to 4095 (CY7C43663AV), or 0 to 16383
(CY7C43683AV).
When the opt ion to p rogram th e of fset re gisters serially is ch o-
sen, the Port A Full/Input Ready (FF/IR) flag remains LOW
until all register bits are written. FF/IR is set HIGH by the LOW-
to-HIGH transition of CLKA after the last bit is loaded to allow
normal FIFO opera tion.
SPM, FS0/SD, and FS1/SEN function the same way in both
CY Standard and FWFT modes.
FIFO Write/Read Operation
The state of the Port A data (A0–35) lines is controlled by Port
A Chip Select (CSA) and Port A Write/Read Select (W/RA).
The A0–35 lines are in the high-impedance state when either
CSA or W/ RA is HIGH. The A0–35 lines are active mail 2 reg-
ister outputs when both CSA and W/RA are LOW.
Data i s loa ded in to the FIFO f r om the A0–35 inputs on a LOW -
to-HIGH transition of CLKA when CSA is LOW , W/RA is HIGH,
ENA is HIGH, MBA is LOW, and FF/IR is HIGH. (s ee Table 2).
FIFO writes on Port A are independent of any concurrent
Port B operation.
The Port B c ontr ol s ig nal s a re i dentical to th os e of Port A w i th
the exception that the Port B Write/Read select (W/RB) is the
inverse of the Port A Write/Read select (W/RA). The state of
the Port B data (B0–35) lines is controlled by the Port B Chip
Select (CSB) and Po rt B Write/Read s elect (W/RB). The B0–35
lines are in the high-impedance state when either CSB is
HIGH or W/RB is LOW. The B0–35 lines are active outputs
when CSB is LOW and W/RB is HIGH.
Data is rea d fro m the FIF O to the B0–35 outputs by a LO W - to-
HIGH transition of CLKB when CSB is LOW, W/RB is HIGH,
ENB is HIGH, MBB is LOW , and EF/OR is HIGH (see Table 3).
FIFO reads and writes on Port B are independent of any con-
current Port A operation.
The set-up and hold tim e co ns trai nts to the port c loc k s for the
port Chip Selects and W rite/Read Selects are only for enabling
write and read operations and are not related to high-imped-
ance control of t he data outputs. If a port enable is LOW during
a clock cycle, the port’s Chip Select and Write/Read Select
may c han ge sta tes during th e set-up and hol d t ime w in dow of
the cycle.
When operating the FIFO in FWFT Mode with the Output
Ready flag LOW , the next word written is automa tically sent to
the FIFO’s output register by the LOW-to-HIGH transition of
the port clock that sets the Output Ready flag HIGH, data re-
siding in the FIFO’s memory array is clocked to the output reg-
ister only when a read is selected using the port’s Chip Sele ct,
Write/Read Select, Enable, and Mailbox Select.
When opera ting the FIFO in CY Stand ard Mode, regardle ss of
whether the Empty Flag is LOW or HIGH, data residing in the
FIFO’s memory array is clocked to the output register only
when a read is selected using the port’s Chip Select, Write/
Read Select, Enable, and Mailbox Select.
Synchronized FIFO Flags
Each FIFO is synchronized to its port clock through at least
two fli p-flop stages. Th is is done to improve flag-si gnal reliabi l-
ity by reducing the probability of the metastable events when
CLKA and CLKB operate asynchronously to one another.
EF/OR and AE are synchronized to CLKB. FF/IR and AF are
synch ronized to CLKA. Table 4 shows the relation ship of e ach
port flag to the FIFO.
Empty/Output Ready Flags (EF/OR)
These are dual -purpose flag s. In the FWFT Mode, the Output
Ready (OR) fu nct ion is s elect ed. When t he Ou tput Ready flag
is HIGH, new data is present in the FIFO output reg ister . When
the Output Ready flag is LOW, the p revious data word remains
in the FIFO output register and any FIFO reads are ignored.
In the CY Standard Mode, the Empty Flag (EF) function is
selected. When the Empty Flag is HIGH, data is available in
the FIFO’s RAM memory for reading to the output register.
When Empty Flag is LOW, the previous data word remains in
the FIFO output register and any FIFO reads are ignored.
The Empty/Output Ready flag of a FIFO is synchronized to
CLKB. For b oth the FW FT and CY Standard modes, the FIFO
read pointer is incremented each time a new word is clocked
to its output register. The state machine that controls an Out-
put Re ady fl ag mon ito rs a w ri te p oin ter and read pointer c om -
parator that indicates when the FIFO SRAM status is empty,
empty+1, or empty+2.
In FWF T Mode, from the time a word is written to a FIFO, i t can
be shifted to the FIFO output register in a minimum of three
cycles of the Output Ready flag synchronizing clock. There-
fore, an Output Ready flag is LOW if a word in memory is the
next data to be sent to the FIFO output register and three cy-
cles have not elapsed since the time the word was written. The
Output Ready flag of the FIFO remains LOW until the third
LOW - to- HI GH tran si tion of th e sy nc hron iz ing c loc k oc cu rs, s i-
multane ously fo rcing the O utput Ready flag HIGH a nd shiftin g
the word to the FIFO output register.
In the CY Standard Mod e, from the time a word is written to a
FIFO, the Empty flag will indicate the presence of data avail-
able for reading in a minimum of two cycles of the Empty flag
synchronizing clock. Therefore, an Empty flag is LOW if a word
in memory is the next data to be sent to the FIFO output reg-
ister an d tw o cy cl es hav e n ot e la pse d s in ce the tim e t he w o rd
was written. The Empty flag of the FIF O remains LOW u ntil the
second LOW-t o-HIGH transition of the synchronizing clock oc-
curs, forc ing the Empty flag HIG H; only then can d ata be read.
A LOW-to-HIGH transition on an Empty/Output Ready flag
synch ronizi ng cloc k begins the first sy nchron izati on cycl e of a
write if the clock transition occurs at time tSKEW1 or greater
after the write. Otherwise, the subsequent clock cycle will be
the first synchronization cycle.
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Full/Input Ready Flags (FF/IR)
This is a dual-purpose flag. In FWFT Mode, the Input Ready
(IR) function is selected. In CY Standard Mode, the Full Flag
(FF) function is selected. For both timing modes, when the
Full/Inp ut Ready flag is HIGH, a memory loca tion is free in the
SRAM to receive new data. No memory locations are free
when the Full/Input Ready flag is LOW and any writes to the
FIFO are ignored.
The Full/Input Read y fl ag o f a FIFO is sy nc hron iz ed to CLKA.
For both FWFT and CY Standar d mod es , eac h tim e a w ord is
written to a FIFO, its write pointer is incremented. The state
machin e th at c ontr ols a Fu ll/Input Read y fl ag m on ito rs a w ri te
pointer and read pointer comparator that indicates when the
FIFO SRAM status is full, full–1, or full–2. From the time a word
is read from a FIFO, its previous memory location is ready to
be written to in a minimum of two cycles of the Full/Input Ready
flag synchronizing clock. Therefore, a Full/Input Ready flag is
LOW if less than two cycles of the Full/Input Ready flag syn-
chronizing clock have elapsed since the next memory write
location has been read. The second LOW-to-HIGH transition
on the Fu ll/Input R eady flag synchron izing c lock after the read
sets the Full/Input Ready flag HIGH.
A LOW -to-HIGH tra nsition o n a Full/Inpu t Ready flag s ynchro-
nizing clock begins the first synchronization cycle of a read if
the clock transition occurs at time tSKEW1 or greater after the
read. Otherwise, the subsequent clock cycle can be the first
sync hronization cycle.
Almost Empty Flags (AE)
The Almost Empty flag of the FIFO is synchronized to port B
clock. The state machine that controls an Almost Empty flag
monitor s a write pointer an d read poi nter comp arator that indi-
cates when the FIFO SRAM status is almost empty, almost
empty+1, or almost empty+2. The Almost Empty state is de-
fined by the co nte nts of reg ister X for AE. Th es e reg isters are
loaded with preset values during a FIFO reset, programmed
from Port A, or programmed serially (see Almost Empty flag
and Almost Full flag offset programming above). An Almost
Empty flag is LOW when its FIF O contains X or less words and
is HIGH when its FIFO contains (X+2) or more words.[2]
The Almost Empty flag is set HIGH by the first CLKB rising
edge aft er two FIF O writes th at fills mem ory to the (X+2) leve l.
A LOW -to-HI GH transitio n of CLKB beg ins the first sy nchroni-
zation cycle if it occurs at time tSKEW2 or greater af ter the write
that fills the FIFO to (X+2) words. Otherwise, the subsequent
synchronizing clock cycle will be the first synchronization cy-
cle.
Almost Full Flag s (AF)
The Almost Full flag of the FIFO is synchronized to port A
clock. The state machine that controls an Almost Full flag mon-
itors a w rite pointer and read point er comparator that indicates
when the FIFO SRAM status is almost full, almost full–1, or
almost full–2. The Almost Ful l s tat e i s d efi ned by th e c on t ent s
of register Y for AF. These registers are loaded with preset
values during a FIFO reset, programmed from Port A, or pro-
gramme d se rially (see Almos t Empt y flag an d Almos t Full fla g
offset programming above). An Almost Full flag is LOW when
the number of words in its FIFO is greater than or equal to
(1024–Y), (40 96–Y), or (1 63 84–Y), for the C Y7C43 6X3 AV re-
spectively. An Almost Full flag is HIGH when the number of
words in its FIFO is less than or equal to [1024–(Y+2)],
[4096–(Y+2)], or [16384–(Y+2)], for the CY7C436X3AV re-
spectively.
The Almo st F ull fla g is se t HIG H by the firs t CLKA ris ing edg e
after two FIFO reads that reduces the number of words in
memory to [1024 /4096/1 6384–(Y+2)] . A LOW -to-HIGH tra nsi-
tion of CLKA begins the first synchronization cycle if it occurs
at time tSKEW2 or greater after the read that reduce s the num-
ber of words in memory to [1024/4096/16384–(Y+2)]. Other-
wise, the subsequ ent synchron izing cloc k cycle will be the first
synchronization cycle.
Mailbox Registers
Each FI FO has a 36-b it bypass register to pas s com mand and
control in form ati on be tween Port A and Port B without pu ttin g
it in queue. The Mailbox Select (MBA, MBB) inputs choose
between a mail register and a FIFO for a port data transfer
operat ion. The usable w idth of both the Ma il1 and Mail2 regis-
ters matches the selected bus size of Port B.
A LOW-to-HIGH transition on CLKA writes A0−35 data to the
Mail1 Reg ister wh en a Port A write i s select ed by CSA, W /RA,
and ENA with MBA HIGH. If the selected Port A bus size is
also 36 bits, then the usable width of the Mail1 Register em-
ploys d ata lines A0−35. If the selected Po rt A bus size is 18 bits,
then the usable width of the Mail 1 Registe r employ s data li nes
A0−17. (In this ca se, A18−35 are don’t care input s.) If t he select -
ed Por t A b us si ze is 9 bits , t hen the usable width of the M ail 1
Register employs data lines A0–8. (In this case, A9−35 are
“Don’t Care” inputs.)
A LOW-to-HIGH transition on CLKB writes B0−35 data to the
Mail2 Reg ister wh en a Port B write i s select ed by CSB, W /RB,
and ENB with MBB HIGH. If the selected Port B bus size is
also 36 bits, then the usable width of the Mail2 Register em-
ploys d ata lines B0–35. If the se lected Port B bus size is 18 bits,
then the usable width of the Mail 2 Registe r employ s data li nes
B0–17. (In this case, B18–35 are don’t care inputs .) If the se lect-
ed Por t B b us si ze is 9 bits , t hen the usable width of the M ail 2
Register employs data lines B0−8. (In this case, B9−35 are
“Don’t Care” inputs.)
Writing data to a mail register sets its corresponding flag
(MBF1 or MBF2) LOW. Attempted w rites to a mail registe r are
ignored while the mail flag is LOW.
When data outputs of a port are active, the data on the bus
comes fro m the FIFO outpu t regis ter if the p ort Ma ilbox Selec t
input is LOW and from the mail register if the port Mailbox
Select input is HIGH.
The Mail1 Register flag (MBF1) is set HIGH by a LOW-to-
HIGH transition on CLKB when a Port B read is selected by
CSB, W/RB, and ENB with MBB HIGH.
The Mail2 Register flag (MBF2) is set HIGH by a LOW-to-
HIGH transition on CLKA when a Port A read is selected by
CSA, W/RA, and ENA with MBA HIGH.
The data in a mail register remains intact after it is read and
changes only when new data is written to the register. The
Endian Select feature has no effect on the mailbox data.
Bus Sizing
The Port B bus can be config ured in a 36-bit long -word, 1 8-bit
word, or 9-bit byte format for data read from FIFO. The levels
applied to the Port B Bus Size Select (SIZE) and the Bus
Match Select (BM) determine the Port B bus size. These levels
should b e static throug hout FIFO operati on. Both bus size se-
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lecti ons are imp lement ed at the co mpletion of Master Res et,
by the time the Full/Input Ready flag is set HIGH.
Two different methods for sequencing data transfer are avail-
able for Port B when the bus size selection is either byte-or
word-size . They are referred to as Big Endian (most significant
byte first) and Little Endian (least significant byte first). The
level applied to the Big Endian Select (BE) input during the
LOW-to-HIGH transition of MRS1/MRS2 selects the endian
method t hat will be active du ring FIFO op eration. BE i s a don’t
care inpu t when t he bu s s ize se lec ted for Port B is long-wo rd.
The endian method i s im pl em ent ed at the compl etion of Ma s-
ter Reset, by the time the Full/Input Ready flag is set HIGH.
Only 36-bit long-word data is written to the FIFO memory on
the CY7C436X3AV. Bus-matching operations are done after
data is read from the FIFO. These bus-matching operations
are no t avai lable wh en tr ansferr ing dat a via m ailbo x regis ters.
Furthermore, both the word- and byte-size bus selections limit
the width of the data bus that can be used for mail register
operatio ns. In this case, on ly those by te lanes b elonging to the
selected word- or byte-size bus can carry mailbox data. The
remaining data outputs will be indeterminate. The remaining
data inputs will be don’t care inputs. For example, when a
word-size bus is selected, then mailbox data can be transmit-
ted only between A0–17 and B0–17. When a byte-size bus is
selec te d , th en m a il bo x d ata c a n be t ra n sm it te d on l y be tw e en
A0–8 and B0–8.
Bus-Matching FIFO Reads
Data is read from the FIFO RAM in 36-bit long-word incre-
ments. If a long-word bus size is implemented, the entire long-
word immediately shifts to the FIFO output register. If byte or
word size is implemented on Port B, only the first one or two
bytes app ear on the selec ted portion of the FIFO output regis-
ter, with the rest of the long-word stored in auxiliary registers.
In this case, subsequent FIFO reads output the rest of the
long-word to the FIFO output register.
When reading data from the FIFO in the byte or word format,
the unused B9–35 or B18–35 outpu ts are ind eterminate.
Retransmit (RT)
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary. Retransmit func-
tion applies to CY standard mode only.
The retransmit feature is intended for use when a number of
writes equal to or less than the depth of the FIFO have oc-
curred and at least one word has been read since the last reset
cycle. A LOW pulse on RT resets the internal read pointer to
the first physical location of the FIFO. CLKA and CLKB may be
free running but ENB must be disabled during and tRTR after
the retrans mit pulse . With ev ery valid re ad cyc le after retrans -
mit, previously accessed data is read and the read pointer is
increme nted unti l it is equal to the write pointer. Flags are gov-
erned by the relative locations of the read and write pointers
and are upd ated during a retra ns mi t cy cl e. Data wr itte n to th e
FIFO afte r activation of RT are transmitted also. The full depth
of the FIFO can be repeatedly retransmitted.
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Document #: 38-06024 Rev. ** Page 24 of 29
A
A27–35 B
A18–26 C
A9–17 D
A0–8
A
B27–35 B
B18–26 C
B9–17 D
B0–8
A B
C D
CD
AB
A
B
C
D
(a) LONG WORD SIZE
(b) WORD SIZE – BIG ENDIAN
(c) WORD SIZE – LITTLE END IAN
(d) BYTE SIZE – BIG ENDIAN
BE BM SIZE
XLX
BE BM SIZE
HHL
BE BM SIZE
LHL
BE BM SIZE
HHH
Write to FIFO
Read from
FIFO
1st: Read from
FIFO
2nd: Read from
FIFO
1st: Read from
FIFO
2nd: Read from
FIFO
1st: Read from
FIFO
2nd: Read from
FIFO
3rd: Read from
FIFO
4th: Read from
FIFO
BYTE OR DER ON
PORT A:
D
C
B
A
(e) BYTE SIZE – LITTLE ENDIAN
BE BM SIZE
LHH
1st: Read from
FIFO
2nd: Read from
FIFO
3rd: Read from
FIFO
4th: Read from
FIFO
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
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Document #: 38-06024 Rev. ** Page 25 of 29
..able
Ta ble 1. Flag Programming
SPM FS1/SEN FS0/SD MRS1/MRS2 X and Y Registers[43]
H H H ↑64
H H L ↑16
H L H ↑8
H L L ↑Parallel programming via Port A
L H L ↑Serial program mi ng vi a SD
L H H ↑Reserved
L L H ↑Reserved
L L L ↑Reserved
Table 2. Port A Enable Function
CSA W/RA ENA MBA CLKA A0–35 Port Function
H X X X X In high-impedance state None
L H L X X In high-impedan ce st ate None
LHHL↑In high-impedance state FIFO write
LHHH↑In high-impedance state Mail1 write
L L L L X Active, Mail2 register None
LLHL↑Active, Mail2 register None
L L L H X Active, Mail2 register None
LLHH↑Active, Mail2 register Mail2 read (set MBF2 HIGH)
Table 3. Port B Enable Function
CSB W/RB ENB MBB CLKB B0–35 Port Function
H X X X X In high-impedance state None
L L L X X In high-impedance state None
LLHL↑In high-impedance state None
LLHH↑In high-impedance state Mail2 write
L H L L X Active, FIFO output register None
LHHL↑Active, FIFO output register FIFO read
L H L H X Active, Mail1 register None
LHHH↑Active, Mail1 register Mail1 read (set MBF1 HIGH)
Note:
43. X register holds the offset for AE; Y register holds the offset for AF.
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Table 4. FIFO Flag Operation (CY Standard and FWFT Modes)
Number of Words in FIFO Memory[2, 4 4 , 4 5, 46, 4 7] Synchronized to CLKB Synchronized to CLKA
CY7C43643AV CY7C43663AV CY7C43683AV EF/OR AE AF FF/IR
0 0 0 L L H H
1 TO X 1 TO X 1 TO X H L H H
(X+1) to
[1024–(Y+1)] (X+1) to
[4096–(Y+1)] (X+1) to
[16384–(Y+1)] H H H H
(1024–Y) to 1023 (4096–Y) to 4095 (16384–Y) to
16383 H H L H
1024 4096 16384 H H L L
Table 5. Data Size for FIFO Long-Word Reads
Size Mode[48] Data Written to FIFO Data Read From FIFO
BM SIZE BE A27–35 A18–26 A9–17 A0–8B27–35 B18–26 B9–17 B0–8
LXXABCDABCD
Table 6. Data Size for Word Reads
Size Mode[48] Data Written to FIFO Read No. Data Read From FIFO
BM SIZE BE A27–35 A18–26 A9–17 A0–8B9–17 B0–8
HLHABCD1AB
2CD
HLLABCD1CD
2AB
Table 7. Data Size for Byte Reads from FIFO
Size Mode[48] Data Written to FIFO Read No. Data Read From
FIFO
BM SIZE BE A27–35 A18–26 A9–17 A0–8B0–8
HHHABCD1 A
2B
3C
4D
HHLABCD1 D
2C
3B
4A
Notes:
44. X is the Almost Empty offset for FIFO used by AE. Y is the Almost Full offset for FIFO used by AF. Both X and Y are selected during a FIFO reset or Port A
programming.
45. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
46. Data in the output register does not count as a “word in FIFO memory”. Since in FWFT Mode, the first word written to an empty FIFO goes unrequested to
the output register (no read operation necessary), it is not included in the FIFO memory count.
47. The OR and IR functions are active during FWFT mode; the EF and FF functions are active in CY Standard Mode.
48. BE is selected at Master Reset; BM and SIZE must be static throughout device operation.
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Document #: 38-06024 Rev. ** Page 27 of 29
3.3V 1K x36 Unidirectional Synchronous FIFO w/ Bus Matching
Speed
(ns) Ordering Code Package
Name Package
Type Operating
Range
7CY7C43643AV–7AC A128 128-Lead Thin Qu ad Flat Packa ge Commercial
10 CY7C43643AV–10AC A128 128-L ea d Thin Qu ad Flat Packa ge Commercial
15 CY7C43643AV–15AC A128 128-L ea d Thin Qu ad Flat Packa ge Commercial
3.3V 4K x36 Unidirectional Synchronous FIFO w/ Bus Matching
Speed
(ns) Ordering Code Package
Name Package
Type Operating
Range
7 CY7C43663AV–7AC A128 128-Lead Thin Quad Flat Package Commercial
10 CY7C43663AV–10AC A128 128-Lead Thin Quad Flat Package Commercial
15 CY7C43663AV–15AC A128 128-Lead Thin Quad Flat Package Commercial
3.3V 16K x36 Unidirectional Synchronous FIFO w/ Bus Matching
Speed
(ns) O rdering Code Package
Name Package
Type Operating
Range
7 CY7C43683AV–7AC A128 128-Lead Thin Quad Flat Package Commercial
10 CY7C43683AV–10AC A128 128-Lead Thin Quad Flat Package Commercial
15 CY7C43683AV–15AC A128 128-Lead Thin Quad Flat Package Commercial
15 CY7C43683AV–15AI A128 128-Lead Thin Quad Flat Package Industrial
Shaded areas contain advance information.
PRELIMINARY
CY7C43643AV
CY7C43663AV
CY7C43683AV
Document #: 38-06024 Rev. ** Page 28 of 29
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry emb odied in a Cypress Semiconductor product. Nor does it convey or imply any license under paten t or other rights. Cypress Se miconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconducto r products in life-support systems application implies that the manu factur er assume s all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
Package Diagram
128-Lead Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A128
51-85101-A
CY7C43643AV
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PRELIMINARY
Document #: 38-06024 Rev. ** Page 29 of 29
Document Title: CY7C43643AV, CY7C43663AV, CY7C43683AV, 3.3V 1K/4K/16K X 36 Unidirectional
Document Number: 38-06024
REV. ECN NO. Issue Date Orig. of Change Description of Change
** 107253 5/23/01 SZV Change from Spec 38-00776 to 38-06024
