© Semiconductor Components Industries, LLC, 2015
November, 2017 − Rev. 5
1Publication Order Number:
ESD8006/D
ESD8006
ESD Protection Diode
Low Capacitance Array for High Speed
Data Lines
The ESD8006 is specifically designed to protect USB 3.0 and
Thunderbolt interfaces from ESD. Ultra−low capacitance and low
ESD clamping voltage make this device an ideal solution for
protecting voltage sensitive high speed data lines. The flow−through
style package allows for easy PCB layout and matched trace lengths
necessary to maintain consistent impedance between high speed
differential lines.
Features
•Low Capacitance (0.25 pF Max, I/O to GND)
•Protection for the Following IEC Standards:
IEC 61000−4−2 (Level 4)
•Low ESD Clamping Voltage
•SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
•USB 3.0/3.1
•Thunderbolt
•Display Port
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating Symbol Value Unit
Operating Junction Temperature Range TJ−55 to +125 °C
Storage Temperature Range Tstg −55 to +150 °C
Lead Solder Temperature −
Maximum (10 Seconds)
TL260 °C
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
ESD
ESD
±15
±15
kV
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
See Application Note AND8308/D for further description of
survivability specs.
MARKING
DIAGRAM
Device Package Shipping
ORDERING INFORMATION
www.onsemi.com
ESD8006MUTAG UDFN8
(Pb−Free)
3000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
1
6T = Specific Device Code
M = Date Code
G= Pb−Free Package
6TMG
G
(Note: Microdot may be in either location)
PIN CONFIGURATION
UDFN8
CASE 517CB
I/O I/O GND I/O I/O I/O
GND GND
GND I/O
12345678
910
SZESD8006MUTAG UDFN8
(Pb−Free)
3000 / Tape &
Reel
ESD8006
www.onsemi.com
3
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise noted)
Symbol Parameter
VRWM Working Peak Voltage
IRMaximum Reverse Leakage Current @ VRWM
VBR Breakdown Voltage @ IT
ITTest Current
VHOLD Holding Reverse Voltage
IHOLD Holding Reverse Current
RDYN Dynamic Resistance
IPP Maximum Peak Pulse Current
VCClamping Voltage @ IPP
VC = VHOLD + (IPP * RDYN)
I
V
VCVRWM
VHOLD
VBR
RDYN
VC
IR
IT
IHOLD
−IPP
RDYN
IPP
VC = VHOLD + (IPP * RDYN)
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified)
Parameter Symbol Conditions Min Typ Max Unit
Reverse Working Voltage VRWM I/O Pin to GND 3.3 V
Breakdown Voltage VBR IT = 1 mA, I/O Pin to GND 5.5 7.0 V
Reverse Leakage Current IRVRWM = 3.3 V, I/O Pin to GND 1.0 mA
Holding Reverse Voltage VHOLD I/O Pin to GND 1.19 V
Holding Reverse Current IHOLD I/O Pin to GND 25 mA
Clamping Voltage (Note 1) VCIEC61000−4−2, ±8 KV Contact See Figures 2 and 3 V
Clamping Voltage
TLP (Note 2)
See Figures 6 through 9
VCIPP = 8 A
IPP = −8 A
IEC 61000−4−2 Level 2 equivalent
(±4 kV Contact, ±4 kV Air)
4.9
−5.0
V
IPP = 16 A
IPP = −16 A
IEC 61000−4−2 Level 4 equivalent
(±8 kV Contact, ±15 kV Air)
8.4
−9.5
Dynamic Resistance RDYN I/O Pin to GND
GND to I/O Pin
0.44
0.49
W
Junction Capacitance CJVR = 0 V, f = 1 MHz between I/O Pins and GND
VR = 0 V, f = 2.5 GHz between I/O Pins and GND
VR = 0 V, f = 5.0 GHz between I/O Pins and GND
VR = 0 V, f = 1 MHz, between I/O Pins
0.32
0.25
0.25
0.16
pF
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. For test procedure see Figures 4 and 5 and application note AND8307/D.
2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.
ESD8006
www.onsemi.com
4
Figure 2. IEC61000−4−2 +8 kV Contact ESD
Clamping Voltage
Figure 3. IEC61000−4−2 −8 kV Contact
Clamping Voltage
TIME (ns) TIME (ns)
VOLTAGE (V)
VOLTAGE (V)
IEC 61000−4−2 Spec.
Level
Test Volt-
age (kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1 2 7.5 4 2
2 4 15 8 4
3 6 22.5 12 6
4 8 30 16 8
Ipeak
90%
10%
IEC61000−4−2 Waveform
100%
I @ 30 ns
I @ 60 ns
tP = 0.7 ns to 1 ns
Figure 4. IEC61000−4−2 Spec
Figure 5. Diagram of ESD Clamping Voltage Test Setup
50 W
Cable
Device
Under
Test Oscilloscope
ESD Gun
50 W
The following is taken from Application Note
AND8307/D − Characterization of ESD Clamping
Performance.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D and AND8308/D.
ESD8006
www.onsemi.com
5
Figure 6. Positive TLP I−V Curve Figure 7. Negative TLP I−V Curve
TLP CURRENT (A)
VC, VOLTAGE (V)
EQUIVALENT VIEC (kV)
TLP CURRENT (A)
VC, VOLTAGE (V)
EQUIVALENT VIEC (kV)
NOTE: TLP parameter: Z0 = 50 W, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns. VIEC is the equivalent voltage
stress level calculated at the secondary peak of the IEC 61000−4−2 waveform at t = 30 ns with 2 A/kV. See TLP description
below for more information.
VC = VHOLD + (IPP * RDYN)
Transmission Line Pulse (TLP) Measurement
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 8. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 9 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels. For more information
on TLP measurements and how to interpret them please
refer to AND9007/D.
Figure 8. Simplified Schematic of a Typical TLP
System
DUT
LS
÷
Oscilloscope
Attenuator
10 MW
VC
VM
IM
50 W Coax
Cable
50 W Coax
Cable
Figure 9. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
ESD8006
www.onsemi.com
6
Figure 10. IV Characteristics Figure 11. CV Characteristics
IO−GND
Figure 12. RF Insertion Loss Figure 13. Capacitance over Frequency
dB (ESD8006..Sdd21)
C_ESD8006_pF
TABLE 1. RF Insertion Loss: Application Description
Interface
Data Rate
(Gb/s)
Fundamental Frequency
(GHz)
3rd Harmonic Frequency
(GHz)
ESD8006 Insertion Loss
(dB)
USB 3.0 5.0 2.5 (m1) 7.5 (m3) m1 = 0.098
m2 = 0.240
m3 = 0.479
m4 = 3.732
Thunderbolt,
USB 3.1
10 5.0 (m2) 15 (m4)
ESD8006
www.onsemi.com
7
With ESD8006Without ESD8006
Figure 14. USB 3.0 Eye Diagram with and without ESD8006. 5 Gb/s
With ESD8006
Without ESD8006
Figure 15. Thunderbolt and USB 3.1 Eye Diagram with and without ESD8006. 10 Gb/s
See application note AND9075/D for further description of eye diagram testing methodology.
ESD8006
www.onsemi.com
10
PCB Layout Guidelines
Steps must be taken for proper placement and signal trace
routing of the ESD protection device in order to ensure the
maximum ESD survivability and signal integrity for the
application. Such steps are listed below.
•Place the ESD protection device as close as possible to
the I/O connector to reduce the ESD path to ground and
improve the protection performance.
♦In USB 3.0 applications, the ESD protection device
should be placed between the AC coupling
capacitors and the I/O connector on the TX
differential lanes as shown in Figure 18. In this
configuration, no DC current can flow through the
ESD protection device preventing any potential
latch-up condition. For more information on latchup
considerations, see below description on Page 11.
•Make sure to use differential design methodology and
impedance matching of all high speed signal traces.
♦Use curved traces when possible to avoid unwanted
reflections.
♦Keep the trace lengths equal between the positive
and negative lines of the differential data lanes to
avoid common mode noise generation and
impedance mismatch.
♦Place grounds between high speed pairs and keep as
much distance between pairs as possible to reduce
crosstalk.
Figure 18. USB 3.0 Connection Diagram
Figure 19. Thunderbolt Recommended PCB Layout
ESD8006
www.onsemi.com
11
Latch-Up Considerations
ON Semiconductor’s 8000 series of ESD protection
devices utilize a snap-back, SCR type structure. By using
this technology, the potential for a latch-up condition was
taken into account by performing load line analysis of
common high speed serial interfaces. Example load lines for
latch-up free applications and applications with the potential
for latch-up are shown below with a generic IV
characteristic of a snapback, SCR type structured device
overlaid on each. In the latch-up free load line case, the IV
characteristic of the snapback protection device intersects
the load-line in one unique point (VOP
, IOP). This is the only
stable operating point of the circuit and the system is
therefore latch-up free. Please note that for USB 3.0
applications, ESD8006 latch-up free considerations are
explained in more detail in the above PCB layout guidelines.
In the non-latch up free load line case, the IV characteristic
of the snapback protection device intersects the load-line in
two points (VOPA, IOPA) and (VOPB, IOPB). Therefore in this
case, the potential for latch-up exists if the system settles at
(VOPB, IOPB) after a transient. Because of this, ESD8006
should not be used for HDMI applications – ESD8104 or
ESD8040 have been designed to be acceptable for HDMI
applications without latch-up. Please refer to Application
Note AND9116/D for a more in-depth explanation of
latch-up considerations using ESD8000 series devices.
Figure 20. Example Load Lines for Latch-up Free Applications and Applications with the Potential for Latch-up
I
V
VDD
ISSMAX
IOP
VOP
I
V
VDD
ISSMAX
IOPA
VOPA
IOPB
VOPB
ESD8006 Latch−up free:
USB 2.0 LS/FS, USB 2.0 HS, USB 3.0/3.1 SS,
DisplayPort
ESD8006 Potential Latch−up:
HDMI 2.0/1.4/1.3a TMDS
Table 1. SUMMARY OF SCR REQUIREMENTS FOR LATCH-UP FREE APPLICATIONS
Application
VBR (min)
(V)
IH (min)
(mA)
VH (min)
(V)
ON Semiconductor ESD8000 Series
Recommended PN
HDMI 2.0/1.4/1.3a TMDS 3.465 54.78 1.0 ESD8104, ESD8040
USB 2.0 LS/FS 3.301 1.76 1.0 ESD8004
USB 2.0 HS 0.482 N/A 1.0 ESD8004
USB 3.0/3.1 SS 2.800 N/A 1.0 ESD8004, ESD8006
DisplayPort 3.600 25.00 1.0 ESD8004, ESD8006
ESD8006
www.onsemi.com
12
PACKAGE DIMENSIONS
ÉÉ
ÉÉ
UDFN8, 3.3 x 1.0, 0.4P
CASE 517CB
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.20 MM FROM TERMINAL TIP.
DIM MIN MAX
MILLIMETERS
A0.45 0.55
A1 0.00 0.05
A3 0.13 REF
b0.15 0.25
D3.30 BSC
D2 0.25 0.45
E1.00 BSC
E2 0.45 0.55
e0.40 BSC
L0.20 0.30
0.10 C
D
E
B
A
2X
2X
A
A1
(A3)
0.10 C
PIN ONE
REFERENCE
0.05 C
0.05 C
CSEATING
PLANE
D2
E2
BOTTOM VIEW
b
e
8X
L
7X
L2
SIDE VIEW
TOP VIEW
NOTE 3
1
2X
8
2X
2X
8X
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
DETAIL A
L1 −−− 0.15
DIMENSION: MILLIMETERS
RECOMMENDED
L1
DETAIL A
L
ALTERNATE
CONSTRUCTIONS
L
ÉÉÉ
ÉÉÉ
ÇÇÇ
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
CONSTRUCTION
DETAIL B
e/2
0.65
1.20
0.25
1.66
0.40
PITCH 0.40
L2 0.30 0.40
A
M
0.10 BC
M
0.05 C
7X
2X
0.50
0.50
G2 1.19 BSC
A
M
0.10 BC
M
0.05 C
G2
PUBLICATION ORDERING INFORMATION
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ESD8006/D
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
◊
