0.1 GHz to 3 GHz,1 dB LSB, 5-Bit,
GaAs Digital Attenuator
Data Sheet HMC470A
Rev. A Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2017 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Attenuation range: 1 dB LSB steps to 31 dB
Insertion loss: 1.7 dB typical at 3 GHz
Excellent attenuation accuracy: 0.3 dB typical
High Input linearity
0.1dB compression (P0.1dB): 27 dBm typical
Third-order intercept (IP3): 48 dBm typical
High power handling: 27 dBm
Low phase shift: 27° at 3 GHz
Single-supply operation: 3 V to 5 V
CMOS-/TTL-compatible parallel control
16-lead, 3 mm × 3 mm LFCSP package
APPLICATIONS
Cellular infrastructure
Microwave radios and very small aperture terminals (VSATs)
Test equipment and sensors
IF and RF designs
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
GENERAL DESCRIPTION
The HMC470A is a 5-bit digital attenuator with a 31 dB
attenuation control range in 1 dB steps.
The HMC470A offers excellent attenuation accuracy and high
input linearity over the specified frequency range from 100 MHz to
3 GHz. However, this digital attenuator features ACG pins for
external ac grounding capacitors to extend the operation below
100 MHz.
The HMC470A operates with a single positive supply voltage
from 3 V to 5 V and provides CMOS-/TTL-compatible parallel
control interface by incorporating an on-chip driver. The
HMC470A comes in a RoHS compliant, compact, 3 mm × 3 mm
LFCSP package.
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
VDD
RF1
NIC
ACG1
V1
V2
V3
V4
V5
RF2
NIC
ACG6
ACG2
ACG3
ACG4
ACG5
HMC470A
PACKAGE
BASE
GND
1dB
2dB
4dB
8dB
16dB
14806-001
HMC470A Data Sheet
Rev. A | Page 2 of 11
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution .................................................................................. 4
Pin Configuration and Function Descriptions ............................. 5
Interface Schematics..................................................................... 5
Typical Performance Characteristics ............................................. 6
Insertion Loss, Return Loss, State Error, Step Error, and
Relative Phase ................................................................................6
Input Power Compression and Third-Order Intercept ............8
Theory of Operation .........................................................................9
Power Supply ..................................................................................9
RF Input and Output ....................................................................9
ACGx Pins ......................................................................................9
Applications Information .............................................................. 10
Evaluation Board ........................................................................ 10
Outline Dimensions ....................................................................... 11
Ordering Guide .......................................................................... 11
REVISION HISTORY
9/2017—Rev. 01.0716 to Rev. A
This Hittite Microwave Products data sheet has been reformatted to
meet the styles and standards of Analog Devices, Inc.
Change to Product Title ................................................................... 1
Updated Outline Dimensions ....................................................... 11
Data Sheet HMC470A
Rev. A | Page 3 of 11
SPECIFICATIONS
VDD = 3 V t o 5 V, VCTL = 0 V or VDD, TCASE = 25°C, 50 Ω system, unless otherwise noted.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
FREQUENCY RANGE 0.1 3.0 GHz
INSERTION LOSS 0.1 GHz to 1.5 GHz 1.3 1.6 dB
1.5 GHz to 2.3 GHz 1.5 1.8 dB
2.3 GHz to 3.0 GHz 1.7 2.0 dB
ATTENUATION
Range Between minimum and
maximum attenuation states,
0.1 GHz to 3.0 GHz
31 dB
Step Size Between any successive
attenuation states, 0.1 GHz to
3.0 GHz
1 dB
Step Error Between any successive
attenuation states, 0.1 GHz to
33 GHz
<±0.2 dB
State Error Referenced to insertion loss
state
All attenuation states, 0.1 GHz to
2.3 GHz
−(0.3 + 2% of
attenuation
state)
+(0.3 + 2% of
attenuation
state)
dB
1 dB to 15 dB attenuation states,
2.3 GHz to 3.0 GHz
−(0.3 + 3% of
attenuation
state)
+(0.3 + 3% of
attenuation
state)
dB
16 dB to 31 dB attenuation
states, 2.3 GHz to 3.0 GHz
−(0.3 + 6% of
attenuation
state)
+(0.3 + 6% of
attenuation
state)
dB
RETURN LOSS RF1 and RF2 pins, all attenuation
states, 0.1 GHz to 3.0 GHz
14 dB
RELATIVE PHASE Between minimum and
maximum attenuation states
0.1 GHz to 1.5 GHz 12 Degrees
1.5 GHz to 3.0 GHz 27 Degrees
SWITCHING CHARACTERISTICS
Between all attenuation states
Rise and Fall Time tRISE, tFAL L 10% to 90% of RF output 50 ns
On and Off Time tON, tOFF 50% VCTL to 90% of RF output 70 ns
INPUT LINEARITY1 All attenuation states, 250 MHz
to 3.0 GHz
0.1 dB Compression P0.1dB VDD = 3 V 25 dBm
VDD = 5 V 27 dBm
Third-Order Intercept IP3 10 dBm per tone, 1 MHz spacing 50 dBm
SUPPLY CURRENT IDD 1.7 mA
DIGITAL CONTROL INPUTS V1 to V5 pins
Voltage
Low VINL 0 0.8 V
High VINH 2.0 VDD V
Current
Low
I
INL
1
µA
High IINH 40 µA
1 Input linearity performance degrades at frequencies less than 250 MHz; see Figure 16 to Figure 19.
HMC470A Data Sheet
Rev. A | Page 4 of 11
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage 7 V
Digital Control Input Voltage
−1 V to V
DD
+1 V
RF Input Power1 (All Attenuation States,
f = 250 MHz to 3 GHz, TCASE = 85°C)
VDD = 3 V 25 dBm
VDD = 5 V 27 dBm
Continuous Power Dissipation, PDISS
(TCASE = 85°C)
0.5 W
Temperature
Junction, TJ 150°C
Storage −65°C to +150°C
Reflow2 ((Moisture Sensitivity Level 3
(MSL3) Rating)
260°C
ESD Sensitivity
Human Body Model (HBM) 250 V (Class 1A)
1 For power derating at frequencies less than 250 MHz, see Figure 2.
2 See the Ordering Guide for more information.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating can be applied at any one time.
Figure 2. Power Derating at Frequencies Less Than 250 MHz
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJC is the junction to case thermal resistance.
Table 3. Thermal Resistance
Package Type θJC Unit
HCP-16-11 1302 °C/W
1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board with five thermal vias. See JEDEC JESD51.
2 The device is set to maximum attenuation state.
ESD CAUTION
1
0
–1
–2
–3
–4
–5
0.1 1
POWER DERATING (dB)
FREQUENCY (GHz)
14806-002
Data Sheet HMC470A
Rev. A | Page 5 of 11
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD Power Supply.
2 RF1 This pin can be used as RF input or output of attenuator. This pin is dc-coupled to VDD and ac matched to
50 Ω. An external dc blocking capacitor is required. Select the capacitor value for the lowest frequency of
operation.
3, 10 NIC Not Internally Connected. These pins are not internally connected; however, all data shown herein was
measured when these pins connected to RF/DC ground of evaluation board.
4 to 9 ACG1 to ACG6 AC Grounding Capacitor Pins. These pins can be left no connected when operating above 700 MHz. For
frequencies less than 700 MHz, connect capacitors larger than 100 pF as close to the ACGx pins as
possible. Select the capacitor value for the lowest frequency of operation.
11 RF2 This pin can be used as RF input or output of attenuator. This pin is dc-coupled to VDD V and ac matched
to 50 Ω. An external dc blocking capacitor is required. Select the capacitor value for the lowest frequency
of operation.
12 to 16 V1 to V5 Parallel Control Voltage Inputs. These pins select the required attenuation (see Table 5).
EPAD Exposed Pad. The exposed pad must be connected to ground for proper operation.
INTERFACE SCHEMATICS
Figure 4. RF1, RF2 Interface Schematic Figure 5. Digital Control Input Interface
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
VDD
RF1
NIC
ACG1
V1
V2
V3
V4
V5
RF2
NIC
ACG6
ACG2
ACG3
ACG4
ACG5
HMC470A
TOP VIEW
(Not to Scale)
NOTES
1. NIC = THESE PINS ARE NOT INTERNALLY CONNECTED;
HOWEVER, ALL DATA SHOWN HEREIN WAS
MEASURED WHEN THESE PINS CONNECTED TO RF/DC
GROUND OF EVALUATION BOARD.
2. EXPOSED PAD. THE EXPOSED PAD MUST BE
CONNECTED TO GROUND FOR PROPER OPERATION.
14806-003
RF1,
RF2
14806-004
V
DD
VDD
1.5kΩ
V1 TO V5
50kΩ
14806-005
HMC470A Data Sheet
Rev. A | Page 6 of 11
TYPICAL PERFORMANCE CHARACTERISTICS
INSERTION LOSS, RETURN LOSS, STATE ERROR, STEP ERROR, AND RELATIVE PHASE
Figure 6. Insertion Loss vs. Frequency over Temperature
Figure 7. RF1 Return Loss vs. Frequency over Major Attenuation States
Figure 8. State Error vs. Attenuation State over Frequency
Figure 9. Normalized Attenuation vs. Frequency over Major Attenuation
States
Figure 10. RF2 Return Loss vs. Frequency over Major Attenuation States
Figure 11. State Error vs. Frequency over Major Attenuation States
0
–3.0
–2.5
–1.5
–0.5
–2.0
–1.0
01234
INSERTION LOSS (dB)
FREQUENCY (GHz)
+85°C
+25°C
–40°C
14806-006
0
–40
01234
RF1 RETURN LOSS (dB)
FREQUENCY (GHz)
–35
–30
–25
–20
–15
–10
–5
0dB
1dB
2dB
4dB
8dB
16dB
31dB
14806-007
04812 32
ATTENUATION STATE (dB)
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
STATE ERROR (dB)
16 20 24 28
0.1GHz
0.5GHz
1.0GHz
2.0GHz
3.0GHz
14806-008
0
–35
–30
–25
–15
–5
–20
–10
NORMALIZED ATTENUATION (dB)
01234
FREQUENCY (GHz)
0dB
1dB
2dB
4dB
8dB
16dB
31dB
14806-009
0
–40
01234
RF2 RETURN LOSS (dB)
FREQUENCY (GHz)
–35
–30
–25
–20
–15
–10
–5
0dB
1dB
2dB
4dB
8dB
16dB
31dB
14806-010
2.0
–2.0
STATE ERROR (dB)
01234
FREQUENCY (GHz)
0dB
1dB
2dB
4dB
8dB
16dB
31dB
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
14806-011
Data Sheet HMC470A
Rev. A | Page 7 of 11
Figure 12. Step Error vs. Attenuation State over Frequency
Figure 13. Relative Phase vs. Attenuation State over Frequency
Figure 14. Step Error vs. Frequency over Major Attenuation States
Figure 15. Relative Phase vs. Frequency over Major Attenuation States
032
ATTENUATION STATE (dB)
1.0
–1.0
STEP ERROR (dB)
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
4 8 12 16 20 24 28
0.1GHz
0.5GHz
1.0GHz
2.0GHz
3.0GHz
14806-012
40
–20
0 4 32
RELATIVE PHASE (Degrees)
ATTENUATION STATE (dB)
–10
0
10
20
30
812 16 20 24 28
0.1GHz
0.5GHz
1.0GHz
2.0GHz
3.0GHz
14806-013
1.0
–1.0
STEP ERROR (dB)
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
01234
FREQUENCY (GHz)
0dB
1dB
2dB
4dB
8dB
16dB
31dB
14806-014
40
–20
–10
10
30
0
20
01234
RELATIVE PHASE (Degrees)
FREQUENCY (GHz)
0dB
1dB
2dB
4dB
8dB
16dB
31dB
14806-015
HMC470A Data Sheet
Rev. A | Page 8 of 11
INPUT POWER COMPRESSION AND THIRD-ORDER INTERCEPT
Figure 16. Input P0.1dB vs. Frequency at Minimum Attenuation State over
Temperature, VDD = 5 V
Figure 17. Input IP3 vs. Frequency at Minimum Attenuation State over
Temperature, VDD = 5 V
Figure 18. Input P0.1dB vs. Frequency at Minimum Attenuation State over
Temperature, VDD = 3 V
Figure 19. Input IP3 vs. Frequency at Minimum Attenuation State over
Temperature, VDD = 3 V
36
20
01234
INPUT P0.1dB (dBm)
FREQUENCY (GHz)
24
28
32
+85°C
+25°C
–40°C
14806-016
60
55
50
45
40
01234
INPUT IP3 (dBm)
FREQUENCY (GHz)
+85°C
+25°C
–40°C
14806-017
36
20
01234
INPUT P0.1dB (dBm)
FREQUENCY (GHz)
24
28
32
+85°C
+25°C
–40°C
14806-018
60
55
50
45
40
01234
INPUT IP3 (dBm)
FREQUENCY (GHz)
+85°C
+25°C
–40°C
14806-019
Data Sheet HMC470A
Rev. A | Page 9 of 11
THEORY OF OPERATION
The HMC470A incorporates a 5-bit attenuator that offers an
attenuation range of 31 dB in 1 dB steps and a driver for
CMOS-/TTL-compatible parallel control of the 5-bit attenuator.
See Table 5 for the truth table.
Table 5. P4 to P0 Truth Table
Digital Control Input1 Attenuation
V1 V2 V3 V4 V5 State (dB)
High High High High High 0 dB (reference)
High High High High Low 1 dB
High High High Low High 2 dB
High High Low High High 4 dB
High
Low
High
High
High
8 dB
Low High High High High 16 dB
Low Low Low Low Low 31 dB
1 Any combination of the control voltage input states shown in Table 5
provides an attenuation equal to the sum of the bits selected.
POWER SUPPLY
The HMC470A requires a single supply voltage applied to the
VDD pin, and CMOS/TTL-compatible control voltages applied
to the V1 to V5 pins. The ideal power-up sequence is as follows:
1. Connect the ground reference.
2. Power up VDD and VSS. The relative order is not
important.
3. Apply the digital control inputs. The relative order of the
digital control inputs is not important.
4. Apply an RF input signal to RF1 or RF2.
The power-down sequence is the reverse of the power-up
sequence.
RF INPUT AND OUTPUT
The HMC470A is bidirectional. The RF1 and RF2 pins are
internally matched to 50 Ω; therefore, they do not require
external matching components. These pins are dc-coupled to
VDD; therefore, dc blocking capacitors are required on RF lines.
ACGx PINS
The HMC470A is a positive bias GaAs attenuator so it requires
floating capacitors between the attenuator bits and ground. The
HMC470A uses on-chip floating capacitors that are sufficient
for operation at frequencies greater than 700 MHz. The HMC470A
also features the ACGx pins to externally connect larger floating
capacitors. Select the value of external floating capacitors based
on the minimum operating frequency, whereas the ACGx pins
can be left open when operating above 700 MHz.
HMC470A Data Sheet
Rev. A | Page 10 of 11
APPLICATIONS INFORMATION
EVALUATION BOARD
The HMC470A uses a 4-layer evaluation board. The copper
thickness is 0.5 oz (0.7 mil) on each layer. The top dielectric
material is 10 mil Rogers RO4350 for optimal high frequency
performance, whereas the middle and bottom dielectric materials
are FR-4 type materials to achieve an overall board thickness of
62 mil. RF and DC traces are routed on the top copper layer.
The bottom and middle layers are grounded planes that provide
a solid ground for the RF transmission lines. The RF transmission
lines are designed using a coplanar waveguide (CPWG) model
with a width of 16 mil and ground spacing of 13 mil to have a
characteristic impedance of 50 Ω. For enhanced RF and thermal
grounding, as many plated through vias as possible are arranged
around transmission lines and under the exposed pad of the
package.
Figure 20 shows the top view of the populated HMC470A
Evaluation board, available from Analog Devices, Inc., upon
request (see the Ordering Guide).
Figure 20. Populated Evaluation Board --- Top View
The evaluation board is grounded from the 2 × 6-pin header, J3.
The supply and digital control pins are also connected to the J3.
A 1 nF decoupling capacitor is placed on the supply trace to
filter high frequency noise.
The RF1 and RF2 ports are connected through 50 Ω transmission
lines to the SMA connectors, J1 and J2, respectively. The RF1
and RF2 ports are ac-coupled with external 330 pF capacitors. A
thru calibration line connects J9 and J10; this transmission line
is used to measure the loss of the PCB over the environmental
conditions being evaluated.
The ACG pins are connected to ground through 330 pF
capacitors.
Figure 21 and Table 6 show the evaluation board schematic and
bill of materials, respectively.
Figure 21. Evaluation Board Schematic
Table 6. List of Materials for EVAL-HMC470A
Item Description
J1, J2 PCB mount, SMA connector
J3, 2 × 6-pin header
J4, J5 PCB mount, 2.9mm RF connector, do not insert
C1, C2 1 nF capacitor, 0402 package
C3 1 nF capacitor, 0603package
C4 to C7 330 pF capacitor, 0402 package
C8, C9 1 nF capacitor, 0402 package, do not insert
U1 HMC470A Digital Attenuator
PCB 106978-4 Evaluation PCB
14806-020
VDD
RF1
NIC
ACG1
V1
V2
V3
V4
V5
RF2
NIC
ACG6
ACG2
ACG3
ACG4
ACG5
U1
HMC470A
C3
1nF
C1
1nF
J1
C2
1nF J2
J3
C8
1nF
J4
C9
1nF J6
C4
330pF C5
330pF C6
330pF
C7
330pF
THRU CAL
14806-021
Data Sheet HMC470A
Rev. A | Page 11 of 11
OUTLINE DIMENSIONS
Figure 22. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.85 mm Package Height
(HCP-16-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature
Range
MSL
Rating2 Package Description
Package
Option Branding3
HMC470ALP3E −40°C to +85°C MSL3 16-Lead Lead Frame Chip Scale Package [LFCSP] HCP-16-1
XXXX
H470A
HMC470ALP3ETR −40°C to +85°C MSL3 16-Lead Lead Frame Chip Scale Package [LFCSP] HCP-16-1
XXXX
H470A
EV1HMC470ALP3 Evaluation Board
1 All models are RoHS Compliant.
2 See the Absolute Maximum Ratings section.
3 XXXX is the 4-digit lot number.
3.10
3.00 SQ
2.90
0.30
0.25
0.20
1.95
1.70 SQ
1.50
1
0.50
BSC
BOTT OM VIEWTOP VIEW
16
58
9
12
13
4
EXPOSED
PAD
0.45
0.40
0.35
0.05 M AX
0.02 NOM
0.20 RE F
0.20 MI N
COPLANARITY
0.08
PIN 1
INDICATOR
0.90
0.85
0.80
03-15-2017-B
PKG-004863
COM PL IANT W I TH JEDE C ST ANDARDS M O - 220-VEED-4.
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE P IN CO NFI GURAT IO N AND
FUNCTION DES CRI P T I ONS
SECTION OF THIS DATA SHEET.
SEATING
PLANE
PIN 1
INDICATOR AREA OPTIONS
(SEE DETAIL A)
DETAIL A
(J EDEC 95)
©2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14806-0-9/17(A)
