eGaN® FET DATASHEET
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EPC2014C
EPC2014C – Enhancement Mode Power Transistor
VDS , 40 V
RDS(on) , 16 mΩ
ID , 10 A
EPC2014C eGaN® FETs are supplied only in
passivated die form with solder bumps
Applications
• High Frequency DC-DC conversion
• Class-D Audio
• Wireless Power Transfer
• Lidar
Benets
• Ultra High Eciency
• Ultra Low RDS(on)
• Ultra Low QG
• Ultra Small Footprint
EFFICIENT POWER CONVERSION
HAL
www.epc-co.com/epc/Products/eGaNFETs/EPC2014C.aspx
G
D
S
Maximum Ratings
PARAMETER VALUE UNIT
VDS
Drain-to-Source Voltage (Continuous) 40 V
Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C) 48
ID
Continuous (TA = 25˚C, RθJA = 43°C/W) 10 A
Pulsed (25°C, TPULSE = 300 µs) 60
VGS
Gate-to-Source Voltage 6V
Gate-to-Source Voltage -4
TJOperating Temperature -40 to 150 °C
TSTG Storage Temperature -40 to 150
Thermal Characteristics
PARAMETER TYP UNIT
RθJC
Thermal Resistance, Junction to Case
3.6
°C/W RθJB
Thermal Resistance, Junction to Board
9.3
RθJA
Thermal Resistance, Junction to Ambient (Note 1)
80
Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See http://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.
All measurements were done with substrate connected to source.
Static Characteristics (TJ = 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 125 μA 40 V
IDSS Drain-Source Leakage VGS = 0 V, VDS = 32 V 50 100 µA
IGSS
Gate-to-Source Forward Leakage VGS = 5 V 0.4 2 mA
Gate-to-Source Reverse Leakage VGS = -4 V 50 100 µA
VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 2 mA 0.8 1.4 2.5 V
RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 10 A 12 16 mΩ
VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.8 V
Gallium Nitride is grown on Silicon Wafers and processed using standard CMOS equipment
leveraging the infrastructure that has been developed over the last 60 years. GaN’s exceptionally
high electron mobility and low temperature coecient allows very low RDS(on), while its lateral
device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end
result is a device that can handle tasks where very high switching frequency, and low on-time are
benecial as well as those where on-state losses dominate.
eGaN® FET DATASHEET
EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 2
EPC2014C
60
45
30
15
00 0.5 1.0 1.5 2.0 2.5 3.0
ID – Drain Current (A)
Figure 1: Typical Output Characteristics
VDS – Drain-to-Source Voltage (V)
VGS = 5 V
VGS = 4 V
VGS = 3 V
VGS = 2 V
RDS(on) – Drain-to-Source Resistance (mΩ)
VGS – Gate-to-Source Voltage (V)
40
50
30
20
10
02.0 2.5 3.0 3.5 4.0 4.5 5.0
Figure 3: RDS(on) vs. VGS for Various Drain Currents
ID = 5 A
ID = 10 A
ID = 15 A
ID = 30 A
ID – Drain Current (A)
VGS – Gate-to-Source Voltage (V)
60
45
30
15
1.00.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Figure 2: Transfer Characteristics
25˚C
125˚C
VDS = 3 V
0
50
40
30
20
10
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0
Figure 4: RDS(on) vs. VGS for Various Temperatures
25˚C
125˚C
ID = 10 A
RDS(on) – Drain-to-Source Resistance (mΩ)
VGS – Gate-to-Source Voltage (V)
Dynamic Characteristics (TJ = 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CISS
Input Capacitance
VDS = 20 V, VGS = 0 V
220 300
pFCRSS
Reverse Transfer Capacitance
6.5 9.5
COSS
Output Capacitance
150 210
RG
Gate Resistance
0.4 Ω
QG
Total Gate Charge
VDS = 20 V, VGS = 5 V, ID = 10 A 2 2.5
nC
QGS
Gate-to-Source Charge
VDS = 20 V, ID = 10 A
0.7
QGD
Gate-to-Drain Charge
0.3 0.5
QG(TH)
Gate Charge at Threshold
0.5
QOSS
Output Charge
VDS = 20 V, VGS = 0 V 4 6
QRR
Source-Drain Recovery Charge
0
All measurements were done with substrate connected to source.
Note 2: COSS(ER) is a xed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS.
Note 3: COSS(TR) is a xed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS.
eGaN® FET DATASHEET
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EPC2014C
All measurements were done with substrate shortened to source.
Capacitance (pF)
100
10
00 5 10 15 20 25 30 35 40
Figure 5b: Capacitance
VDS – Drain-to-Source Voltage (V)
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
60
45
30
15
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
ISD – Source-to-Drain Current (A)
VSD – Source-to-Drain Voltage (V)
Figure 7: Reverse Drain-Source Characteristics
25˚C
125˚C
Figure 9: Normalized Threshold Voltage vs. Temperature
Normalized Threshold Voltage
1.4
1.3
1.2
1.0
1.1
0.9
0.8
0.7
0.6 0 25 50 75 100 125 150
TJ – Junction Temperature (°C)
ID = 2 mA
Capacitance (pF)
300
250
200
150
100
50
00 5 10 15 20 25 30 35 40
Figure 5a: Capacitance
VDS – Drain-to-Source Voltage (V)
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
5
4
3
2
1
0
0 0.5 1.0 1.5 2.0
Figure 6: Gate Charge
VGS – Gate-to-Source Voltage (V)
QG – Gate Charge (nC)
ID = 10 A
VDS = 20 V
Figure 8: Normalized On Resistance vs. Temperature
ID = 10 A
VGS = 5 V
Normalized On-State Resistance R
DS(on)
2
1.8
1.6
1.4
1.2
1.0
0.8 0 25 50 75 100 125 150
TJ – Junction Temperature (°C)
eGaN® FET DATASHEET
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EPC2014C
Figure 11: Transient Thermal Response Curves
Junction-to-Board
tp, Rectangular Pulse Duration, seconds
Duty Cycle:
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJB x RθJB + TB
PDM
t1
t2
0.5
0.1
0.05
0.02
0.01
Single Pulse
ZθJB
, Normalized Thermal Impedance
10-4
10-5 10-3 10-2 10-1 1 10+1
1
0.1
0.01
0.001
Junction-to-Case
tp, Rectangular Pulse Duration, seconds
Duty Cycle:
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJC x RθJC + TC
PDM
t1
t2
0.5
0.2
0.1
0.05
0.02
0.01
Single Pulse
ZθJC
, Normalized Thermal Impedance
10-5
10-6 10-4 10-3 10-2 10-1 1
1
0.1
0.01
0.001
0.0001
IG – Gate Current (mA)
VGS – Gate-to-Source Voltage (V)
Figure 10: Gate Current
25˚C
125˚C
9
8
7
5
6
4
3
2
1
00 1 2 3 4 5 6
eGaN® FET DATASHEET
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EPC2014C
2014
YYYY
ZZZZ
Part
Number
Laser Markings
Part #
Marking Line 1
Lot_Date Code
Marking line 2
Lot_Date Code
Marking Line 3
EPC2014C 2014 YYYY ZZZZ
Die orientation dot
Gate Pad bump is
under this corner
DIE MARKINGS
YYYY
2014
ZZZZ
TAPE AND REEL CONFIGURATION
7” reel
a
d e f g
c
b
Note 1: MSL 1 (moisture sensitivity level 1) classied according to IPC/JEDEC industry standard.
Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket,
not the pocket hole.
Die
orientation
dot
Gate
solder bar is
under this
corner
Die is placed into pocket
solder bar side down
(face side down)
Loaded Tape Feed Direction
Dimension (mm) target min max
a 8.00 7.90 8.30
b 1.75 1.65 1.85
c (note 2) 3.50 3.45 3.55
d 4.00 3.90 4.10
e 4.00 3.90 4.10
f (note 2) 2.00 1.95 2.05
g 1.5 1.5 1.6
EPC2014C (note 1)
4 mm pitch, 8 mm wide tape on 7” reel
Figure 12: Safe Operating Area
0.1
1
10
100
0.1 1 10 100
ID – Drain Current (A)
VDS - Drain-Source Voltage (V)
Limited by RDS(on)
TJ = Max Rated, TC = +25°C, Single Pulse
100 ms
10 ms
1 ms
100 µs
Pulse Width
100 ms
10 ms
1 ms
100 µs
eGaN® FET DATASHEET
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EPC2014C
RECOMMENDED
LAND PATTERN
(measurements in µm)
Pad no. 1 is Gate;
Pad no. 2 is Substrate;*
Pads no. 3 and 5 are Drain;
Pad no. 4 is Source
*Substrate pin should be connected to Source
The land pattern is solder mask dened
Solder mask is 10 µm smaller per side than bump
DIE OUTLINE
Solder Bar View
Side View
Information subject to
change without notice.
Revised May, 2019
Ecient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights, nor the rights of others.
eGaN® is a registered trademark of Ecient Power Conversion Corporation.
EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx
Pad no. 1 is Gate;
Pad no. 2 is Substrate;*
Pads no. 3 and 5 are Drain;
Pad no. 4 is Source
*Substrate pin should be connected to Source
DIM MICROMETERS
MIN Nominal MAX
A1672 1702 1732
B1057 1087 1117
c829 834 839
d311 316 321
e235 250 265
f195 200 205
g400 400 400
B
A
x2
e g g
c
d
x2
2
3 5
1
4
f
x3
f
815 Max
100 +/- 20
Seating Plane
(685)
400 400
1087
1702
180 180
814
x2
296
x2
1
3 5
2
4
x3
RECOMMENDED
STENCIL DRAWING
(units in µm)
Recommended stencil should be 4 mil (100 μm)
thick, must be laser cut , opening per drawing.
The corner has a radius of R60.
Intended for use with SAC305 Type 3 solder,
reference 88.5% metals content.
Additional assembly resources available at
http://www.epc-co.com/epc/DesignSupport/
AssemblyBasics.aspx
400 400
1087
1732
180 180
814
x2
296
x2
1
3 5
2
4
x3
R60