CY7C43643AV
CY7C43663AV/CY7C43683AV
PRELIMINARY
3.3V 1K/4K/ 16K x36 Unid irectional
Synchronous FIFO w/ Bus Matching
Cypress Semiconductor Corporation • 3901 North First Str eet • San Jose • CA 95134 • 408-943-2600
A ugust 11, 2000
V
Features
• High-speed, low-power, unidirectional, First-In Fi rst-
Out (FIFO) memori es w/ bus mat ching capabil it ies
• 1Kx36 (CY7C43643AV)
• 4Kx36 (CY7C43663AV)
• 16Kx36 (CY7C43683AV)
• 0.25-micron CMOS for opti m um speed/power
• High- speed 133-MHz operat ion (7.5- ns read/write c ycle
times)
• Low power
—ICC = 60 mA
—ISB = 10 mA
• Fully asynchronous and simultaneous read and write
operati on permitted
• M ailbox bypass register for each FIFO
• Parallel and Serial Programmable Almost Full and
Almost Empty flags
• Retransmit functio n
• Standard or FWFT user selectable mode
• Partial Reset
• Big or Little Endian format for word or byte bus sizes
• 128-Pin TQFP packaging
• Easily expandable in width and depth
Logic Block Diagra m
Po rt A
Control
Logic Port B
Control
Logic
Mail1
Register
Input
Register
Output
Register
Write
Pointer Read
Pointer
Status
Flag Logic
Programmable
Flag Offset Timing
Mode
1K/4K/16K
x36
Dual Ported
Memory
Mail2
Register
FIFO,
Mail1
CLKA
CSA
W/RA
ENA
MBA
RT
MRS1
PRS
FF/IR
AF
SPM
FS0/SD
FS1/SEN
A0–35
MBF2
BE/FWFT
B0–35
CLKB
CSB
W/RB
ENB
MBB
BE
BM
SIZE
EF/OR
AE
MBF1
Mail2
Reset
Logic
Bus Matching
36
36
MRS2
Registers
CY7C43643AV
CY7C43663AV/CY7C43683AV
2
PRELIMINARY
Pin Configuration[1]
Note:
1. Pin-compatible to IDT723623/33/43 family.
CY7C43643AV
CY7C43663AV
CY7C43683AV
TQFP
Top View
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
FS0/SD
MRS2
FS1/SEN
GND
NC
MRS1
MBA
MBF2
NC
AF
VCC
PRS
FF/IR
CSA
ENB
W/RB
CSB
GND
NC
EF/OR
NC
AE
VCC
MBF1
MBB
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
B30
B26
B27
B28
B29
B31
NC
GND
B32
B33
B34
B35
VCC
NC
CLKB
GND
SIZE
B16
B17
B18
B19
B20
B21
B22
B23
GND
BM
B24
B25
RT
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
A2
B0
GND
A0
A1
VCC
SPM
A3
A4
A5
GND
A6
A7
A8
A9
B9
B8
B7
VCC
B6
GND
B5
B4
B3
B2
B1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
VCC
A29
GND
A30
A31
A32
A34
A35
GND
CLKA
ENA
W/RA
A12
A20
GND
A18
A19
A21
VCC
A22
GND
FWFT/STAN
A23
A24
A25
A26
A27
A28
A33
72
71
70
69
68
67
66
65
B12
B10
B11
GND
B13
B14
B15
VCC
30
31
32
33
34
35
36
37
38
NC
A10
A11
GND
A13
A14
A15
A16
A17
NC
CY7C43643AV
CY7C43663AV/CY7C43683AV
3
PRELIMINARY
Functional Description
The CY7C436X3AV is a monolithic, high-speed, low-power,
CMOS Unidirectional Synchronous FIFO memory which sup-
ports clock frequencies up to 133 MHz and has read access
times as fast as 6 ns .
The CY7C436X3AV is a synchronous ( clocked) FIFO, mean-
ing ea ch port emplo ys a synchron ous i nterf ace . All data t r ans-
f er s throug h a port are gate d to the LO W - to-HI GH trans iti on of
a port clock by enable signals. The clocks for each port are
independent of one another and can be asynchronous or co-
incident. The enables for each port are arranged to provide a
simple unidirectional int erface between micropr ocessors and/
or buses with sy nchronous contr ol.
Commu nicati on betw een eac h port ma y b ypas s the FIF Os vi a
two mailbox registers. The mailbox registers’ width matches
the sel ected P ort B bus width. Each mailb ox regis ter has a f lag
(MBF1 and MBF2) to sign al when new mail has been stored.
Two kinds of rese t are a vail able on th e CY7C436X3A V : Master
Reset and P artial Reset. Mast er Reset init ializ es t he read and
write point ers to the first loc ation of the memory array, config-
ures the FIFO for Big or Little Endian byte arrangement, and
selects serial flag programm ing, par allel flag programming, or
one of the three possible default flag offset settings, 8, 16, or
64. The FIFO also has two Master Reset pins, MRS1 and
MRS2.
Par tial Reset also sets the read and write pointers to the first
location of the memory. Unli ke Master Reset, an y settings ex-
ist ing prior to P artial Reset (i.e., pr ogramming method a nd par-
tial flag default offsets) are retained. Partial Reset is useful
sinc e it permits f lushi ng of the FI FO mem ory wi thout changin g
any configurat ion settings. The FIFO has its own independent
Partia l Re set pin, PR S.
The CY7C436X3AV have two modes of operation: In the CY
Standard Mode, the first word written to an empty FIFO is de-
posited into the memory array. A read operatio n is requi red to
access that word (along with all other words residing in mem-
ory). In the First-Word Fall-Through Mode (FWFT), the first
long-word (36-bit wide) written to an em pty FIFO appears au-
tomatically on the out puts, no re ad operatio n required (never-
theless, accessing subsequent words does necessitate a for-
mal read request). The state of the FWFT/STAN pin during
FIFO operation determines the mode in use.
The FIFO has a com bined Empty/Out put Ready fla g (EF/OR)
and a combined Full/ Input Ready flag (FF/IR). The EF and FF
funct ions are select ed in the CY Stand ard Mode . EF indicat es
whether the memory is f ull or not. The IR and OR f unctions are
selected in the First-Word Fall-Through Mode. IR indicates
whether or not the FIFO has available memory locations. OR
show s whether the F IFO has data avai labl e fo r readin g or not.
It marks the presence of val id data on the outputs.
The FIFO has a programmable Almost Em pty fl ag (AE) and a
programmable Almost Full flag (AF). A E indi cates when a se-
lected number of words written to FIFO memory achieve a
predetermined “almost em pty stat e.” AF i ndicates when a se-
lected number of words written to the memory achieve a pre-
determined “almost full state.” (See Note #.)
IR and AF are synchronized to the port clock that writes data
into its array. OR and AE are synchronized to the port clock
that r eads dat a from it s arr ay. Pro gram mabl e of fset f or AE and
AF are loaded in parallel using Por t A or in serial via the SD
input. Three default of fset settings are also provided. The AE
threshold can be set at 8, 16, or 64 locations from the empty
boundary and AF thr esh old ca n b e set at 8, 1 6, or 64 locat i ons
from the full boundary. All these choices are made using the
FS0 and FS1 inputs during Master Reset .
Two or more devices may be used in parallel to create wider
data paths. If at any time the FIFO i s not activ ely performing a
function, the chip will automatically power down. During the
Power Down state, supply current consumption (ICC) is at a
minimum . In itia ting any oper ati on ( by act iv at ing cont rol inputs )
will immediately take the device out of the Power Down state.
The CY7C436X3AV are characterized for operation from 0°C
to 70°C commercial and from –40°C to 85°C indust rial. Input
ESD protec tion is g re ater t han 2001V, and la tch-up is p re v ent -
ed by the use of guard rings.
Selection Gu ide
CY7C43643/63/83AV
-7 CY7C43643/63/83AV
-10 CY7C43643/63/83AV
-15
Maximum Frequency (MHz) 133 100 66.7
Maximum Access Time (ns) 6 8 10
Minimum Cycle Time (ns) 7.5 10 15
Minimum Data or Enable Set-Up (ns) 3 4 5
Minimum Data or Enable Hold (ns) 0 0 0
Maxim um Flag Delay (ns) 6 8 10
Active Power Supply
Current (ICC1) ( m A) Commercial 60 60 60
Industrial 60
CY7C43643AV CY7C43663AV CY7C43683AV
Density 1K x 36 4K x 36 16K x 36
Package 128 TQFP 128 TQFP 128 TQFP
CY7C43643AV
CY7C43663AV/CY7C43683AV
4
PRELIMINARY
Pin Definitions
Signal Name Description I/O Function
A0–35 Por t A Data I 36- bit unidirectional data por t for side A.
AE Almost Empty
Flag (Port B) O Progr ammab le Almost Empty flag sy nchroni z ed to CLKA. It is LO W when the nu mber
of words i n the FI FO 2 is l ess than or equal to the value in the Al mo st Empty A offs et
register, X. (See Note #35.)
AF Almost Full Flag O Programmable Almost Full flag synchronized to CLKA. It is LOW whe n the number of
empty loc ations in the FIFO is less than or equal to the value i n the Almost Full A offset
regist er, Y. (See Note #35.)
B0–35 Por t B Data O 36-bit unidirectional data por t for side B.
BE/FWFT Big Endi an/
First-Word F all-
Through Select
I This is a dual-purpose pin. During Maste r Reset, a HIGH on BE wil l select Bi g Endian
operat ion. I n this cas e, dependi ng on the bus size , the most sig nificant b yte or word on
P ort A is tr ansf erred to P ort B fir st. A LO W on BE will select Little Endi an operat ion. In
this c ase, t he leas t sign ific ant b yte or w ord on P ort A is tr ansferred t o P ort B firs t. Af ter
Master Res et, this pi n selects t he timing mode . A HIGH on FWFT selec ts CY Sta ndard
Mode, a L O W sel ect s Firs t-Wo rd F a ll- Thro ugh Mode . Once t he timing mode ha s bee n
selected, the level on FWFT must be static throughout device oper ation.
BM Bus Match
Select (Port B) I A HIGH on this pin enab les eith er b yte or word bu s width on P o rt B , dependin g on the
state of SIZE. A LOW sel ects long-word operation. BM works with SIZE and BE to
select the bus size and endian arr angem ent for Port B . The level of BM mu st be static
throughout device operation.
CLKA Port A Clock I CLKA is a continuous clock that sy nchroniz es all dat a transf ers through P ort A a nd can
be asynchronous or coincident to CLKB. FF/IR and AF are all synchronized to the LOW-
to- HIGH tran s itio n o f CLKA.
CLKB Port B Clock I CLKB is a continuous clock that sy nchroniz es all dat a transf ers through P ort B a nd can
be asynchronous or coincident to CLKA. FB/I R , E F /OR, AF, and AE are all synchro-
nized to the LOW-to-HIGH transition of CLKB.
CSA Port A Chip
Select ICSA must be LOW to enable a LOW-to HIGH transit ion of CLKA to read or write on
Port A. The A0–35 outputs are in the high-impedance state when CSA is HIG H.
CSB Port B Chip
Select ICSB must be LOW to enable a LOW-to HIGH transit ion of CLKB to read or write on
Port B. The B0–35 outputs are in the high- impedance state when CSB is HIGH .
EF/OR Empty/Output
Ready Flag
(Port B)
O This is a dual-f unction pin. In the CY Standard Mode , the EF function i s selected. EF
indicates whether or not the FIFO memory is empty. In the FWFT mode, the OR function
is selec ted. OR indi cates the pres ence of valid dat a on B0–35 outputs, availabl e for
reading . FF/OR is sync hronized to the LOW-to-HIG H tr ansition of CLKB.
ENA P ort A Enab le I ENA must be HI GH to ena ble a L O W -to- HIGH tr ansi tion of CLKA to rea d or write dat a
on Port A.
ENB P ort B Enab le I ENB must be HI GH to ena ble a L O W -to- HIGH tr ansi tion of CLKB to rea d or write dat a
on Port B.
FF/IR Port B Full/Input
Ready Flag O This is a dual-function pin. In the CY Standard Mode, the FF function is se lect e d . FF
indic ates whether or not the FIFO memory is full. In th e FWFT mode, the IR funct ion
is selected. IR i ndicates whethe r or not th ere is space av ailab le for writing to the FIFO
memory. F F/IR is synchronized to the LOW-to-HIGH transition of CLKA.
FS1/SEN Flag Offset
Select 1/ Seri al
Enable
I FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register program -
ming. During M aster Re set, FS1/ SEN and FS0 /SD, together with SPM, se lect the f lag
offset programming method. Three offset register programming methods are available:
automatically lo ad one of three preset values (8, 16, or 64), parallel l oad from Port A,
and serial load. When serial load i s selec ted f or flag offs et regi ster p rog ramming, FS1/
SEN is used a s an enable sync hronous to the LOW- to-HI GH transiti on of CLKA. When
FS1/SEN is LOW, a risi ng edge on CLKA loads t he bit present on FS0/SD in to t he X
and Y regi sters . The number of bi t writ es requi red t o progr am t he off set re gister s is 2 0
for the CY7C43643, 24 for the CY7C43663, and 28 for the CY7C43683. The first bit
writ e stores the Y-register MSB and the last bit write stores the X-regi ster LSB.
FS0/SD Flag Off set
Select 0/ Seri al
Data
I
MBA Port A Mailbox
Select I A HIGH level on MBA chooses a mai lbox register f or a Port A r ead or write operati on.
CY7C43643AV
CY7C43663AV/CY7C43683AV
5
PRELIMINARY
MBB Port B Mailbox
Select I A HIGH level on MBB chooses a mai lbox register f or a Port B r ead or write operati on.
When a read operat ion is perf ormed on P ort B, a HIGH l evel on MBB select s data from
the Mail1 register for output and a LO W level selects FIFO output register data for
output. Data can only be written into Mail 2 register through Port B (MBB HIGH) and
not into the FIFO memory.
MBF1 Mail1 Regi ster
Flag OMBF1 is set LOW by a LOW-to-HIGH tr ansition of CLKA tha t writes dat a to the Mail1
regist er. Writ es to the Mail 1 register are i nhibited whil e M B F1 is LOW. MBF1 is set
HIGH by a LOW- to-HI GH tra nsition of CLKB when a Po rt B read is sele cted and MBB
is HIGH. M BF1 is set HIGH following eit her a Master or P artial Reset.
MBF2 Mail2 Regi ster
Flag OMBF2 is set LOW by a LOW-to-HIGH tr ansition of CLKB tha t writes dat a to the Mail2
regist er. Writ es to the Mail 2 register are i nhibited whil e M B F2 is LOW. MBF2 is set
HIGH by a LOW- to-HI GH tra nsition of CLKA when a Po rt A read is sele cted and MBA
is HIGH. M BF2 is set HIGH following eit her a Master or P artial Reset.
MRS1 Master Reset I A LOW on this pin initializes the FIFO read and writ e point ers to the first location of
memory and sets the P ort B output register to all zeroes. A LOW pulse on MRS1 selects
the programming method (serial or parallel) and one of three programmable flag default
offsets. It also configures Por t B for bus size and endian arrangem ent. Four LOW-to-
HIGH tr ansitions o f CLKA an d four LOW -to-HI GH transitions o f CLKB must occur while
MRS1 is LOW.
MRS2 Master Reset I A LOW on this pin initializes the Mail2 Regis ter.
PRS P artial Reset I A LOW on this pin initializes the FIFO read and write point ers to the firs t lo cation of
memory and sets the Port B output reg ister to all zeroes. During Parti al Reset, the
current ly select ed bus size, endi an arrangement, program m ing method (serial or par-
allel), and progr amm able fl ag settings are all retained.
RT Retransmit I A LOW str obe on this pin will ret ransmit t he data in th e FIFO. This is achieved by
bringin g the r ead pointe r back t o locati on zer o . The user will sti ll need t o pref orm read
operations to retr ansmit the dat a. Retr ansmit func tion applies to CY sta ndard mod e
only.
SIZE Bus Size Sel ect I A HIGH on this pin when BM is HIGH selec ts byte b us (9- bit) size on Port B. A LOW
on this pin when BM is HIGH selects word (18-bit) bus size. SIZE works with BM and
BE to select the bus size and endi an arrangement for P ort B. The level of SIZE must
be static t hroughout device operation.
SPM Serial
Programming I A LO W on this pin se lects serial prog ramming of parti al flag offsets. A HIGH on thi s pin
selects parallel program m ing or def ault offsets (8, 16, or 64).
W/RA Port A Write/
Read Select I A HIGH selects a write operation and a LOW selects a read operation on Port A for a
LO W-to-HIGH transition of CLKA. The A0–35 outputs ar e in the hi gh-i m pedance state
when W/RA is H IGH .
W/RB Po rt B Write/
Read Select I A LOW selects a write operation and a HIGH selec ts a read operation on Port B for a
LOW-to-HIG H transition of CLK B. The B0–35 out puts are in the high-impedance state
when W/RB is LOW.
Pin Definitions (continued)
Signal Name Description I/O Function
CY7C43643AV
CY7C43663AV/CY7C43683AV
6
PRELIMINARY
Maximum Ratings[2]
(Above which the useful l ife may be impair ed. For user gui de-
li nes, not tes ted.)
Storage Temperat ure ... .. .................... ..........–65°C to +150°C
Ambient Temperature wi th
Power Applied...............................................–55°C to +125°C
Supply Voltage to Ground Potential............... –0.5V to +7.0V
DC Voltage Applied to Output s
in High Z State[3]......................................–0.5V to VCC+0.5V
DC Input Voltage[3]...................................–0.5V to VCC+0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage ... .. ...... .. ......... ...... ......... ......>2001V
(per MIL- STD-883, Method 3015 )
Latch-Up Current.................................... ................. >200 mA
Operating Range
Range Ambient
Temperature VCC[4]
Commercial 0°C to +70°C 3.3V ± 10%
Industrial –40°C to +85°C 3.3V ± 10%
Electrical Characteristics Ov er the Operating Range
Parameter Description Test Conditions
CY7C43643/63/83AV
UnitMin. Max.
VOH Output HIGH Voltage VCC = 3. 0V,
IOH = –2.0 mA 2.4 V
VOL Output LOW Voltage VCC = 3. 0V,
IOL = 8.0 mA 0.5 V
VIH Input HIGH Vol tage 2.0 VCC V
VIL Input LOW Voltage –0.5 0.8 V
IIX Input Leakage Curr ent VCC = Max. –10 +10 µA
IOZL
IOZH Output OFF, High Z
Current VSS < VO< VCC –10 +10 µA
ICC1[5] Active Power Suppl y
Current Com’l60 mA
Ind 60 mA
ISB[6] Average Standby
Current Com’l10 mA
Ind 10 mA
Capacitance[7]
Parameter Description Test Conditions Max. Unit
CIN Input Capac it ance TA = 25°C, f = 1 MHz,
VCC = 3.3V 4pF
COUT Output Capacitance 8pF
Notes:
2. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
3. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
4. Operating VCC Range for -7 speed is 3.3V ± 5%.
5. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables s witch at 20 MHz, while data inputs switch at 10 MHz. Outputs
are unloaded.
6. All inputs = VCC – 0.2V, except RCLK and WCLK (which are at frequency = 0 MHz). All outputs are unloaded.
7. Tested initially and after any design or process changes that may affect these parameters.
CY7C43643AV
CY7C43663AV/CY7C43683AV
7
PRELIMINARY
AC Test Loads and Waveforms (-10, -15)
AC Test Loads and Waveforms (-7)
Switching Characteristics Over the Operating Range
Parameter Description
CY7C43643/63/
83AV
-7
CY7C43643/
63/83AV
-10
CY7C43643/
63/83AV
-15
UnitMin. Max. Min. Max. Min. Max.
fSClock Frequency, CLKA or CLKB 133 100 67 MHz
tCLK Clock Cycle Time, CLKA or CLKB 7.5 10 15 ns
tCLKH Pulse Duration, CLKA or CLKB HIGH 3.5 4 6 ns
tCLKL Pulse Duration, CLKA or CLKB LOW 3.5 4 6 ns
tDS Se t-Up Time, A0–35 bef ore CLKA↑ and B0–35 before
CLKB↑3 4 5 ns
tENS Set-Up Time, CSA, W/ RA , ENA, and MBA before
CLKA↑; CSB, W/ RB, ENB, and MBB before CLKB↑3 4 5 ns
tRSTS Set-Up Time, MRS1/MRS2 or PRS LOW before
CLKA↑ or CLKB↑[9] 2.5 4 5 ns
tFSS Set-Up Time, FS0 and FS1 before MRS1/MRS2
HIGH 5 7 7.5 ns
tBES Set -Up Ti me, BE/FWFT before MRS1/MRS2 HIGH 5 7 7.5 ns
tSPMS Set-Up Time, SPM befor e MRS 1 /MRS2 HIGH 5 7 7.5 ns
tSDS Set-Up Time, FS0/SD before CLKA↑3 4 5 ns
tSENS Set-Up Time, FS1/SEN before CLK A↑3 4 5 ns
tFWS Set- U p T ime, F WFT before CLKA↑0 0 0 ns
tDH Hold Time, A0–35 after CLKA↑ and B0–35 after
CLKB↑0 0 0 ns
tENH Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑;
CSB, W/ R B, ENB, and MBB afte r CLKB↑0 0 0 ns
Note:
8. CL = 5 pF fo r tDIS.
9. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3.0V
3.3V
OUTPUT
R2=680Ω
CL =3 0 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
≤3ns ≤3ns
ALL INPUT PULSES
R1=330Ω
[8]
3.0V
GND
90%
10%
90%
10%
≤3ns ≤3ns
ALL INPUT PULSES
I/O
50Ω
V
CC
/2
Z0=50Ω
CY7C43643AV
CY7C43663AV/CY7C43683AV
8
PRELIMINARY
tRSTH Hold Time, MRS1/MRS2 or P R S LOW af te r CLK A↑
or CLKB↑[9] 1 2 2 ns
tFSH Hold Ti me, FS0 and FS1 after MRS1/MRS2 HIGH 1 1 2 ns
tBEH Ho ld Tim e, BE/FWFT after MRS1/MRS2 HI GH 1 1 2 ns
tSPMH Hold Time, SPM after MRS1/MRS2 HIGH 1 1 2 ns
tSDH Hold Time, FS0/SD af ter CLKA↑0 0 0 ns
tSENH Hold Time, FS1/SEN af ter CLKA↑0 0 0 ns
tSPH Hold Time, FS1/SEN HIGH after MRS1/MRS2 HIGH 0 1 2 ns
tSKEW1[10] Skew Time between CLKA↑ and CLKB↑ for E F/OR
and FF/IR 5 5 7.5 ns
tSKEW2[10] Ske w Time between CLKA↑ and CLKB↑ for AE and
AF 7 8 12 ns
tAAccess Time, CLKA↑ to A0–35 and C LKB↑ to B0–35 1 6 1 8 3 10 ns
tWFF Propagation Delay Time, CLKA↑ to FF/IR 1 6 1 8 2 10 ns
tREF Propagation Delay Time, CLKB ↑ to EF/OR 1 6 1 8 2 10 ns
tPAE Propagation Delay Time, CLKB ↑ to AE 1 6 1 8 1 10 ns
tPAF Propagation Delay Time, CLKA ↑ to AF 1 6 1 8 1 10 ns
tPMF Propagation Delay Time, CLKA↑ to MBF 1 LOW or
MBF2 HIGH and CLKB↑ to MBF2 LOW or MBF1
HIGH
0 6 0 8 0 12 ns
tPMR Propagation Delay Time, CLKA↑ to B0–35[11] and
CLKB↑ to A0–35[12] 1 7 2 11 312 ns
tMDV Propagati on Delay Time, MBA to A0–35 Valid an d
MBB to B0–35 Valid 1 6 2 9 3 11 ns
tRSF Propag ation Dela y Time , MRS1/MRS2 or PRS LOW
to AE LOW, AF HIGH,FF/ I R LO W , EF/ OR LO W and
MBF1/MBF2 HIGH
1 6 1 10 115 ns
tEN Enable Time, CSA or W/RA LOW to A0–35 Active and
CSB LOW and W/RB H IG H to B 0–35 Active 1 6 2 8 2 10 ns
tDIS Disabl e Time, CSA or W/RA H IGH to A0–35 at High
Impedance and CSB HIGH or W/RB LOW to B0–35
at Hig h Impedance
1 5 1 6 1 8 ns
tPRT Retransm it Pulse Width 60 60 60 ns
tRTR Retransmit Recovery Time 90 90 90 ns
Notes:
10. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between the CLKA cycle and the CLKB
cycle.
11. Writing data to the Mail1 register when the B0–35 outputs are active and MBB is HIGH.
12. Writing data to the Mail2 register when the A0–35 outputs are active and MBA is HIGH.
Switching Characteristics Over the Operating Range (continued)
Parameter Description
CY7C43643/63/
83AV
-7
CY7C43643/
63/83AV
-10
CY7C43643/
63/83AV
-15
UnitMin. Max. Min. Max. Min. Max.
CY7C43643AV
CY7C43663AV/CY7C43683AV
9
PRELIMINARY
Swi tc hi n g Wavefo rms
Note:
13. PRS1 must be HIGH during Master Reset.
Master Reset Loading X and Y with a Preset Value of Eight
CLKA
tRSF
tRSF
tRSF
tWFF
tFSS tFSH
tSPMS tSPMH
tBES tBEH
tRSTH
tRSTS
tFWS
CLKB
MRS1,
MRS2
BE/FWFT
SPM
FS1/SEN,
FS0/SD
FF/IR
EF/OR
AE
AF
MBF1
[13]
tRSF
tRSF
CY7C43643AV
CY7C43663AV/CY7C43683AV
10
PRELIMINARY
Notes:
14. MRS1/MRS2 must be HIGH during Partial Reset.
15. CSA=LO W, W/RA=HIGH, MBA=LOW. It is not necessary to program offset register on consecutive clock cycles.
16. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKB for FF/IR to transition HIGH in the next cycle. If the time between the rising
edge of CLKA and rising edge of CLKB is less than tSKEW1, then FF/IR may transition HIGH one cycle later than shown.
Swi tc hi n g Wavefo rms (continued)
Partial Reset (CY Standard and FWFT Modes)
tRSF
tRSF
tRSF
tRSTS tRSTH
CLKA
CLKB
PRS
FF/IR
EF/OR
AE
AF
MBF1
[14]
tWFF
tRSF
tRSF
Parallel Program ming of t he Almost-Full Flag and Almost-Empty Flag Offset Values after Reset
(CY Standard and FWFT Modes)
tWFF
tFSS
tDS
tFSS tFSH
tFSH
tENS tENH
tDH
tSKEW1[16]
AF Offset (Y) First Word to FIFO
CLKA
MRS1,
MRS2
SPM
FS1/SEN,
FS0/SD
FF/IR
ENA
A0−35
[15]
AE Offset (X)
CY7C43643AV
CY7C43663AV/CY7C43683AV
11
PRELIMINARY
Notes:
17. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until IRA is set HIGH.
18. Programmable offsets are written serially to the SD input in the order AF offset (Y) then AE offset (X).
19. Read From FIFO.
Swi tc hi n g Wavefo rms (continued)
Serial Programm ing of the Almost-Full Flag and Almost-E mpty Flag
Offse t Values (CY Standard and FWFT Modes)
tFSS tSPH tSENS tSENH tSENH
tSENS
tSDH
tSDS tSDH
tSDS
tWFF
AF Offset (Y) MSB
tFSS tFSH
CLKA
MRS1,
MRS2
SPM
FF/IR
FS1/SEN
[17]
FS0/SD [18]
AE Offset (X) LSB
OR
tCLKH tCLKL
tENS
tDIS
tENS tEN
tCLK
tDIS
tENH
tENS tENH
tA
tA
tA
tA
tEN
tEN
tMDV
tMDV
W1[19] W2[19]
W1[19] W2[19]
W3[19]
Previous Data
No Operation
CLKB
EF/OR
CSB
W/RB
MBB
ENB
B0–35
(Standard Mode)
B0–35
(FW FT Mode)
Port B Long-Word Read Cycle Timing for FIFO (CY Standard and FWFT Modes)
HIGH
CY7C43643AV
CY7C43663AV/CY7C43683AV
12
PRELIMINARY
Notes:
20. Unused bytes B18–35 contains all zeroes for word-size reads.
21. Unused bytes B9–17, B18–26, and B27–35 contain all zeroes for byte-size reads.
Swi tc hi n g Wavefo rms (continued)
OR
OR
tDIS
tENS tENH
tA
tA
tA
tA
tEN
tEN
tMDV
tMDV tDIS
Previo us Data
Read 1
Read 1
Read 2
Read 2
Read 3
No Operation
CLKB
EF/OR
CSB
W/RB
MBB
ENB
B0–17
(Standard Mode)
B0–17
(FWFT Mode)
P ort B Wor d Read Cycle Timing for FIFO (CY Standard and FWFT Modes)[20]
HIGH
tDIS
tENStENH
tA
tA
tA
tA
tEN
tEN
tMDV
tMDV tDIS
tA
tA
tA
tA
Previous Data
Read 1
Read 1
Read 2
Read 2
Read 3
Read 3
Read 4
Read 4
Read 5
No Operation
HIGH
CLKB
EF/OR
CSB
W/RB
MBB
ENB
B0–8
(Standard Mode)
B0–8
(FWFT Mode)
Port B Byte Read Cycle Timing for FIFO (CY Stand ard and FWFT Modes ) [21]
OR
CY7C43643AV
CY7C43663AV/CY7C43683AV
13
PRELIMINARY
Notes:
22. If Port B size is word or byte, EF is set LOW by the last word or byte read from the FIFO, respectively.
23. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for OR to transition HIGH and to clock the next word to the FIFO output
register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of OR HIGH and load
of the first word to the output register may occur one CLKB cycle later than shown.
Swi tc hi n g Wavefo rms (continued)
tCLKH tCLKL
tENS
tCLK
tEN
tENS
tEN
tA
tDS
W1
LOW
tDH
HIGH
HIGH
FIFO Empty
LOW
HIGH
LOW
Old Data in FIFO Output Register W1
tENS tENH
tREF tREF
tCLKH tCLKL
tCLK
tSKEW1[23]
CLKA
CSA
W/RA
MBA
ENA
FF/IR
A0–35
CLKB
EF/OR
CSB
W/RB
MBB
ENB
B0–35
OR Flag Timing and First Data Word Fall Through when FIFO is Empty (FWFT Mode) [22]
CY7C43643AV
CY7C43663AV/CY7C43683AV
14
PRELIMINARY
Note:
24. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EF to transition HIGH in the next CLKB cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of EF HIGH may occur one CLKB cycle later than shown.
Swi tc hi n g Wavefo rms (continued)
tCLKH tCLKL
tENS
tENH
tENS
tENH
tA
tDS
W1
LOW
tDH
HIGH
HIGH
FIFO Empty
LOW
HIGH
LOW
W1
tENStENH
tREF tREF
tCLKH tCLKL
tCLK
tCLK
tSKEW[24]
CLKA
CSA
W/RA
MBA
ENA
FF/IR
A0–35
CLKB
EF/OR
CSB
W/RB
MBB
ENB
B0–35
EF Flag Timi ng and Fir st Data Read Fall Through when FIFO is Empty (CY Standar d M ode) [22]
CY7C43643AV
CY7C43663AV/CY7C43683AV
15
PRELIMINARY
Notes:
25. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that reads the last word or byte write of the long-word, respectively.
26. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition HIGH in the next CLKA cycle. If the time between the
rising CLKB edge and rising CLKA edge is less than tSKEW1, then IR may transition HIGH one CLKA cycle later than shown.
Swi tc hi n g Wavefo rms (continued)
tCLKH tCLKL
tENStENH
tA
LOW
HIGH
HIGH
FIFO Full
LOW
HIGH
tENStENH
tWFF tWFF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[26]
tDH
tDS
tENH
tENS
Pr eviou s Word in FIFO Outp ut Regis ter Next Word From FIFO
To FIFO
CLKB
CSB
W/RB
MBB
ENB
EF/OR
B0–35
CLKA
FF/IR
CSA
W/RA
MBA
ENA
A0–35
IR Flag Timing and First Avail able Writ e when FIFO is Full (FWFT Mode ) [25]
LOW
CY7C43643AV
CY7C43663AV/CY7C43683AV
16
PRELIMINARY
Note:
27. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FF to transition HIGH in the next CLKA cycle. If the time between the
rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of FF HIGH may occur one CLKA cycle later than shown.
Swi tc hi n g Wavefo rms (continued)
tCLKH tCLKL
tENStENH
tA
LOW
HIGH
HIGH
FIFO Full
LOW
HIGH
tENStENH
tWFF tWFF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[27]
tDH
tDS
tENH
tENS
Previou s Word in FIFO Output Register Next Word From FIFO
CLKB
CSB
W/RB
MBB
ENB
EF/OR
B0–35
CLKA
FF/IR
CSA
W/RA
MBA
ENA
A0−35
FF Flag Timing and First Available Write when FIFO is Full (CY Standard Mode)[25]
LOW
CY7C43643AV
CY7C43663AV/CY7C43683AV
17
PRELIMINARY
Notes:
28. FIFO Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been
read from the FIFO.
29. D = Maximum FIFO Depth = 1K for the CY7C43643, 4K f or the 43663, and 16K for the CY7C43683.
30. If Port B size is word or byte, tSKEW2 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
31. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition HIGH in the next CLKA cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than tSKEW2, then AF may transition HIGH one CLKB cycle later than shown.
32. FIFO Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been
read from the FIFO.
33. If Port B size is word or byte, AE is set LOW by the last word or byte read from FIFO, respectively.
34. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition HIGH in the next CLKB cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than tSKEW2, then AE may transition HIGH one CLKB cycle later than shown.
35. Programmable flag deasserts one clock cycle less than IDT’s equivalent (72V36x3). When FIFO is operated at the almost empty/full boundary, there may
be an uncertainty of up to 2 clock cycles for flag deassertion, but the flag will always be asserted exactly when the FIFO content reaches the programmed
value. Refer to “Designing with CY7C436xx Synchronous FIFOs” application note for more details on flag uncertainties.
Swi tc hi n g Wavefo rms (continued)
Timing for AF when FIFO is Almos t Full (CY Stan dard and FW FT Modes)
tPAF
tENH
tENS
tPAF
tENS tENH
[D–(Y1+1)] Words in FIFO (D–Y )Words in FIFO
tSKEW2[31]
CLKA
ENA
AF
CLKB
ENB
[28, 29, 30, 35]
tENH
tENS
tSKEW2[34]
CLKA
ENA
CLKB
AE
ENB
Timing for AE when FIFO is Almost Empty (CY Standard and FWFT Modes)[32, 33, 35]
tPAE
tPAE
tENS tENH
X1 Word in FIFO 1 (X+1)Words in FIFO1
CY7C43643AV
CY7C43663AV/CY7C43683AV
18
PRELIMINARY
Note:
36. If Port B is configured for word size, data can be written to the Mail1 register using A0–17 (A18–35 are “Don’t Care” inputs). In this first case B0–17 will have
valid data (B18–35 will be indeterminate). If Port B is configured for byte size, data can be written to the Mail1 Register using A0–8 (A9–35 are “Don’t Care”
inputs). In this second case, B0–8 will have valid data (B9–35 will be indeterminate).
Swi tc hi n g Wavefo rms (continued)
tENH
tENS
tENH
tENS
tENH
tENS
tENH
tENS
tDH
tDS
W1
tPMF tPMF
tEN tMDV tPMR
tENS tENH
tDIS
FIFO Output Register W1 (Remains valid in Mail1 Register after read)
CLKA
CSA
W/RA
MBA
ENA
A0–35
CLKB
MBF1
CSB
W/RB
MBB
ENB
Timing for Mail1 Register and MBF1 Flag (CY Standard and FWFT Modes)[36]
B0−35
CY7C43643AV
CY7C43663AV/CY7C43683AV
19
PRELIMINARY
Notes:
37. If P ort B is configured for word size , data can be written to the Mail2 register using B0–17 (B18–35 are don’t care inputs). In this first case A0–17 will have valid
data (A18–35 will be indeterminate). If P ort B is configured for byte size, data can be written to the Mail2 Register using B0–8 (B9–35 are “Don’t Care” inputs).
In this second case, A0–8 will have valid data (A9–35 will be indeterminate).
38. Clocks are free-running in this case. CY standard mode only.
39. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTR.
40. For the AE and AF flags, two clock cycles are necessary after tRTR to update these flags.
Swi tc hi n g Wavefo rms (continued)
tENH
tENS
tENH
tENS
tENH
tENS
tENH
tENS
tDH
tDS
W1
tPMF tPMF
tEN tMDV tPMR
tENS tENH
tDIS
FIFO2 Output Register W1 (Remains valid in Mail2 Register after read)
CLKB
CSB
W/RB
MBB
ENB
B0–35
CLKA
MBF2
CSA
W/RA
MBA
ENA
A0−35
Timing for Mail2 Register and MBF2 Flag (CY Standard and FWFT Mod es)[37]
FIFO Retransmit Timing
ENB
RT1
tPRT tRTR
EFB/FFA
[ 37 , 38, 39, 40 ]
CY7C43643AV
CY7C43663AV/CY7C43683AV
20
PRELIMINARY
Signal Description
Master Reset (MRS1, MRS2)
The FIFO memor y of the CY7C436X3AV undergoes a com-
plete reset by taking its associated Master Reset (MRS1,
MRS2) input LOW for at least four Port A clock (CLKA) and
four Port B clock (CLKB) LOW-to-HIGH transitions. The Mas-
ter Reset input can switch asynchronously to the clocks. A
Master Reset initializes the internal read and write pointers
and forces the Full/Input Ready flag (FF/IR) LOW, the Empty/
Output Re ady flag (EF/OR) LOW, the Almost Em pty flag (AE)
LOW , and the Almost Full f lag (AF) HIGH. A Master Reset als o
forces the Mailbox flag (MBF1, MB F2) of the parallel m ailbox
register HIGH. After a Master Reset, the FIFO’s Full/Input
Ready flag is set HIGH after two clock cycles to begin normal
operation. A Master Reset must be performed on the FIFO
after power up, before data is written to its memory.
A LOW-to-HIGH transition on a FIFO Master Reset (MRS1,
MRS2) input latches the value of the Big Endian (BE) input,
determining the order by which bytes ar e transferred through
Port B.
A LOW-to-HIGH transition on a FIFO reset (MRS1, MRS2)
input latches the values of the Flag Select (FS0, FS1) and
Serial Programming Mode (SPM) inputs for choosing the Al-
most Full and Almost Empty offset programming method (see
Almost Empty and Almost Full fla g offset progr amming belo w).
P artial Reset (PRS)
Each of the t wo FIFO memories of the CY7C436X3AV under-
goes a limited reset by taking its associated Partial Reset
(PRS) in put LOW f or at l east f our P ort A c loc k (C LKA) and f our
P ort B clock (CLKB) LO W-to- HIGH trans itions. The Partial Re-
set inputs can switch asynchronously to the clocks. A Part ial
Reset i nitiali zes the internal read and write poi nters an d forces
the Full/Input Ready flag (FF/IR) LOW, the Empty/Output
Ready flag (EF/OR) LOW, the Almost Empty flag (AE) LOW,
and th e Almost Full f lag (AF) HIGH. A P artial Reset also forces
the Mai lbo x f lag (MBF1, MB F2) of the par all el mail bo x regi ster
HIGH. After a Par tial Reset, the FIFO’s Full/Input Ready flag
is set HIGH aft er two clock cycles to begin normal operation.
Whatever flag offsets, programming method (parallel or seri-
al), and t iming mode (FWFT or CY Standard m ode) are cur-
rently selected at the time a Partial Reset is initiated, those
settings will remain unchanged upon completion of the reset
operation. A Partial Reset may be useful in the case where
reprogramming a FIFO following a Master Reset would be in-
convenient.
Big Endian/First-Word Fall-Through (BE/FWFT)
This is a dual-purpose pin. At the time of Master Reset , the BE
select function is active, permitting a choice of Big or Little
Endian byte arrangement for data wri tten to or read from Port
B. This selection determines the order by which bytes (or
w ords) of data are t r ansf erred th rough t his port. F or the fol low-
ing illustrations, assume that a byte (or word) bus size has
been selected f or Port B.
A HIGH on the BE/FWFT input when the Master Reset (MRS1,
MRS2) inputs go from LOW to HIGH will select a Big Endian
arrangement. When data is moving in the direction from Por t
A to Por t B, the m ost significant byte (word) of the long-word
written to Port A will be transferred to Port B first; the least
signi fican t byte (word) of the long -word written to P ort A will be
transf erred to Port B last.
A LOW on the BE/FWFT input when t he Master Res et (MRS1,
MRS2) in puts go from LOW to HIGH will select a Li ttle Endian
arrangement. W hen data is moving in the direction from Por t
A to Por t B, the least significant byte (word) of the long-word
written to Port A will be transferred to Port B first; the most
signi fican t byte (word) of the long -word written to P ort A will be
transf erred to Port B last.
After Master Reset , the FWFT select function is activ e, permit-
ting a choice between two possible timing modes: CY Stan-
dard Mode or First-Word Fall-Through (FWFT) Mode. Once
the Master Reset (MRS1, MRS2) input is HIGH, a HIGH on the
BE/FWFT input at the second LOW-to-HIGH transition of
CLKA will select CY Standard Mode. This mode uses the Emp-
ty Flag function (EF) to indicate whether or not t here are any
words present in the FIFO memo ry. It uses the Ful l Fl ag func-
tion ( FF) to in dicate whether or not the FIFO memory has any
free space f or writi ng. In CY Stand ard Mode, every word read
from the FIFO, including the first, must be requested using a
for mal read operation.
Once t he Maste r R eset (M R S1 , MRS2) input is HIGH, a LO W
on the BE/FWFT input of the second LOW-to-HIGH transit ion
of CLKA will select FWFT Mode. This mode uses the Output
Ready function (OR) to indicate whether or not ther e is valid
data at the data outputs (B0–35). It also uses the Input Ready
function (IR) to indicate whether or not the FIFO memory has
any free space for writing. In the FWFT mode, the first word
written to an empty FIFO goes direct ly to d ata outp uts, no r ead
request necessary. Subsequent words must be accessed by
performing a formal read operation.
Followi ng Master Reset , the level appli ed to the BE/FWFT in -
put to choose the desired timing mode must remain static
throughout the FIFO operation.
Programming the Al mos t Empty and Almost Full Flags
Two regi sters i n the CY7C436 X3A V ar e used t o hold t he offse t
val ues fo r the Almost Empty and Almost Full flags . The P ort B
Almost Empty f lag (AE) offse t regi ster is l abeled X. The Po rt A
Almost Full flag (AF) offset register is labeled Y. The index of
each regi ster name cor respond s wi th prese t va lue s during the
reset of a FIFO, programmed in parallel using the FI FO’s Port
A data inputs, or programmed in serial using the Ser ial Data
(SD) input (see Table 1).
To load a FIFO’s Almost Empt y flag and Almost Ful l fl ag offse t
registers with one of the three preset values listed in Ta bl e 1,
the Serial Program Mode (SPM) and at least one of t he flag-
select inputs must be HIGH during the LOW-to-HIGH transition
of it s Master Reset i nput (MRS1 , MRS2). F or example, to l oad
the preset value of 64 into X and Y, SPM, FS0 and FS1 must
be HIGH when the FIFO reset (M RS1, MRS2) returns HIGH.
When using one of the preset values for the flag offsets, the
FIFO can be reset simultaneously or at differ ent times.
To program the X and Y registers from Port A, perf orm a M as-
ter Reset on both FIFOs simultaneously with SPM H IGH and
FS0 and FS1 LOW during the LOW-to-HIGH transition of
MRS1, MRS2. Af te r th i s re s e t is co mp le te , th e fi rs t two w rite s
to the FIFO do not stor e data in RAM but load the offse t regis -
ters in the order Y and X. The Por t A data inputs used by the
offset registers are (A0–9), (A0–11), or (A0–13), for the
CY7C436X3AV, respectively. The highest numbered input is
used as the most significant bit of the binar y number in each
CY7C43643AV
CY7C43663AV/CY7C43683AV
21
PRELIMINARY
case. Valid progr am m ing values for the regi sters r ange from 0
to 1023 for the CY7C43643AV; 0 to 4095 for the
CY7C43663AV; 0 to 16383 for the CY7C43683AV. (See foot-
note #35) Before program ming t he offset regist ers, F F/IR i s se t
HIGH. FIFOs begin normal operation after programming is
complete.
To program the X and Y registers serially, initiate a Master
Reset with SPM LOW, FS0/SD LO W , and FS1/SEN HI GH dur-
ing the LOW-to-HIGH transition of MRS1, MRS2. After this
reset is complete, the X and Y register values are loaded bit -
wise through t he FS0/SD input on each LOW-t o-HIGH transi-
tion of CLKA that the FS1/SEN input is LOW. Twenty, twenty-
f our, or tw enty -eight b it wri tes ar e ne eded to compl ete t he pro-
gramming for the CY7C4 36X3AV, respectively. The two regi s-
ters are written in the order Y then fi nally X. The first-bit write
stores the most significant bit of the Y register and the l ast-bit
write stores the l east si gnif icant bit of the X r egist er . Each reg-
ister value can be programmed from 0 to 1023
(CY7C43643AV), 0 to 4095 (CY7C43663AV), or 0 to 16383
(CY7C43683AV).
When the opt ion t o p rogr am t he off set r egist ers seriall y is cho-
sen, the Port A Full/Input Ready (FF/IR) flag remains LOW
unti l all re gister bits are written. FF/IR is set HIGH by the LOW-
to-HIGH transition of CLKA aft er the last bit is l oaded to allow
normal FIFO operation.
SPM, FS0/SD, and FS1/SEN function the same way in both
CY Standard and FWFT modes.
FIFO Write/Read Operation
The state of the Port A data (A0–35) lines is controlled by Por t
A Chip Select (CSA) and Port A Write/Read Select (W/RA).
The A0–35 lines are in the high-impedance state when either
CSA or W/RA is HI GH. The A0–35 lines are active mail 2 reg-
ist er outputs when both CSA and W/RA are LOW.
Data i s loaded in to the FIFO from the A0–35 i nputs on a LOW -
to- HIGH tra nsition of CLKA when CSA is LOW , W/RA is HIGH,
ENA is HIGH, MBA is LOW, and FF/IR is HIGH. (see Table 2).
FIFO wri tes on Port A are indepe ndent of any concurrent Port
B operation.
The Port B control signals a re identical to those of Port A with
the excepti on that the P ort B Write/Read select (W/RB) is the
inverse of the Port A Write/Read select (W/RA) . The state of
the Por t B data (B0–35) lines is controlled by t he Port B Chip
Selec t (CSB) a nd P o rt B W rite/Read se lect (W/RB). The B0–35
lines are in the high-impedance state when either CSB is
HIGH or W/RB is LOW. The B0–35 lines are active outputs
when CSB is LOW and W/RB is HIGH.
Data is read from the FIFO to the B0–35 outputs by a LO W-to-
HIGH transition of CLKB when CSB is LOW, W/RB is HIGH,
ENB is HIGH, MBB is L O W , an d EF/OR is HIGH (see Table 3).
FIFO reads and writes on Port B are in dependent of any con-
current Port A operation.
The set-up and hol d time constr aints to the port clocks for the
port Chip Selects and Write/Read Selects are only for enabling
write and r ead operations and are not related to high-imped-
ance co ntrol of the data out puts. I f a port enab le is L OW during
a clock cycle, the port’s Chip Select and Write/Read Select
ma y change states during the set-up and hold time windo w of
the cycle.
When operating the FIFO in FWFT Mode with the Output
Ready flag LOW , the next word written is automatically sent to
the FIFO’s output register by the LOW-to-HIGH transition of
the port clock that sets the Output Ready flag HIGH, data r e-
sidi ng in t he F IFO’s memory ar ra y i s cl oc ked t o the out put reg -
ister only when a read i s selec ted usi ng t he port’s Chip Select ,
Write/Read Select, Enable, and Mailbox Select.
When ope rati ng the FIFO in CY St andard Mode , regar dless o f
whether t he Emp ty Fl ag is LOW or HIGH, data resi ding in the
FIFO’s memory array is clocked to the output register only
when a read is selected using the port’s Chip Select, Write/
Read Select, Enable, and Mailbox Select.
Synchronized FIFO Flags
Each FIFO is synchronized to its port clock through at least
two flip- flop stages . This is done to impro ve flag-signal reliabil-
ity by reducing the probability of the metastable events when
CLKA and CLKB operate asynchronou sly to one ano ther. EF/
OR an d AE are sy nchr oniz ed to CLKA. FF/IR and AF are syn-
chroni zed to CLKB. Table 4 shows the relationship of each port
flag to the FIFO.
Empty/Output Ready Fla gs (EF/OR)
These are dual-pu rpose flags. In t he FW FT M ode, the Output
Ready (OR) fun ction i s select ed. When the Out put Ready fl ag
is HIGH, new data i s prese nt in the F IFO output regist er. When
the Output Ready flag is LO W , t he previ ous data word r emains
in the FIFO output register and any FIFO reads are ignored.
In the CY Standard Mode, the Empty Flag (EF) function is
selected. When the Empty Flag is HIGH, data is available in
the FIFO’s RAM memory for reading to the output register.
When Empty Flag is LOW, the previous data word remains in
the FIFO output registe r and any FIFO reads are igno red.
The Empty/Out put Ready fla g of a FIFO is synchroniz ed to the
port clock that reads data from its array. For both the FWFT
and CY Standard modes, the FIFO read pointer is incr em ent-
ed each time a new word is clocked to its output register. The
state machine that controls an Output Ready flag monitors a
write p ointer and read pointer co mp arator that indicates when
the FIFO SRAM status is empty, empty+1, or empty+2.
In FWFT Mode, from t he time a wor d is written to a FI FO , it can
be shifted to the FIFO output register in a minimum of three
cycles of the Output Ready flag synchronizing clock. There-
fore, an Output Ready flag is LOW if a word in memory is the
next data to be sent to the FIFO output register and three cy-
cles ha ve not elap sed since th e time t he word was written. The
Output Ready flag of the FIFO remains LOW until the third
LO W- to-HIGH tra nsition of the synchroni zing cloc k occurs, si-
multa neously forci ng the Outpu t Read y flag HIG H a nd shif ting
the word to the FIFO out put register.
In the CY Standard Mode, f rom the time a word is written to a
FIFO, the Empty flag will indicate the presence of data avail-
able for reading in a minimum of two cycles of the Empty flag
synchro nizing cl ock. Th erefor e, an Empty flag is LOW if a word
in memory is the next data to be sent to the FIFO output reg-
ister and two cycles have not elapsed since the time the word
was writt en. The Empty flag of the F IFO remains LOW unt il the
second LO W -to- HIGH trans ition of the sync hronizing clock oc-
curs , for cing the Empty flag HIGH; only then can data be read.
A LOW-to-HIGH transition on an Empty/Output Ready flag
synchronizin g clock begins t he firs t synchroni zation c ycle of a
write if the clock transition occurs at time tSKEW1 or greater
after the write. Otherwise, the subsequent clock cycle will be
the first synchronization cycle.
CY7C43643AV
CY7C43663AV/CY7C43683AV
22
PRELIMINARY
Full/Input Ready Flags (FF/IR)
This is a dual-purpose flag. In FWFT Mode, the Input Ready
(IR) function is selected. I n CY Standard Mode, the Full Flag
(FF) function is selected. For both timing modes, when the
Full /Inpu t Ready fl ag is HI GH, a memory locat ion is free in th e
SRAM to receive new data. No memory locations are free
when the Full/Input Ready flag is LOW and any wr ites to the
FIFO are i gnored.
The Full /Input Ready flag of a FIFO is synchr onized to the port
cloc k that writes data to its arra y. For bot h FWFT and CY Stan-
dard modes, each time a word is written to a FIFO, its write
point er is increment ed. The st at e machine t hat cont ro ls a Full/
Input Ready flag monitors a write pointer and read pointer
comp arator that i ndicates when t he FIFO SRAM status is full ,
full–1, or full–2. From the time a word is read from a FIFO, its
previous memory location is ready to be written to in a mini-
mum of two cycles of the Full/Input Ready flag synchronizing
clock. Therefore, a Full/Input Ready flag is LOW if less than
two cycles of the Full/Input Ready flag synchronizing clock
have elapsed since the next m emory wri te location has been
read. The second LOW-to-HIGH transition on the Full/Input
Ready flag synchronizing clock after the read sets the Full/
Input Ready flag HIGH.
A LO W -to -HIGH tr ansition on a Full/I nput Ready f lag synchr o-
nizing clock begins the first synchronization cycle of a read if
the clock transition occurs at time tSKEW1 or greater after the
read. Otherwise, the subsequent clock cycle can be the first
synchronizat ion cycle.
Almost Empty Fl ags (AE)
The Almost Empty flag of the FIFO is synchronized to por t B
clock. The state machine that controls an Almost Empty flag
monit ors a wri te poi nter an d read poi nt er compar ator th at indi-
cates when the FIFO SRAM status is almost empty, almost
empty+1, or almost em pty+2. The Almost Empty state is de-
fined by the contents of register X for AE. These registers are
loaded with preset values during a FIFO reset, programmed
from Port A, or programmed serially (see Almost Empty flag
and Almost Full flag offset programming above). An Almost
Empty f lag is LO W when i ts FIFO contai ns X or less words and
is HIGH when its FIFO contains (X+1) or more words. (See
footnot e #35)
Two LOW-to-HIGH transitions of the Almost Empty flag syn-
chronizing clock are required after a FIFO write for its Almost
Empty fl ag to ref lect the ne w le ve l of fill . Theref or e, the Almost
Empty fl ag of a FIFO cont aining (X+1) or more words re mains
LO W if two cycles of its synchroni zing clock have not elapsed
since the write that filled the memory to the (X+1) level. An
Almost Empty flag is set HIGH by the second LOW-to-HIGH
transition of its synchronizing clock after the FIFO write that
fills memory to the (X+1) level. A LOW -to-HIGH transition of an
Almost Empty flag synchronizing clock begins the first syn-
chronization cycle if it occurs at time tSKEW2 o r greater a fter
the write t hat fills t he FIFO to (X+ 1) words . Otherwise, the sub-
sequent synchronizing clock cycle will be the first synchroni-
zation cycle .
Almost Full Flags (AF)
The Almost Full flag of the FIFO is synchronized to port A
clock. The state machine that controls an Almost Full flag mon-
it ors a write point er and read poi nter compar ator that indicates
when the FIFO SRAM status is almost full, almost full–1, or
almost full–2. The Almost Full state is defined by the content s
of register Y for AF. These registers are loaded with preset
values during a FIFO reset, programmed from Port A, or pro-
gramm ed serially (see A lmost Empty flag and Almos t F ull flag
offset programming above). An Almost Full flag is LOW when
the number of words in its FIFO is greater than or equal to
(1024–Y), (4096–Y), or (16384–Y) , fo r the CY7C436X3AV re-
spectively. An Almost Full flag is HIGH when the number of
words in its FIFO is less than or equal to [1024–(Y+1)],
[4096–(Y+1)], or [16384–(Y+1)], for the CY7C436X3AV re-
spectively.
Two LOW-to-HIGH transitions of th e Almost Full fl ag synchro-
nizing clock are required after a FIFO read for its Almost Full
flag to reflect the new level of fill. Therefore, the Almost Full
flag of a FIFO containing [1024/4096/16384–(Y+1)] or less
words remains LOW if two cycles of its synchronizing clock
have not elapsed since the read that reduced the number of
words in memory to [ 102 4/4096/ 16384 –(Y+1 )] . An Al mo st F ull
flag is set HIGH by the second LOW-to-HIGH transition of i ts
synchro nizin g cl ock after th e FIFO re ad that re duces t he n um-
ber of wor ds in memory to [1024/409 6/1 6384–(Y+1)]. A LOW -
to-HIG H transition of an Almost Full flag synchronizing clock
begins t he first synchroni zation cy cle if it o ccurs at t ime tSKEW2
or greater after the read that reduces the number of words in
memory to [1024/4096/16384–(Y+1)]. Otherwise, the subse-
quent synchronizing clock cycle will be the first synchroniza-
tion cycle.
Mailbox Regist ers
Each FIFO has a 36-bi t bypass register to pass command and
control information between Port A and Port B without putting
it in queue. The Mailbox Select (MBA, MBB) inputs choose
between a mail register and a FIFO for a port data transfer
operation. The usable wi dth of both the Mail1 and Mail2 regis-
ters matches the sel ected bus size of Port B.
A LOW-to-HIGH transition on CLKA writes A0−35 data to the
Mail1 Reg ister when a P ort A write is se lecte d by CSA , W/RA ,
and ENA with MBA HIGH. If the selected Port A bus size is
also 36 bits, then the usable width of the Mail1 Register em-
plo ys data li nes A0−35. If the sel ected P ort A bus size is 18 bit s,
then th e usab le wi dth of the M ail 1 Regist er emp lo ys data l ines
A0−17. (In this case, A18−35 ar e do n’t care inputs.) If the select-
ed Port A bus siz e is 9 bits, then the us able width of the Mail1
Register employs data lines A0–8. (In this case, A9−35 are
“Don’t Care” inputs.)
A LOW-to-HIGH transition on CLKB writes B0−35 data to the
Mail2 Regist er when a Port B write is se lected by CSB , W/RB,
and ENB with MBB HIGH. If the selected Port B bus size is
also 36 bits, then the usable width of the Mail2 Register em-
plo ys data li nes B0–35. If the sel ected P ort B bus size i s 18 bits ,
then th e usab le wi dth of the M ail 2 Regist er emp lo ys data l ines
B0–17. (In this case, B18–35 are don’t car e input s.) If t he sel ect -
ed Port B bus siz e is 9 bits, then the us able width of the Mail2
Register employs data lines B0−8. (In this case, B9−35 are
“Don’t Care” inputs.)
Writing data to a mail register sets its corresponding flag
(MBF1 or MBF2) LO W. Attempte d write s to a mail register are
ignored while the mail flag is LOW.
When data outputs of a port are active, the data on the bus
comes from t he FIF O output re giste r if the port Mailbo x Sel ect
input is LOW and from the mail register if the port Mailbox
Select input is HIGH.
CY7C43643AV
CY7C43663AV/CY7C43683AV
23
PRELIMINARY
The Mail1 Register flag (MBF1) is set HIGH by a LOW-to-
HIGH transition on CLKB when a Port B read is selected by
CSB, W/RB, and ENB with M BB HIGH. For a 36-bit bus size,
36 bits of mailbox data are placed on B 0–35. F or an 18-bit bus
siz e , 18 bi ts of mai lbo x da ta are placed on B0–17. (In this case ,
B18–35 are indeterminate.) For a 9-bit bus size, 9 bits of mail-
box data are placed on B0–8. (In th is cas e, B9–35 are indeter-
minate.)
The Mail2 Register flag (MBF2) is set HIGH by a LOW-to-
HIGH transition on CLKA when a Port A read is selected by
CSA, W/ R A , and ENA with MBA HIGH.
For a 36-bit bus size, 36 bits of mailbox data are placed on
A0–35. For a n 18-b it b us size , 18 bits of mailbo x data are placed
on A0–17. (I n this c ase, A 18–35 are indeterminate.) For a 9- bit
bus size, 9 bits of mailbox data are placed on A0–8. (In this
case, A9–35 are indeterminate.)
The data in a mail register remains intact after it is read and
changes only when new data is written to the register. The
Endian Select feature has no effect on the mailbox data.
Bus Sizi ng
The Port B bus ca n be confi gured in a 36-bit l ong-word, 18-bit
word, or 9-bi t byte for mat for data read from FIFO. The levels
applied to the Port B Bus Size Select (SIZE) and the Bus
Match Se lect (BM) de termine th e P ort B b us size . These le v els
shoul d be static through out FIFO operat ion. Bot h bus size se-
lections are implemented at the completion of Master Reset,
by the time the Full /Input Ready flag is set HIGH.
Two different methods for sequencing data transfer are avail-
able for Port B when the bus size selection is either byte-or
word-size. They are ref erred t o as Big Endian (most sign ificant
byte first) and Little Endian (least significant byte first). The
level applied to the Big Endian Select (BE) input during the
LOW-to-HIGH transition of MRS1/MRS2 selects the endian
method t hat wil l be ac tiv e during F IFO ope ration. BE is a don’t
care i nput when the bus size selected for Port B is long- word.
The endian method is impleme nted at the c om pletion of Mas-
ter Reset, by the time the Full/Input Ready flag is set HIGH.
On ly 36- bit long- word dat a is w ritt en to the FIF O mem or y on
the CY7C436X3AV. Bus-matching operations are done after
data is read from the FIFO. These bus-matching operations
are not available when tr ansferring data via mail box registers.
Furthermore , both t he w ord- and by te-siz e b us s elections lim it
the width of the data bus that can be used for mail register
operat ions. I n this case , only those byte lanes bel onging to the
selected word- or byte-size bus can carr y mailbox data. The
remaining data outputs will be indeterminate. The remaining
data inputs will be don’t care inputs. For example, when a
word-size b us is sel ected, then mailbox data can be transmit -
ted only between A0–17 and B0–17. When a byte-size bus is
selected, then mail box data can be transmitted only between
A0–8 and B0–8.
Bus-Matching FIFO Reads
Data is read from the FIFO RAM in 36-bit long-word incre-
ments. I f a lo ng-word b us siz e is i mplem ented, the ent ire l ong -
word immediately shifts to the FIFO output register. If byte or
word size is implemented on Por t B, only the first one or two
byte s appea r on the sel ected portion of the FIFO out put reg is-
ter, with the rest of th e long- word stor ed in auxi liary registers .
In this case, subsequent FIFO reads output the rest of the
long-word to the FIFO output register.
When readi ng data from the FIFO in the byte or word format,
the unused B0–35 outputs are indeterminate.
Retransmit (RT)
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessar y. Retransmit func-
tion applies to CY standard mo de only.
The retransmit feature is intended for use when a number of
writes equal to or less than the depth of the FIFO have oc-
curred and at l east one word has be en read si nce the l ast rese t
cycle. A LOW pulse on RT resets the inter nal read pointer to
the firs t phy sical location of the FIF O. CLKA and CLKB ma y be
free runni ng but ENB must be disabled during and tRTR after
the ret ransmit pulse. With ev ery valid read cycle after retrans -
mit, previ ously accessed data i s read and the read pointer is
incremented until it is equal to the write pointer . Flags are gov-
er ned by the relative locations of the read and write pointers
and are updated during a retran sm it cycle. Data written to t he
FIFO after activation of RT are trans mitte d also . The full dept h
of the FIFO can be r epeatedly retransmit ted.
CY7C43643AV
CY7C43663AV/CY7C43683AV
24
PRELIMINARY
A
A27–35 B
A18–26 C
A9–17 D
A0–8
A
B27–35 B
B18–26 C
B9–17 D
B0–8
A B
C D
CD
AB
A
B
C
D
(a) LO NG WORD SIZE
(b) WORD SIZE – BIG ENDIAN
(c) WORD S IZE – LITTLE ENDIAN
(d) BYTE SIZE – BIG ENDIAN
BE BM SIZE
XLX
BE BM SIZE
HHL
BE BM SIZE
LHL
BE BM SIZE
HHH
Writ e to FI FO
Read from
FIFO
1st: Read from
FIFO
2nd: Read from
FIFO
1st: Read from
FIFO
2nd: Read from
FIFO
1st: Read from
FIFO
2nd: Read from
FIFO
3rd: Read from
FIFO
4th: Read from
FIFO
BYTE ORDER ON
PORT A:
D
C
B
A
( e) BYT E SIZE – LITTLE ENDIAN
BE BM SIZE
LHH
1st: Read from
FIFO
2nd: Read from
FIFO
3rd: Read from
FIFO
4th: Read from
FIFO
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
CY7C43643AV
CY7C43663AV/CY7C43683AV
25
PRELIMINARY
..a ble
Table 1. Flag Programming
SPM FS1/SEN FS0/SD MRS1/MRS2 X and Y Registers[41]
H H H ↑64
H H L ↑16
H L H ↑8
H L L ↑Para llel programming via Port A
L H L ↑Serial programming via SD
L H H ↑Reserved
L L H ↑Reserved
L L L ↑Reserved
Table 2. Port A Enable Function
CSA W/RA ENA MBA CLKA A0–35 Outputs Port Function
H X X X X In high-impedance state None
L H L X X In high-impedance state None
LHHL↑In high-impedance state FIF O write
LHHH↑In high -impedance state Mail1 write
L L L L X Active, Mail2 regi ster None
LLHL↑Active, Mail2 registe r None
L L L H X Ac ti ve , Mail2 registe r None
LLHH↑Active, Mail2 register Mail2 read (set MBF2 HIGH)
Table 3. Port B Enable Function
CSB W/RB ENB MBB CLKB B0–35 Outputs Port Function
H X X X X In high-impedan ce state None
L L L X X In hig h-i m pedance state None
LLHL↑In hig h-i m pedance state None
LLHH↑In hig h-i m pedance state Mail2 write
L H L L X A cti ve, FIFO output register None
LHHL↑Activ e, FIFO output register FIFO read
L H L H X Active, Mail1 regi ster None
LHHH↑Acti ve, Mail1 regist er Mail1 rea d (set M B F1 HIGH)
Note:
41. X register holds the offset for AE; Y register holds the offset for AF.
CY7C43643AV
CY7C43663AV/CY7C43683AV
26
PRELIMINARY
Table 4. FIFO Flag Operation (CY Standard and FWFT Modes)
Number of Words in FIFO Memory[35, 42, 43, 44, 45] Synchronized to CLKB Synchronized to CLKA
CY7C43643AV CY7C43663AV CY7C43683AV EF/OR AE AF FF/IR
0 0 0 L L H H
1 TO X 1 TO X 1 TO X H L H H
(X+1) to
[1024–(Y+1)] (X+1) to
[4096–(Y+1)] (X+1) to
[16384–(Y+1)] H H H H
(1024–Y) to 1023 (4096–Y) to 4095 (16384–Y) to
16383 H H L H
1024 4096 16384 H H L L
Table 5. Data Size for FIFO Long- Word Reads
Size Mode[46] Data Writt en to FIF O Data Read From FIFO
BM SIZE BE A27–35 A18–26 A9–17 A0–8B27–35 B18–26 B9–17 B0–8
LXXABCDABCD
Table 6. Data Size for Word Reads
Size Mode[46] Data Writt en to FIF O Read No. Da ta Read Fr om FIFO
BM SIZE BE A27–35 A18–26 A9–17 A0–8B9–17 B0–8
HLHABCD1AB
2CD
HLLABCD1CD
2AB
Table 7. Data Size for Byte Reads from FIFO
Size Mode[46] Data Written to FIFO Read No. Data Read Fr om
FIFO
BM SIZE BE A27–35 A18–26 A9–17 A0–8B0–8
HHHABCD1 A
2B
3C
4D
HHLABCD1 D
2C
3B
4A
Notes:
42. X is the Almost Empty offset for FIFO used by AE. Y is the Almost Full offset for FIFO used by AF. Both X and Y are selected during a FIFO reset or Port A
programming.
43. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
44. Data in the output register does not count as a “word in FIFO memory”. Since in FWFT Mode , the first word written to an empty FIFO goes unrequested to
the output register (no read operation necessary), it is not included in the FIFO memory count.
45. The OR and IR functions are active during FWFT mode; the EF and FF functions are active in CY Standard Mode.
46. BE is selected at Master Reset; BM and SIZE must be static throughout device operation.
CY7C43643AV
CY7C43663AV/CY7C43683AV
27
PRELIMINARY
Document #: 38-00776-A
3.3V 1K x36 Unidire ctional Synchronous FIFO w/ Bus Matching
Speed
(ns) O rd er i ng Co de Package
Name Package
Type Operating
Range
7CY7C43643AV–7AC A128 128- Lead Thin Quad Flat Package Commercial
10 CY7C43643AV–10AC A128 128-Lead Thin Quad Flat P ackage Commercial
15 CY7C43643AV–15AC A128 128-Lead Thin Quad Flat P ackage Commercial
3.3V 4K x36 Unidire ctional Synchronous FIFO w/ Bus Matching
Speed
(ns) Orderi ng Code Package
Name Package
Type Operating
Range
7 CY7C43663AV–7AC A128 128-Lead Thin Quad Flat Packag e Commercial
10 CY7C43663AV–10AC A128 128-Lead Thin Quad Fl at Pac kage Commercial
15 CY7C43663AV–15AC A128 128-Lead Thin Quad Fl at Pac kage Commercial
3.3 V 16K x36 Unidirection al Synchronous FIFO w/ Bus Matching
Speed
(ns) Ordering Code Package
Name Package
Type Operating
Range
7 CY7C43683AV–7AC A128 128-Lead Thin Quad Fla t Package Commercial
10 CY7C43683AV–10AC A128 128-Lead Thin Quad Flat P ackage Commer cial
15 CY7C43683AV–15AC A128 128-Lead Thin Quad Flat P ackage Commer cial
15 CY7C43683AV–15AI A128 128-Lead Thin Quad Flat Package Industrial
Shaded areas contain advance information.
CY7C43643AV
CY7C43663AV/CY7C43683AV
PRELIMINARY
© Cypress Semiconductor Corporation, 2000. The i nformation contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuit ry other than circuitry embodied in a Cypress Semiconduc tor product. Nor does it con vey or imply any lice nse under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-s upport systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package D i ag r am
128-Lead Thin Plastic Quad Flat pack (14 x 20 x 1.4 mm) A128
51-85101-A
