CMX7032 CML Microcircuits COMMUNICATION SEMICONDUCTORS D/7032_FI2.0/9 October 2013 AIS Rx Data Processor NMEA 0183-HS Output DATASHEET CMX7032FI-2.x: Marine AIS Rx-only data processor designed for LimiterDiscriminator based RF systems Features: Dual GMSK Demodulators Low-Power (3.0V to 3.6V) Operation AIS Data Output in RS232 - NMEA 0183 Format Limiter-Discriminator Rx Interface Optimum Rx Co-channel Performance Automatic FI Loading from EEPROM for Host-less Operation Low Profile 64 Pin Leadless VQFN and LQFP Packages Automatic Identification System (AIS) for Marine Safety Configurable by Function ImageTM (FI) Compatible with PE0201 Kit Two RF Synthesisers Compatible with DE70321 Kit Two Auxiliary System Clock Generators For AIS Rx-only Modules GPS GPS Mesage Buffer RS232 UART Rx Section Rx1: LimiterDiscriminator Rx2: LimiterDiscriminator HDLC NRZI Decoder GMSK Decoder HDLC NRZI Decoder GMSK Decoder Auxiliary Section AIS Radio Receiver GPIO Dual Clock Generators Dual RF Synthesisers 2013 CML Microsystems Plc Mesage Buffer RS232 Driver Peripheral Device (PC, PDA, custom display) NMEA Formater and Message Arbitrator Mesage Buffer Reset and Power Control CMX7032 TCXO AIS Rx-only Baseband IC with RF Synthesizer 1 CMX7032 Brief Description A highly integrated Baseband Signalling Processor IC, the CMX7032 used with 7032FI-2.x fulfils the requirements of the Rx-only Marine Automatic Identification System (AIS) receiver market. The AIS system allows ships and base stations to communicate their position and other data to each other without the need for a centralised controller. This allows vessels to "see" each other and take appropriate action to avoid collision and so improve marine safety. The system uses a GMSK 9600 baud data link in the Marine VHF radio band. The system requirements are defined in ITU-M 1371-4. When used with the 7032FI-2.x the device operates in a Rx-only mode and comprises two parallel LimiterDiscriminator Rx paths and an RS232 style/NMEA 0183-HS compatible output (38400 baud). The device performs signal demodulation with associated AIS functions, such as training sequence detection, NRZI conversion and HDLC processing (flags, bit de-stuffing, CRC check). Integrated Rx data buffers are also provided which removes the need for a host C. Provision of a number of user-programmable areas in the FI allows the RF synthesisers of the CMX7032 to be programmed directly, which simplifies the system hardware design, reducing the overall equipment cost and size. Allowance is made in the RS232 interface for an external GPS device to be connected to reduce the proliferation of interface connections in the final product design.7032FI-2.0 is compatible with CMX7032 devices with batch code 67228 or later. Devices from earlier batch codes may be used with care, but are not recommended for production. The CMX7032 device utilises CML's proprietary FirmASIC component technology. On-chip sub-systems are configured by a Function ImageTM: this is a data file that is uploaded during device initialisation and defines the device's function and feature set. The Function ImageTM can be loaded automatically from an external EEPROM or from a host Controller over the built-in RS232 serial interface. The device's functions and features can be enhanced by subsequent Function ImageTM releases, facilitating in-the-field upgrades. This Datasheet is the first part of a two-part document comprising Datasheet and User Manual: the User Manual can be obtained by registering your interest in this product with your local CML representative. These documents refer specifically to the features provided by Function ImageTM 2.x. 2013 CML Microsystems Plc 2 D/7032_FI2.0/9 AIS Rx-only Baseband IC with RF Synthesizer CMX7032 CONTENTS 1 Brief Description................................................................................................................................ 2 1.1 History ........................................................................................................................................ 4 2 Block Diagram ................................................................................................................................... 6 3 Signal List .......................................................................................................................................... 8 3.1 Signal Definitions ..................................................................................................................... 10 4 Recommended External Components .......................................................................................... 11 5 PCB Layout Guidelines and Power Supply Decoupling .............................................................. 13 6 General Description ........................................................................................................................ 14 6.1 Overview .................................................................................................................................. 14 6.2 AIS System Formats ................................................................................................................ 14 7 Detailed Descriptions ...................................................................................................................... 16 7.1 Clock Source ........................................................................................................................... 16 7.2 Power Supply ........................................................................................................................... 16 7.3 Peripheral Interface ................................................................................................................. 16 7.3.1 Interface Hardware ...................................................................................................... 16 7.3.2 Interface Format........................................................................................................... 16 7.3.3 Operational Mode......................................................................................................... 17 7.3.4 GPS Pass Through ...................................................................................................... 18 7.4 Function ImageTM Load ........................................................................................................... 19 7.4.1 FI Loading from EEPROM ........................................................................................... 19 7.4.2 FI Loading from Host Controller ................................................................................... 20 8 System Description and Tasks ...................................................................................................... 21 8.1.1 Signal Routing .............................................................................................................. 21 8.1.2 Operating Modes ......................................................................................................... 21 8.1.3 Modem and Data Units ................................................................................................ 21 8.1.4 Rx Operation ................................................................................................................ 22 8.2 Configuration Options .............................................................................................................. 22 8.3 RF Synthesiser ........................................................................................................................ 23 8.4 System Clock Synthesisers ..................................................................................................... 26 9 Performance Specification ............................................................................................................. 27 9.1 Electrical Performance ............................................................................................................ 27 9.1.1 Absolute Maximum Ratings ......................................................................................... 27 9.1.2 Operating Limits ........................................................................................................... 28 9.1.3 Operating Characteristics ............................................................................................ 29 9.1.4 Parametric Performance .............................................................................................. 32 9.2 SPI Timing ............................................................................................................................... 33 TABLES Table 1 Table 2 Table 3 Table 4 Definition of Power Supply and Reference Voltages ..................................................................... 10 Component Values ........................................................................................................................ 12 Message Structure ........................................................................................................................ 17 BOOTEN Pin States ...................................................................................................................... 19 2013 CML Microsystems Plc 3 D/7032_FI2.0/9 AIS Rx-only Baseband IC with RF Synthesizer CMX7032 FIGURES Figure 1 CMX7032 FI-2.x Block Diagram .................................................................................................... 6 Figure 2 Typical System Block Diagram ...................................................................................................... 7 Figure 3 CMX7032 FI-2 Recommended External Components ................................................................ 11 Figure 4 CMX7032 Power Supply Connections and De-coupling .............................................................. 13 Figure 5 FI Loading from EEPROM ........................................................................................................... 20 Figure 6 Rx Task Operation ....................................................................................................................... 22 Figure 7 Example RF Synthesiser Components ........................................................................................ 23 Figure 8 Single RF Synthesiser Block Diagram ......................................................................................... 24 Figure 9 System Clock Generation ............................................................................................................ 26 Figure 10 SPI Interface Timing .................................................................................................................. 33 Figure 11 Mechanical outline for 64-pad VQFN package (Q1) .................................................................. 34 Figure 12 Mechanical outline for 64-pin LQFP (leaded) package (L9) ...................................................... 34 1.1 History Version 9 8 7 6 Changes Update which allows GPS baud rate to be set by the state of pin 56 Update to reflect that pins 15 and 16 will be set low or high at the start or end respectively of a received burst to provide channel status indication References to ITU-R M.1371-1 changed to `-4' to reflect the latest version of the specification Update to RF Synthesiser parameters, following evaluation. Addition of operating voltage range clarification (3.0V to 3.6V) into History files Reference to "thickstub" tools being removed from section 7.4.2 added into History files. Contact CML for further help on EEPROM in-circuit programming. Corrected typographical errors in section 9 (VDD, etc). Function ImageTM flowchart (Fig 5) revised to show "$PCML CMX703220nn<cr><lf>" as the data string output after successfully loading the FI. Corrections to BOOTEN pin states, Table 4 Other minor typographical and stylistic updates GPS pass-through sentences updated Power-on reset response updated to include version identification 2013 CML Microsystems Plc 4 Date 11/9/13 29/7/11 18/9/09 9/9/09 D/7032_FI2.0/9 AIS Rx-only Baseband IC with RF Synthesizer 5 4 3 2 1 CMX7032 Correction of FI reference to 2.0 Correction to signal flow direction on SPI bus and addition of C-BUS Mode connection to Block Diagram (Figure 1) Emphasis of unused pins which need to be connected to Vss or Vdd, section 3 Correction to signal flow of Burst_Det and RFVss signals in Figure 3 Reference to potential FI upgrades and version number reporting added to sections 7.3.3 and 7.4 Clarification of required clock frequency for operation of CMX7032 with FI-2.0 in section 9.1.2 Correction of Rx input impedance in parametric specification, section 9.1.3 Correction of N and R division ratio limits in section 9.1.3 Clarification of typical and maximum current consumption in section 9.1.3 Addition/correction of notes 23, 24 and 34 to section 9.1.3 Clarification of operation of b13 in System CLK 1 and 2 registers, section 11.1.3 Change status of FI-2.0.0.2 to full release in section 13 minor editorial changes and clarifications Text references to SYSCLK1 and 2 corrected in section 11. EEPROM registers for RF PLL N/R corrected in Table 4 References to CMX7042 removed Section 11.1.3, default SYSCLK states and operation of b13 corrected EEPROM (not C_BUS) locations - Figure 9 corrected Text regarding HEX files added in section 11 Pin 57 now connected to DVdd. This is required to guarantee reliable operation Pin 29 now connected to AVss. This is required to guarantee reliable operation Pin 56 now connected to DVss. This is required to guarantee reliable operation Information on the Q1 package exposed metal pad added AIS Channel Number added to Table 2 Notes 6 and 7 added to Table 1 Loop filter example changed to coincide with that on DE70321 CLK, RxIN, PLL, Charge Pump parameters updated Tcch parameter updated minor editorial changes and clarifications Original document 2013 CML Microsystems Plc 5 6/10/08 22/9/08 3/9/08 31/1/08 23/7/07 D/7032_FI2.0/9 AIS Rx-only Baseband IC with RF Synthesizer 2 CMX7032 Block Diagram RXDATA UART Detector Buffer TXDATA Receive Functions BURSTDET NMEA 0183 Arbiter and Formatter RX1FB RX1N GMSK Decoder NRZI Decoder HDLC Decoder Rx1 GMSK AIS Buffer Input 1 FSDET1 VBIAS Mux RX2FB RX2N GMSK Decoder VBIAS NRZI Decoder HDLC Decoder Rx2 GMSK AIS Buffer Input 2 FSDET2 Auxiliary Functions Auxiliary System Clocks LNAENA GPIO System Clock 1 SYSCLK1 System Clock 2 SYSCLK2 General Purpose I/O RF1N RF Synthesiser 1 RF1P CP1OUT ISET1 RF Synthesisers RF2N RF Synthesiser 2 RF2P CP2OUT ISET2 RFVDD CPVDD RFVSS RFCLK EPSI EEPROM SPI Port Crystal Oscillator Internal Systems Control CBUSMODE RESETN XTALN BOOTEN2 DVSS VDEC DVDD AVSS VBIAS Boot Control Reg Bias AVDD EPSCSN XTAL/CLK EPSO BOOTEN1 EPSCLK System Control Main Clock Digital PLL Figure 1 CMX7032 FI-2.x Block Diagram 2013 CML Microsystems Plc 6 D/7032_FI2.0/9 AIS Rx-only Baseband IC with RF Synthesizer CMX7032 Figure 2 Typical System Block Diagram 2013 CML Microsystems Plc 7 D/7032_FI2.0/9 AIS Rx-only Baseband IC with RF Synthesizer 3 CMX7032 Signal List CMX7032 64-pin Q1/L9 Pin Name Type 1 - OP reserved: connect to DVDD with a 100k resistor 2 RF1N IP RF Synthesiser #1 Negative Input 3 RF1P IP RF Synthesiser #1 Positive Input 4 RFVSS PWR 5 CP1OUT OP 1st Charge Pump output 6 ISET1 IP 1st Charge Pump Current Set input 7 RFVDD PWR 8 RF2N IP RF Synthesiser #2 Negative Input 9 RF2P IP RF Synthesiser #2 Positive Input 10 RFVSS PWR 11 CP2OUT OP 2nd Charge Pump output 12 ISET2 IP 2nd Charge Pump Current Set input 13 CPVDD PWR 14 RFCLK IP RF Clock Input (common to both synthesisers)1 15 FSDET1 OP Frame Sync Detect 1 - goes low upon detecting the start flag of a received burst on Channel 1 and high at the end of the burst2 16 FSDET2 OP Frame Sync Detect 2 - goes low upon detecting the start flag of a 2 received burst on Channel 2 and high at the end of the burst 17 - NC reserved - do not connect this pin 18 VDEC PWR 19 - NC reserved - do not connect this pin 20 SYSCLK1 OP Synthesized Digital System Clock Output 1 21 DVSS PWR 22 - NC reserved - do not connect this pin 23 LNAENA OP LNA_enable: active lo when demodulator is running 24 RX1N IP Rx1 inverting input 25 RX1FB OP Rx1 input amplifier feedback 26 RX2N IP Rx2 inverting input 27 RX2FB OP Rx2 input amplifier feedback Description The negative supply rail (ground) for the RF synthesisers The 2.5V positive supply rail for the RF synthesisers. This should be decoupled to RFVSS by a capacitor mounted close to the device pins. The negative supply rail (ground) for the 2nd RF synthesiser The 3.3V positive supply rail for the RF charge pumps. This should be decoupled to RFVSS by a capacitor mounted close to the device pins Internally generated 2.5V digital supply voltage. Must be decoupled to DVSS by capacitors mounted close to the device pins. No other connections allowed, except for optional connection to RFV DD. Digital Ground 1 To minimise crosstalk, this signal should be connected to the same clock source as XTAL/CLK input. By default, this is connected internally at power-on, alternatively, this may be achieved by connecting the pin to the XTALN output when a 19.2MHz source is in use. 2 Internal filtering and processing delays should be taken into account when evaluating timings. 2013 CML Microsystems Plc 8 D/7032_FI2.0/9 AIS Rx-only Baseband IC with RF Synthesizer CMX7032 CMX7032 64-pin Q1/L9 Pin Name Type 28 - NC reserved - do not connect this pin 29 - IP reserved: connect to AVSS 30 AVSS PWR 31 - NC reserved - do not connect this pin 32 - NC reserved - do not connect this pin Description Analogue Ground 33 VBIAS OP Internally generated bias voltage of about AV DD/2, except when the device is in `Powersave' mode when VBIAS will discharge to AVSS. Must be decoupled to AVSS by a capacitor mounted close to the device pins. No other connections allowed. 34 - NC reserved - do not connect this pin 35 - NC reserved - do not connect this pin 36 - NC reserved - do not connect this pin 37 - NC reserved - do not connect this pin 38 - NC reserved - do not connect this pin 39 AVDD PWR 40 - NC reserved - do not connect this pin 41 - NC reserved - do not connect this pin 42 AVSS PWR 43 - NC reserved - do not connect this pin 44 - NC reserved - do not connect this pin 45 VDEC PWR 46 XTAL/CLK IP 19.2MHz input from the external clock source 47 XTALN OP The output of the on-chip Xtal oscillator inverter. NC as a 19.2MHz Clock source is used 48 DVDD PWR Digital +3.3V supply rail. This pin should be decoupled to DV SS by capacitors mounted close to the device pins 49 RXDATA IP 50 TXDATA TS OP RS232: Serial data output in NMEA 0183-HS format 51 RESETN IP+PU Reset Input 52 DVSS PWR Digital Ground 53 - NC reserved - do not connect this pin 54 BURSTDET OP AIS Burst detected - active lo 55 SYSCLK2 OP Synthesised Digital System Clock Output 2 56 GPSRATE IP Determines the GPS baud rate. For 4800 baud connect to DVSS, for 38400 baud connect to DVDD via a 47k resistor. 2013 CML Microsystems Plc Analogue +3.3V supply rail. Levels and thresholds within the device are proportional to this voltage. This pin should be decoupled to AV SS by capacitors mounted close to the device pins. Analogue Ground Internally generated 2.5V supply voltage. Must be decoupled to DV SS by capacitors mounted close to the device pins. No other connections allowed, except for the optional connection to RFV DD. RS232: Serial data input from the C/GPS 9 D/7032_FI2.0/9 AIS Rx-only Baseband IC with RF Synthesizer CMX7032 CMX7032 64-pin Q1/L9 Pin Name 57 CBUSMODE 58 EPSI OP EEPROM Serial Interface: SPI bus Output 59 EPSCLK OP EEPROM Serial Interface: SPI bus Clock 60 EPSO IP+PD EEPROM Serial Interface: SPI bus Input 61 EPSCSN OP 62 BOOTEN1 IP+PD Used in conjunction with BOOTEN2 to determine the operation of the bootstrap program 63 BOOTEN2 IP+PD Used in conjunction with BOOTEN1 to determine the operation of the bootstrap program 64 DVSS PWR Digital Ground EXPOSED METAL PAD SUB ~ Type IP+PD Description Connect to DVDD EEPROM Serial Interface: SPI bus Chip Select On Q1 packages only : the central metal pad may be connected to Analogue Ground (AVSS) or left unconnected. No other electrical connection is permitted. Notes: IP OP TS OP PWR NC = = = = = Input (+PU/PD = internal pullup/pulldown resistor) Output 3-state Output Power Supply Connection No Connection 3.1 Signal Definitions Table 1 Definition of Power Supply and Reference Voltages Signal Name AVDD DVDD RFVDD CPVDD VDEC VBIAS AVSS DVSS RFVSS Pins AVDD DVDD RFVDD CPVDD VDEC VBIAS AVSS DVSS RFVSS 2013 CML Microsystems Plc Usage Power supply for analogue circuits Power supply for digital circuits Power supply for RF synthesiser circuits Power supply for RF charge pump Power supply for core logic, derived from DVDD by on-chip regulator Internal analogue reference level, derived from AVDD Ground for all analogue circuits Ground for all digital circuits Ground for all RF circuits 10 D/7032_FI2.0/9 AIS Rx-only Baseband IC with RF Synthesizer Recommended External Components 2 3 RESETN TXDATA IC3 PSS XC6101 1 IC2 EEPROM 25HP512 IC4 RS232/422 Buffer 4 5 CBUSMODE 5 6 DVDD 7 8 DVDD DVSS 4 CMX7032 R9 RXDATA 49 50 51 52 BURSTDET 53 56 57 58 59 60 61 37 13 36 14 35 15 34 16 33 VDEC C23 C21 C22 XTAL/CLK VDEC C3 DVSS AVss C17 C18 AVDD C19 VBIAS 32 38 12 31 39 11 C24 C20 40 10 17 RFCLK CMX7032Q1/L9 9 30 FSDET2 41 29 RFVss 42 8 28 FSDET1 43 7 RX1FB 25 RX2N 26 RX2FB 27 C25 C26 6 24 ISET2 44 RX1N CP2OUT RFVss CPVDD 45 5 23 RF2P 4 LNAENA RF2N 46 22 C27 3 21 C28 ISET1 47 20 RFVss RFVDD 2 SYSCLK1 CP1OUT 48 19 RF1P DVDD 1 18 RF1N 62 R1 DVss 63 64 DVDD 55 SYSCLK2 DVss 54 2 4 3 1 GPSRATE DVDD C7 AVss C12 DVSS R5 R6 C13 R7 R8 Figure 3 CMX7032 FI-2 Recommended External Components 2013 CML Microsystems Plc 11 D/7032_FI2.0/9 AIS Rx-only Baseband IC with RF Synthesizer CMX7032 Table 2 Component Values R1 R5 R6 R7 R8 R9 100k 100k - note 2 100k 100k - note 3 100k 47k - note 8 C3 C4 C7 C12 C13 C17 C18 C19 C20 10nF not fitted 100nF 47pF 47pF 10F 10nF 10nF 10F C21 C22 C23 C24 C25 C26 C27 C28 10nF 10nF 10nF 10F 10nF 10F 10nF 10F IC2 IC3 IC4 XTAL/CLK 25HP512 XC6101 ADM1385 19.2MHz See note 1 Resistors 5%, capacitors and inductors 20% unless otherwise stated. Notes: 1. 2. 3. 4. 5. 6. 7. 8. CLK is a 19.2MHz external clock generator. R5 should be selected to provide the desired dc gain of the input, as follows: GAINRX1N = 100k / R5 The gain should be such that the resultant output at the RX1FB pin is within the input signal range specified in 9.1.3. R7 should be selected to provide the desired dc gain of the input as follows: GAINRX2N = 100k / R7 The gain should be such that the resultant output at the RX2FB pin is within the input signal range specified in 9.1.3. Care should be taken in connecting the output of the Limiter-Discriminator device to the Rx input pins of the CMX7032. The format of the GMSK signal requires that the frequency response of the input circuits extends to below 10Hz, however the variations in the incoming AIS signals from many different stations require that the input must rapidly follow the changes in dc and signal levels without de-grading the signal seen at the Rx input pins. C12 and C13 should be chosen to minimise the phase distortion of the input signal and provide a flat amplitude response up to at least 4800Hz. A single 10F electrolytic capacitor (C24, fitted as shown) may be used for smoothing the power supply to both VDEC pins, providing they are connected together on the pcb with an adequate width power supply trace. Alternatively, separate smoothing capacitors should be connected to each VDEC pin. High frequency decoupling capacitors (C3 and C23) must always be fitted as close as possible to both V DEC pins. The BOOTEN pins (pins 62 and 63) are configured in this diagram for loading from EEPROM, other loading modes are available see section 7.4. Pin 56 (GPSRATE) - connect to DVSS or pull high to DVDD via R9. 2013 CML Microsystems Plc 12 D/7032_FI2.0/9 AIS Rx-only Baseband IC with RF Synthesizer 5 CMX7032 PCB Layout Guidelines and Power Supply Decoupling Figure 4 CMX7032 Power Supply Connections and De-coupling Component Values as per Table 2. Notes: 1. It is important to protect the analogue pins from extraneous inband noise and to minimise the impedance between the CMX7032 and the supply and bias de-coupling capacitors. The supply decoupling capacitors should be as close as possible to the CMX7032. It is therefore recommended that the printed circuit board is laid out with separate ground planes for the AV SS, RFVSS and DVSS supplies in the area of the CMX7032, with provision to make links between them close to the CMX7032. Use of a multi-layer printed circuit board will facilitate the provision of ground planes on separate layers. 2. The central metal pad (which is exposed on Q1 package only) may be electrically unconnected or, alternatively, may be connected to Analogue Ground (AVSS). No other electrical connection is permitted. 3. VBIAS is used as an internal reference for detecting and generating the various analogue signals. It must be carefully decoupled to ensure its integrity so, apart from the decoupling capacitor shown, no other loads should be connected. If VBIAS needs to be used to set the discriminator mid-point reference, it must be buffered with an external high input impedance buffer. 4. The 2.5V VDEC output can be used to supply the 2.5V RFV DD, to remove the need for an external 2.5V regulated supply. VDEC can be directly connected to RFVDD. 2013 CML Microsystems Plc 13 D/7032_FI2.0/9 AIS Rx-only Baseband IC with RF Synthesizer 6 CMX7032 General Description 6.1 Overview Rx Modem Functions Fixed modulation format: o AIS 25kHz channel (GMSK, 9600bps, 2.4kHz deviation, BT=0.4) Simultaneous reception of two AIS channels AIS Burst mode with full AIS frame formatting (HDLC-type) o Frame sync recognition o Bit de-stuffing o NRZI decoding o Training sequence and start/stop flag detection o CRC checking Four 160 byte Rx data buffers can automatically store up to four 5-slot AIS bursts (2 per Rx channel) Rx signal input gain 100 - 600 MHz RF Synthesisers Two Integer-N synthesisers Flexible design minimizes reference spurs for low phase noise results Charge pump o High/low soft selectable current setting to speed large frequency channel changes o Nominal current user defined by external resistor value I/O Functions Output port to enable external LNA circuit Output port to indicate valid AIS burst received System Functions All internal subsystems are controlled from the Function ImageTM so removing the need for a host C Internal system clocks derived from RF synthesiser reference oscillator eliminate the need for additional clock oscillator(s) User clock synthesisers generate two clocks for external use Function ImageTM loads and executes directly from low-cost EEPROM Integrated 2.5V regulator can develop 2.5V from required 3.3V supply RS232 interface allows external GPS input to be connected and the data passed-through to the peripheral device. The GPS baud rate is selectable to either 4800 or 38400 baud. 6.2 AIS System Formats The AIS system uses two basic channel access mechanisms - Self Organising Time Division Multiple Access (SOTDMA) and Carrier-Sensing Time Division Multiple Access (CSTDMA). The 7032FI-2.0 is compatible with both systems. The SOTDMA system is detailed in ITU-R M.1371-4 and IEC 61993-2 while the CSTDMA is detailed in IEC 62287. The CSTDMA system is used in the implementation of the Class B-CS AIS. This requires the Receiver to monitor the first part of a slot for an existing AIS transmission from another station before deciding to use the slot for its own transmission or aborting and selecting a different slot. The SOTDMA system is used in the Class A and Base Station AIS as well as the Class B-SOTDMA AIS standard. 2013 CML Microsystems Plc 14 D/7032_FI2.0/9 AIS Rx-only Baseband IC with RF Synthesizer CMX7032 The device will transfer all currently known AIS messages and formats, it is the peripheral device that must convert them into the relevant format for the user. The relevant International standards are: [0] ITU-R M.1371-4 [1] IEC 61993-2 Class A [2] IEC 62287-1 Class B CSTDMA [3] IEC 62287-2 Class B SOTDMA [4] IEC 62320-1 Base Station [5] IEC 62320-2 Aids to Navigation [6] IEC 61162 NMEA data format 2013 CML Microsystems Plc 15 D/7032_FI2.0/9 AIS Rx-only Baseband IC with RF Synthesizer 7 CMX7032 Detailed Descriptions 7.1 Clock Source The 7032FI-2.x must be used with a 19.2MHz oscillator. The RFCLK on the CMX7032 should also be derived from this source to avoid the generation of unwanted spurious signals. The default settings route the RFCLK directly from the XTAL/CLK pin internally, so no external connection is required in this configuration. 7.2 Power Supply The CMX7032 is designed to function using the VDD values shown in section 9.1.2. To achieve the published performance figures it is necessary to ensure that all power supplies are adequately de-coupled to remove spurious signals or noise. The CMX7032 stores the Function ImageTM internally in static RAM, therefore it is imperative that DVDD is maintained at all times to ensure the correct operation of the device. It is recommended that an external power supply supervisor is connected to the RESETN pin so that the device can be reset to its default state in the event of the power supply voltage being outside the specified levels (brown-out protection). Care should be taken in the design of the power supply circuits to ensure that DVDD power-on rise time characteristic allows the BOOTEN pins to achieve their correct state before the device becomes active. 7.3 Peripheral Interface This section provides a general description of the RS232 serial interface protocol used to transfer data between the CMX7032, used with 7032FI-2.x, and the peripheral device. 7.3.1 Interface Hardware The 7032FI-2.x receives AIS data bursts and after extracting the information from them, re-formats them into the NMEA 0183 format as defined in IEC 62287, IEC 61993 and IEC 61162 and outputs them on the TXDATA pin of the RS232 UART at 38400 baud, 8 bits, no parity. No hardware or software handshaking is implemented. A suitable level shifter/inverter/buffer should be used to interface this signal to the peripheral device for true RS232 or RS422 compatibility. 7.3.2 Interface Format The 7032FI-2.x will only output data if the AIS burst has been correctly decoded with a valid CRC field. All bursts that have detected errors will be discarded. All error-free bursts will be presented at the TXDATA pin, irrespective of their data content, up to the maximal length of the data buffer, therefore it is the responsibility of the peripheral device to decode the NMEA 0183 data message as appropriate. This ensures that any changes or additions to the AIS messages or structures will not adversely affect the operation of the 7032FI-2.x. The 7032FI-2.x has been successfully tested with a number of commercial PC-based and PDA software packages3. The NMEA message structure is defined in IEC 61162 for AIS applications using the "encapsulated message" format, as shown in Table 3. 3 See www.shipplotter.com for a suitable PC-based software package. Others are available. 2013 CML Microsystems Plc 16 D/7032_FI2.0/9 AIS Rx-only Baseband IC with RF Synthesizer CMX7032 Table 3 Message Structure !AIVDM,x1,x2,x3,a,c--c,x4*hh<CR><LF> ASCII ! AIVDM , x1 HEX 21 2C x2 x3 a c--c x4 * 2A hh cr lf 0D 0A Description Start of Sentence: starting delimiter. Address Field: identifying type of talker and sentence format. Field Delimiter: starts each field except address and checksum fields. Total Number of Sentences field: encapsulated information often requires more than one sentence. Sentence Number Field: identifies which sentence of the total number of sentences this is. Sequential Message Identifier Field: field is incremented each time an encapsulated message is generated with the same formatter as a previously encapsulated message. AIS Channel (A or B) Data Sentence Block: AIS data coded as 6-bit fields. Fill Bits Field: represents the number of fill bits added to complete the last six-bit coded character. Checksum Delimiter: indicates that the following two alphanumeric characters show the HEX value of the checksum. Checksum Field: calculated by exclusive-OR'ing the 8 data bits (no start bits or stop bits) of each character in the sentence, between, but excluding "!" and "*". The hexadecimal value of the most significant and least significant 4 bits of the result are converted to two ASCII characters (0-9, A-F (upper case)) for transmission. Carriage return. Line feed. The message has a maximum length of 80 characters, which can be easily exceeded by an AIS message, so the multi-sentence feature is used in most cases. Some peripheral equipment is available which can handle messages in excess of the standard limit, in which case a bit in the User Configuration register can be used to instruct the CMX7032 to ignore the limit and produce a single sentence. This feature can increase the efficiency of the RS232 interface but should be used with caution. 7.3.3 Operational Mode The 7032FI-2.x has no user selectable modes of operation. It is entirely autonomous in its operation and if the device is configured to load the FI from EEPROM, then there is no host or controller interaction required. Once the device has powered up, it will check the BOOTEN pins for their status, and if set for EEPROM mode, will load the FI automatically. Once successfully loaded, it will output the proprietary NMEA 0183 data string: $PCML CMX7032-2010<cr><lf> to indicate that it is now operating. The User Configuration registers will then be read and the SYSCLKs and RF PLLs set up accordingly. (Note: FI version 2.0.0.2 does not report the version number in the data string). As soon as the start of a burst is detected on either channel at the RX1N and RX2N inputs, the FSDET1 or FSDET2 pin will be set low until the end of the received burst. These pins therefore act as channel status indicators and will behave in the same way regardless of the message type (valid, invalid or corrupt). The device will then begin to attempt to decode the signal and once a valid preamble and start flag has been detected, place the received data into its internal buffer. On reception of a stop flag it will then decode the data and check the received checksum field. If the checksum indicates that the message has been received with no errors, it will then be passed to the NMEA formatter and placed in the output buffer. The device will automatically return to decoding signals at its input. Note that should a stop flag not be detected within the maximum allowed AIS message length, then the decode process will be reset and restarted automatically. The conditions that result in a message being discarded are: 2013 CML Microsystems Plc 17 D/7032_FI2.0/9 AIS Rx-only Baseband IC with RF Synthesizer CMX7032 Message too long or missing end flag This indicates that the received message, after bit de-stuffing, is too long to fit into the internal message buffer. This condition could be caused by a missing or corrupted end flag. CRC mismatch This indicates that the received frame checksum does not match that calculated by the CMX7032, most probably as the result of one or more message bits being corrupted. New frame header found when message buffer full This happens if the internal message buffers are still in use when another message arrives. End flag not on byte boundary This indicates that the received message, after bit de-stuffing, is not a multiple of 8 bits. Assuming that the message was transmitted correctly, probably caused by an end flag being missed due to noise, and a subsequent message's start flag being mis-identified as the expected end flag or a bit error causing the bit de-stuffer to fail. This process is performed on both Rx channels in parallel, but the NMEA data formatter will present the first decoded message to the RS232 UART while holding the second message in its internal buffer so that no data is lost. As there is no provision for handshaking on the UART, the peripheral device must be capable of reading the data back at the full 38400 baud rate, otherwise some data may be lost or the message corrupted. An active low pulse will be output on the BURSTDET pin when an AIS message is being transmitted over the RS232 port. 7.3.4 GPS Pass Through Many applications (eg: chart plotter) also require an input from a positioning device. This is usually accomplished using a GPS unit. If the peripheral device has a limited number of communications ports, it is possible to attach the GPS sensor to the CMX7032 RS232 input, where it is turned round, so as to present both GPS and AIS data to the peripheral device on the IC's RS232 output. Whenever the device is not actively outputting received AIS data, it will monitor the RXDATA pin for a valid GPS NMEA sentence (at either 4800 or 38400 baud, depending on the setting of pin 56). If a message with a valid GPS identifier is found, it will be placed in the buffer and be output on the TXDATA pin at 38400 baud. Note that while the 7032FI-2.x is receiving data on the RXDATA pin it cannot output AIS data on the TXDATA pin at the same time due to the difference in baud rates. For this reason, the GPS sentences are checked for a valid header so that the 7032FI-2.x can return to AIS output mode as soon as possible, so as to avoid buffer over-runs and potential loss of AIS data on a busy channel. The valid GPS identifiers that are checked for are: o $--GGA o $--GLL o $--GSA o $--GSV o $--RMC o $--VTG o $--DSC o $--DSE All other messages are discarded Once a message from the GPS has been received by the device, it will check the AIS buffers for data. This means that if the GPS sends multiple messages in quick succession, some may be ignored in preference to the AIS data. 2013 CML Microsystems Plc 18 D/7032_FI2.0/9 AIS Rx-only Baseband IC with RF Synthesizer CMX7032 7.4 Function ImageTM Load The Function ImageTM (FI) file, which defines the operational capabilities of the device, may be obtained from the CML Technical Portal, following registration. This is in the form of a 'C' header file which can be included into the host controller software or an Intel HEX file which can be programmed into an external TM EEPROM. The maximum possible size of Function Image is 46kbytes, although a typical FI will be less than this. Note that the BOOTEN pins are only read at power-on or after the RESETN pin returns high and must remain stable throughout the FI loading process. Once the FI load has completed, the BOOTEN pins are ignored by the CMX7032 until the next power-up. Each time the device is powered up its Function ImageTM must first be loaded. This assigns internal device resources and determines all device features. The device does not operate until the Function ImageTM is loaded. The BOOTEN pins are both fitted with internal 100k (approx.) pull down resistors. For EEPROM load, only BOOTEN1 needs to be pulled high, however, if it is required to program the EEPROM in-situ from the host, either jumpers to VDD or links to host I/O pins should be provided (see Table 4). Note that the BOOTEN pins MUST be in a valid state at power-up. Once the FI has been loaded, the CMX7032 performs these actions: (1) the product identification code and FI version number is reported e.g $PCML CMX70322010. (The 2.0.0.2 release does not include the version number). (2) LNAENA output pin is cleared to 0. If an invalid device is detected, the device will become unresponsive and a power-on reset is required to recover from this state. Table 4 BOOTEN Pin States RS232 Host load reserved EEPROM load No FI load Note: BOOTEN2 1 1 0 0 BOOTEN1 1 0 1 0 DVDD MUST be maintained at all times to preserve the Function ImageTM data. If DVDD is suspected of exceeding the specification limits, then a full power-on reset and an FI re-load should be performed to maintain the integrity of the device. 7.4.1 FI Loading from EEPROM If the `C' header file is used then the FI must be converted into a format suitable for the EEPROM programmer (normally Intel Hex) and loaded into the EEPROM either by a host or an external programmer. Alternatively, the CML Technical Portal also holds an Intel HEX file of the same FI. Any changes to the User Configuration registers must be completed before programming the EEPROM, either by changing the `C' header file or the data in the EEPROM programmer's buffer. The CMX7032 needs to have the BOOTEN pins set to EEPROM load, and then on power-on, the CMX7032 will automatically load the data from the EEPROM. 2013 CML Microsystems Plc 19 D/7032_FI2.0/9 AIS Rx-only Baseband IC with RF Synthesizer CMX7032 BOOTEN2=0 BOOTEN1=1 Power-up/Reset CMX7032 Wait for "$PCML CMX7032-20nn<cr><lf>" to appear on the RS232 / NMEA 0183 output (where nn is the FI version number) CMX7032 is now ready for use VDD note: BOOTEN1 and BOOTEN2 may be changed at this point, if required BOOTEN1 BOOTEN2 Jumpers for programming EEPROM (if required) Figure 5 FI Loading from EEPROM The CMX7032 has been designed to function with Atmel AT25HP512 serial EEPROM and the ATF512 flash EEPROM devices4, however other manufacturers' parts may also be suitable. The time taken to load the FI is dependant on the XTAL/CLK source frequency, but should be less than 500ms. 7.4.2 FI Loading from Host Controller The FI can be included into a host controller software build and downloaded into the CMX7032 at powerup over the RS232 interface. The BOOTEN pins must be set to the RS232 load configuration, the XTAL/CLK source set to 6.144MHz and the CMX7032 powered up. The data can then be sent directly over the RS232 to the CMX7032 at 115200baud. Following a successful FI load, the XTAL/CLK source should be returned to 19.2MHz to ensure correct operation. Further details of the data format and process are available through the CML Technical Portal. 4 Note that these two memory devices have slightly different addressing schemes. FI-2.x is compatible with both schemes. 2013 CML Microsystems Plc 20 D/7032_FI2.0/9 AIS Rx-only Baseband IC with RF Synthesizer 8 CMX7032 System Description and Tasks This section describes the operation of main sections of the 7032FI-2.x and the interface provided to the external device(s). 8.1.1 Signal Routing The 7032FI-2.x provides processing capability for two simultaneous AIS receive channels which are allocated to the RX1N and RX2N pins of the device. Both of these inputs are configured around an inverting op-amp stage to facilitate gain and filtering adjustments. 8.1.2 Operating Modes The 7032FI-2.x automatically enters into its Operating mode when the Function Image TM has been successfully loaded. If the 7032FI-2.x does not load correctly the device will not operate. 8.1.3 Modem and Data Units The 7032FI-2.x is logically divided into two main units, each of which can accept and perform tasks separately: o Modem Unit o Data Unit The Modem Unit is primarily responsible for processing the Rx input signals to recover the Rx data they represent and storing that data in the internal Rx data buffers. The Data Unit is primarily responsible for transferring and arbitrating data from the internal data buffers (including the external GPS input) to the RS232 interface and converting the data into NMEA 0183 format. 2013 CML Microsystems Plc 21 D/7032_FI2.0/9 AIS Rx-only Baseband IC with RF Synthesizer CMX7032 8.1.4 Rx Operation Typical stages of Rx task operation are depicted in Figure 6 and occur as follows: 1. A Modem task is automatically started on power up and continues to run indefinitely. This instructs the IC to transfer any received data from the Rx1/2 Modems to the Rx1/2 Data Buffers. 2. The RxBRDY flags indicate to the Data Arbiter that data is ready and outputs it to the RS232 UART in NMEA 0183 format. 3. After the data has been sent, the Data Arbiter will re-check the Rx1/2 Data Buffers for valid data and output it as in Step 2. 4. If there is no data in Rx1/2 data buffers, the Data Arbiter will re-set the RS232 UART to 4800 baud and check for valid GPS data. If valid GPS data is detected, it will be loaded into the GPS data buffer and when complete, will be re-output at 38400baud. GPS Data checker GPS Data Buffer RS232 UART Rx Data Buffer (88 words) sw sw demodulator Rx Data Buffer (88 words) Data arbiter and NMEA formatter R1BRDY R1OVF R2OVF RxState R2BRDY Rx Data Buffer (88 words) sw sw demodulator Rx Data Buffer (88 words) Figure 6 Rx Task Operation 8.2 Configuration Options The device allows some of its parameters to be configured to a particular target application by changing the values of the User Configuration register locations of the FI (see User Manual section 10). o RF PLL 1 o RF PLL 2 o SysCLK1 o SysCLK2 o NMEA 0183 sentence mode 2013 CML Microsystems Plc 22 D/7032_FI2.0/9 AIS Rx-only Baseband IC with RF Synthesizer CMX7032 8.3 RF Synthesiser The CMX7032 includes two Integer-N RF synthesisers, each comprising a divider, phase comparator and charge pump. The divider has two sets of N and R registers: one set can be used for transmit and the other for receive. The division ratios can be set up by means of the User Configuration registers in the FI. External RF components are needed to complete the synthesiser circuit. A typical schematic for one synthesiser, with external components, is shown in Figure 7. Figure 7 Example RF Synthesiser Components R31 R32 R33 0 820R 0 C31 C32 C33 C34 C35 68nF 470nF Not Fitted 1nF 1nF Resistors 5%, capacitors and inductors 20% unless otherwise stated. Note: R31 is chosen within the range 0 to 30k and selects the nominal charge pump current. It is recommended that C34 and C35 are kept close to the VCO and that the stub from the VCO to the CMX7032 is kept as short as possible. The loop filter components should be placed close to the VCO. 2013 CML Microsystems Plc 23 D/7032_FI2.0/9 AIS Rx-only Baseband IC with RF Synthesizer CMX7032 Figure 8 Single RF Synthesiser Block Diagram The two RF synthesisers are programmable to any frequency in the range 100MHz to 600MHz. Figure 8 is a block diagram of one synthesiser channel. The RF synthesiser clock is the same 19.2MHz clock as is used by the baseband circuitry. The RF synthesiser clock is common to both channels. The charge pump supply ( CPVDD) is also common to both channels. The RF input pins (RFnN and RFnP), CPnOUT, ISETn and RFVSS pins are channel specific and designated as either RF1P, RF1N, CP1OUT, ISET1, RFV SS or RF2P, RF2N, CP2OUT, ISET2, RFVSS on the Signal List in section 3. The N and R values for Tx and Rx modes are channel specific. The divide by N counter is 20 bits; the R counter is 13 bits. Typical external components are shown in Figure 7. Both synthesisers are phase locked loops (PLLs) of the same design, utilising external VCOs and loop filters. The VCOs need to have good phase noise performance although it is likely that the high division ratios used will result in the dominant noise source being the reference oscillator. The phase detectors are of the phase-frequency type with a high impedance charge pump output requiring just passive components in the loop filter. Two levels of charge pump gain are available to the user, to facilitate the possibility of locking at different rates under program control. A current setting resistor (R31) is connected between the ISETn pin (one for each PLL system) and the respective RFVSS. This resistor will have an internally generated band gap voltage expressed across it and may have a value of 0 to 30k, which (in conjunction with the on-chip series resistor of 9.6k) will give charge pump current settings over a range of 2.5mA down to 230A (including the control bit variation of 4 to 1). The value of the current setting resistor (R31) is determined in accordance with the following formulae: gain bit set to 1: R31 (in ) = (24/Icp) - 9600 gain bit cleared to 0: R31 (in ) = (6/Icp) - 9600 where Icp is the charge pump current (in mA). Note that the charge pump current should always be set to at least 230A. The 'gain bit' refers to either bit 3 or bit 11 in the RF Synthesiser Control register. The step size (comparison frequency) is programmable; to minimise the effects of phase noise this should be kept as high as possible. This can be set as low as 2.5kHz (for a reference input of 20MHz or less), or up to 200kHz - limited only by the performance of the phase comparator. 2013 CML Microsystems Plc 24 D/7032_FI2.0/9 AIS Rx-only Baseband IC with RF Synthesizer CMX7032 The frequency for each synthesiser is set by using two registers: an `R' register that sets the division value of the input reference frequency to the comparison frequency (step size), and an `N' register that sets the division of the required synthesized frequency from the external VCO to the comparison frequency. This yields the required synthesized frequency (Fs), such that: Fs = (N / R) x FREF where FREF is the selected reference frequency Other parameters for the synthesisers are the charge pump setting (high or low) Since the set-up for the PLLs takes 4 x "RF Synthesiser Data register" writes it follows that, while updating the PLL settings, the registers may contain unwanted or intermediate values of bits. These will persist until the last register is written. The names "Tx" and "Rx" are arbitrary and may be assigned to other functions as required. They are independent sets of registers, one of which is selected to command each PLL by changing the settings in the RF Synthesiser Control register. For optimum performance, a common master clock should be used for the RF synthesisers (RFCLK) and the baseband sections (Main and Auxiliary System Clocks). Using unsynchronised clocks can result in spurious products being generated in the synthesiser output and in some cases difficulty may be experienced with obtaining lock in the RF synthesisers. The 7032FI-2.x is configured to use the internal clock for both RF synthesisers by default. Lock Status The lock status is not available on this FI. RF Inputs The RF inputs are differential and self-biased (when not powersaved). They are intended to be capacitively coupled to the RF signal. The signal should be in the range 0dBm to -20dBm (not necessarily balanced). To ensure an accurate input signal the RF should be terminated with 50 as close to the chip as possible and with the "P" and "N" inputs capacitively coupled to the input and ground, keeping these connections as short as possible. The RF input impedance is almost purely capacitive and is dominated by package and printed circuit board parasitics. Guidelines for using the RF Synthesisers RF input slew rate (dv/dt) should be 14 V/s minimum. The RF Synthesiser 2.5V digital supply (RFVDD) can be powered from the VDEC output pin. RF clock sources and other, different clock sources must not share common IC components, as this may introduce coupling into the RF. Unused ac-coupled clock buffer circuits should be tied to a dc supply, to prevent them oscillating. By default the RF clock source is routed to the XTAL/CLK input internally. It is recommended that the RF Synthesisers are operated with maximum gain Iset (ie. ISETn tied to RFVSS). The loop components should be optimised for each VCO. 2013 CML Microsystems Plc 25 D/7032_FI2.0/9 AIS Rx-only Baseband IC with RF Synthesizer CMX7032 8.4 System Clock Synthesisers Two System Clock outputs, SYSCLK1 and SYSCLK2, are available to drive additional circuits, as required. These are phase locked loop (PLL) clocks that can be programmed via the System Clock registers in the User Configuration block of the FI. The System Clock PLL Configuration registers control the values of the VCO Output divider and Main Divide registers, while the System Clock Ref. Configuration registers control the values of the Reference Divider and signal routing configurations. The PLLs are designed for a comparison frequency of 96kHz. The System Clock output divider stages are designed so that they have a 1:1 Mark-to-Space ratio when an even divide number is selected. to RF Synthesiser Ref CLK selection LPF Ref CLK div /1 to 512 $9FE4:b0 $9FE5 PD SysCLK1 SysCLK1 Ref Div 48 - 192kHz (96kHz typ) SysCLK1 VCO 24.57698.304MHz (49.152MHz typ) VCO PLL div /1 to 1024 $9FE2:b0-1 $9FE3 SysCLK1 Pre-CLK $9FE4:b3-7 LPF Ref CLK div /1 to 512 $9FE8:b0 $9FE9 PD SysCLK2 SysCLK2 Ref Div 48 - 192kHz (96kHz typ) SYSCLK1 Output 384kHz-50MHz SysCLK2 VCO 24.57698.304MHz (49.152MHz typ) VCO PLL div /1 to 1024 $9FE6:b0-1 $9FE7 SysCLK2 Pre-CLK $9FE8:b3-7 OSC VCO op div /1 to 64 $9FE2:b2-7 VCO op div /1 to 64 $9FE6:b2-7 SYSCLK2 Output 384kHz-50MHz Internal Main Clock External 19.2MHz Clock Figure 9 System Clock Generation The 7032FI-2.x XTAL/CLK input should be driven by an externally generated 19.2MHz clock, in which case the default settings following FI load will provide 9.6MHz and 19.2MHz clock sources. 2013 CML Microsystems Plc 26 D/7032_FI2.0/9 AIS Rx-only Baseband IC with RF Synthesizer 9 CMX7032 Performance Specification 9.1 Electrical Performance 9.1.1 Absolute Maximum Ratings Exceeding these maximum ratings can result in damage to the device. Min. 0.3 0.3 0.3 0.3 0.3 0.3 0.3 30 Max. 4.5 4.5 4.5 4.5 DVDD + 0.3 AVDD + 0.3 RFVDD + 0.3 +30 Unit V V V V V V V mA 20 +20 mA 0 0 0 0 0.3 0.3 50 50 V V mV mV All Packages Storage Temperature Operating Temperature Min. 55 40 Max. +125 +85 Unit C C Q1 Package (64-pad VQFN) Total Allowable Power Dissipation at Tamb = 25C ... Derating L9 Package (64-pin LQFP) Total Allowable Power Dissipation at Tamb = 25C ... Derating Min. - - Min. - - Max. 3500 35 Max. 1690 16.9 Unit mW mW/C Unit mW mW/C Supply: DVDD- DVSS AVDD- AVSS RFVDD- RFVSS CPVDD- RFVSS Voltage on any pin to DVSS Voltage on any pin to AVSS Voltage on any pin to RFVSS (excluding CPVDD) Current into or out of any power supply pin (excluding VBIAS) (i.e. VDEC, AVDD, AVSS, DVDD, DVSS, CPVDD, RFVDD or RFVSS) Current into or out of any other pin Voltage differential between power supplies: DVDD and AVDD or CPVDD AVDD and CPVDD DVSS and AVSS or RFVSS AVSS and RFVSS 2013 CML Microsystems Plc 27 D/7032_FI2.0/9 AIS Rx-only Baseband IC with RF Synthesizer CMX7032 9.1.2 Operating Limits Correct operation of the device outside these limits is not implied. Supply Voltage: DVDD - DVSS AVDD - AVSS CPVDD - RFVSS RFVDD - DVSS VDEC - DVSS Operating Temperature Clock Frequency (CMX7032 device with FI-2.0 loaded) 1 2 3 4 Min. Max. Unit 1 2 3.0 3.0 3.0 2.25 2.25 40 19.2MHz 20ppm 3.6 3.6 3.6 2.75 2.75 +85 19.2MHz + 20ppm V V V V V C 0 46 kBytes 3 Function Image size Notes: Notes 4 The VDEC supply is automatically created from DVDD by the on-chip voltage regulator. The RFVDD supply can be supplied from the VDEC supply, if preferred. The CMX7032 hardware limits for clock frequency (without an FI loaded) are 3.0MHz to 24.576MHz. These limits are then restricted by the FI which is loaded. The current Function Image size (FI-2.0.1.0) is 28kBytes 2013 CML Microsystems Plc 28 D/7032_FI2.0/9 AIS Rx-only Baseband IC with RF Synthesizer 9.1.3 CMX7032 Operating Characteristics For the following conditions unless otherwise specified: External components as recommended in Figure 3. Maximum load on digital outputs = 30pF. Clock Frequency = 19.2MHz (20ppm); Tamb = 40C to +85C. AVDD = DVDD = CPVDD = 3.0V to 3.6V; RFVDD = 2.25V to 2.75V. Reference Signal Level = 300mV pk-pk with AVDD = 3.3V. Signal levels track with supply voltage, so scale accordingly. Signal to Noise Ratio (SNR) in bit rate bandwidth. Input stage gain = 0dB. Output stage attenuation = 0dB. DC Parameters Supply Current Rx Mode DIDD (DVDD = 3.3V, VDEC = 2.5V) AIDD (AVDD = 3.3V) Additional current for one RF Synthesiser RFIDD (CPVDD = 3.3V, RFVDD = 2.5V) Additional current for one Auxiliary System Clock (output running at 4MHz) DIDD (DVDD = 3.3V, VDEC = 2.5V) AIDD (AVDD = 3.3V) CLK Input Logic `1' Input Logic `0' Input Current (Vin = DVDD) Input Current (Vin = DVSS) RS232 Interface and Logic Inputs Input Logic `1' Input Logic `0' Input Leakage Current (Logic `1' or `0') Input Capacitance RS232 Interface and Logic Outputs Output Logic `1', (IOH = 120A) Output Logic `1', (IOH = 1mA) Output Logic `0', (IOL = 360A) Output Logic `0', (IOL = -1.5mA) "Off" State Leakage Current VBIAS Output Voltage Offset wrt AVDD/2 (IOL < 1A) Output Impedance 2013 CML Microsystems Plc Notes 21 22 23 23 24 Min. Typ. Max. Unit - - 14.4 5.8 22.0 9.0 mA mA - 2.5 4.5 mA - - 250 300 - - A A 70% - - 40 - - - - - 30% 40 - DVDD DVDD A A 70% - 1.0 - - - - - - 30% 1.0 7.5 DVDD DVDD A pF 90% 80% - - - - - - - - - - 10% 15% 10 DVDD DVDD DVDD DVDD A - - 2% 22 - - AVDD k 25 21 26 29 D/7032_FI2.0/9 AIS Rx-only Baseband IC with RF Synthesizer CMX7032 AC Parameters CLK Input 'High' Pulse Width 'Low' Pulse Width Input Impedance (at 19.2MHz) Powered-up Resistance Capacitance Powered-down Resistance Capacitance Clock Frequency Clock Stability/Accuracy Clock Start Up (from powersave) System Clk 1/2 Outputs XTAL/CLK Input to CLOCK_OUT Timing: (in high to out high) (in low to out low) `High' Pulse Width `Low' Pulse Width Notes Min. Typ. Max. Unit 31 31 15 15 - - - - ns ns - - - - - - 150 20 300 20 19.2 - 20 - - - - - 20 - k pF k pF MHz ppm ms - - 76 76 15 15 81.38 81.38 - - 87 87 ns ns ns ns - 30 - ms - 10 0.3 80 > 10 - - - 90 2.7 - M %VDD Vp-p k - - 80 1.0 - - dB MHz 5.0 70% - 2 19.2 - - - 40.0 - 30% 8191 MHz RFVDD RFVDD - 100 -15 14 1088 - 1.88 470 - - - - - - - 197 2.5 625 10% 5% 500 600 0 - 1048575 - 3.3 820 - - kHz MHz dBm V/s 32 32 33 33 VBIAS Start Up Time (from powersave) RxIN Input Input Impedance Input Signal Range Input Signal Envelope Load Resistance (feedback pins) Amplifier Open Loop Voltage Gain (I/P = 1mV rms at 100Hz) Unity Gain Bandwidth 34 35 RF Synthesiser - Phase Locked Loops Reference Clock Input Frequency Input Logic `1' Input Logic `0' Divide Ratios (R) 64, 66 61 61 62 RF Synthesiser Comparison Frequency Input Frequency Range Input Level (at 600MHz) Input Slew Rate Divide Ratios (N) 1Hz Normalised Phase Noise Floor Charge Pump Current (high) Charge Pump Current (low) Charge Pump Current - voltage variation Charge Pump Current - sink to source match 2013 CML Microsystems Plc 67 65 68 63 63 30 dBc/Hz mA A per V of ISET D/7032_FI2.0/9 AIS Rx-only Baseband IC with RF Synthesizer Notes: 21 22 23 24 25 26 31 32 33 34 35 36 37 41 42 43 44 51 53 61 62 63 64 65 66 67 68 CMX7032 Tamb = 25C, not including any current drawn from the device pins by external circuitry. RF and auxiliary circuits disabled. Nominal voltage only, maximum figure is extrapolated from that obtained under test conditions. When using the external components shown in Figure 3 and Figure 7 and when supplying the current for RFVDD from the regulated 2.5V digital (VDEC) supply. Characteristics when driving the XTAL/CLK pin with an external clock source. Applies when utilising VBIAS to provide a reference voltage to other parts of the system. When using VBIAS as a reference, VBIAS must be buffered. VBIAS must always be decoupled with a capacitor as shown in Figure 4. Timing for an external input to the XTAL/CLK pin. XTAL/CLK input driven by an external source. 6.144MHz XTAL fitted and 6.144MHz output selected. With no external components connected, and measured at dc. After multiplying by gain of input circuit, with external components connected. Gain applied to signal at output of buffer amplifier: RX1FB or RX2FB. Design Value. Overall attenuation input to output has a tolerance of 0dB 1.0dB. Power-up refers to issuing an RS232 message. These limits apply only if VBIAS is on and stable. Small signal impedance, at AVDD = 3.3V and Tamb = 25C. With respect to the signal at the feedback pin of the selected input port. With the output driving a 20k load to AVDD/2. Denotes output impedance of the driver of the auxiliary input signal, to ensure <1 bit additional error under nominal conditions. Guaranteed monotonic with no missing codes. Square wave input. Separate dividers provided for each PLL. External ISET resistor (R31) = 0 (Internal ISET resistor = 9k6 nominally). For optimum performance of the synthesiser subsystems, a common master clock should be used for the RF Synthesisers and the baseband sections. Using unsynchronised clocks is likely to result in spurious products being generated in the synthesiser outputs and in some cases difficulty may be experienced in obtaining lock in the RF Synthesisers. Operation outside these frequency limits is possible, but not guaranteed. Below 150MHz, a square wave input may be required to provide an acceptable slew rate. Lower input frequencies may be used subject to division ratio requirements being maintained. It is recommended that RF Synthesiser 1 be used for higher frequency use st (eg: RF 1 LO) and RF Synthesiser 2 be used for lower frequency use (eg: IF LO). 1Hz Normalised Phase Noise Floor (PN1Hz) can be used to calculate the phase noise within the PLL loop by: Phase Noise (in band) = PN1Hz + 20 log10(N) + 10log10(fcomparison). 2013 CML Microsystems Plc 31 D/7032_FI2.0/9 AIS Rx-only Baseband IC with RF Synthesizer 9.1.4 CMX7032 Parametric Performance For the following conditions unless otherwise specified: External components as recommended in Figure 3. Maximum load on digital outputs = 30pF. CLK Frequency = 19.2MHz (20ppm); Tamb = 40C to +85C. AVDD = DVDD = CPVDD = 3.0V to 3.6V; RFVDD = 2.25V to 2.75V. Reference Signal Level = 300mV pk-pk with AVDD = 3.3V. Signal levels track with supply voltage, so scale accordingly. Signal to Noise Ratio (SNR) in bit rate bandwidth. Input stage gain = 0dB, Output stage attenuation = 0dB. Receive Parameters AIS (GMSK 9600bps), 25kHz channel Bit rate Accuracy BT Storage Time Packet Error Rate (PER) limit PER with -10dB Co-channel Interference PER with 10dB SNR Rx Buffer Size (burst mode) Notes 1 2 3 Min. Typ. Max. Unit - - - - - - - - 0.4 8 - - - - 50 - - 20% 20% 20% 2 x176 ppm bits bytes Notes: 1. Through GMSK/FSK receive filters. 2. Measured at baseband to IEC 62287-1. 3. Measured at baseband with simulated FM channel noise. 2013 CML Microsystems Plc 32 D/7032_FI2.0/9 AIS Rx-only Baseband IC with RF Synthesizer CMX7032 9.2 SPI Timing Figure 10 SPI Interface Timing Serial (SPI) Bus Interface Timing Notes Min. Typ. Max. TCK Clock cycle time - 16 - TCL Clock 'low' pulse width - 8 - TCH Clock 'high' pulse width - 8 - tDOV tDOH TDS TDH Out data valid time Out data hold time In data set up time In data hold time - 0 20 20 10 - - - 80 - - - tCLC Chip select low to clock rising edge - 4 - tCCH Clock falling edge to chip select high - 4 - Notes: 1. 2. Unit Xtal Clock Periods Xtal Clock Periods Xtal Clock Periods ns ns ns ns Xtal Clock Periods Xtal Clock Periods The serial (SPI) bus clock frequency is the CMX7032 internal (Main Clock / 16) frequency. At power-on, the internal Main Clock is connected directly to the XTAL/CLK pin. An EEPROM should be chosen which is compatible with these timings. Maximum 30pF load on each serial bus interface line. 2013 CML Microsystems Plc 33 D/7032_FI2.0/9 AIS Rx-only Baseband IC with RF Synthesizer CMX7032 DIM. * * * MIN. TYP. MAX. 9.00 BSC A B C F G H J K L L1 P T 0.80 7.00 7.00 0.00 0.18 0.20 0.30 0 9.00 BSC 0.90 1.00 7.80 7.80 0.05 0.30 0.25 0.50 0.15 0.40 0.50 0.20 NOTE : A & B are reference data and do not include mold deflash or protrusions. All dimensions in mm Angles are in degrees Exposed Metal Pad Index Area 1 Dot Index Area 2 Dot Chamfer Index Area 1 is located directly above Index Area 2 Depending on the method of lead termination at the edge of the package, pull back (L1) may be present. L minus L1 to be equal to, or greater than 0.3mm The underside of the package has an exposed metal pad which should ideally be soldered to the pcb to enhance the thermal conductivity and mechanical strength of the package fixing. Where advised, an electrical connection to this metal pad may also be required Figure 11 Mechanical outline for 64-pad VQFN package (Q1) Order as CMX7032Q1 Figure 12 Mechanical outline for 64-pin LQFP (leaded) package (L9) Order as CMX7032L9 2013 CML Microsystems Plc 34 D/7032_FI2.0/9 AIS Rx-only Baseband IC with RF Synthesizer CMX7032 About FirmASIC CML's proprietary FirmASIC component technology reduces cost, time to market and development risk, with increased flexibility for the designer and end application. FirmASIC combines Analogue, Digital, Firmware and Memory technologies in a single silicon platform that can be focused to deliver the right feature mix, performance and price for a target application family. Specific functions of a FirmASIC device are determined by uploading its Function ImageTM during device initialization. New Function ImagesTM may be later provided to supplement and enhance device functions, expanding or modifying end-product features without the need for expensive and time-consuming design changes. FirmASIC devices provide significant time to market and commercial benefits over Custom ASIC, Structured ASIC, FPGA and DSP solutions. They may also be exclusively customised where security or intellectual property issues prevent the use of Application Specific Standard Products (ASSP's). Handling precautions: This product includes input protection, however, precautions should be taken to prevent device damage from electro-static discharge. CML does not assume any responsibility for the use of any circuitry described. No IPR or circuit patent licences are implied. CML reserves the right at any time without notice to change the said circuitry and this product specification. CML has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification. Specific testing of all circuit parameters is not necessarily performed.