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Data Sheet

BOSCH -1/85-

Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

CC770

(Stand Alone CAN Controller)

Data Sheet

Revision 1.8

14.09.2010

Robert Bosch GmbH

Automotive Electronics

Data Sheet

BOSCH -2/85-

Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

Disclaimer

1) The products of the division Automotive Electronics of Robert Bosch GmbH

(hereinafter "Bosch AE Components") are developed for use in automotive sys-

tems. They may only be used within the parameters of this product data sheet.

The information in this data sheet is only given to describe certain components

and their functions and shall not be considered as warranted characteristics.

Any liability for infringement of intellectual property rights due to applying the

information for the data sheet shall be excluded.

2) The examination of ﬁtness for the intended use is the sole responsibility of the

customer. The resale and/or use of Bosch AE Components are at the cus-

tomer’s own risk and at his own responsibility. All operating parameters must be

validated by the customer for each customer application by technical experts of

the customer.

3) Unless otherwise expressly agreed in writing and without limitation Bosch AE

Components are not designed, intended, or authorized for use as components

in systems intended to support or sustain life.

4) In the event of any use of Bosch AE Components outside the Bosch expressly

approved applications, speciﬁed environments, installation conditions or in the

event of any unintended use or misuse, Customer shall indemnify and hold

Bosch harmless against all claims, costs, incidental or consequential damages,

and expenses arising out of such use, directly or indirectly.

5) The Customer must monitor the market for the purchased Bosch AE Compo-

nents, particularly with respect to product safety and inform Bosch AE without

delay of all security relevant incidents.

6) Unless otherwise expressly agreed in writing Bosch reserves the right, at any

time, to change the data sheet.

Data Sheet

BOSCH -3/85-

Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

Ordering information

Device Name : CC770

Packages : LQFP 44, PLCC44

Product Number : CC770F LQFP44 package(lead-free) : 0 272 240 159

CC770F PLCC44 package(lead-free): 0 272 240 160

CC770E LQFP44 package(lead-free): 0 272 240 007

CC770E PLCC44 package(lead-free): 0 272 240 123

CC770E PLCC44 package : 0 272 230 535

Data Sheet

BOSCH -4/85-

Rev. 1.8CC770

14.09.2010

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1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1 Feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

1.2 Feature description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

1.3 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

1.4 CC770 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

1.4.1 CAN Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

1.4.2 Intelligent Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

1.4.3 CPU Interface Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

1.4.4 Clockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

1.4.5 Two 8-Bit Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

2. Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3. Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.1 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.2 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

3.2.1 Reset values of CC770 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

3.2.2 Reset values of CC770 output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

3.3 Software Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

3.4 Configuration of Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

3.5 Silent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

3.6 Low Current Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.1 CC770 Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.2 Control Register (00H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

4.3 Status Register (01H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

4.3.1 Status Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

4.4 CPU Interface Register (02H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

4.4.1 Clocking Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

4.5 High Speed Read Register (04+05H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

4.5.1 Double Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

4.6 Global Mask - Standard Register (06-07H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

4.7 Global Mask - Extended Register (08-0BH) . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

4.8 Acceptance Filtering Implications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

4.9 Message 15 Mask Register (0C-0FH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

4.10 ClkOut Register (1FH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

4.11 Bus Configuration Register (2FH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

4.12 Receive Error Counter (6FH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Data Sheet

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4.13 Transmit Error Counter (7FH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

4.14 Bit Timing Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

4.14.1 Bit Timing Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

4.14.2 CC770 Bit Timing Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

4.14.3 CC770 Bit Time Segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

4.14.4 Calculation of the Bit Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

4.14.5 Example for Bit Timing at high Baudrate . . . . . . . . . . . . . . . . . . . . . . . . .40

4.14.6 Bit Timing Registers 0 + 1 (3FH + 4FH) . . . . . . . . . . . . . . . . . . . . . . . . . .40

4.15 Interrupt Register (5FH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

4.16 Serial Reset Address (FFH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

4.17 CC770 Message Objects (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

4.17.1 Message Object Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

4.17.2 Control 0 + 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

4.17.3 Handling of Message Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

4.17.4 Arbitration 0, 1, 2, 3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

4.17.5 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

4.17.6 Data Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

4.18 Special Treatment of Message Object 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

5. Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

5.1 Port 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

5.2 Port 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

6. FLOW DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

6.1 CC770 handling of Message Objects 1-14 (Transmit) . . . . . . . . . . . . . . . . . . . .55

6.2 CC770 handling of Message Objects 1-14 (Receive) . . . . . . . . . . . . . . . . . . . . .56

6.3 CPU Handling of Message Objects 1-14 (Transmit) . . . . . . . . . . . . . . . . . . . . .57

6.4 CPU Handling of Message Objects 1-14 (Receive) . . . . . . . . . . . . . . . . . . . . . .58

6.5 CPU Handling of Message Object 15 (Receive) . . . . . . . . . . . . . . . . . . . . . . . .59

7. CPU Interface Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

7.1 CPU Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

7.2 Parallel Interfacing Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

7.3 Serial Interface Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

7.4 Serial Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

7.5 Serial Control Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

8. Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

8.1 Handling Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

8.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Data Sheet

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Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

8.3 D.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

8.4 A.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

8.4.1 A.C. Characteristics for start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

8.4.2 A.C. Characteristics for clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

8.4.3 A.C. Characteristics for CAN interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

8.4.4 A.C. Characteristics for 8/16-Bit Multiplexed Modes (Modes 0, 1) . . . . . .68

8.4.5 A.C. Characteristics for 8-Bit Multiplexed Mode 2 . . . . . . . . . . . . . . . . . . .71

8.4.6 A.C. Characteristics for 8-Bit Non-Multiplexed Asynchronous (Mode 3) . .73

8.4.7 A.C. Characteristics for 8-Bit Non-Multiplexed Synchronous (Mode 3) . . .76

8.4.8 A.C. Characteristics for Serial Interface Mode . . . . . . . . . . . . . . . . . . . . . .78

8.4.9 Waveforms for testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

9. Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

9.1 Interrupt update during Initialization Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

9.1.1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

9.1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

9.1.3 Work-around . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

10. Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

10.1 Documentation of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

10.1.1 Changes on Revisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

10.1.1.1 Revision 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

10.1.1.2 Revision 1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

10.1.1.3 Revision 1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

10.1.1.4 Revision 1.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

10.1.1.5 Revision 1.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

10.1.1.6 Revision 1.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

10.1.1.7 Revision 1.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

10.1.1.8 Revision 1.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

10.1.1.9 Revision 1.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Data Sheet

BOSCH -7/85-

Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

1. Introduction

1.1 Feature list

• Supports CAN Protocol Version 2.0 A, B

• Standard Data and Remote Frames

• Extended Data and Remote Frames

• Programmable Global Mask

• Standard Message Identiﬁer

• Extended Message Identiﬁer

• 15 Message Objects of 8-byte Data Length

• 14 Tx/Rx Buffers

• 1 Rx Buffer with Shadow Buffer and Programmable Mask

• Programmable Bit Rate

• Flexible CPU Interface

• 8-bit Multiplexed

• 16-bit Multiplexed

• 8-bit Synchronous Non-Multiplexed

• 8-bit Asynchronous Non-Multiplexed

• Serial Interface

• Two 8-bit Bidirectional l/O Ports

• Flexible Interrupt Structure

• Flexible Status Interface

• Programmable Clock Output

• LQFP44 and PLCC44 Package, Chip

1.2 Feature description

The CC770 is a highly integrated serial communications controller that performs serial com-

munication according to the CAN Protocol Version 2.0 A, B. The CAN protocol uses a multi-

master (contention based) bus conﬁguration for the transfer of “communication objects”

between nodes of the network. This multi-master bus is also referred to as CSMA/CR or

Carrier Sense, Multiple Access, with Collision Resolution.

The CC770 performs all serial communication functions such as transmission and recep-

tion of messages, message ﬁltering, transmit search, and interrupt search with minimal

interaction from the host microcontroller, or CPU. The CC770 supports the standard and

extended message frames in CAN Speciﬁcation 2.0 part B. It has the capability to transmit,

receive, and perform message ﬁltering on extended message frames with a 29-bit message

identiﬁer. Due to the backward compatible nature of CAN Speciﬁcation 2.0, the CC770 also

fully supports the standard message frames in CAN Speciﬁcation 2.0 part A.

A communication object consists of an identiﬁer along with control data segments. The con-

Common_Introduction.fm

Data Sheet

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trol segment contains all the information needed to transfer the message. The data seg-

ment contains from 0 to 8 bytes in a single message. All communication objects are stored

in the Memory of the corresponding CAN chip for each node. A transmitting node broad-

casts its message to all other nodes on the network. An acceptance ﬁlter at each node

decides whether to receive that message. A message is accepted only if a communication

object with a matching message identiﬁer has been set up in the CAN Memory for that

node.

CAN not only manages the transmission and reception of messages but also the error han-

dling, without any burden on the CPU.

CAN features several error detection mechanisms. These include Cyclical Redundancy

Check (CRC) and bit coding rules (“bit stufﬁng/destufﬁng“). The polynomial of the CRC has

been optimized for control applications with short messages. If a message was corrupted

by noise during transmission, it is not accepted at the receiving nodes. Current transmis-

sion status is monitored in the control segment of the appropriate communication object

within the transmitting node, automatically initiating a repeated transmission in the case of

lost arbitration or errors. CAN also has built-in mechanisms to locate error sources and to

distinguish permanent hardware failures from occasional soft errors. Defective nodes are

switched off the bus, implementing a fail-safe behaviour (thus, hardware errors will not let

defective nodes control the bus indeﬁnitely).

The message storage is implemented in an intelligent memory, which can be addressed by

the CAN controller and the CPU. The CPU controls the CAN controller by selectively modi-

fying the various registers and bit ﬁelds in the Memory. The content of the various bit ﬁelds

are used to perform the functions of acceptance ﬁltering, transmit search, interrupt search

and transfer completion.

In order to initiate a transfer, the transmission request bit has to be written to the message

object. The entire transmission procedure and eventual error handling is then done without

any CPU involvement. If a communication object has been conﬁgured to receive messages,

the CPU easily reads its data registers using CPU read instructions. The message object

may be conﬁgured to interrupt the CPU after every successful message transmission or

reception.

The CC770 features a powerful CPU interface that offers ﬂexibility to directly interface to

many different CPUs. It can be conﬁgured to interface with CPUs using an 8-bit multiplexed,

16-bit multiplexed, or 8-bit non-multiplexed address/data bus for different architectures. A

ﬂexible serial interface is also available when a parallel CPU interface is not required.

The CC770 provides storage for 15 message objects of 8-byte data length. Each message

object can be conﬁgured as either transmit or receive, except for the last message object.

The last message object is a receive only double buffer with a dedicated acceptance mask

designed to allow select groups of different message identiﬁers to be received.

The CC770 also implements a global acceptance masking feature for message ﬁltering.

This feature allows the user to globally mask any identiﬁer bits of the incoming message.

There are different programmable global mask registers for standard and extended mes-

sages.

The CC770 provides an improved set of network management and diagnostic functions

including fault conﬁnement and a built-in monitoring tool. The built-in monitoring tool alerts

the CPU when a global status change occurs. Global status changes include message

transmission and reception, error frames, or sleep mode wake-up. In addition, each mes-

sage object offers full ﬂexibility in detecting when a data or remote frame has been sent or

Data Sheet

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received.

1.3 Functional Overview

The CC770 CAN controller consists of six functional blocks. The CPU Interface logic man-

ages the interface between the CPU (host microcontroller) and the CC770 using an

address/data bus or the SPI. The CAN controller interfaces to the CAN bus and implements

the protocol rules of the CAN protocol for the transmission and reception of messages. The

RAM is the interface layer between the CPU and the CAN bus. The two port blocks provide

8-bit low speed I/O capability. The clockout block allows the CC770 to drive other chips,

such as the host-CPU.

The CC770 RAM provides storage for 15 message objects of 8-byte data length. Each

message object has a unique identiﬁer and can be conﬁgured to either transmit or receive,

except for the last message object. The last message object is a receive only buffer with a

special mask design to allow select groups of different message identiﬁers to be received.

Each message object contains control and status bits. A message object with the direction

set as receive will send a remote frame by requesting a message transmission. A message

object with the direction set as transmit will be conﬁgured to automatically send a data

frame whenever a remote frame with a matching identiﬁer is received over the CAN bus. All

message objects have separate transmit and receive interrupts and status bits, allowing the

CPU full ﬂexibility in detecting when a remote or data frame has been sent or received.

The CC770 also implements a global masking feature for acceptance ﬁltering. This feature

allows the user to globally mask, or ‘‘don’t care’’, any identiﬁer bits of the incoming mes-

sage. This mask is programmable to allow the user to design an application-speciﬁc mes-

sage identiﬁcation strategy. There are separate global masks for standard and extended

frames.

The incoming message ﬁrst passes through the global mask and is matched to the identiﬁ-

ers in message objects 1-14. If there is no identiﬁer match then the message passes

through the local mask in message object 15. The local mask allows a large number of

infrequent messages to be received by the CC770. Message object 15 is also buffered to

allow the CPU time to service a message received.

Data Sheet

BOSCH -10/85-

Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

1.4 CC770 Block Diagram

The CC770 consists of the following functional blocks:

Figure 1: Block Diagram of CC770.

1.4.1 CAN Controller

The CAN controller controls the data stream between the Memory (parallel data) and the

CAN busline (serial data). The CAN controller also handles the error management logic and

the message objects.

1.4.2 Intelligent Memory

The Memory is content addressable (CAM) for the CAN Controller which does the accept-

ance ﬁltering in one clock cycle, whereas the CPU Interface Logic accesses the Memory

via register address (RAM). The advantage of this access is the speed and the minimized

area.

The access to the CAM is timeshared between the CPU Interface Logic and the CAN bus

(through the CAN controller). The Memory is addressed from 00H to FFH.

CAN

CONTROLLER

CPU

INTERFACE

LOGIC

PORT1 PORT2 INTELLIGENT

CLKOUT

TX0

TX1

RX0

RX1

CLKOUTMODE1

MODE0

CONTROL

ADDRESS/

PORT1 PORT2

BUS

DATA BUS

MEMORY

SPI

Data Sheet

BOSCH -11/85-

Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

1.4.3 CPU Interface Logic

The CC770 provides a ﬂexible CPU interface capable of interfacing to many commonly

used microcontrollers. The following ﬁve modes could be selected using two CPU interface

MODE0 and MODE1 pins and the RD# and WR# pins:

Mode 0 (1) is an 8-bit multiplexed address data bus using RD# and WR# pins.

If the RD# and WR# pins are tied low at reset in Mode 0, the serial interface (SPI) mode is

entered.

Mode 1 (2) selects 16-bit multiplexed address data bus.

Mode 2 (3) selects an 8-bit multiplexed address data bus using E and R/W# pins.

Mode 3 (4) selects an 8-bit non-multiplexed address data bus for either synchronous or

asynchronous communication.

1.4.4 Clockout

The on-chip clock generator consists of an oscillator, clock divider register and a driver cir-

cuit. The Clockout output range is XTAL (external crystal frequency) to XTAL/15.

The Clockout output driving strength (slew rate) is programmable in four steps.

1.4.5 Two 8-Bit Ports

Two 8-bit low speed input/output (I/O) ports are available on-chip. Depending on the CPU

interface selected, at least 7 and up to 16 of these I/O pins are available for system use.

1. MODE1 pin = 0, MODE0 pin = 0

2. MODE1 pin = 0, MODE0 pin = 1

3. MODE1 pin = 1, MODE0 pin = 0

4. MODE1 pin = 1, MODE0 pin = 1

Data Sheet

BOSCH -12/85-

Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

2. Package Diagram

Figure 2: Package Diagrams of CC770

(Package: PLCC44)

RD#/E

ALE/AS

AD0

AD1

AD2

VCC

MODE0

AD3

AD4/MOSI

AD5

AD6/SPICLK

CS#

DSACK0#

P2.7/WRH#

P2.6/INT#

P2.5

P2.4

P2.3

P2.2

P2.1

P2.0

(WR#/WRL#)/

(R/W#)

XTAL1

XTAL2

VSS2

RX1

RX0

VSS1

INT#

TX1

TX0

CLKOUT

READY/MISO

AD7

P1.0/AD8

P1.1/AD9

P1.2/AD10

P1.3/AD11

P1.4/AD12

P1.5/AD13

P1.6/AD14

P1.7/AD15

MODE1

RESET#

Product Number

Date Code

Strip Mark

Wafer Lot No.

RD#/E

ALE/AS

AD0

AD1

AD2

VCC

MODE0

AD3

AD4/MOSI

AD5

AD6/SPICLK

CS#

DSACK0#

P2.7/WRH#

P2.6/INT#

P2.5

P2.4

P2.3

P2.2

P2.1

P2.0

(WR#/WRL#)/

(R/W#)

XTAL1

XTAL2

VSS2

RX1

RX0

VSS1

INT#

TX1

TX0

CLKOUT

READY/MISO

AD7

P1.0/AD8

P1.1/AD9

P1.2/AD10

P1.3/AD11

P1.4/AD12

P1.5/AD13

P1.6/AD14

P1.7/AD15

MODE1

RESET#

(Package: LQFP44)

Product Number

Date Code Assembly Lot

(last 5 digits)

Lot No.

Common_PackageDiagram.fm

Data Sheet

BOSCH -13/85-

Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

3. Product Description

3.1 Pin Description

Symbol LQFP

pin PLCC

pin Function

WR#/

WRL#/

R/W#

1 7 For CPU Interface Modes 0 and 1.

For Mode 1, 16-bit multiplexed mode, function is: write low byte

For CPU Interface Mode 2 and 3.

CS# 2 8 A low level on this pin enables the CPU to access the CC770.

DSACK0# 3 9 DSACK0# is an open-drain output(1) to sychronize accesses from the CPU to the

CC770 for CPU Interface Mode 3.

P2.7/

WRH# 4 10 Port 2, Bit 7(2)

For Mode 1, 16-bit multiplexed mode, function is: write high byte

P2.6/

INT# 5 11 Port 2, Bit 6(2)

Interrupt output (INT#) when MUX bit = 1 in CPU Interface Register

P2.5 6 12 Port 2, Bit 5(2)

P2.4 7 13 Port 2, Bit 4(2)

P2.3 8 14 Port 2, Bit 3(2)

P2.2 9 15 Port 2, Bit 2(2)

P2.1 10 16 Port 2, Bit 1(2)

P2.0 11 17 Port 2, Bit 0(2)

XTAL1 12 18 Input for an external clock.

XTAL2 13 19 Push-pull output from the internal oscillator. XTAL2 and XTAL1 are the crystal con-

nections to an internal oscillator. If an external oscillator is used, XTAL2 may not be

connected. XTAL2 may not be used as a clock output to drive other CPUs.

VSS2 14 20 Ground (0V) connection must be shorted externally to a VSS board plane to provide

analog ground for PLL.

RX1 15 21 Inverting input from CAN bus transceiver if DcR0 bit in the Bus Conﬁguration Register

(Address 2FH) is set.

RX0 16 22 Input from CAN bus transceiver if DcR0 bit in the Bus Conﬁguration Register

(Address 2FH) is zero.

VSS1 17 23 Ground (0V) connection must be shorted externally to a VSS board plane to provide

digital ground.

INT# 18 24 The interrupt pin is an open drain output (requires external pull up resistor) to the

CPU.

The function of this pin is determined by the MUX bit in the CPU Interface Register

(Address 02H), see chapter 4.4.

TX1 19 25 Inverted serial push-pull data output to the CAN bus transceiver. During a recessive

bit TX1 is low, during a dominant bit TX1 is high.

Table 1: Pin description

Common_PinDescription.fm

Data Sheet

BOSCH -14/85-

Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

TX0 20 26 Serial push-pull data output to the CAN bus transceiver. During a recessive bit TX0 is

high, during a dominant bit TX0 is low.

CLKOUT 21 27 Programmable clock output. This push-pull output may be used to drive the clock

input of the CPU.

READY/

MISO

22 28 READY is an open-drain output to synchronize accesses from the CPU to the CC770

for CPU Interface Modes 0 and 1.

MISO is the serial push-pull data output in the SPI mode.

RESET# 23 29 Reset pin for CC770 initialisation. Timing requirements described in chapter 8.4.1.

MODE1 24 30 Select, together with Pin 44, one of the four parallel interface modes.(3)

P1.7-0 25-32 31-38 Port 1 with multi Function Pins, see Table 2.(2)

AD7-3 33-37 39-43 Multi Function Pins, see Table 2.

MODE0 38 44 Select, together with Pin 30, one of the four parallel interface modes. See chapter

7.1.(3)

VCC 39 1 Power connection must be shorted externally to +5V DC to provide power to the

entire chip.

AD2-0 40-42 2 - 4 Multi Function Pin, see Table 2.

ALE/

AS 43 5 ALE used for CPU Interface Modes 0 and 1.

AS used for Mode 2. (In Mode 3, pin must be tied high.)

RD#/

E44 6 RD# used for CPU Interface Modes 0 and 1.

E used for Mode 2. (In Mode 3 Asynchronous, pin must be tied high.)

Symbol LQFP

pin PLCC

pin Function

Table 1: Pin description

Data Sheet

BOSCH -15/85-

Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

Notes to pin descriptions:

(1) DSACK0# is often used as a pulldown output with a 3.3 kΩpullup resistor and a 100 pF

load capacitance. An open-drain output is used because several peripherals may be con-

nected to the DSACK0# line. The CC770 speciﬁes a TCHKH timing (CS# high to DSACK0#

high) equal to 55 ns, however a 3.3 kΩresistor will not sufﬁciently charge the line when

DSACK0# is ﬂoated by the CC770. To meet this timing, the CC770 has an active pullup that

drives the DSACK0# output until it is high, and then the pullup is turned off. Therefore, the

pullup is active for a short time only.

Since the DSACK is also an input (to observe logic pin level for active pullup) this pin must

be connected to an external pullup resistor in any case to avoid oscillation. If DSACK is not

needed by application, the pullup resistor could have a higher impedance than 3.3 kΩ(e.g.

100 kΩ) to reduce current peaks.

(2) Port1 and Port2 pins are weakly held high until the Port Conﬁguration Registers have

been written (locations 9FH and AFH respectively).

(3) MODE0 and MODE1 pins are internally connected to weak pulldowns. These pins will

Symbol LQFP

pin PLCC

Mode 0

8-Bit

Multiplexed

(RD# & WR#)

Mode 1

16-Bit

Multiplexed

Mode 2

8-Bit

Multiplexed

(E & R/W#)

Mode 3

8-Bit

Non-

Multiplexed

SPI-Mode

Serial

Interface

AD0 42 4 AD0 AD0 AD0 A0 ICP

AD1 41 3 AD1 AD1 AD1 A1 CP

AD2 40 2 AD2 AD2 AD2 A2 CSAS

AD3 37 43 AD3 AD3 AD3 A3 STE

AD4/MOSI 36 42 AD4 AD4 AD4 A4 MOSI

AD5 35 41 AD5 AD5 AD5 A5 Unused

AD6/SPICLK 34 40 AD6 AD6 AD6 A6 SPICLK

AD7 33 39 AD7 AD7 AD7 A7 Unused

P1.0/AD8 32 38 P1.0 AD8 P1.0 D0 P1.0

P1.1/AD9 31 37 P1.1 AD9 P1.1 D1 P1.1

P1.2/AD10 30 36 P1.2 AD10 P1.2 D2 P1.2

P1.3/AD11 29 35 P1.3 AD11 P1.3 D3 P1.3

P1.4/AD12 28 34 P1.4 AD12 P1.4 D4 P1.4

P1.5/AD13 27 33 P1.5 AD13 P1.5 D5 P1.5

P1.6/AD14 26 32 P1.6 AD14 P1.6 D6 P1.6

P1.7/AD15 25 31 P1.7 AD15 P1.7 D7 P1.7

Table 2: Multi Function Pins

Data Sheet

BOSCH -16/85-

Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

be pulled low during reset if unconnected. Following reset, these pins ﬂoat.

3.2 Hardware Reset

3.2.1 Reset values of CC770 registers

The registers of the CC770 have the following values after reset:

Notes:

The error management counters and the Bus Off state are reset by a hardware reset.

If a hardware reset occurs at power on, registers deﬁned as unchanged should be inter-

preted as undeﬁned.

Also regard timing requirements of reset pin described in chapter 8.4.1.

Control Register 00H 01H

Status Register 01H undeﬁned

CPU Interface Register 02H 61H

High Speed Register 04+05H unchanged

Global Mask - Standard 06+07H unchanged

Global Mask - Extended 08-0BH unchanged

Message 15 Mask 0C-0FH unchanged

Clockout Register 1FH 00H or 01H depending on

CPU Interface Mode

Bus Conﬁguration 2FH 00H

Bit Timing Register 0 3FH 00H

Bit Timing Register 1 4FH 00H

Interrupt Register 5FH 00H

P1 Conﬁguration Register 9FH 00H

P2 Conﬁguration Register AFH 00H

P1 In BFH FFH

P2 In CFH FFH

PI Out DFH 00H

P2 Out EFH 00H

SPI Reset Address FFH not readable

Message Objects 1-15 unchanged

Table 3: Reset values of CC770 registers

Data Sheet

BOSCH -17/85-

Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

3.2.2 Reset values of CC770 output pins

The behaviour of CC770 output pins in reset procedure:

3.3 Software Initialization

Software initialization is started by setting the Init bit in the Control Register, either by soft-

ware, hardware reset, or by going Bus Off. While Init is set, all message transfers to and

from the CC770 are stopped and the TX0 and TX1 outputs are recessive. The error

counters are unchanged. Initialization is used to conﬁgure the CC770 memory without

interference to or by CAN bus.

Resetting Init bit completes initialization and the CC770 synchronizes itself to the CAN bus

by waiting for 11 consecutive recessive bits (called bus idle) before it will take part in bus

activities.

Note:

The Bus Off recovery sequence (see CAN Speciﬁcation Rev. 2.0) cannot be shortened by

setting or resetting Init. If the device goes Bus Off, it will set Init of its own accord, stopping

all bus activities. Once Init has been cleared by the CPU, the device will then wait for 129

occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal oper-

ations. At the end of the Bus Off recovery sequence, the Error Management Counters will

be reset.

During the waiting time after the resetting of Init, each time a sequence of 11 recessive bits

has been monitored, a Bit0Error code is written to the Status Register, enabling the CPU to

readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to

monitor the proceeding of the Bus Off recovery sequence.

Software initialization does not change conﬁguration register values.

3.4 Conﬁguration of Bit Timing

After setting bits Init and CCE in the CAN Control Register, the bit timing can be conﬁgured

by writing to the Bit Timing Registers.

Pin output state

while reset is active output state

direct after reset

MODE0/MODE1 weakly pulled low high impedance

Port 1/2 weakly pulled high

CLOCKOUT active

TX0 1 (recessive)

TX1 0 (recessive)

INT# ﬂoat

DSACK0# ﬂoat

Table 4: Reset states of CC770 output pins

Data Sheet

BOSCH -18/85-

Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

While Bit Timing Register 0 controls the (Re)Synchronisation Jump Width and the Baud

Rate Prescaler, Bit Timing Register 1 is used to deﬁne the position of the Sample Point

inside a Bit Time. For a detailed description how to program the bit timing see chapter 4.14.

3.5 Silent Mode

The CAN Controller can be set in Silent Mode by programming the Bus Conﬁguration Reg-

ister bits DcR1 and DcR0 both to one and PEn to zero.

In Silent Mode, the CC770 is able to receive valid data frames and valid remote frames, but

it sends only recessive bits on the CAN bus and it cannot start a transmission. If the CAN

Controller is required to send a dominant bit (ACK bit, overload ﬂag, active error ﬂag), the

bit is rerouted internally so that the CAN Controller monitors this dominant bit, although the

CAN bus may remain in recessive state.

The Silent Mode can be used to analyze the trafﬁc on a CAN bus without affecting it by the

transmission of dominant bits (Acknowledge Bits, Error Frames).

3.6 Low Current Modes

Power Down and Sleep Modes are activated by the PwD and Sleep bits in the CPU Inter-

face Register (02H) under the control of the programmer. During Power Down and Sleep

Mode the CPU Interface Register is the only accessible register. In these modes the oscilla-

tor is not active and no access to the message objects is possible.

The CC770 immediately enters Power Down Mode after the PwD bit in the CPU Interface

CAN Bus. The CC770 exits from Power Down by either a hardware reset or by resetting the

PwD bit to "0". The CPU must read the hardware reset bit (bit 7, register 02H) to ensure the

CC770 has exited Power Down.

The CC770 enters Sleep Mode after the Sleep bit in the CPU Interface Register (bit 3, reg-

ister 02H) is set and a possibly ongoing transmission on the CAN Bus has ﬁnished. Sleep

mode is exited by resetting the Sleep bit or when there is activity on the CAN bus. The

CC770 requires a minimum of tPU to come out of Sleep Mode after bus activity occurs to

ensure the oscillator and the PLL is stable, see chapter 8.4.1.

Power Down and Sleep Mode should not be entered directly after reset. The user program

must perform a minimum Memory conﬁguration at any time (preferably during the initializa-

tion) prior to entering these modes.

Programming the following registers satisﬁes the minimum conﬁguration requirement:

• Control Register (00H) (set CCE bit to "1")

• CPU Interface Register (02H) (DMC bit application speciﬁc)

• Bit Timing Register 0 (3FH) (application speciﬁc)

• Bit Timing Register 1 (4FH) (application speciﬁc)

• All MO Control 0 Registers (reset MsgVal bit to "0")

• Control Register (00H) (reset Init and CCE bits to "0")

Data Sheet

BOSCH -19/85-

Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

4. Functional Description

This section explains the functional operation of the CC770 by describing the registers used

to conﬁgure the chip and Message Objects.

4.1 CC770 Address Map

The CC770 allocates an address space of 256 bytes. All registers are organized as 8-bit

registers.

Address Register

00H Control

01H Status

02H CPU Interface

03H reserved

04+05H High Speed Read

06+07H Global Mask - Standard

08-0BH Global Mask - Extended

0C-0FH Message 15 Mask

10-1EH Message 1

1FH ClkOut *

20-2EH Message 2

2FH Bus Conﬁguration *

30-3EH Message 3

3FH Bit Timing 0 *

40-4EH Message 4

4FH Bit Timing 1 *

50-5EH Message 5

5FH Interrupt

60-6EH Message 6

6FH Receive Error Counter

70-7EH Message 7

7FH Transmit Error Counter

Table 5: CC770 address map

Common_FunctionalDescription.fm

Data Sheet

BOSCH -20/85-

Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

NOTE:

*The CPU may write to the Conﬁguration Registers only if the CCE bit is "1" (Control Regis-

ter).

4.2 Control Register (00H)

The default value of the Control Register after a hardware reset is 01H.

Reserved bits read as "0" and must be written as "0".

80-8EH Message 8

8FH reserved

90-9EH Message 9

9FH P1CONF *

A0-AEH Message 10

AFH P2CONF *

B0-BEH Message 11

BFH P1IN

C0-CEH Message 12

CFH P2IN

D0-DEH Message 13

DFH P1OUT

E0-EEH Message 14

EFH P2OUT

F0-FEH Message 15

FFH Serial Reset Address

765 4 3210

res CCE EAF res EIE SIE IE Init

rw rw rw r rw rw rw rw

Address Register

Table 5: CC770 address map

Data Sheet

BOSCH -21/85-

Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

CCE Change Conﬁguration Enable

one The CPU has write access to the Conﬁguration Registers (ClkOut, Bus Conﬁg-

uration,...). Init bit should be set in order to stop CAN bus activities, if the values

in the Bit Timing Registers must be changed.

zero The CPU has no write access to the Conﬁguration Registers.

This bit is reset by the CPU to provide protection against unintentional rewriting of critical

registers by the CPU following the initialization sequence.

EAF Enable Additional Functions

one The Receive Error Counter (address 6FH) and the Transmit Error Counter

(address 7FH) can be read. The additional mask bits MDir and MXtd in the

Message 15 Mask are enabled.

zero The addresses 6FH and 7FH are reserved. The additional mask bits MDir and

MXtd in the Message 15 Mask are disabled and will be read as 00, independent

of the last value written to those bits while EAF was "1".

The CC770 provides additional functions giving the programmer the possibility to read the

Error Counters and to mask Xtd and Dir bits in the Message 15 Mask, allowing the recep-

tion of all possible messages not received by other Message Objects.

To enable this functions the programmer has to set the EAF bit.

EIE Error Interrupt Enable

one Error interrupts enabled. A change in the error status of the CC770 (Boff or

Warn changes from 0 to 1 or vice versa from 1 to 0) will cause an interrupt to be

generated.

zero Error interrupts disabled. No error interrupt will be generated.

Error interrupts are BOff and Warn in the Status Register. Error Interrupt Enable is set by

the CPU to allow the CC770 to interrupt CPU when an abnormal number of CAN bus errors

have been detected.

It is recommended to enable this interrupt during normal operation.

SIE Status Change Interrupt Enable

one Status Change Interrupt enabled. An interrupt will be generated when a CAN

bus error is detected in the Status Register or a transfer (reception or transmis-

sion) is successfully completed, independent of the interrupt enable bits in any

Message Object.

zero Status Change Interrupt disabled. No status interrupt will be generated.

Status Change Interrupts are WakeUp, RxOK, TxOK, and LEC0-2 in the Status Register.

RxOK occurs upon every successful message transmission on the CAN bus, regardless of

whether the message is stored by the CC770.

The LEC bits are very helpful to indicate whether Bit or Form Errors are occurring. In nor-

mal operation it is not advised to enable this interrupt for LEC since the CAN protocol was

designed to handle these error conditions in hardware by error frames and the automatic

Data Sheet

BOSCH -22/85-

Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

retransmission of messages. When cumulative LEC occur, the warning and BusOff ﬂags

will be set. The Error Interrupt should be enabled to detect these conditions.

In most applications, the SIE bit should not be set. Since this interrupt will occur for every

message, the CPU will be unnecessarily burdened. Instead, interrupts should be imple-

mented on a Message Object basis so interrupts occur only for messages that are used by

the CPU.

The SIE bit is set by the CPU.

NOTE:

If the Status Change Interrupts and Message Object receive/transmit interrupts are ena-

bled, there will be two interrupts for each message successfully received or transmitted by a

Message Object.

IE Interrupt Output Enable

one Interrupt Pin enabled.

zero Interrupt Pin disabled. The CC770 will generate no interrupts although the

Interrupt Register (5FH) will still be updated.

Applies to EIE, SIE, and Message Object Tx/Rx interrupts. For example the Interrupt Regis-

ter (5FH) contains a value other than zero, indicating the interrupt source (Message Object

or Status), and the IE bit is set to one, an interrupt will be generated. No interrupt will be lost

because of periodic setting or resetting of this bit.

The Interrupt Output Enable bit is set by the CPU.

INIT Initialization

one Software initialization is enabled.

zero Software initialization is disabled.

Following a hardware reset, this bit will be set.

The Init bit is written by the CPU and is set by the CC770 when it goes busoff. Initialization

is a state which allows the user to conﬁgure the CC770 Memory without the chip participat-

ing in any CAN bus transmissions. While Init equals one, all message transfers to and from

the CAN bus are stopped, and the status of the CAN bus output Tx is recessive. Initializa-

tion will most often be used the ﬁrst time after power-up and when the CC770 has removed

itself from the CAN bus after going busoff.

Init should not be used in normal operation when the CPU is modifying transmit data; the

CPUUpd bit in the Control 1 register from each Message Object is used in this case.

4.3 Status Register (01H)

The default value of the Status Register after a hardware reset is undeﬁned.

76 5 43210

BOff Warn WakeUp RxOK TxOK LEC

rr rrwrw rw

Data Sheet

BOSCH -23/85-

Rev. 1.8CC770

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BOff Bus Off Status

one There is an abnormal rate of occurrences of errors on the CAN bus.

zero The CC770 is not busoff.

The Bus Off condition occurs when the Transmit Error Counter in the CC770 has reached

the limit of 256. In consequence, the CC770 is going busoff. During busoff, no messages

can be received or transmitted. When this ﬂag changes, an interrupt will occur if the EIE

and IE bits of the Control Register (00H) are set.

The Bus Off Status bit is written by the CC770.

Note:

This bit represents the status of the CAN core (protocol FSM), thus when CC770 is in Bus

Off state, this bit could only be reset by a successful processed busoff recovery sequence.

By resetting the Init bit in the Control Register (location 00H), the busoff recovery sequence

begins. The busoff recovery sequence resets the Transmit and Receive Error Counters.

After the CC770 counts 129 packets of 11 consecutive recessive bits on the CAN bus, the

busoff state is exited and BOff ﬂag is reset.

Warn Warning Status

one There is an abnormal rate of occurrences of errors on the CAN bus.

zero There is no abnormal occurrence of errors.

The Warning condition occurs when an error counter (REC or TEC) in the CC770 has

reached the limit of 96. When this ﬂag changes, an interrupt will occur if the EIE and IE bits

of the Control Register (00H) are set.

The Warning Status bit is written by the CC770.

WakeUp Wake Up Status

one The CC770 has left Power Down or Sleep mode.

zero No wake up.

Setting the Sleep bit in CPU Interface register (02H) to "1" will place the CC770 into Sleep

mode. While in Sleep mode, the WakeUp bit is "0". The WakeUp bit will become "1" when

bus activity is detected or when the CPU writes the Sleep bit to "0". The WakeUp bit will

also be set to "1" after the CC770 comes out of Power Down mode.

The WakeUp bit and WakeUp interrupt is reset by reading the Status Register.

This bit is written by the CC770.

RxOK Receive Message Successfully

one Since this bit was last reset to zero by the CPU, a message has been success-

fully received.

zero Since this bit was last reset by the CPU, no message has been successfully

received.

This bit is never reset by the CC770. A successfully received message may be any CAN

Data Sheet

BOSCH -24/85-

Rev. 1.8CC770

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editing, distribution, as well as in the event of applications for industrial property rights.

bus transmission that is error-free, regardless of whether the CC770 has conﬁgured a Mes-

sage Object to receive that particular message identiﬁer.

The CC770 will set this bit, the CPU may clear it.

TxOK Transmit Message Successfully

one Since this bit was last reset to zero by the CPU, a message has been success-

fully transmitted (error free and acknowledged by at least one other node).

zero Since this bit was last reset by the CPU, no message has been successfully

transmitted.

This bit is never reset by the CC770.

The CC770 will set this bit, the CPU may clear it.

LEC Last Error Code

0 No error

1 Stuff Error

More than 5 equal bits in a sequence have occurred in a part of a received

message where this is not allowed.

2 Form Error

The ﬁxed format part of a received frame has the wrong format.

3 Acknowledgment Error (AckError)

The message transmitted by this device was not acknowledged by another

node.

4 Bit 1 Error

During the transmission of a message (with the exception of the arbitration

ﬁeld), the CC770 wanted to send a recessive level (bit of logical value 1), but

the monitored CAN bus value was dominant.

5 Bit 0 Error

During the transmission of a message, the CC770 wanted to send a dominant

level (bit of logical value 0), but the monitored CAN bus value was recessive.

During busoff recovery, this status is set each time a recessive bit is received

(indicating the CAN bus is not stuck dominant).

6 CRC Error

The CRC checksum was incorrect in the message received. The CRC received

for an incoming message does not match with the CRC value calculated by this

device for the received data.

7 Unused

This ﬁeld contains a code which indicates the type of the ﬁrst error to occur in a frame on

the CAN bus. If a message has been transferred (reception or transmission) without error,

this ﬁeld will be cleared to ‘0’.

The code ‘7’ is unused and may be written by the CPU to check for updates.

Data Sheet

BOSCH -25/85-

Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

4.3.1 Status Interrupts

If the SIE bit in the Control Register (00H) is set and the CC770 has updated the Status

a Status Change Interrupt occurs. Reading the Status Register will clear the Status Change

Interrupt.

A Status Change Interrupt will occur on every successful reception or transmission, regard-

less of the state of the RxOK and TxOK bits. Therefore, if TxOK is set and a subsequent

transmission occurs, an interrupt will occur (if enabled) even though TxOK was previously

equal to one.

There are two ways to implement the receive and transmit interrupt handling.

The ﬁrst method uses the TxIE and RxIE bits in the Control 0 register of each Message

Object. Whenever a message is transmitted or received by a Message Object, the Interrupt

object with the rx/tx event. If the IE bit of register 00H is set, the CC770 interrupt line gets

active. This interrupt handling requires a minimal CPU intervention and is therefore recom-

mended for almost all applications.

The second method is based on the CC770 status interrupts. Setting the SIE bit of the Con-

trol register (00H) to "1" will generate an interrupt whenever a successful message trans-

mission or reception occurs. The TxOK bit will be set when any of the Message Objects

transmits a message. The RxOK bit will be set on any successfully received message. This

may be any CAN bus transmission that is error-free, regardless of whether the CC770 has

conﬁgured a Message Object to receive that particular message identiﬁer. This method

allows the software to react on any CAN transmission sent over the CAN bus, which could

be useful e.g. for CAN bus analysers. Due to the very high interrupt rate, this method is not

recommended for standard CAN applications.

4.4 CPU Interface Register (02H)

The value of the CPU Interface Register during the hardware reset is E1H, after the end of

the hardware reset the default value is 61H.

RstSt Hardware Reset Status

one The hardware reset of the CC770 is active (RESET is low). While reset is

active, no access to the CC770 is possible, except read access on the CPU

interface register.

zero Normal operation.

The CPU must ensure this bit is zero before further access to the CC770 after reset.

This bit is written by the CC770.

DSC Divide System Clock (SCLK).

one The system clock is equal to XTAL/2.

76543210

RstST DSC DMC PwD Sleep MUX StEn CEn

r rwrwrwrwrwrwrw

Data Sheet

BOSCH -26/85-

Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

zero The system clock is equal to XTAL.

This bit is written by the CPU.

DMC Divide Memory Clock (MCLK)

one The memory clock is equal to SCLK/2.

zero The memory clock is equal to SCLK.

This bit is written by the CPU.

PwD Power Down Mode enable and Sleep Mode enable

Information about low Current Modes see chapter 3.6.

The Sleep bit and the Power Down bit may be set and reset by the CPU. The Sleep bit will

also be reset by CAN bus activity during Sleep Mode.

MUX (see text below)

one LQFP44: Pin 18 = ﬂoat, pin 5 = INT#.

PLCC44: Pin 24 = ﬂoat, pin 11 = INT#.

zero Normal operation:

LQFP44: Pin 18 = INT#, pin 5 = P2.6.

PLCC44: Pin 24 = INT#, pin 11 = P2.6.

This bit is written by the CPU.

Bit 2 (MUX) controls whether the interrupt output is available at pin P2.6/INT# (MUX = 1) or

pin INT# (MUX = 0). The CC770 lets pin INT# ﬂoat if MUX = 1.

StEn Clockout Stretch Enable

one The Clockout for the CPU is stretched to lengthen the read and write cycles of

the CC770 instead of generating wait states.

Example: CPU read data from CC770

When the CPU writes the address byte to the CC770 the Clockout is disabled,

until the data of the selected address is available for read.

zero The Clockout is not streched.

CEn Clockout enable

one Clockout signal is enabled, (default after reset).

zero Clockout signal is disabled.

PwD Sleep Function

0 0 Both Power Down and Sleep Modes are not active.

0 1 Sleep Mode is active. These bits are written by the CPU.

1 X Power Down Mode is active.

Table 6: Function of Power Down and Sleep bits

Data Sheet

BOSCH -27/85-

Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

Accesses to the CPU Interface Register are asynchronous, so it is possible to read and

write this register even if there is no clock input or during Power Down Mode and Sleep

Mode.

4.4.1 Clocking Description

There are two analogue clocks and four digital clocks in the CC770. The analogue clocks

are the crystal oscillator clock (XTAL) and the PLL clock (PLLCLK). The digital clocks are

the system clock (SCLK), the memory clock (MCLK), the CLOCKOUT pin signal, and the

SPI clock (SPICLK). While the SPI clock is directly controlled by the SPI master, the other

digital clocks are derived from the analogue clocks.

The PLLCLK (two times the frequency of XTAL) is provided as clock source for SCLK in

order to allow a sufﬁcient system clock frequency SCLK for high CAN bit rates at a moder-

ate XTAL frequency. The balanced two-phase clock SCLK is always the result of a divide-

by-2; CPU Interface Register's bit DSC decides whether the PLL (DSC="0", SCLK=XTAL)

or XTAL (DSC=”1”, SCLK=XTAL/2) is the source of SCLK. SCLK is the clock of the CAN's

bit timing and other CAN protocol functions.

The memory clock MCLK is derived from SCLK, it is either the same as SCLK (DMC=”0”) or

it is SCLK/2 (DMC=”1”), compensating for the limited clocking range of the CC770's Con-

tent Addressable Memory (CAM).

The CLOCKOUT pin signal is always derived from PLLCLK, its actual frequency is control-

led by the CDv value in the ClkOut register (1FH).

If the CLOCKOUT pin is not used and the SCLK frequency is sufﬁcient at XTAL/2, then the

PLL should be disabled in order to reduce the CC770's electromagnetic interference (EMI).

This is done by setting DSC="1", StEn="1", and CEn="0".

When the PLL is enabled, the minimum XTAL frequency is 8 MHz. Since the CC770's

design is fully static, the XTAL frequency may be lower than 8 MHz when the crystal at the

XTAL pins is replaced by a clock generator and the PLL is disabled.

Notes:

Frequency of SCLK = fXTAL/(1 + DSC bit)

Frequency of MCLK = fSCLK/(1 + DMC bit) = fXTAL/[(1 + DSC bit) * (1 + DMC bit)]

fXTAL SCLK MCLK DSC bit DMC bit

8 MHz 8 MHz 8 MHz 0 0

10 MHz 10 MHz 5 MHz 0 1

12 MHz 6 MHz 6 MHz 1 0

16 MHz 8 MHz 8 MHz 1 0

20 MHz 10 MHz 5 MHz 1 1

Table 7: Maximum MCLK frequency for various oscillator frequencies

Data Sheet

BOSCH -28/85-

Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

4.5 High Speed Read Register (04+05H)

High Speed Read Register (04H)

High Speed Read Register (05H)

The value of the High Speed Read register is not affected by a hardware reset.

The High Speed Read register is a read only register and is the output buffer for the CPU

Interface Logic. This register is part of the CPU Interface Logic and is not located in the

RAM.

During a read to the RAM (low speed registers) this register is loaded with the value of the

low speed register being accessed.

The High Speed Read register is available to provide a method to read the CC770 when the

CPU (host microcontroller) is unable to satisfy read cycle timings for low speed CC770 reg-

isters. In other words, if the read access time of the CC770 is too slow for the CPU and the

CPU cannot extend the read bus cycle, the following double read method should be used.

Note:

The double read method does not avoid the wait time after preceding read or write, see AC-

timing parameters tRLDV1, tEHDV, and tCLDV. This wait time is to be interposed between

the two accesses.

4.5.1 Double Read Operation

The CPU can execute double reads where the ﬁrst read addresses the low speed register

and the second read addresses the High Speed Read register. The ﬁrst read is a dummy

read for the CPU, however the low speed register value is stored in the High Speed Read

desired low speed register.

The advantage of double reads is both read operations have fast access times. The ﬁrst

read of the low speed register requires 40 ns (verify in current data sheet) to load the High

Speed Read Register (the data on the address/data pins is not valid). The second read of

the High Speed Read register requires 55 ns (verify in current data sheet) and the data on

the address/data bus is valid.

Therefore, if the access time of a low speed register is too long for the CPU then a second

76543210

Low Byte

76543210

High Byte

Data Sheet

BOSCH -29/85-

Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

read to the High Speed Register will produce the correct data. Please note Low and High

Speed registers have different access timing speciﬁcations in the CC770 data sheet.

During a 16-bit read access the low and high byte will contain the 16-bit value from the read

access. For an 8-bit read access the low byte will contain the value from the read access.

4.6 Global Mask - Standard Register (06-07H)

Global Mask (06H)

Global Mask (07H)

The value of the Global Mask Standard is not affected by a hardware reset.

Reserved bits read as "1".

Mskx Mask bit at position X

one must-match (incoming bit value must match to the corresponding bit in the Arbi-

tration Register from a Message Object)

zero don’t care (accept a "0" or "1" for that bit position)

The Global Mask Standard register applies only to messages using the standard CAN Iden-

tiﬁer and thereby to Message Objects with the Xtd bit set to "0". This feature, also called

message acceptance ﬁltering, allows the user to Globally Mask, or “don’t care” any identi-

ﬁer bits of the incoming message. This mask is programmable to allow the user to develop

an application speciﬁc masking strategy.

Note:

When a remote frame is sent, an CC770 receiver node will use the Global Mask Registers

to determine whether the remote frame matches to any of its Message Objects. If the

CC770 is programmed to transmit a message in response to a remote frame message

identiﬁer, the CC770 will transmit a message with the message identiﬁer of the CC770 Mes-

sage Object. The result is the remote message and the responding CC770 transmit mes-

sage may have different message identiﬁers because some CC770 Global Mask Register

bits are "don’t care".

76543210

Msk28 Msk27 Msk26 Msk25 Msk24 Msk23 Msk22 Msk21

rw rw rw rw rw rw rw rw

76543210

Msk20 Msk19 Msk18 res

rw rw rw r

Data Sheet

BOSCH -30/85-

Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

4.7 Global Mask - Extended Register (08-0BH)

Global Mask Extended (08H)

Global Mask Extended (09H)

Global Mask Extended (0AH)

Global Mask Extended (0BH)

The value of the Global Mask Extended is not affected by a hardware reset.

Reserved bits read as "0".

Mskx Mask bit at position x

one must-match (incoming bit value must match to the corresponding bit in the Arbi-

tration Register from a Message Object)

zero don’t care (accept a "0" or "1" for that bit position)

The Global Mask extended register applies only to messages using the extended CAN

identiﬁer and thereby to Message Objects with the Xtd bit set to "1". This feature allows the

user to Globally Mask, or “don’t care”, any identiﬁer bits of the incoming message. This

mask is programmable to allow the user the develop an application speciﬁc masking strat-

egy.

Note:

When a remote frame is sent, an CC770 receiver node will use its Global Mask Registers to

76543210

Msk28 Msk27 Msk26 Msk25 Msk24 Msk23 Msk22 Msk21

rw rw rw rw rw rw rw rw

76543210

Msk20 Msk19 Msk18 Msk17 Msk16 Msk15 Msk14 Msk13

rw rw rw rw rw rw rw rw

76543210

Msk12 Msk11 Msk10 Msk9 Msk8 Msk7 Msk6 Msk5

rw rw rw rw rw rw rw rw

76543210

Msk4 Msk3 Msk2 Msk1 Msk0 res

rw rw rw rw rw r

Data Sheet

BOSCH -31/85-

Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

determine whether the remote frame matches to any of its Message Objects. If the CC770

is programmed to transmit a message in response to a remote frame message identiﬁer,

the CC770 will transmit a message with the message identiﬁer of the CC770 Message

Object. The result is the remote message and the responding CC770 transmit message

may have different message identiﬁers because some CC770 Global Mask Register bits

are "don’t care".

4.8 Acceptance Filtering Implications

The CC770 implements two acceptance masks which allow Message Objects to receive

messages with a range of message identiﬁers (IDs) instead of just a single message ID.

This provides the application the ﬂexibility to receive a wide assortment of messages from

the bus.

The CC770 observes all messages on the CAN bus and stores any message that matches

a message’s ID programmed into an “active” Message Object. It is possible to deﬁne which

message ID bits must identically match those programmed in the Message Objects to store

the message. Therefore, ID bits of incoming messages are either “must-match” or “don’t-

care”. By deﬁning bits to be “don’t-care”, Message Objects will receive multiple message

IDs.

4.9 Message 15 Mask Register (0C-0FH)

Message 15 Mask Register (0CH)

Message 15 Mask Register (0DH)

Message 15 Mask Register (0EH)

76543210

Msk28 Msk27 Msk26 Msk25 Msk24 Msk23 Msk22 Msk21

rw rw rw rw rw rw rw rw

76543210

Msk20 Msk19 Msk18 Msk17 Msk16 Msk15 Msk14 Msk13

rw rw rw rw rw rw rw rw

76543210

Msk12 Msk11 Msk10 Msk9 Msk8 Msk7 Msk6 Msk5

rw rw rw rw rw rw rw rw

Data Sheet

BOSCH -32/85-

Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

Message 15 Mask Register (0FH)

The value of the Message 15 Mask is not affected by a hardware reset.

Reserved bit read as "0".

Mskx Mask bit at position X

one must-match (incoming bit value must match to the corresponding bit in the Arbi-

tration Register from the Message Object 15)

zero don’t care (accept a "0" or "1" for that bit position)

MDir Mask Direction Bit (EAF must be set, see note)

one must-match (incoming Direction bit value must match to the corresponding bit

in the Arbitration Register from the Message Object 15)

zero don’t care (Message Object 15 accepts Remote and Data Frames)

MXtd Mask Extended Bit (EAF must be set, see note)

one must-match (incoming Xtd bit value must match to the corresponding bit in the

Arbitration Register from the Message Object 15)

zero don’t care (Message Object 15 accepts Standard and Extended Identiﬁer

Frames)

Notes:

The Message 15 Mask Register is a programmable local mask. This feature allows the user

to locally mask, or “don’t care”, any identiﬁer bits of the incoming message for Message

Object 15. Incoming messages are ﬁrst checked for an acceptance match in Message

Objects 1- 14 before passing through to Message Object 15. Consequently, the Global

Mask and the Local Mask apply to messages received in Message Object 15 in that way,

that Message 15 Mask is “ANDed” with the Global Mask. This means that any bit deﬁned as

“don’t-care” in the Global Mask will automatically be a “don’t care” bit for message 15.

For the receive-only Message Object 15, it is also possible to mask the bits Dir and Xtd,

allowing the reception of Standard and Extended as well as Data and Remote Frames in

this Message Object.

To enable the MDir and MXtd bits the EAF bit has to be set in the Control Register 00H.

If EAF="0", the additional mask bits MDir and MXtd in the Message 15 Mask Register are

disabled and the bits will be read as "00", independent of the last value written to those bits

while EAF was set. The internal interpretation is "11", so the bits Dir and Xtd must match for

acceptance ﬁltering.

76543210

Msk4 Msk3 Msk2 Msk1 Msk0 MDir MXtd res

rw rw rw rw rw rw rw r

Data Sheet

BOSCH -33/85-

Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

4.10 ClkOut Register (1FH)

The default value of the ClkOut Register after a hardware reset is 00H (Modes 0 and 1 and

serial mode) or 01H (Modes 2 and 3).

The ClkOut register controls the frequency of the ClkOut signal as well as the slew rate.

The default frequency of ClkOut depends on the CPU interface mode. For Modes 0, 1 and

serial mode the default frequency is XTAL. For Modes 2 and 3 the default frequency is

XTAL/2. The following tables list the programmable ClkOut frequencies and the slew rates:

76543210

0 0 SL1 SL0 CDv

r r rw rw rw

CDv ClkOut Frequency

0000 XTAL

0001 XTAL/2

0010 XTAL/3

0011 XTAL/4

0100 XTAL/5

0101 XTAL/6

0110 XTAL/7

0111 XTAL/8

1000 XTAL/9

1001 XTAL/10

1010 XTAL/11

1011 XTAL/12

1100 XTAL/13

1101 XTAL/14

1110 XTAL/15

1111 Reserved

Table 8: Programming ClkOut

Data Sheet

BOSCH -34/85-

Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

Note:

The SL0/1 bits adjusts the driving current of the CLKOUT pin. So the resulting slew rate

also depends on the external capacitance of the CLKOUT circuit. Therefore the optimum

conﬁguration of the SL0/1 bits is application speciﬁc, EMI requirements have to be

regarded.

4.11 Bus Conﬁguration Register (2FH)

The default value of the bus Conﬁguration Register after a hardware reset is 00H.

Reserved bit 2 read as "0".

PEn Polarity Switch Enable

one Polarity switch Pol is enabled. Silent Mode is not functional.

zero Polarity switch Pol is disabled. Bit Pol has no function.

Pol Polarity Switch

one A logical one is interpreted as dominant and a logical zero is recessive on the

Rx0 input, if PEn is set and DcR0 is not set.

zero A logical one is interpreted as recessive and a logical zero is dominant bit on

the Rx0 input.

DcT1 Disconnect TX1 output

one TX1 output driver disabled, recommended for applications with bus driver ICs.

zero TX1 output driver enabled.

SL1 SL0 slew rate

0 0 fast

0 1 medium to fast

1 0 medium to slow

1 1 slow

Table 9: Programming ClkOut slew rates

76543210

res PEn Pol res DcT1 res DcR1 DcR0

rw rw rw rw rw r rw rw

Data Sheet

BOSCH -35/85-

Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

DcR1 Silent Mode

one Silent Mode is active, if DcR0 bit is set and PEn is zero.

zero Normal operation.

In Silent Mode, the CC770 is able to receive valid data frames and valid remote frames, but

it sends only recessive bits on the CAN Bus and it cannot start a transmission. Rx0 is used

as non inverted CAN input. The polarity switch Pol has no function in silent mode. For addi-

tional Information, see chapter 3.5.

DcR0 Select Rx input

one Rx1 is enabled and used as inverted CAN input, if PEn is not set.

zero Rx0 is enabled and used as non inverted CAN input.

Notes:

To be compatible to other CAN controllers, the reserved bits 7 and 4 remain writeable.

4.12 Receive Error Counter (6FH)

The default value of the Receive Error Counter after a hardware reset is 00H.

EP Error Passive

one At least one of the error counters (REC or TEC) has reached the error passive

level as deﬁned in the CAN speciﬁcation.

zero Both error counters are below the error passive level.

REC6-0 Receive Error Counter

Actual state of the Receive Error Counter. Values between 0 and 127.

Note:

The Receive Error Counter is only readable, if the EAF bit is set in the Control Register.

Otherwise EP and REC6-0 are reserved bits.

4.13 Transmit Error Counter (7FH)

The default value of the Transmit Error Counter after a hardware reset is 00H.

76543210

EP REC6-0

76543210

TEC7-0

Data Sheet

BOSCH -36/85-

Rev. 1.8CC770

14.09.2010

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TEC7-0 Transmit Error Counter

Actual state of the Transmit Error Counter. Values between 0 and 255.

Note:

The Transmit Error Counter is only readable, if the EAF bit is set in the Control Register.

Otherwise TEC7-0 are reserved bits.

Data Sheet

BOSCH -37/85-

Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

4.14 Bit Timing Registers

4.14.1 Bit Timing Overview

A CAN message consists of a series of bits that are transmitted in consecutive bit times. A

bit time accounts for propagation delay of the bit, CAN chip input and output delay, and syn-

chronization tolerances. This section describes components of a bit time from the perspec-

tive of the CAN Speciﬁcation and the CC770.

According to the CAN Speciﬁcation, the nominal bit time is composed of four time seg-

ments. These time segments are separate and non-overlapping as shown below:

Figure 3: Time Segments of Bit Time

SYNC_SEG Synchronisation Segment

This part of the bit time is used to synchronize the various nodes on the bus. An

edge is expected to lie within this segment.

PROP_SEG Propagation Time Segment

This part of the bit time is used to compensate for the physical delay times

within the network. It is twice the sum of the signal’s propagation time on the

bus line, the input comparator delay and the output driver delay.

NOTE:

The factor of two accounts arbitration which requires nodes consecutively to

synchronize to different transmitters.

PHASE_SEG1, PHASE_SEG2: Phase Buffer Segment1,2

These segments are used to compensate for edge phase errors and can be

lengthened or shortened by resynchronization.

SAMPLE POINT:

The sample point is the point of time at which the bus level is read and inter-

preted as the value of that respective bit. Its location is at the end of

PHASE_SEG1.

4.14.2 CC770 Bit Timing Deﬁnitions

In this application, the Synchronisation Segment is represented by tSync, the Phase Buffer

SYNC_SEG

SAMPLE TRANSMIT

NOMINAL BIT TIME

PHASE_SEG2PHASE_SEG1PROP_SEG

POINT

Data Sheet

BOSCH -38/85-

Rev. 1.8CC770

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Segment2 is represented by tTSeg2, while tTSeg1 is the summation of the Propagation Time

Segment and the Phase Buffer Segment1.

The preceding ﬁgure represents a bit time from the perspective of the CC770. A bit time is

subdivided into time quanta. One time quantum is derived from the System Clock (SCLK)

and the Baud Rate Prescaler (BRP). Each segment is a multiple of the Time Quantum tq.

The length of these segments is programmable, with the exception of the Synchronisation

Segment, which is always 1 tq long.

Figure 4: Bit Timing

4.14.3 CC770 Bit Time Segments

The following are relationships of the CC770 bit timing:

bit time= tSyncSeg + tTSeg1 + tTSeg2 (see preceding ﬁgure)

tSyncSeg = 1 • tq

tTSeg1 = ( TSeg1 + 1 ) • tq

tTSeg2 = ( TSeg2 + 1 ) • tq

tq= ( BRP + 1 ) • tSCLK

fBit = fXTAL / [(DSC + 1) • (BRP + 1) • (TSeg1 + TSeg2 + 3)]

The DSC bit is programmed in the CPU Interface Register, the variables TSeg1,TSeg2,

and Baud Rate Prescaler BRP are the programmed numerical values from the Bit Timing

Registers. The actual interpretation by the hardware of these values is such that one more

than the values programmed here is used, as shown in the brackets from the equations.

4.14.4 Calculation of the Bit Time

The programming of the bit time has to regard the CAN Speciﬁcation Rev. 2.0 and depends

on the desired baudrate, the CC770 oscillator frequency fXTAL and on the external physical

delay times of the bus driver, of the bus line and of the input comparator. The delay times

are summarised in the Propagation Time Segment, its actual value tProp is:

tSyncSeg tSyncSeg

tTSeg1 tTSeg2

1 bit time

1 time quantum

(tq)Sample Point Transmit Point

Data Sheet

BOSCH -39/85-

Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

tProp is two times the maximum of the sum of physical bus delay, the input compara-

tor delay, and the output driver delay rounded up to the nearest multiple of tq.

To fulﬁl the requirements of the CAN speciﬁcation, the following conditions must be met :

tTSeg2 ≥ 1 • tq= Information Processing Time

tTSeg2 ≥ tSJW

tTSeg1 ≥ 2 • tq

tTSeg1 ≥ tSJW + tProp

tTSeg1 ≥ tSJW + tProp + 2tq for 3 Sample Mode (bit Spl="1" in register 4FH)

Note:

In order to achieve correct operation according to the CAN protocol the total bit time should

be at least 8 tq, i.e. TSeg1 + TSeg2 ≥ 5 (as programmed in the Bit Timing Register 1).

To operate with a baudrate of 1 MBit/s, the frequency of SCLK has to be at least 8 MHz, in

consequence fXTAL has to be at least 16 MHz.

The maximum tolerance df for XTAL depends on the Phase Buffer Segment1 (PB1), the

Phase Buffer Segment2 (PB2), and the Resynchronisation Jump Width (SJW):

df ≤

AND

df ≤

(PB1 = tTSeg1 - tProp ; PB2 = tTSeg2)

min PB1PB2,()

2 13 bit time PB2–×()×

-----------------------------------------------------------------

SJW

20 bit time×

--------------------------------

Data Sheet

BOSCH -40/85-

Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

4.14.5 Example for Bit Timing at high Baudrate

Conﬁguration:

fXTAL = 20 MHz, fSCLK = 10MHz (DSC=1), BRP = 0, bitrate should be 1 MBit/s.

tq100 ns = tSCLK = tXTAL • 2

delay of bus driver 50 ns

delay of receiver circuit 30 ns

delay of bus line (40m) 220 ns = 520 ns, round up ↵

tProp 600 ns = 6 • tq

tSJW 100 ns = 1 • tq

tTSeg1 700 ns = tProp + tSJW

tTSeg2 200 ns = Information Processing Time + 1 • tq

tSync-Seg 100 ns = 1 • tq (fix)

bit time 1000 ns = tSync-Seg + tTSeg1 + tTSeg2

maximal oscillator tolerance 0.39 % =

In this example, the Bit Timing Registers must be programmed with the following values:

Bit Timing Register 0 (3FH): 00H

Bit Timing Register 1 (4FH): 16H

4.14.6 Bit Timing Registers 0 + 1 (3FH + 4FH)

Bit Timing Registers are used to deﬁne the CAN bus frequency, the sample point within a

bit time, and the mode of synchronization.

Bit Timing Register 0 (3FH)

The default value of the Bit Timing Register 0 after a hardware reset is 00H.

SJW (Re) Synchronization Jump Width

The valid programmed values are 0-3. The SJW deﬁnes the maximum number

of time quanta a bit time may be shortened or lengthened by one resynchroni-

zation.

The actual interpretation of this value by the hardware is to use one more than

the programmed value.

76543210

SJW BRP

rw rw

min PB1PB2,()

2 13 bit time PB2–×()×

----------------------------------------------------------------

0.1µs

2131µs0.2µs–×()×

-----------------------------------------------------------

Data Sheet

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editing, distribution, as well as in the event of applications for industrial property rights.

BRP Baud Rate Prescaler

The valid programmed values are 0-63. The baud rate prescaler programs the

length of one time quantum as follows: tq=t

SCLK •(BRP + 1) where tSCLK is the

period of the system clock (SCLK).

Bit Timing Register 1 (4FH)

The default value of the Bit Timing Register 1 after a hardware reset is 00H.

Spl Sampling Mode

one The CAN bus is sampled three times per bit time for determining the valid bit

value using majority logic.

zero Bus is sampled once, may result in faster bit transmissions rates.

Sampling mode = "0" may result in faster bit transmissions rates, while sampling mode = "1"

is more immune to noise spikes on the CAN bus.

TSeg2 Time Segment 2

The valid programmed values are 0-7. TSeg2 is the time segment after the

sample point.

The actual interpretation of this value by the hardware is one more than the

value programmed by the user.

TSeg1 Time Segment 1

The valid programmed values are 1-15. TSeg1 is the time segment before the

sample point.

The actual interpretation of this value by the hardware is one more than the

value programmed by the user.

4.15 Interrupt Register (5FH)

The default value of the Interrupt Register after a hardware reset is 00H.

76543210

Spl TSeg2 TSeg1

rw rw rw

76543210

IntId

Data Sheet

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IntId Interrupt Identiﬁer

The Interrupt Register is a read-only register. The value in this register indicates the source

of the interrupt. When no interrupt is pending, this register holds the value "0". If the SIE bit

in the Control Register (00H) is set and the CC770 has updated the Status Register, the

Interrupt Register will contain a "1". This indicates an interrupt is pending due to a change

in the Status Register. The value 2 + Message Object Number indicates the IntPnd bit in the

corresponding Message Object is set. There is an exception in that Message Object 15 will

have the value 2, giving Message Object 15 the highest priority of all Message Objects.

For example, a message is received by Message Object 13 with the IE (Control Register)

and RxIE (Message Object 13 Control 0 Register) bits set. The interrupt pin will be pulled

low and the value 15 (0FH) will be placed in the Interrupt Register.

If the value of the Interrupt Register equals "1", then the Status Register at location 01H

must be read to update this Interrupt Register. The Status Change Interrupt has a higher

priority than interrupts from the Message Objects. Register 5FH is automatically set to "0"

or to the lowest value corresponding to a Message Object with IntPnd set. When the value

of this register is two or more, the IntPnd bit of the corresponding Message Object Control

Interrupt Source Value

none 00H

Status Register 01H

Message Object 15 02H

Message Object 1 03H

Message Object 2 04H

Message Object 3 05H

Message Object 4 06H

Message Object 5 07H

Message Object 6 08H

Message Object 7 09H

Message Object 8 0AH

Message Object 9 0BH

Message Object 10 0CH

Message Object 11 0DH

Message Object 12 0EH

Message Object 13 0FH

Message Object 14 10H

Table 10: Interrupt Register values with corresponding Interrupt Sources

Data Sheet

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The CC770 will respond to each status change event independently and will not bundle

interrupt events in a single interrupt signal. However, if two status change events occur

before the ﬁrst is acknowledged by the CPU, the next event will not generate a separate

interrupt output. Therefore, when servicing Status Change Interrupts, the user code should

check all useful status bits upon each Status Change Interrupt.

After resetting the IntPnd bit in the Control 0 Register of individual Message Objects, the

minimum delay of the CC770 resetting the interrupt pin and updating the Interrupt Register

(5FH) is 3 MCLK cycles and a maximum of 14 MCLK cycles (after the CPU write operation

to this register is ﬁnished). When a Status Change Interrupt occurs, reading the Status

ing the IntPnd bit of the Message Object will deactivate the INT# pin.

4.16 Serial Reset Address (FFH)

The serial reset address is used to synchronize accesses between the CC770 and the

CPU.

For example the CPU cannot provide a chip select signal, it is possible to write as many

ones into the CC770 SPI until you get the value "AAH" from the MISO pin. Then the CC770

is synchronized and data transfer could be started. For further informations see chapter 7.4.

4.17 CC770 Message Objects (MO)

4.17.1 Message Object Structure

The Message Object is the means of communication between the host microcontoller and

the CAN controller in the CC770. Message Objects are conﬁgured to transmit or receive

messages.

There are 15 Message Objects located at ﬁxed addresses in the CC770. Each Message

Object starts at a base address that is a multiple of 16 bytes and uses 15 consecutive

bytes. For example, Message Object 1 starts at address 10H and ends at address 1EH.

The remaining byte in the 16 byte ﬁeld is used for other CC770 functions. In the above

example the byte at address 1FH is used for the ClkOut register.

Message Object 15 is a receive-only Message Object that uses a local mask called the

Message 15 Mask Register. This mask allows a large number of infrequent messages to be

received by the CC770. In addition, Message Object 15 is buffered to allow the CPU more

time to receive messages.

76543210

Serial Reset Address

Data Sheet

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4.17.2 Control 0 + 1 Registers

Control 0 Register (Base Address + 0)

Control 1 Register (Base Address + 1)

The values of the Control 0 and Control 1 registers are not affected by a hardware reset.

Each bit in the Control 0 and Control 1 bytes occurs twice; once in true form and once in

Address Function

Base Address +0 Control 0

+1 Control 1

+2 Arbitration 0

+3 Arbitration 1

+4 Arbitration 2

+5 Arbitration 3

+6 Conﬁguration

+7 Data 0

+8 Data 1

+9 Data 2

+10 Data 3

+11 Data 4

+12 Data 5

+13 Data 6

+14 Data 7

Table 11: Message Object Structure

76543210

MsgVal TxIE RxIE IntPnd

rw rw rw rw

76543210

RmtPnd TxRqst MsgLst/CPUUpd NewDat

rw rw rw rw

Data Sheet

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complement form. This bit representation makes testing and setting these bits as efﬁcient

as possible. The advantage of this bit representation is to allow write access to single bits of

the byte, leaving the other bits unchanged without the need to perform a read/modify/write

cycle.

For example, a CPU would set the TxRqst bit of the Control 1 byte with the following instruc-

tions:

...

MO_CTRL1.REQU #0011;Message Object 1 Control 1 register

...

LDA #$EF ;set TxRqst of Message Object 1

STA MO_CTRL1.R;

The representation of these two bits is described below:

MsgVal Message Valid

set The Message Object is valid.

reset The Message Object is invalid.

The MsgVal ﬂag is an individual halt ﬂag for each Message Object. While this ﬂag is reset

the CC770 will not access this Message Object for any reason. This ﬂag may be reset at

any time if the message is no longer required, or if the identiﬁer is being changed. If a mes-

sage identiﬁer is changed, the Message Object must be made invalid ﬁrst, and it is not nec-

essary to reset the chip following this modiﬁcation.

The CPU must reset the MsgVal ﬂag of all unused messages during initialization of the

CC770 before the Init bit of the Control Register (00H) is reset. The contents of Message

Objects may be reconﬁgured dynamically during operation and the MsgVal ﬂag assists

reconﬁguration in many cases.

The MsgVal ﬂag must be set to indicate the Message Object is conﬁgured and is ready for

communication transactions.

This ﬂag is written by the CPU.

IMPORTANT NOTE:

Direction MSB LSB Meaning

Write 0 0 not allowed (indeterminate)

0 1 reset

1 0 set

1 1 unchanged

Read 0 1 reset

1 0 set

Table 12: Representation of bit pairs in Control Registers

Data Sheet

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Two or more Message Objects must not have the same message identiﬁer and also be valid

at the same time!

If more than one CC770 transmit Message Object has the same message ID, a successful

transmission of the higher numbered Message Objects will not be recognized by the

CC770. The lower numbered Message Object will be falsely identiﬁed as the transmit Mes-

sage Object and its transmit request ﬂag will be reset. The actual transmit Message Object

will re-transmit without end because its transmit request ﬂag will not be reset.

This could result in a catastrophic condition since the higher numbered Message Object

may dominate the CAN bus by resending its message without end.

To avoid this condition, applications should require all transmit Message Objects to use

message IDs that are unique. If this is not possible, the application should disable lower

numbered Message Objects with similar message IDs until the higher numbered Message

Object has transmitted successfully.

TxIE Transmit Interrupt Enable

set An interrupt will be generated after a successful transmission of a frame.

reset No interrupt will be generated after a successful transmission of a frame.

The Transmit Interrupt Enable ﬂag enables the CC770 to initiate an interrupt after the suc-

cessful transmission by the corresponding Message Object.

This ﬂag is written by the CPU.

RxIE Receive Interrupt Enable

set An interrupt will be generated after a successful reception of a frame.

reset No interrupt will be generated after a successful reception of a frame.

This ﬂag enables the CC770 to initiate an interrupt after the successful reception by the cor-

responding Message Object.

This ﬂag is written by the CPU.

NOTE:

In order for TxIE or RxIE to generate an interrupt, IE in the Control Register must be set.

IntPnd Interrupt Pending

set This Message Object has generated an interrupt.

reset No interrupt was generated by this Message Object since the last time the CPU

cleared this ﬂag.

This ﬂag is set by the CC770 following a successful transmission or reception as controlled

by the RxIE and TxIE ﬂags.

The CPU must clear this ﬂag when servicing the interrupt.

RmtPnd Remote Request Pending

Data Sheet

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set The transmission of this Message Object has been requested by a remote

node and is not yet done.

reset There is no waiting remote request for the Message Object.

This ﬂag is only used by Message Objects with direction = transmit. This ﬂag is set by the

CC770 after receiving a remote frame which matches its message identiﬁer, taking into

account the Global Mask Register. The corresponding Message Object will respond by

transmitting a message, if the CPUUpd ﬂag is reset. Following this transmission, the CC770

will clear the RmtPnd ﬂag. In other words, when this ﬂag is set it indicates a remote node

has requested data and this request is still pending because the data has not yet been

transmitted.

NOTE:

Setting RmtPnd will not cause a remote frame to be transmitted. The TxRqst ﬂag is used to

send a remote frame from a receive Message Object.

TxRqst Transmit Request

set The transmission of this Message Object has been requested and has not been

completed.

reset This Message Object is not waiting to be transmitted.

This ﬂag is set by the CPU to indicate the Message Object data should be transmitted. Set-

ting TxRqst will send a data frame for a transmit Message Object and a remote frame for a

receive Message Object.

If direction = receive a remote frame is sent to request a remote node to send the corre-

sponding data.

TxRqst is also set by the CC770 (at the same time as RmtPnd in Message Objects whose

direction = transmit) when it receives a remote frame from another node requesting this

data. This ﬂag is cleared by the CC770 along with RmtPnd when the message has been

successfully transmitted, if the NewDat ﬂag has not been set.

MsgLst Message Lost

Only valid for Message Objects with direction = receive.

set The CC770 has stored a new message in this Message Object when NewDat

was still set.

reset No message was lost since the last time this ﬂag was reset by the CPU.

This ﬂag is used to signal that the CC770 stored a new message into this Message Object

when the NewDat ﬂag was still set. Therefore, this ﬂag is set if the CPU did not process the

contents of this Message Object since the last time the CC770 set the NewDat ﬂag; this

indicates the last message received by this Message Object overwrote the previous mes-

sage which was not read and is lost.

This deﬁnition is only valid for Message Objects with direction = receive. For Message

Objects with direction = transmit, the deﬁnition is replaced by CPUUpd.

Data Sheet

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CPUUpd CPU Updating

Only valid for Message Objects with direction = transmit.

set This Message Object may not be transmitted.

reset This Message Object may be transmitted, if direction = transmit.

The CPU sets this ﬂag to indicate it is updating the data contents of the Message Object

and the message should not be transmitted until this ﬂag has been reset. The CPU indi-

cates message updating has been completed by resetting this ﬂag (it is not necessary to

use the MsgVal ﬂag to update the Message Object’s data contents).

The purpose of this ﬂag is to prevent a remote frame from triggering a transmission of

invalid data.

NewDat New Data

set The CC770 or CPU has written new data into the data section of this Message

Object.

reset No new data has been written into the data section of this Message Object

since the last time this ﬂag was cleared by the CPU.

This ﬂag has different meanings for receive and transmit Message Objects.

4.17.3 Handling of Message Objects

For Message Objects with direction = receive, the CC770 sets the NewDat ﬂag whenever

new data has been written into the Message Object.

When the received data is written into Message Objects 1-14, the unused data bytes will be

overwritten with non-speciﬁed values.

The CPU should clear the NewDat ﬂag before reading the received data and then check if

the ﬂag remained cleared when all bytes have been read. If the NewDat ﬂag is set, the CPU

should re-read the received data to prevent working with a combination of old and new

data. See ﬂow diagram in chapter 6.4.

When the received Data is matched to Message Object 15, new data is written into the

shadow register. The foreground register is not over-written with new data. For Message

Object 15 messages, the data should be read ﬁrst, the IntPnd reset, and then the NewDat

and RmtPnd ﬂags are reset. Resetting the NewDat and RmtPnd ﬂags before resetting the

IntPnd ﬂag will result the interrupt line remaining active. See ﬂow diagram in chapter 6.5.

For Message Objects with direction = transmit, the CPU should set the NewDat ﬂag to

indicate it has updated the message contents. This is done at the same time the CPU

clears the CPUUpd ﬂag. This will ensure that if the message is actually being transmitted

during the time the message was being updated by the CPU, the CC770 will not reset the

TxRqst ﬂag. In this way, the TxRqst ﬂag is reset only after the actual data has been trans-

ferred. See ﬂow diagram in chapter 6.3.

Each ﬂag in the Control 0 and Control 1 registers may be set and reset by the CPU as

required.

Data Sheet

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Conditions required to trigger a transmission:

NOTES:

To initiate a transmission, the Control Register 1 of the Message Object should have the

TxRqst and NewDat ﬂags set to "1". Therefore, this register may be written with the value

066H.

A remote frame may be received, an interrupt ﬂag set, and no data frame transmitted in

response by conﬁguring a Message Object in the following manner. Set the CPUUpd and

RxIE ﬂags in the Message Object Control Register to "1". Set the Dir bit in the Message

Conﬁguration Register to "1". A remote frame will be received by this Message Object, the

IntPnd ﬂag will be set to "1" and no data frame will be sent in response.

Message Object Priority

If multiple Message Objects are waiting to transmit, the CC770 will ﬁrst transmit the mes-

sage from the lowest numbered Message Object, regardless of message identiﬁer priority.

If two Message Objects are capable of receiving the same message (possibly due to mes-

sage ﬁltering strategies), the message will be received by the lowest numbered Message

Object. For example, if all acceptance mask bits were set as “don’t care”, Message Object 1

will receive all messages.

4.17.4 Arbitration 0, 1, 2, 3 Registers

Arbitration 0 (Base Address + 2):

Arbitration 1 (Base Address + 3):

Flags Register Remote Frame Data Frame

Init Control 0

MsgVal MO-Control 0 set

TxRqst MO-Control 1 set

MsgLst/CPUUpd MO-Control 1 reset

NewDat MO-Control 1 don’t care should be set

Dir MO-Conﬁguration 0 1

Table 13: Bit combinations to start transmissions

76543210

ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21

rw rw rw rw rw rw rw rw

76543210

ID20 ID19 ID18 ID17 ID16 ID15 ID14 ID13

rw rw rw rw rw rw rw rw

Data Sheet

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Arbitration 2 (Base Address + 4):

Arbitration 3 (Base Address + 5):

The values of the Arbitration registers are not affected by a hardware reset.

Reserved bits read as "0".

ID0-ID28 Message Identiﬁer

ID0-ID28 is the identiﬁer for an extended frame.

ID18-ID28 is the identiﬁer for a standard frame.

NOTE:

When the CC770 receives a message, the entire message identiﬁer, the Data Length Code

(DLC), the Direction bit (Dir) and the Extended Identiﬁer bit (Xtd) are stored (additionally to

the data section) into the corresponding Message Object.

4.17.5 Conﬁguration Register

Conﬁguration (Base Address + 6):

The value of the Conﬁguration register is not affected by a hardware reset.

Reserved bits read as "0".

76543210

ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5

rw rw rw rw rw rw rw rw

76543210

ID4 ID3 ID2 ID1 ID0 res

rw rw rw rw rw r

76543210

DLC Dir Xtd res

rw rw rw r

Data Sheet

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DLC Data Length Code

The valid programmed values are 0-8. The Data Length Code of a Message

Object is written with the value corresponding to the data length.

Dir Direction

one Direction = transmit. When TxRqst is set, the Message Object will be transmit-

ted.

zero Direction = receive. When TxRqst is set, a remote frame will be transmitted.

When a message is received with a matching identiﬁer, the message will be

stored in the Message Object.

Xtd Extended Identiﬁer

one This Message Object will use an extended 29 bit message identiﬁer.

zero This Message Object will use a standard 11 bit message identiﬁer.

If the Message Conﬁguration Register bit Xtd is "0" to specify a standard frame, the CC770

will reset the extended bits in the Arbitration Registers (arbitration bits 0-17) to "0" whenever

a data frame is stored in this message object.

An extended receive Message Object (Xtd = "1") will not receive standard messages

(except if this bit is masked out, which is possible for Message Object 15 only).

If a Message Object receives a data frame from the CAN bus, the entire message identiﬁer,

the Data Length Code (DLC), the Direction bit (Dir) and the Extended Identiﬁer bit (Xtd) are

stored (additionally to the data section) into this Message Object. Therefore, if acceptance

ﬁltering (masking registers) is used, the masked-off "don’t care" bits will be rewritten corre-

sponding to the message ID of the incoming message.

4.17.6 Data Bytes

Data Bytes (Base Address + 7 ... Base Address + 14):

The values of the data byte 0-7 registers are not affected by a hardware reset.

When the CC770 writes new data into the message buffer, only the data bytes deﬁned by

the DLC are valid. Unused data bytes will be overwritten by non-speciﬁed values.

76543210

data bytes 0,1,2,3,4,5,6,7

Data Sheet

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4.18 Special Treatment of Message Object 15

Message Object 15 is a receive-only Message Object with a programmable local mask

called the Message 15 Mask Register. Since this Message Object is a receive only Mes-

sage Object, the TxRqst and the TxIE ﬂags have been hardwired inactive and the CPUUpd

ﬂag has no meaning.

The incoming messages for Message Object 15 will be written into a two-message alternat-

ing buffers to avoid the loss of a message if a second message is received before the CPU

has read the ﬁrst message. Once Message Object 15 is read, it is necessary to reset the

NewDat and the RmtPnd ﬂags to allow the CPU to read the shadow message buffer which

will receive the next message or which may already contain a new message.

If two messages have been received by Message Object 15, the ﬁrst will be accessible to

the CPU. The alternate buffer will be overwritten if a subsequent (third receive) message is

received. Once again, after reading message 15, the user program should reset the IntPnd

ﬂag followed by a reset of the NewDat and RmtPnd ﬂags in the Message Object Control

Registers.

The Xtd bit in the Message Conﬁguration Register determines whether a standard or an

extended frame will be received by this Message Object. This bit could be masked out, see

chapter 4.9.

Data Sheet

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5. Port Registers

5.1 Port 1 Registers

P1CONF (9FH)

The default value of the P1CONF register after a hardware reset is 00H.

P1CONF 0-7 Port 1 Input/Output Conﬁguration bits

one Port pin conﬁgured as a push-pull output.

zero Port pin conﬁgured as a high-impedance input.

Port pins are weakly held high until this register has been written.

P1IN (BFH)

The default value of the P1IN register after a hardware reset is FFH.

P1IN 0-7 Port 1 Data In

one A one (high voltage) is read from the pin.

zero A zero (low voltage) is read from the pin.

P1OUT (DFH)

The default value of the P1OUT register after a hardware reset is 00H.

P1OUT 0-7 Port 1 Data Out

one A logical one (high voltage) is written to the pin.

zero A logical zero (low voltage) is written to the pin.

76543210

P1CONF 0-7

76543210

P1IN 0-7

76543210

P1OUT 0-7

Common_PortRegisters.fm

Data Sheet

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5.2 Port 2 Registers

P2CONF (AFH)

The default value of the P2CONF register after a hardware reset is 00H.

P2CONF 0-7 Port 2 Input/Output Conﬁguration bits

one Port pin conﬁgured as a push-pull output.

zero Port pin conﬁgured as a high-impedance input.

Port pins are weakly held high until this register has been written.

P2IN (CFH)

The default value of the P2IN register after a hardware reset is FFH.

P2IN 0-7 Port 2 Data In

one A one (high voltage) is read from the pin.

zero A zero (low voltage) is read from the pin.

P2OUT (EFH)

The default value of the P2OUT register after a hardware reset is 00H.

P2OUT 0-7 Port 2 Data Out

one A logical one (high voltage) is written to the pin.

zero A logical zero (low voltage) is written to the pin.

76543210

P2CONF 0-7

76543210

P2IN 0-7

76543210

P2OUT 0-7

Data Sheet

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6. FLOW DIAGRAMS

The following ﬂowcharts describe the operation of the CC770 and suggested ﬂows for the

host-CPU.

6.1 CC770 handling of Message Objects 1-14 (Transmit)

These are the operations the CC770 executes to transmit Message Objects. This diagram

is useful to identify when the CC770 sets bits in the Control Registers.

Figure 5: CC770 handling of Message Objects 1-14 (Transmit)

bus free ?

NewDat := 0

load message

into shift register

transmission

successful?

NewDat=1 TxRqst := 0

IntPnd := 1

send message

yes

TxRqst := 1

RmtPnd := 1

IntPnd := 1

yes

RxIE = 1

TxRqst=1

TxIE = 1

received remote frame

with matching identifier ?

DATA REMOTE

CPUUpd=0

RmtPnd := 0

Common_FlowDiagrams.fm

Data Sheet

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6.2 CC770 handling of Message Objects 1-14 (Receive)

These are the operations the CC770 executes to receive Message Objects. This diagram is

useful to identify when the CC770 sets bits in the Control Registers.

Figure 6: CC770 handling of Message Objects 1-14 (Direction = Receive)

bus idle ?

TxRqst=1

NewDat := 0

load identifier and

control into shift register

transmission

successful?

TxRqst := 0

RmtPnd := 0

TxIE = 1

IntPnd := 1

send remote frame

yes

store message

TxIE = 1

IntPnd := 1

yes

RmtPnd := 0

NewDat = 1

no MsgLst := 1

yes

TxRqst := 0

NewDat := 1

received frame with

matching identifier to this

message object ?

REMOTE DATA

MsgLst =0

Data Sheet

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6.3 CPU Handling of Message Objects 1-14 (Transmit)

These are the operations the host-CPU executes to transmit Message Objects 1-14.

Figure 7: CPU Handling of Message Objects 1-14 (Transmit)

Power Up ( reset values )

want to sent ?

CPUUpd := 0

yes

CPUUpd := 1

write data bytes

Update Data Field

Initialisation

TxIE := ( application specific )

RxIE := ( application specific )

IntPnd := 0

RmtPnd := 0

TxRqst := 0

CPUUpd := 1

Identifier := ( application specific )

DLC := ( application specific )

Dir := transmit

Xtd := ( application specific )

MsgVal := 1

NewDat := 1

update message ?

TxRqst := 1

yes

NewDat := 0

Data Sheet

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6.4 CPU Handling of Message Objects 1-14 (Receive)

These are the operations the host-CPU executes to receive Message Objects 1-14.

Figure 8: CPU Handling of Message Objects 1-14 (Receive)

Power Up ( reset values )

NewDat =1 ? no

Process Messages

Initialisation

request update ?

TxRqst := 1

yes

NewDat := 0

read message

yes

TxIE := ( application specific )

RxIE := ( application specific )

IntPnd := 0

RmtPnd := 0

TxRqst := 0

MsgLst := 0

Identifier := ( application specific )

DLC := ( don’t care )

Dir := receive

Xtd := ( application specific )

MsgVal := 1

NewDat := 0

NewDat =0 ?

process message

yes

Data Sheet

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Rev. 1.8CC770

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6.5 CPU Handling of Message Object 15 (Receive)

These are the operations the host-CPU executes to receive Message Object 15.

Figure 9: CPU Handling of Message Object 15 (Receive)

Power Up ( reset values )

New Dat = 1 ?

IntPnd := 0

yes

Message 15 Mask :=(application specific)

NewDat := 0

read and process message

RmtPnd := 0

Process Message

Initialisation

Toggle to

alternative buffer

RxIE := ( application specific )

IntPnd := 0

RmtPnd := 0

MsgLst := 0

NewDat := 0

Identifier := ( application specific )

DLC := ( don’t care )

Dir := receive

Xtd := ( application specific )

MsgVal := 1

Data Sheet

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7. CPU Interface Logic

The CIL (CPU Interface Logic) is a ﬂexible interface between the CPU and the CC770 RAM.

The CIL allows a direct serial interface or parallel interface connection to the CC770 for

most commonly used CPUs. Therefore it converts serial or parallel address/control/data

signals from the CPU into parallel read and write accesses to the internal memory bus.

The internal memory bus is a non-multiplexed parallel bus that is used by both the CIL and

the CAN Controller to read and write to the Message Memory.

7.1 CPU Interface Description

There are ﬁve CPU interface modes used to interface a CPU to the CC770. These include

four parallel interface modes (mode 0 to mode 3) and one serial interface mode (SPI).

While RESET# is active, the two mode pins (MODE0, MODE1) select one of the following

interface modes:

Note:

The MODE0 and MODE1 inputs are weakly pulled low while RESET# is active, but they

have high impedance after reset. Therefore they must be driven to a valid logical value after

reset.

7.2 Parallel Interfacing Techniques

Mode 0

Mode 0 is intended to interface controllers using pins ALE, RD#, WR# to control an 8-bit

multiplexed address/data bus. A READY output is provided to force wait states in the CPU.

Mode 1

Mode 1 is intended to interface controllers using pins ALE, RD#, WR# to control an 16-bit

multiplexed address/data bus. A READY output is provided to force wait states in the CPU.

Mode 2

Mode 2 is intended to interface controllers using pins AS, E, R/W# to control an 8-bit multi-

plexed address/data bus. A READY output is provided to force wait states in the CPU.

MODE1 MODE0 Interface Mode

0 0 Mode 0: 8-bit multiplexed architecture with RD# & WR#.

If both RD# and WR# are driven low during reset, the SPI mode

is selected instead of Mode 0.

0 1 Mode 1: 16-bit multiplexed architecture

1 0 Mode 2: 8-bit multiplexed architecture with E & R/W#

1 1 Mode 3: 8-bit non-multiplexed architecture

Table 14: CPU interface modes

Common_CPUInterfaceLogic.fm

Data Sheet

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Mode 3

Mode 3 is intended to interface to controllers using an 8-bit non-multiplexed address/data

bus. The asynchronous mode uses R/W#, CS#, and DSACK0# (E=1). The synchronous

mode uses R/W#, CS#, and E. Mode 3 uses the address/data bus as the address bus and

Port 1 as the data bus.

For CPUs which do not provide a READY or DSACK0# input and do not meet the address/

data bus timing restrictions, a double read mechanism must be used. When writing to the

CC770 the programmer must ensure that the time between two consecutive write accesses

is not less than two memory clock (MCLK) cycles. When reading the CC770, a double read

is programmed. The ﬁrst read will be to the message object memory address and the sec-

ond read will be to the High Speed Read register (04H, 05H). After the ﬁrst CPU read

access, the CC770 stores the data contents to the High Speed Read register for the second

read.

7.3 Serial Interface Techniques

The serial interface on the CC770 is fully compatible to the SPI protocol of Motorola® and

will interface to most commonly used serial interfaces. The serial interface is implemented

in slave mode only, and responds to the master using the specially designed serial interface

protocol. This serial interface allows an interconnection of several CPU’s and peripherals on

the same circuit board.

Figure 10: Interconnection for serial communication

MOSI: Master Out Slave In

The MOSI pin is the data output of the master device (CPU) and the data input

of the slave device (CC770). Data is transferred serially from the master to the

slave on the signal line, with the most signiﬁcant bit ﬁrst and least signiﬁcant bit

last.

MISO: Master In Slave Out

The MISO pin is the data output of the slave device (CC770) and the input of

the master device (CPU). Data is transferred serially from the slave to the mas-

ter on the signal line, with the most signiﬁcant bit ﬁrst and least signiﬁcant bit

last.

CS#: Chip Select (used as Slave Select for the SPI interface)

An asserted state on the slave select input (CS#) enables the CC770 to accept

data on the MOSI pin. The CS# must not toggle during data transfer.

The CC770 will only drive data to the serial data register if CS# is at asserted

state.

MOSI

MISO

SPICLK

CS#

MOSI

MISO

SPICLK

CS#

CPU

(master) CC770

(slave)

Data Sheet

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SPICLK: Serial Clock

The master device provides the serial clock for the slave device. Data is trans-

ferred synchronously to this clock in both directions. The master and the slave

devices exchange a data byte during a sequence of eight clock pulses.

7.4 Serial Interface Protocol

The general format of the data exchange from the CC770 to the master is a bit-for-bit

exchange on each SPICLK clock pulse. Bit exchanges in multiples of 8 bits and up to 15

bytes of data are allowed. A maximum of 17 bytes can be send to the CC770-SPI, including

one address byte, one SPI Control Byte, and 15 data bytes.

At the beginning of a transmission over the serial interface, the ﬁrst byte will be the address

of the CC770 special function register or the CC770 RAM to be accessed. The next byte

transmitted is a Control Byte, which contains the number of bytes to be transmitted and

whether this is to be a read or write access to the CC770. These ﬁrst two bytes are followed

by the data bytes (1 to 15).

To ensure the CC770 device is not out of synchronization, the CC770 will transmit the val-

ues "AAH" and then "55H" through the MISO pin while the master transmits the Address

and Control Byte. The master may check for the reception of these bytes.

If the master did not receive the ﬁrst synchronization byte ("AAH"), the Data transmitted

since the last reception of the synchronization bytes are invalid. The CPU should abort the

actual transmission. The CC770 can be re-synchronised by transmitting an FFH byte (SPI

Reset Address).

If the master receives the ﬁrst synchronization byte ("AAH") but not the second one ("55H"),

the transmission of the address was disturbed. The CPU should abort the actual transmis-

sion in order to prevent data loss through transmission or reception of data from wrong

addresses. The CC770 can be re-synchronised by transmitting an FFH byte (SPI Reset

Address).

When the SPI receives an Address or Control byte with the value FFH, the SPI interface will

be reset. In this case, the SPI will assume the next byte is an address.

AD0 (ICP) Idle Clock Polarity

one SPICLK is idle high.

zero SPICLK is idle low.

AD1 (CP) Clock Phase

one Data sampled on the falling edge of SPICLK (ICP = 0) or data is sampled on

the rising edge of SPICLK (ICP = 1).

zero Data is sampled on the rising edge of SPICLK (ICP = 0) or data is sampled on

the falling edge of SPICLK (ICP = 1).

AD2 (CSAS) Chip select active state

one Asserted state of CS# is logic high.

zero Asserted state of CS# is logic low.

Data Sheet

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AD3 (STE) Synchronization Transmission Enable

one The ﬁrst two bytes which will be sent to the CPU after CS# is asserted are AAH

and 55H.

zero The ﬁrst two bytes which will be sent to the CPU after CS# is asserted are 00H

and 00H.

Enables the transmission of the synchronization bytes while the Address and Control Bytes

are transferred.

Figure 11: Serial data communication

7.5 Serial Control Byte

The Serial Control Byte is transmitted by the CPU to the CC770 as follows:

Dir Serial transmission direction

zero The data bytes will be read, so the CC770 will transfer information to the CPU.

one The data bytes will be sent from the CPU to the CC770.

Sync Synchronisation

These three bits must always be sent as "000".

SDLC Serial Data Length Code

These four bits contains the number of bytes to be transmitted. Valid pro-

grammed values are 1-15.

The ﬁrst data byte (third byte of the SPI protocol) will be written to or read from the CC770

address (ﬁrst byte of the SPI protocol). After this, the address is incremented by the SPI

logic and the next data byte is written or read from this address. In one data stream, a max-

7 6 5 43210

Dir Sync SDLC

sample points

ICP CP

MSB LSB

Data Sheet

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Rev. 1.8CC770

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imum of 15 data bytes can be transferred. A DLC of zero is not allowed. After a DLC of zero

is received, the SPI must be resynchronized. The SPI must also be resynchronized if one of

the Synchronisation Bits was received as "1".

When the CPU conducts a READ, the CPU sends an address byte and a Serial Control

Byte. While the CC770 responds back with data, it ignores the MOSI pin (transmission from

the CPU).

The CPU may transmit the next address and Serial Control Byte after CS# is de-activated

and then re-activated. This means the chip select should be activated and de-activated for

each read or write transmission.

Synchronization bytes must be monitored carefully. For example, if the CC770 does not

transmit the AAH and 55H synchronization bytes correctly, then the previous transmission

may be incorrect too. The MISO pin is tri-stated if CS# is inactive.

Figure 12: CC770 SPI Interface Schematic

The MODE0 and MODE1 pins may be left open since they are weakly pulled low during

reset.

MOSI

MISO

SPICLK

CS#

CPU

(master)

CC770

(slave)

Int Request

Reset# MOSI

MISO

SPICLK

CS#

Int Request

Reset#

AD0

AD1

AD2

AD3

RD#

WR#

XTAL1

XTAL2

Vss

application

speciﬁc

Vcc

MODE0

MODE1

Vss

Data Sheet

BOSCH -65/85-

Rev. 1.8CC770

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8. Electrical Speciﬁcation

8.1 Handling Instructions

Handle with extreme care. Pins should not be touched. Follow ESD (Electrostatic Dis-

charge) protection procedure.

8.2 Absolute Maximum Ratings

Functional operation under any of these conditions is not implied. Operation beyond the lim-

its in this table may impair the lifetime of the device.

Note: For the conditions listed above the IC is protected against latch up effects.

*Category: A Parameter measured as analog value in series test program.

B Parameter tested as go/nogo test in series test program.

C Characterized only or guaranteed by design.

8.3 D.C. Characteristics

Conditions: VCC = 5V ±10%, Ambient Temperature TA = -40°C to +125°C

Parameter Value Cat*

Maximum rise-time of Supply-Voltage 1 V/µsC

Maximum Supply-Voltage (VCC-VSS) - 0.5 V to +7.0 V C

Maximum current at all inputs/outputs ± 25 mA C

Protection of I/O against ESD (HBM) PLCC44: ± 800V (1.5 kΩ,100 pF)

LQFP44: ± 1000V (1.5 kΩ,100 pF) C

Storage temperature PLCC44: -40°C to +150°C

LQFP44: -50°C to +150°CC

Table 15: Absolute Maximum Ratings

Parameter Min Max Unit Conditions Cat

VIL Input Low Voltage -0.5 0.8 V B

VIH Input High Voltage (All

inputs except RESET#) 3.0 VCC+0.5 V B

VIH1 Input High Voltage RESET#

Hysteresis on RESET# 3.0

200 VCC+0.5 V

mV B

VOL Output Low Voltage 0.45 V IOL = 1.6 mA A

Table 16: D.C. Characteristics

Common_ECharacteristics.fm

Data Sheet

BOSCH -66/85-

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(1) Typical value based on characterization data.

(2) All pins are driven to VSS or VCC, VCC = 5V, fXTAL = 16 MHz, fMCLK = 8 MHz

(3) Pull down resistors for mode 0 and 1 pins and pull up resistors for port 1 and 2 pins.

8.4 A.C. Characteristics

The following A.C. characteristics are valid for these operating conditions:

• Ambient Temperature TA -40 to +125°C

• Power supply VCC = 5V±10%, VSS = 0V

• Pin load CL = 100 pF

8.4.1 A.C. Characteristics for start-up

NOTES:

1. Cold reset means, that VCC is driven to a valid level while RESET# is asserted. In this

case, RESET# must be driven low for tCR minimum (measured from a valid VCC level)

to ensure the oscillator and the PLL are stable, see ﬁgure 13. No falling edge on the

Reset pin is required during cold reset phase.

2. The start up time of the oscillator (tSU_OSC) is application speciﬁc and highly depends

on the selected crystal respective the clock driver. The start up time of the oscillator

may be different in the cases of hardware reset and power up from sleep mode. The

times have to be determined as part of CC770 validation in the target application.

VOH Output High Voltage VCC-0.8 V IOH = -200 µAA

ILK Input Leakage Current ±1µAV

SS<VIN<VCC A

CIN Pin Capacitance(1) 10 pF fXTAL = 1 kHz C

ICC Supply Current(2) 50 mA A

ISLEEP Sleep Current, no Load(2) 100 µAA

IPD Power down Current(2) 25 µA XTAL1 clocked A

Rpull Pull resistor impedance(3) 15 kΩC

Symbol Parameter Min Max Cat

tSU_PLL Start Up Time of PLL 1 ms C

tCR Cold Reset Assertion Time(1) tSU_PLL + tSU_OSC(2) C

tWR Warm Reset Assertion Time(3) 1µsC

tPU Power Up from Sleep Mode(4) tSU_PLL + tSU_OSC(2) C

Table 17: A.C. Characteristics for start-up

Parameter Min Max Unit Conditions Cat

Table 16: D.C. Characteristics

Data Sheet

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3. Warm reset means, that VCC remains valid while RESET# is asserted. In this case,

RESET# must be driven to a low level for tWR minimum, see ﬁgure 13.

Figure 13: Timing for CC770 reset

4. When the Low Current Mode is left (by writing to Interface Register bits Sleep or PwD,

or by CAN activity in case of Sleep Mode), the CC770 may take up to tPU to come out of

Sleep/PwD Mode (until restarted oscillator and PLL are stable), see chapter 3.6.

8.4.2 A.C. Characteristics for clocks

NOTES:

1. The XTAL frequency may be lower than 8 MHz when the crystal at the XTAL pins is

replaced by a clock generator and the PLL is disabled, see chapter 4.4. This implies,

that the System and Memory clocks, which are derived from XTAL, will be lower accord-

ingly.

2. Load at CLKOUT pin should not exceed 50 pF.

3. Deﬁnition of CDVis the value loaded in the CLKOUT register representing the CLKOUT

divisor.

8.4.3 A.C. Characteristics for CAN interface

Symbol Parameter Min Max Cat

1/tXTAL Oscillator Frequency 8 MHz(1) 20 MHz B

1/tSCLK System Clock Frequency 4 MHz(1) 10 MHz B

1/tMCLK Memory Clock Frequency 2 MHz(1) 8 MHz B

tCOPD CLKOUT Period(2) (CDV(3) + 1) ∗ tXTAL C

tCHCL CLKOUT High Period(2) (CDV(3)+1)∗0.5∗

tXTAL-10ns (CDV(3)+1)∗

0.5∗tXTAL+15ns C

Table 18: A.C. Characteristics for clocks

Symbol Parameter Min Max Cat

tRx2Tx Internal delay Rx -> Tx 42 ns B

Table 19: A.C. Characteristics for CAN interface

tCR

VCC

RESET#

valid

Cold Reset

tWR

VCC

RESET#

Warm Reset

Data Sheet

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8.4.4 A.C. Characteristics for 8/16-Bit Multiplexed Modes (Modes 0, 1)

Symbol Parameter Min Max Conditions Cat

tAVLL Address Valid to ALE Low 7.5 ns B

tLLAX Address Hold after ALE Low 10 ns B

tLHLL ALE High Time 30 ns B

tLLRL ALE Low to RD# Low 20 ns B

tCLLL CS# Low to ALE Low 10 ns B

tQVWH Data Setup to WR# High 27 ns B

tWHQX Input Data Hold after WR# high 10 ns B

tWLWH WR# Pulse Width 30 ns B

tWHLH WR# High to next ALE High 8 ns B

tWHCH WR# High to CS# High 0 ns B

tRLRH RD# Pulse Width

This time is long enough to initiate a double read

cycle by loading the High Speed Registers

(04H, 05H), but is too short to READ from 04H

and 05H (See tRLDV)

40 ns B

tRLDV RD# Low to Data Valid

(only for registers 02H, 04H, 05H) 0 ns 55 ns B

tRLDV1 RD# Low Data to Data Valid

(for registers except 02H, 04H, 05H)

Read Cycle without previous write (1)

Read Cycle with previous write (1) 1.5tMCLK+100ns

3.5tMCLK+100ns

tRHDZ Data Float after RD# High 0 ns 45 ns B

tCLYV CS# Low to READY Setup

Condition: Load Cap. on the READY

output: 50 pF

32 ns

40 ns VOL=1.0V

VOL=0.45V B

tWLYZ WR# Low to READY Float

for a write cycle if no previous write is pending(2) 145 ns B

tWHYZ End of Last Write to READY Float

for a write cycle if a previous write cycle is

active(2)

2tMCLK +100ns B

tRLYZ RD# Low to READY Float

(for registers except 02H, 04H, 05H)

read cycle without previous write (1)

read cycle with a previous write (1) 2tMCLK+100ns

4tMCLK+100ns

tWHDV WR# High to Output Data Valid on port

1/2 tMCLK 2tMCLK+500ns B

Table 20: A.C. Characteristics for 8/16-Bit Multiplexed Modes (Modes 0, 1)

Data Sheet

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NOTES:

In 16 bit mode, two CC770 addresses will be accessed in parallel. The high byte (AD15-8)

contains the data related to the odd CC770 addresses and low byte (AD7-0) contains the

data related to the even CC770 addresses. Therefore the LSB of the address is without

function. The write access to the odd and even addresses is controlled by separate write

select lines WRH# and WRL#, to enable byte and word accesses. The timing is equivalent

to signal WR#. The read access is controlled by the single select line RD#, thus read

accesses are always word accesses.

1. Deﬁnition of ‘‘read cycle without a previous write’’:

The time between the rising edge of WR#/WRH# (for the previous write cycle) and the

falling edge of RD# (for the current read cycle) is greater than 2 tMCLK .

2. Deﬁnition of ‘‘write cycle with a previous write’’:

The time between the rising edge of WR#/WRH# (for the previous write cycle) and the

rising edge of WR#/WRH# (for the current write cycle) is less than 2 tMCLK .

Figure 14: Timing for 8/16-Bit Multiplexed Modes (Modes 0, 1)

tCLLL

tAVLL

Address

tRLDV tRHDZ

tRLRH tWHCH

tLHLL

tLLAX

ALE

BUS

RD#

CS#

WR#

BUS

PORT1/2

Address Data in

Data out

tWLWH tWHLH

tQVWH tWHQX

tWHDV

tLLRL

Data Sheet

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Figure 15: Ready Output Timing (write cycle, no previous write is pending)

Figure 16: Ready Output Timing (write cycle, previous write cycle is active)

Figure 17: Ready Output Timing for a Read Cycle

CS#

Ready

WR#

tWLYZ

tCLYV

CS#

Ready

WR#

tWHYZ

CS#

RD#

ALE

Ready

tCLYV

tRLYZ

Data Sheet

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8.4.5 A.C. Characteristics for 8-Bit Multiplexed Mode 2

NOTES:

1. Deﬁnition of ‘‘Read Cycle without a Previous Write’’:

The time between the falling edge of E (for the previous write cycle) and the rising edge

of E (for the current read cycle) is greater than 2 tMCLK .

Symbol Parameter Min Max Cat

tAVSL Address Valid to AS Low 7.5 ns B

tSLAX Address Hold after AS Low 10 ns B

tELDZ Data Float after E Low 0 ns 45 ns B

tEHDV E High to Data Valid for registers 02H,

04H, 05H 0 ns 45 ns B

read cycle without a previous write (1)

read cycle with a previous write

(registers except for 02H, 04H, 05H)

1.5tMCLK+100ns

3 tMCLK+100ns B

tQVEL Data Setup to E Low 30 ns B

tELQX Input Data Hold after E Low 20 ns B

tELDV E Low to Output Data Valid port 1/2 tMCLK 2tMCLK+500ns B

tEHEL E High Time 45 ns B

tELEL End of previous write (Last E Low) to

E Low for a write cycle 2 tMCLK B

tSHSL AS High Time 30 ns B

tRSEH Setup Time of R/W# to E High 30 ns B

tSLEH AS Low to E High 20 ns B

tCLSL CS# Low to AS Low 20 ns B

tELCH E Low to CS# High 0 ns B

Table 21: A.C. Characteristics for 8-Bit Multiplexed Mode 2

Data Sheet

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Figure 18: Timing for 8-Bit Multiplexed Mode 2

tCLSL

tAVSL

Address

tEHDV tELDZ

tEHEL

tRSEH

tSHSL

tSLAX

BUS

CS#

R/W#

BUS

PORT1/2

Address Data in

Data out

tQVEL tELQX

tELDV

tSLEH

tELCH

R/W#

Data Sheet

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8.4.6 A.C. Characteristics for 8-Bit Non-Multiplexed Asynchronous (Mode 3)

NOTES:

E and AS must be tied high in this mode.

Symbol Parameter Min Max Cat

tAVCL Address or R/W# Valid to CS# Low

Setup 3ns B

tCLDV CS# Low to Data Valid for High

Speed Registers (02H, 04H, 05H) 0 ns 55 ns B

For Low Speed Registers (Read

Cycle without Previous Write) (1) 0 ns 1.5 tMCLK +100 ns B

For Low Speed Registers (Read

Cycle with Previous Write) (1) 0 ns 3.5 tMCLK +100 ns B

tKLDV DSACK0# Low to Output Data Valid

for High Speed Read Register 23 ns B

For Low Speed Read Register < 0 ns B

tCHDV CC770 Input Data Hold after CS#

High 15 ns B

tCHDH CC770 Output Data Hold after CS#

High 0 ns B

tCHDZ CS# High to Output Data Float 35 ns B

tCHKH1 CS# High to DSACK0# = 2.4V (2) 0 ns 55 ns B

tCHKH2 CS# High to DSACK0# = 2.8V 150 ns B

tCHKZ CS# High to DSACK0# Float 0 ns 100 ns B

tCHCL CS# Width between Successive

Cycles 25 ns B

tCHAI CS# High to Address Invalid 7 ns B

tCHRI CS# High to R/W# Invalid 5 ns B

tCLCH CS# Width Low 65 ns B

tDVCH CPU Write Data Valid to CS# High 20 ns B

tCLKL CS# Low to DSACK0# Low for High Speed

Registers and Low Speed Registers Write

Access without Previous Write (3)

0 ns 67 ns B

tCHKL End of previous write (CS# High) to

DSACK0# Low for a write cycle with

a previous write (3)

0 ns 2 tMCLK + 145

ns B

Table 22: A.C. Characteristics for 8-Bit Non-Mux Asynchronous (Mode 3)

Data Sheet

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1. Deﬁnition of ‘‘Read Cycle without a Previous Write’’:

The time between the rising edge of CS# (for the previous write cycle) and the falling

edge of CS# (for the current read cycle) is greater than 2 tMCLK .

2. An on-chip pullup will drive DSACK0# to approximately 2.4V. An external pullup is

required to drive this signal to a higher voltage.

3. Deﬁnition of ‘‘Write Cycle without a Previous Write’’:

The time between the rising edge of CS# (for the previous write cycle) and the rising

edge of CS# (for the current write cycle) is greater than 2 tMCLK .

Figure 19: Timing for 8-Bit Non-Mux Asynchronous Mode (Mode 3), read cycle.

Address

tCLDV

tAVCL tCLCH tCHCL

tCHDZ

tCHDH

tCLKL tKLDV

tCHKH

tCHKZ

tCHAI

Data

CS#

R/W#

DSACK0#

Data Sheet

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Figure 20: Timing for 8-Bit Non-Mux-Async Mode (Mode 3), write cycle.

Address

tAVCL tCLCH tCHCL

tCHDV

tCLKL

tCHKH

tCHKZ

tCHAI

Data

CS#

R/W#

DSACK0#

tDVCH

Data Sheet

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8.4.7 A.C. Characteristics for 8-Bit Non-Multiplexed Synchronous (Mode 3)

NOTES:

1. Deﬁnition of ‘‘Read Cycle without a Previous Write’’:

The time between the falling edge of E (for the previous write cycle) and the rising edge

of E (for the current read cycle) is greater than 2 tMCLK .

Symbol Parameter Min Max Cat

tEHDV E High to Data Valid out of High

Speed Register (02H, 04H, 05H) 55 ns B

Read Cycle without previous

write for Low Speed Registers (1) 1.5 tMCLK +100 ns B

Read Cycle with previous write

for Low Speed Registers (1) 3.5 tMCLK +100 ns B

tELDH Data Hold after E Low for a read

cycle 5 ns B

tELDZ Data Float after E Low 35 ns B

tELDV Data Hold after E Low for a write

cycle 15 ns B

tAVEH Address and R/W# to E setup 25 ns B

tELAV Address and R/W# Valid after E

falls 15 ns B

tCVEH CS# Valid to E High 0 ns B

tELCV CS# Valid after E Low 0 ns B

tDVEL Data Setup to E Low 55 ns B

tEHEL E Active width 100 ns B

tAVAV Start of a write cycle after a pre-

vious Write Access 2 tMCLK B

tAVCL Address or R/W# to CS# Low

Setup 3 ns B

tCHAI CS# High to Address Invalid 7 ns B

Table 23: A.C. Characteristics for 8-Bit Non-Mux Asynchronous (Mode 3)

Data Sheet

BOSCH -77/85-

Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

Figure 21: Timing for 8-Bit Non-Mux Synchronous Mode (Mode 3), read cycle.

Figure 22: Timing for 8-Bit Non-Mux Synchronous Mode (Mode 3), write cycle.

Address

tAVCL tCHAI

tELAV

Data

CS#

R/W#

tCVEH

tAVEH

tEHEL

tELDZ

tELDH

tEHDV

tELCV

Address

tAVCL tCHAI

tELAV

Data

CS#

R/W#

tCVEH

tAVEH

tEHEL

tELDV

tDVEL

tELCV

tAVAV

Data Sheet

BOSCH -78/85-

Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

8.4.8 A.C. Characteristics for Serial Interface Mode

Symbol Parameter Min Max Unit Cat

fSPICLK SPI Clock Frequency 0.5 fMCLK MHz B

tCYC 1/fSPICLK 1/fMCLK 2000 ns B

tSKHI Clock High Time 45 ns B

tSKLO Clock Low Time 45 ns B

tLEAD Enable Lead Time 70 ns B

tLAG Enable Lag Time 70 ns B

tACC Access Time 60 ns B

tPDO Data Out Delay Time 30 ns B

tHO Data Out Hold Time 0 ns B

tDIS Data Out Disable Time 125 ns B

tSETUP Data Setup Time 25 ns B

tHOLD Data Hold Time 25 ns B

tRISE Input Rise Time 45 ns C

tFALL Input Fall Time 45 ns C

tCS Chip Select High Time 125 ns B

Table 24: A.C. Characteristics for Serial Interface Mode

Data Sheet

BOSCH -79/85-

Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

Figure 23: Timing for Serial Interface Mode (Polarity=0,Phase=0)

Figure 24: Timing for Serial Interface Mode (Polarity=1,Phase=1)

tHOLD

CS#

SPICLK

MISO

MOSI

tSKLO tFALL

tCYC

tLEAD

tRISE

tACC

tSETUP

tLAG tCS

tDIS

tSKHI

tPD0

tHO

tHOLD

CS#

SPICLK

MISO

MOSI

tLEAD

tACC

tSETUP

tLAG tCS

tDIS

tFALL tSKLO tSKHI tCYC tRISE

tPDO

tHO

Data Sheet

BOSCH -80/85-

Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

8.4.9 Waveforms for testing

Figure 25: Input and output reference waveforms

VCC

VSS

Output

Input

Timing parameter

A.C. test inputs are driven at the VCC and VSS

levels.

A.C. test outputs are measured at 1/2 VCC.

Input rise and fall times (10%/90%) < 10ns

1/2VCC

Data Sheet

BOSCH -81/85-

Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

9. Errata

9.1 Interrupt update during Initialization Mode

9.1.1 Scope

This erratum is only related to older steppings of the CC770, the latest F step1is not

affected by the issues described in this chapter.

Furthermore, this erratum applies only to applications that use the interrupt register and

interrupt pin.

9.1.2 Description

The CC770’s interrupt register is not updated while the Init bit (Initialization-Mode) is set.

The contents of the interrupt register must be considered invalid until Init is cleared. Since

the interrupt register may be frozen at a value /= 0x00, the Interrupt Enable bit IE needs to

be cleared when Init is set, to avoid a continuous active level at the interrupt pin.

9.1.3 Work-around

Apart from hardware reset, there are two possibilities how the Init bit can be set; either by

software or by the event "Entering BusOff State".

When Init is set by software, IE needs to be cleared by the same write-access to the

CC770’s control register. This will disable the Interrupt pin and does not change the internal

interrupt state.

When Init is set by the event "Entering BusOff State", the interrupt service routine needs to

clear IE (this will disable the Interrupt pin and does not change the internal interrupt state),

or it may alternatively clear Init, thereby also starting the BusOff Recovery Sequence.

1. CC770F: LQFP44 package (lead-free) 0 272 240 159 & PLCC44 package (lead-free) 0 272 240 160

DataSheet_Errata.fm

Data Sheet

BOSCH -82/85-

Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

Figure 1: Block Diagram of CC770.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 2: Package Diagrams of CC770 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 3: Time Segments of Bit Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 4: Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 5: CC770 handling of Message Objects 1-14 (Transmit). . . . . . . . . . . . . . 55

Figure 6: CC770 handling of Message Objects 1-14 (Direction = Receive). . . . . 56

Figure 7: CPU Handling of Message Objects 1-14 (Transmit) . . . . . . . . . . . . . . . 57

Figure 8: CPU Handling of Message Objects 1-14 (Receive) . . . . . . . . . . . . . . . . 58

Figure 9: CPU Handling of Message Object 15 (Receive). . . . . . . . . . . . . . . . . . . 59

Figure 10: Interconnection for serial communication. . . . . . . . . . . . . . . . . . . . . . 61

Figure 11: Serial data communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 12: CC770 SPI Interface Schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 13: Timing for CC770 reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 14: Timing for 8/16-Bit Multiplexed Modes (Modes 0, 1) . . . . . . . . . . . . . . 69

Figure 15: Ready Output Timing (write cycle, no previous write is pending). . . 70

Figure 16: Ready Output Timing (write cycle, previous write cycle is active) . . 70

Figure 17: Ready Output Timing for a Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 18: Timing for 8-Bit Multiplexed Mode 2. . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 19: Timing for 8-Bit Non-Mux Asynchronous Mode (Mode 3), read cycle. 74

Figure 20: Timing for 8-Bit Non-Mux-Async Mode (Mode 3), write cycle. . . . . . . 75

Figure 21: Timing for 8-Bit Non-Mux Synchronous Mode (Mode 3), read cycle. 77

Figure 22: Timing for 8-Bit Non-Mux Synchronous Mode (Mode 3), write cycle. 77

Figure 23: Timing for Serial Interface Mode (Polarity=0,Phase=0). . . . . . . . . . . . 79

Figure 24: Timing for Serial Interface Mode (Polarity=1,Phase=1). . . . . . . . . . . . 79

Figure 25: Input and output reference waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 80

Data Sheet

BOSCH -83/85-

Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

Table 1: Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Table 2: Multi Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Table 3: Reset values of CC770 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Table 4: Reset states of CC770 output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Table 5: CC770 address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Table 6: Function of Power Down and Sleep bits . . . . . . . . . . . . . . . . . . . . . . . . . .26

Table 7: Maximum MCLK frequency for various oscillator frequencies . . . . . . . .27

Table 8: Programming ClkOut . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 9: Programming ClkOut slew rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Table 10: Interrupt Register values with corresponding Interrupt Sources . . . . .42

Table 11: Message Object Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Table 12: Representation of bit pairs in Control Registers . . . . . . . . . . . . . . . . . .45

Table 13: Bit combinations to start transmissions . . . . . . . . . . . . . . . . . . . . . . . . .49

Table 14: CPU interface modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Table 15: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Table 16: D.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Table 17: A.C. Characteristics for start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Table 18: A.C. Characteristics for clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Table 19: A.C. Characteristics for CAN interface . . . . . . . . . . . . . . . . . . . . . . . . . .67

Table 20: A.C. Characteristics for 8/16-Bit Multiplexed Modes (Modes 0, 1) . . . .68

Table 21: A.C. Characteristics for 8-Bit Multiplexed Mode 2 . . . . . . . . . . . . . . . . .71

Table 22: A.C. Characteristics for 8-Bit Non-Mux Asynchronous (Mode 3) . . . . .73

Table 23: A.C. Characteristics for 8-Bit Non-Mux Asynchronous (Mode 3) . . . . .76

Table 24: A.C. Characteristics for Serial Interface Mode . . . . . . . . . . . . . . . . . . . .78

Data Sheet

BOSCH -84/85-

Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

10. Appendix

10.1 Documentation of Changes

10.1.1 Changes on Revisions

10.1.1.1 Revision 1.0

Initial version.

10.1.1.2 Revision 1.1

Speciﬁcation left preliminary state.

Protection against ESD reduced to 800 V.

Timing parameters tCOPD and tCHCL are now categorized to C.

10.1.1.3 Revision 1.2

Package Diagram now more detailed.

Clockout pin is active while reset is active, see chapter 3.2.2.

Flare clocking limitations, see chapter 4.4.1.

Behaviour of Serial Reset address, see chapter 4.16.

Mode0/1 Pins must be connected in any conﬁguration, see note in chapter 7.1

fSPICLK must not be higher than fMCLK, see chapter 8.4.8.

Notes to the design steps B and C are not supported anymore.

10.1.1.4 Revision 1.3

Add errata description for CC770 with stepping D.

Product number of package diagram modiﬁed.

10.1.1.5 Revision 1.4

Introduction of new LQFP44 package.

10.1.1.6 Revision 1.5

Add important information for DSACK pin wiring at the end of chapter 3.1.

Correct table in chapter 3.2.2. The port 1 and 2 pull up resistors are not off but on directly

after reset, according notes to pin descriptions at the end of chapter 3.1.

Add information for entering power down, see chapter 3.6.

Add further information to BOff and Warn status bits, see chapter 4.3.

Better differentiation between CC770 interrupt methods, see chapter 4.3.1.

Correct packet count value of Bus Off Recovery Sequence to 129, see chapter 4.3.

Correct reset value of CPU Interface register, see chapter 4.4.

Add information about tCLDV, see chapter 4.5.

Correct timing for second read to High Speed register, see chapter 4.5.1.

Add information about pull up control, see chapter 5.

Correct description of the EP ﬂag in Receive Error Counter (6FH). This bit does not ﬂag the

receive error passive only, but both receive and transmit error passive. Thus the ﬂag was

renamed to EP, see chapter 4.12.

DataSheet_Appendix.fm

Data Sheet

BOSCH -85/85-

Rev. 1.8CC770

14.09.2010

editing, distribution, as well as in the event of applications for industrial property rights.

Add impedance of pull up and pull down resistors, see chapter 8.3.

Add information to interface modes 0 & 1, see chapter 8.4.

Add new chapter for a further erratum concerning all CC770 steps, see chapter 9.

10.1.1.7 Revision 1.6

Update of chapter chapter 9. according veriﬁcation of work-around for BusOff erratum.

10.1.1.8 Revision 1.7

Renamed "BusOff" erratum to "Interrupt update during Initialization Mode" erratum (new

name describes cause instead of effect) and alternative workaround proposed.

Removed errata description for D-Step of CC770 from Data Sheet (this stepping was never

shipped to external customers).

Editorial changes.

Added parameters for start-up, see chapter 8.4.1.

Added parameter for internal Rx -> Tx delay, see chapter 8.4.3.

10.1.1.9 Revision 1.8

Updated revision history related to revision 1.7.

Added ordering information for F-Step of CC770.

Clariﬁed description of reserved bits in Bus Conﬁguration Register, see chapter 4.11.

Added description of bit 6 in Bus Conﬁguration Register, see chapter 4.11.

Added information about the inﬂuence of bit 6 on Silent Mode, see chapter 3.5 and chapter

4.11.

Erratum "Interrupt update during Initialization Mode" does not apply to F-Step, see chapter

9.1.