eRe eee ee) DATA Slee T 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51 RA+ 8-bit CMOS (low voltage, low power and high speed) microcontroller families Preliminary specification 1997 May 30 Supersedes data of 1997 Apr 23 IC20 Data Handbook Philips PHILIPS Semiconductors go DH i LI PS VyPhilips Semiconductors Preliminary specification 8-bit CMOS (low voltage, low power and high speed) microcontroller families 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+1/RB+/RC+/RD+/80C51RA+ DESCRIPTION Three different Single-Chip 8-Bit Microcontroller families are presented in this datasheet: 80C32/8XC52/8xC54/8XC58 80051 FA/8XC51 FA/8XC51 FB/8XC51FC 80051 RA+/8XC51RA+/8XC51 RB+/8XC51 RC+/8XC51RD+ For applications requiring 4K ROM/EPROM, see the 8XC51/80C31 8-bit CMOS (low voltage, low power, and high speed) microcontroller families datasheet. All the families are Single-Chip 8-Bit Microcontrollers manufactured in advanced CMOS process and are derivatives of the 80C51 microcontroller family. All the devices have the same instruction set as the 80C51. These devices provide architectural enhancements that make them applicable in a variety of applications for general control systems. FEATURES 80051 Central Processing Unit Speed up to 33MHz Full static operation Operating voltage range: 2.7Vto5.5V @ 16MHz Security bits: ROM -2 bits OTP/EPROM 3 bits Encryption array 64 bytes RAM expandable to 64K bytes 4 level priority interrupt 6 or? interrupt sources, depending on device Four 8-bit I/O ports ROM/EPROM RAM Size Programmable | Hardware e . Memory Size (X by 8) Timer Counter | Watch Dog Full-duplex enhanced UART (X by 8) (PCA) Timer Framing error detection BDC31/EXC51 Automatic address recognition Pp trol mod OK/4K 128 No | No ower control modes - Clock can be stopped and resumed 80C32/8XC52/54/58 Idle mode OK/8K/16K/32K | 256 | No No Power down mode 80051 FA/8XC51 FA/FB/FC Programmable clock out OK/8K/16K/32K | 256 | Yes No Second DPTR register 80C51RA+/8XC51 RA+/RB+/RC+ Asynchronous port reset OK/8K/16K/32K | 512 | Yes Yes Low EMI (inhibit ALE) 8XC51AD+ 64K | i024 | Yes | Yes LOGIC SYMBOL The ROMless devices, 80032, 80C51FA, and 80C51RA+ can Noo Nss address up to 64K of external memory. All the devices have four yy XTAL <> + 8-bit lO ports, three 16-bit timer/event counters, a multi-source, a7 <> <> four-priority-level, nested interrupt structure, an enhanced UART L >| 2 4 | ADDRESS AND and on-chip oscillator and timing circuits. For systems that require = <> 5 | DATABUS extra memory capability up to 64k bytes, each can be expanded i 1 . <* & : , using standard TTL-compatible memories and logic. xtate <> +> . . = +$+ | T2 Its added features make it an even more powerful microcontroller for <> T2EX applications that require pulse width modulation, high-speed I/O and RST . L up/down counting capabilities such as motor control. It also has a EAMpp >| >| 6 more versatile serial channel that facilitates multiprocessor PSEN >) = communications. wy ALEPROC<> > z e! S| RxD <_| 5] TxD< = | > <__> _y | TNT oo | $3 Lw <> Ni > <>| o> ADDRESS BUS =| T1 o |> -<_ _ 5 WH _*, <_ 3 Fb< _+ <_r +| w suaoage 1997 May 30Philips Semiconductors Preliminary specification 8-bit CMOS (low voltage, low power 8XC52/54/58/80C32 tC ( vitage, P vy: 8XC51 FA/FB/FC/80C51 FA and high speed) microcontroller families 8XC51RA+/RB+/RC+/RD+/80C51RA+ BLOCK DIAGRAM PO.0-P0.7 P2.0-P2.7 ~-=--=-==-=--- i | PORT 0 PORT 2 | DRIVERS DRIVERS vi | 2 ze rt Lat Vgs| Vv = [RAS iste ae | [powernouk fi J U U J J y u 1 B STACK REGISTER ACC POINTER I Z PROGRAM [4 ADDRESS K- TMP2 TMP1 REGISTER R Nu il K > BUFFER d L SFRs TIMERS PC | | | | | | | | | | | | | | | | | | | | a aLEPROG #4 TIMING PSW P.C.A (FA & RAL only} MENTER = zs ata 4T 16 PROGRAM COUNTER K> PSEN 6 Ew SEA DPTR'S AND | 2 2N , MULTIPLE > EAVpp CONTROL] F AST zu U | PD PORT 1 PORT 3 | LATCH LATCH | OSCILLATOR U U | PORT 1 4 PORT 3 | DRIVERS DRIVERS a a a a THA CB ode OO ~ o P1O-P17 P3.0-P3.7 Sueoss ib 1997 May 30 3Preliminary specification 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C5 1 RA+ Philips Semiconductors 8-bit CMOS (low voltage, low power and high speed) microcontroller families ; gasnssozed agsanrsozed} gasnzsozed| dlo ZZ0ELOS | O10 AS PEd FEI PEND INSEid 'G8t+ 01 OF agsnzeoosd gasnssoosd agsanrsoosd | gasnzsoosd | WOU 8go/8 rso48 2g048 l6ZLLOS | s& O10 AS aBeyoeq AUll-Ul [ENC ISeld G8+ Ol OF NdAnzeoosd Nearer NeStveo sed | _Nesneocee pale Ndsngsoo0sd Ndanrsoosd | Ndan@soosd | WOU dNssol8d Vwdnrsosed| vvdneso/8d| dlo Z-28+LOS| 910 AS JBUIED AID pepee] WSE|iq 'SBt 1 OF YWANzeo08d dnsso08d Vvdnrsoosd | WANeso08d | WOU gsoz98 rsoze 2g08 ZZ0ELOS | O10 AS Ed Fl PEND WseIlq OZ+ O10 gaanzeoosd =e Sears Red | _seenesored | ote aganssoosd ddanrsoosd | daanzsoosd | WOU ggo/98 PSO18 2990/8 /6Z1LOS | O10 AS obeys Sull-Ul [ENC IISE|q O/+ O10 Ndanzeoosd Nearest se Roane Red | __Neiseted | ote Ndangsoosd Ndanrsoosd |} Ndanzsoosd | WOU gsoz98 psoze 2G048 Z-281LOS | ce clo AS JaWeD dIYD papeay SISElq OL+t O10 yvanzeoosd ee weed | _vvere ee pe vvanesoosd vvanrsoosd| vvanzsoo0sd | WOU ggo/98 psos9 Zgo49 Z-20ELOS | 72 910 AS Ed Tl PEND INSeid GBt O1 OF - Erne } ep ddslesoosd daddlrsoosd | g. dal2so08d | WOU gso/98 rsoz98 29048 22811OS| +210 AS JOUIED IUD pepeey WSBIq 'S8t 1 OF Waleeoosd versed Wvaresi ted | _V vsnueed | ote Wdlesoosd VWdlrsoosd | v AL@so08d | WOU 8so/98 pSo/8 2g048 l6ZLLOS | +2010 AS eBexoed SUll-Ul [ENC ISeld G8+ Ol OF - Neste Nera red | _Nesieoceep ae N dsleso0sd Ndalrsoo0sd} NdAL@soosd | WOU gso/98 psoze 2g048 ZL0ELOS | 7210 AS Ed Fl PEND WseIlq OZ+ O10 - seed eee eed | _ dst aaalesoosd ddalrsoosd| a dalzsoosd | WOU ggo/98 psos9e 2G048 2-28L10S | +2 O10 AS Jaed dIYD papeay SISElq OLt O10 yvale2eoosd e re} eee yValesoosd VValrsoosd | vWal2so08d | WOU ggo/98 psos8 2998 L-6z-LLOS | +2010 AS ebeysed Sull-ul feng IISe|d Os+ O10 - Ndaleso/8d Ndelrsozed NdalesoZ8d | dio Ndalesoosd Nda@lrsoosd | Ndalzsoosd | WOU eso/98 PSOt98 Zg0498 Z-Z0ELOS| 9b O10 | ASGOLALZ Ed Tl PEND INSeid GBt O1 OF qasszeoosd ae Sess eed | See eee pa gassesoosd dassrsoosd| da4szso08d | WOU ggo48 PSO18 29048 Z28LLOS| GLO | AGSOLAL S| Jalueg dD pepee) ose |q Sgt 01 OF Vv vASzeo0sd eee weed | eee ef te V4S8so08d Vvasrso08d | vViS2S008d | WOU 8go/98 rSO48 2g048 16ZLLOS}] 9LOlO | AFSOLALZ| eBex9eq eUll-Ul fend INseIq G8+ Ol OF NddSzeo0sd Nessred eed | Nese pate NdjSesoosd Nddsrso0sd | Ndds2zso08d | WOU adasesosed ddasrso/8d}| ddaszsosed| dlo ZL0ELOS| QF olo | AGOLALZ Ed Tel PEND Wseld O/+ 010 adaseeoosd gaasesoosd adasrsoosd| ddaszsoosd | WOU yvasesosed VvaSrSo/8d| vvdSzso/8d | dio Z-28LlOS| 9b ola | ASSGOLALZ Jaed dIYD papeay SISElq OLt O10 yWaSzeo0sd vvasesoosd VvaSrso08d | _ WaS2s008d | WOU eg0/98 S018 29948 L6Z-LLOS}] SLOIO | ASSOALZ obese Sull-Ul [ENC IISe|q OZ+ O10 Ndaszeoosd neeee ie Ressrcled | Ndebele Ndasesoosd NdaSrsoosd | Ndaszsoosd | WOU # (ZHI) FONVY 3DVHOVd ONY SSOINOH 8X HE 8x OL 8X48 oma =| OFS | JDVLIOA Dd. JONVY SHNLWHadWaL 3ZIS AMOWSIN | SZISAHOWSW | JZIS AHOWSN NOLLVAYOANI SNIGAGHO 2008 ANV 8S/PS/eSDX8 1997 May 30Preliminary specification 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C5 1 RA+ Philips Semiconductors 8-bit CMOS (low voltage, low power and high speed) microcontroller families ar-oslsozed | af-aalsozed | af-walsozed | dlo ZLOELOS| f&10 AS SPE II PEND ISEld Uld-Fr GBt OF OF ar-ws so08d aroslsoesd | af-dalsoeed | af-wilsoeed | WOU 1soz8 .$028 1soz8 ZL8LLOS| s& 0 AS seuseg dio pape] onseid Uld-ry get olor | yr-vaisooeg LWOSseOied | Wes Sree jee pe yr-oalsoesd | wr-ddisoesd | vrvalsoesd | WO" s028 $028 S048 /6ZllOS] & O10 AS Bid Oul|-Ul feng ouSeid Uid-OF gB+ Ooh | Nrw4isoosq -NOOSOled | NT eS soled | Need | te Nf-Os'sossd | Nf-dsisoesd | Nf-walsoesd | WOU 1soz8 -d41soz8 Wd S028 eLOELOS | fs 0 AS PEd IY PEND SEI Uld-rr 'OZ+t O10 di-v4isoosg Siete ed | eee Se ai-Oslsoesd | di-dsisoesd | al-wilsoesd | WOU 1s928 -d41Soz8 Wd 1S0/8 ZL8llos| s&o10 AS euseg dud pepe oNseid Uld-ry os+o10 | vi-v4isoosd - Seed | Vee eee Vi-Oalsoesd | Wreddlsoeed | vi-vilsoesd | WOY -941S0z8 .SO298 -VIlSOz8 /8ZL1OS]} O10 AS BY. EU-Ul [ENG WSE|d Uld-OF 02+ O10 N-v4iso8g LOTTE eee Ni-OsbsOesd | Niraslsoesd | Ni-wilsoesd | WOX SOs8 d41soz8 -W4lSOz8 ZLOELOS | 7% 910 AS PB Il PEND ISEld Uld-Fr GBt OL OP - _ | ere te dd-Os!soesd | aa-aalsoesd | aa-walsoesd | WOU S028 -d41soz8 -W4 S028 ZL8LLOS| +zo10 AS seuseg dio pape] onseid Uld-ry gst oor | ya-v4isoosg | YE YS sored | Vered sored | vera eured ple Va-Os 068d | Va-dslsoeed | va-wisossd | WOU -94 1S028 $048 Wa SOz8 -6zllOS]| 7Z O10 AS Bq OUI-Ul [ENG WSEld Uld-OF SBt Ol OF - eee eee ee Nd-041S0e8d | Nd-ds'sossd | Na-v4lsoesd | WOY GOs8 d4 S048 W4 }G048 ZLOELOS | +Z 910 AS Ed WY PEND ISEld Uld-rr OL+ O10 - EeE Err av-OsS0E8d | dav-dslsoeed | av-wisossd | WOU SO/8 d41G048 W4 S028 ZABLLOS| 7% 910 AS aze9 diyo papesy auseid Uld-rb oZ+ O10 | Yw-W4isoosd PSE | ree pte VW-Od!SoE8d | vW-dalsoeed | vv-W4lsossd | WOu -94 1028 s928 WI 1SOL8 /82L1OS| Pz o10 AS BY. EU-Ul [ENG WSE|d Uld-OF 02+ O10 - Meet | Mvres ele 4 NV Ne eee | ote Nw-O41soeed | Ny-d4lsoeed | Nv-vdlsoesd | WOY aS-O4'SO48d | aS-assozed | as-walso/ed | dlo ZLOELOS| 9190 | ASSOALZ | ed FY PEND Seid Uld-rr GBt+OlLOP- | aS-W4 }SO08d gsO41sossd | aS-aslsoesd | as-walsoesd | WOY , WS-O4'SO48d | WS-d4lsoz8d | vS-valso/8d | dlo ZLBbLOS] 94910 | ASSOALS | JeweO dD papesy ONSelq Uld-ry S8+ OOF | WS-V4-SO08d WS-O4'sOe8d | vS-d4lsoesd | vS-valsoesd | WOU -94 19028 S44 1S0z8 S-V41SO/8 Lezttos| 9:10 | agsoracz | Big eur-u) eng onseiq uld-oF set ror | Ng-v4isoogg JOE eed | NEE eae pe NS-O41S0E8d_| NS-dalsoesd | NS-wW4lsossd | WOU Os SOz8 pds S048 P-WAlSOL8 ZLOELOS| 91910 | AGSOALZ Ed WY PEND ISEld Uld-rr OL+ O10 ar-viisoosd Pe Ss ored | ar ee sored | Severed | ote dros lsoesd | ar-asisoesd | drwalsoesd | WOY ; Wr-04!SO48d | Wr-dalsoz8d | vrvalso/ed | dlo ZABLLOS| 9190 | ASGOALZ | Jaleo dio papeey oNseld Uld-ry O/+O10 | Wr-Wd1SO08d We-O4lsoesd | vroadisoesd | wr-walsoesd | WOu Nr-Os1S0/8d | Ne-ddlsozed | Ne-Wilsozed | dlo -6ZLlOS] 91 OO] ASSOALE Bq GUI}-Ul [ENG WSEld Uld-OF OZ+ O10 Ne-W4 bS008d Nr-Os1so0eed | Nr-ddisoeed | Ne-Wilsoeed | WOY # (ZHIN) 3ONVY 3OVAOVd GNV SSOINOU 8X Ze 8x 9b gx 48 oma =| 03y4 | ADVIIOA Oo SONVY SHNLWHAdWAL 3ZIS AMOWSW | 3ZIS ANOWAW | 3ZIS ANOWSW NOLLVINYOANI SONINSCHO V4lLSD08 ONV 34/44 lSOX8 1997 May 30Preliminary specification 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C5 1 RA+ Philips Semiconductors 8-bit CMOS (low voltage, low power and high speed) microcontroller families ditgy }S048d WOdd3a 6 . - L-6ZLLOS | 8 O10 AS oto | Nitwuisoosd | NitGuisozed | NitoHisozed | Nit@ulsozed | NitWHIsoved | d1o NitaHisoeed | NItOHLSOeed | NItdHiSOeed | NitvHisoeed | WOH s-roe1os| +2010 hg OE Fld PEND ANSE] Uld-r> - Ag+OH1GO/8d | adtaylsozed | adtwHiSOzed | dO GB+ 01 0b dd+oulsoesd | ad+aulsoeed | aatvulsosed | WOH srarios| szo10 hg seureg diyp pepes] aISe|q Uld-rp - VEOH GO/8d | vatdulsozed | vatwHiso/ed | dO SB Ol OP vatoulsoesd | vataulsoesd | VatVHISOesd | WOU -ezitos| +ze10 hg Bq Oulu FENG ANSEIg Uig-OF - N@+oulsozed | Nataulsozed | Natwulsozed | dO SB Ol OP NatoulSOsed | Natadlsosed | Natvulsosed | WOU s-roe1os| +2010 A oeq Tel PEND NSE Id Uld-rr - aV+OH!SO/8d | avtdulsozed | avtvHisoved| do OL* O10 avtoulsoesd | avtaulsoeed | avtvHisossd | WOU z-a1tos| $2010 AS 4allieD dIYD papes] IISe\d Uld-rr _ WWtOHISO/8d | VWtdylso/ed | WwtvHiSO/ed | dO 02* OFO vwtou lsoeed | vWtaHlsoeed | WWtVHISOesd | NOH -ezitos | $zo10 AS Bq OUI-U [ENG INSeld Uld-OF _ N+OulSOzed | NvtaHiSozed | NvtWHISOzed | dO 02* OFO NV+OHLSOSed | NV+aHisosed | N+VHISosed | WOU . StGH1SO/8d | aStoulsozed | astaHisosed | astvuisozed | do Z-L0EL08] 9110] ASSoArZ | "PYd WS PAO Md Mid'yy | astyulsoosd astaulsoeed | astoulsoced | astayisoesd | astvulsoeed | WOH . WStGH1SOZ8d | vStOHlsozed | vStaHisosed | vstvulsozed | do Z-281L08| 91 10] Ags orarca | MPO SMO PePeaT oNseld Uld-Pr | ory coogd S8* OLOP- VStdH soeed | WStOHlSOSed | vStaHsosed | vStvulsosed | WOU . . . NS+H1S0/8d | NStOH:SO/8d | NStaHiSOzed | NStwHiSOzed | dO Fezilos} sic1o| agsaaze | Md SILER ousPid Mid | Nc+yyicooad SBF OF Ob- NStdHFSOeed | NS+OULSOesd | NStaHLSOesd | NStWHLSOesd | WOY ; a@r+aHlso/ed | artoulsozed | drtayiso/ed | artyulsozed | do Z-L0ELOS] 9Lor0} Ags ArZ| "PPA W RO AW eld UidY | aetyulsoosd dvtauisoeed | artoulsoced | drtayisoesd | artyulsoesd | WOU Art+dY /SOs8d WOdd3a d - Z-81L08| 91 010] Ags orqzz | Pd ONO RNS seid PE) vitwulsoogd | veraulsozed | wrroulsozed | wrrauisozed | wrrvulsozed | do vrtauisoesd | vrtoulsoced | vrrayisoesd | vrtvulsoesd | WOU drtqdy +$0/8d WOdd34 Lezilos| gto] assoace| 4 cee erog | Net weiSoogd | NrtGyisozed | NrtOulsoved | Nrtaulsozed | Nrtvulsozed | d1O Nrtdylsoeed | NrtOHlsoeed | NrtaHisoesd | NrtwHisoesd | WOH # (ZHW) | SONVY AOVHAOVd ONV SSOINOU 8x 4r9 8% NZS $x HL axw8 oma =| OaH4] FOVIIOA | 0. FONVHY SYNLVHAdWAL JzIS AMOWSW | JZIS ANOWSW | 3zIs ANOWAW | 3ZIS ANOWSIN NOLLVINUOANI SNIYSAGHO tHLSO08 ONY t0y/*00/*Eu/F VU LSOZ8 1997 May 30Preliminary specification 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C5 1 RA+ Philips Semiconductors 8-bit CMOS (low voltage, low power and high speed) microcontroller families YIE FE|4 PEND IISe]g Uld-FF argu +$048d arto /S048d drt+dy -s048d artvy }S048d dio Z-LOELOS | O10 AS GBt olor artvu iso0sd arauisossd | artoulsoesd | artauisossd | artvHisoesd | WOH . wrtauisozed | wr+oulsozed | wrtaylsozed | wrtvulsozed | dlo Z-L81L0S | O10 AS ZO1U89 GIO pepes 1 OIseld Ud? | yrs iso08d WPtaHlsoEsd | wr+OHlsoEsd | vrtaHlsoesd | vrtvHlsoEsd | WOY . . . Nr+aulsozed | NTOulSOzed | Nrtauisozed | NPtvHISOZed | dlo |-621L0s | O10 AS Pie utr rend ouseid Wid OF | ptye.so0Kd Nau lsoeed | NPOHLSOEed | Nrtaulsoeed | NPtVvHLSOEed | WOY . aitdylsoze8d | aitoulsozed | altauisozed | altvulsozed | do 2-L0EL0S8 | 10 AS eee eo tT tt | altwaLsoosd altaulsoesd | aitoulsoesd | aitayisoesd | aitvulsoesd | WOU Alte + SO48d WOud4s 2-281L08 | O10 AS Zeule9 GUO pepeeluseld Ud-ry | yisvuisoosd | wirauisozed [| viroulsozed | vitauisozed | wiewuisozed | do WitGyLsoeed | vitoHlsoesd | vitauisoeed | vitvHisoesd | WOH 4 (ZHI) | SONVH AOVHOVd ONV SS9IINOH 8X HPS 8X Wee 8X HSL 8x48 pwd | oaus| SDVLIOA | 0. 3ONVY SHNLWuadWAL 3ZIS AYOWAW | 3ZIS AUOWSW | 3ZIS ANOWAIN | 3ZIS ANOWSIN 1997 May 30Philips Semiconductors Preliminary specification 8-bit CMOS (low voltage, low power and high speed) microcontroller families 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ PIN CONFIGURATIONS DUAL IN-LINE PACKAGE PIN FUNCTIONS T2P1.0/ 4 | T2EX/P1.1] 2| ECUPI.2[ 3| CEXO/P1 3] 4 CEX1/P1.4[ 5 | CEX2/P15| 6 | CEX3/P1.6[ 7 | CEX4/P1.7[ 8| RST[9| FxDyP3.0[ 10} TxDyP3.1| 11] INTOPS 2| 12 INTTP3.3[ 19 To/P3.4{ 14] T1P3.5| 15 WHIPS 6| 16 Dips. 7/17| XTAL2 | 19 XTAL1 | 19 Vss [20] yO DUAL IN-LINE PACKAGE 40] a9] aa] a7] a] as a] a3] a9] Ed Ey) 3] a3] 27 EJ a5] zy 3] 22] 24] Voc PO.o/ADO PoO.1/AD1 Po.2/AD2 PO.3/AD3 Po.4/AD4 PO.5/ADS Po. 6/ADB Po. 7/AD? EANVpp ALE/PROG PSEN P2.7/A15 P?.B/A14 P2.5/A13 P24/A12 P2.3YA11 P2.2/A10 P2.1/A9 P2.0/A8 Suoo021 CERAMIC AND PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS Pin Function 1 Nic* 2 Pt.0T2 3 PI.A1T2EX 4 P12/Ecl 5 P1.3/CEXo 6 P1.4/CExX1 7 P1.5/CEX2 & P1.6/CEXS3 9g P1.7/CEX4 10 RST 11 P3.0/RxD 12 = WNICc* 13 -P3.1/TxD 14. - P3.2INTO 15 P3.34NTT *NO INTERNAL CONNECTION Loc Function P3.4/TO P3.5/T1 P3.6ANR P3.7/AD ATAL2 XTALI Vss NIc* P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 40 28 BE: a 29 Pin Function 31 P2.7/A1S 32 PSEN 330 ALE/PROG 34 NIc* 35 EAVep 36 =PO.7IAD7 37 = PO.6/ADB 38 = =PO.S'ADS 390 Po.4/AD4 40 =PO3/AD3 4 PO.2/AD2 42 PoOt/AD1 43 Po.o/ADO 44. Voc SU00023 1997 May 30 PLASTIC QUAD FLAT PACK PIN FUNCTIONS Pin Function 1 P1.S/CEX2 2 P1.B/CEX3 3 P1.7/CEX4 4 RST 5 P3.0/RxD 6 NIC* 7 P3.1/TxD 8 P3.2,1NTO 9 P3.3/1NTT 10 = -P3.4/TO 11 P3.5/T1 12. P3.64VA 13 P3.7/AD 14 XTAL2 15 XTAL1 NO INTERNAL CONNECTION Pin Function Ves NIC* P2.0/A8 P21/A9 P2.2/A10 P?2.3YA11 P2.4/A12 P2.5/A13 P2.B/A14 P2.7/A15 PSEN ALE/PROG NIC* EAVpp PO.7/AD7 Pin Function 3 Po.B/AD6 32 PO.SADS. 33 Po.4/AD4 34 PO.3'ADS 35 PO.2/AD2 36 PO.1/AD1 37 PO.G/ABO 38 Voc 39 NIC* 40 P1aT2 41 P1.14/T2EX 42 P1.2/ECI 43 P1.3/CEXO 44 P14/CEX1 suo024Philips Semiconductors Preliminary specification -bi 8XC52/54/58/80C32 6-bit CMOS (low voltage, low Power 8XC51 FA/FB/FC/80C51 FA and high speed) microcontroller families 8XC51RA+/RB+/RC+/RD+/80C51RA+ PIN DESCRIPTIONS PIN NUMBER MNEMONIC] DIP | LCC | QFP | TYPE | NAME AND FUNCTION Vss 20 22 16 | Ground: OV reference. Vec 40 44 38 | Power Supply: This is the power supply voltage for normal, idle, and power-down operation. PO.0-0.7 39-32 | 43-36 | 37-30 VQ | Port O: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port Ois also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the code bytes during program verification and received code bytes during EPROM programming. External pull-ups are required during program verification. P1.0-P1.7 1-8 2-9 | 40-44, VG | Port 1: Port 1 is an 8-bit bidirectional I/G port with internal pull-ups. Port 1 pins that have 1s 1-3 written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: |\.). Port 1 also receives the low-order address byte during program memory verification. Alternate functions for BXC51FX and 8XC51RX+ Port 1 include: 1 2 40 VO T2 (P1.0): Timer/Counter 2 external count input/Clockout (see Programmable Clock-Out) 2 3 41 | T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Gontrol 3 4 42 | ECI (P1.2): External Clock Input to the PCA 4 5 43 VG GEX0 (P1.3): Capture/Compare External I/O for PCA module 0 5 6 44 va GEX1 (P1.4): Capture/Compare External I/O for PCA module 1 6 7 1 va GEX2 (P1.5): Capture/Compare External I/O for PGA module 2 7 8 va GEX3 (P1.6): Capture/Compare External I/O for PCA module 3 8 9 3 vo CEX4 (P1.7): Capture/Compare External I/O for PCA module 4 P2.0-P2.7 | 21-28 | 24-31 | 18-25 VO | Port 2: Port 2is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: |j_). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. Some Port 2 pins receive the high order address bits during EPROM programming and verification. P3.0-P3.7 | 10-17] 11, 5, VO | Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s 13-19 | 7-13 written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: ||_). Port 3 also serves the special features of the 80C51 family, as listed below: 10 11 5 | RxD (P3.0): Serial input port 11 13 7 o TxD (P3.1): Serial output port 12 14 8 | INTO (P3.2): External interrupt 13 15 g | INT1 (P3.3): External interrupt 14 16 10 | TO (P3.4): Timer 0 external input 15 17 11 | T1 (P3.5): Timer 1 external input 16 18 12 6 WR (P3.6): External data memory write strobe 17 19 13 6 RD (P3.7): External data memory read strobe RST 9 10 4 | Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to Vsg permits a power-on reset using only an external capacitor to Ver. ALE/PROG 30 33 27 | Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted ata constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG) during EPROM programming. ALE can be disabled by setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction. 1997 May 30 9Philips Semiconductors Preliminary specification 8-bit CMOS (low voltage, low power and high speed) microcontroller families 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ PIN DESCRIPTIONS (Continued) PIN NUMBER MNEMONIG DIP Loc QFP TYPE NAME AND FUNCTION PSEN EAVpp XTAL1 XTAL2 29 31 19 18 32 35 21 20 26 29 15 14 o Program Store Enable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory locations OO00H and 7FFFH. If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than 7FFFH. This pin also receives the 12.75V programming supply voltage (Vpp) during EPROM programming. If security bit 1 is programmed, EA will be internally latched on Reset. Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Crystal 2: Output from the inverting oscillator amplifier. NOTE: To avoid latch-up effect at power-on, the voltage on any pin at any time must not be higher than Vee + 0.5V or Vgg 0.5V, respectively. 1997 May 30 10Philips Semiconductors Preliminary specification -bi 8XC52/54/58/80C32 6-bit CMOS (low voltage, low Power 8XC51 FA/FB/FC/80C51 FA and high speed) microcontroller families 8XC51RA+/RB+/RC+/RD+/80C51RA+ Table 1. 8XC52/54/58/80C32 Special Function Registers SYMBOL DESCRIPTION spiRECT use ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION RESET ACC* Accumulator EQH E7 E6 E5 E4 E3 E2 E1 Ed OOH AUXR# Auxiliary 8EH - - - - - - - AO XxXXXXxXXOB AUXR1# Auxiliary 1 A2H - - - LPEP# - - - DPS xxx0xxx0B Be B register FOH F7 F F5 F4 F3 F2 Fi FO 00H DPTR: Data Pointer (2 bytes) DPH Data Pointer High 83H QOH BPL Data Pointer Low 82H 00H AF AE AD AC AB AA Ag AS IE* Interrupt Enable A8H EA | - | Er2 | ES | Ett | EX1 | ETO | Exo | oxo00000B BF BE BD BC BB BA Bg Ba IP* Interrupt Priority BgH - | - | Pre | PS | PT1 | PX1 | PTO | PXO | xx000000B8 B7 Be BS B4 B3 B2 Bt Bo IPH# Interrupt Priority High B7H - | - | PT2H | PSH | PTIH | PX1H | PTOH | PXOH | xxo00000B a7 86 a5 84 a3 82 81 80 Po* Port 0 80H AD7 | ADS | ADS | AD4 | ADS | AD2 | ADI | ADO | FFH 97 96 95 94 93 92 91 90 Pit Port 1 90H - {| - [| - [| - | - | - | T2ex | 12) | FFH AT AB AS A4 Ag A2 Al AQ P2* Port2 AOQH | ADI5 | AD14 | ADI3 | ADI2 | ADi1 | ADO | AD9 | ADB | FFH B7 B6 BS B4 B3 B2 Bt BO P3* Port 3 BOH RD | WR | 71 | To | INT? | INTO | TxD | RxD | FFH PCON#! =| Power Control 87H | SMODi | SMOD0 | - | POF? | GFi | GFo | PD | IDL | 00xx0000B D7 D D5 D4 D3 D2 DI Do PSw* Program Status Word DOH cy | ac | Fo | RSi | RSo | OV | - | P oogo00x0B RACAP2H#E | Timer 2 Capture High CBH OOH RACAP2L# | Timer 2 Capture Low CAH OOH SADDR# Slave Address ASH 00H SADEN# Slave Address Mask BSH OOH SBUF Serial Data Buffer 99H XXXXXXXXB OF gE aD 9C 9B 9A 99 98 SCON* Serial Control 98H |SMO/FE}] SMi | SM2 | REN | TB8 | RBB | Tl | ARI 00H SP Stack Pointer 81H 07H BF 8E aD BC 8B BA 89 88 TCON* Timer Control 88H TF1 | TRI | TRO | TRO | 161 | IT1 | leo | [To | 00H CF CE CD CC cB CA cag ca T2CON* = | Timer 2 Control C8H TF2 | EXF2 | RCLK | TCLK | EXEN2 | TR2 | C/T2 | CP/RL2 | 00H T2MOD# Timer 2 Mede Control CSH - - - - - - T20E DCEN | xxxxxx00B THO Timer High 0 8CH OOH TH1 Timer High 1 8DH 00H TH2# Timer High 2 CDH OOH TLO Timer Low 0 8AH OOH TL1 Timer Low 1 8BH 00H TL2# Timer Low 2 CCH 00H TMOD Timer Mode 89H GATE | c/T | M1 | Mo GATE | CT | M1 MO | OOH * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. Reserved bits. 1. Reset value depends on reset source. 2. Bit will not be affected by Reset. 3. LPEP Low Power EPROM operation (OTP/EPROM only) 1997 May 30 11Philips Semiconductors Preliminary specification 8-bit CMOS (low voltage, low power and high speed) microcontroller families 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ Table 2. 8XC51FA/FB/FC, 8XC51RA+/RB+/RC+/RD+ Special Function Registers DIRECT BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION RESET SYMBOL | DESCRIPTION _| appRESs | MSB LsB | VALUE ACC* Accumulator EQH E7 E6 E5 E4 E3 E2 E1 EO Q0H AUXR# Auxiliary 8EH - - - - - - EXTRAM AO xxxxxx00B (RX+ only} AUXR1# Auxiliary 1 A2H - - - LPEP? - - - DPS xxx0xxx0B B* B register FOH F7 F6 F5 F4 F3 F2 FA FO QOH CCAPOH# | Module 0 Capture High FAH XXXXXXXXB CCAP1H# | Module 1 Capture High FBH XXXXXXXXB CCAP2H# | Module 2 Capture High FCH XXXXXXXXB CCAPSH# | Module 3 Capture High FDH XXXXXXXXB CCAP4H# | Module 4 Capture High FEH XXXXXXXXB CCAPOL# | Module 0 Capture Low EAH XXXXXXXXB CCAP1IL# | Module 1 Capture Low EBH XXXXXXXXB CCAP2L# | Module 2 Capture Low ECH XXXXXXXXB CCAP3L# | Module 3 Capture Low EDH XXXXXXXXB CCAP4L# | Module 4 Capture Low EEH XXXXXXXXB CCAPMO# | Module 0 Mode DAH - EGOM | CAPP | CAPN MAT TOG PWM ECCF | xooo0000B CCAPM1# | Module 1 Mode DBH - EGOM | CAPP | CAPN MAT TOG PWM ECCF | xo000000B CCAPM2# | Module 2 Mode DGH - EGOM | CAPP | CAPN MAT TOG PWM EGGF | xoo00000B CCAPM3# | Module 3 Mode DDH - EGOM | CAPP | CAPN MAT TOG PWM ECCF | xoo00000B CCAPM4# | Module 4 Mode DEH - EGOM | CAPP | CAPN MAT TOG PWM ECCF | xoo00000B DF DE DD DC DB DA Ds D8 CCON*# | PCA Counter Control D8H cF | cR | - | ccF4 | CcFs | CcF2 | CCF1 | CCFO | 00x00000B CH# PCA Gounter High FSH OGH CL# PCA Counter Low ESH Q0H CMOD# | PCA Counter Mode D9H | CIOL |woTe| - | - | - |cpPsi] cpso | ECF | coxxx000B DPTR: Data Pointer (2 bytes) DPH Data Pointer High 83H OOH DPL Data Pointer Low 82H Q0H AF AE AD AG AB AA AQ AB IE* Interrupt Enable A8H EA | ec | er2 | es | evi | Exi | Eto | Exo | 00H BF BE BD BC. BB BA Bg Ba IP* Interrupt Priority B&H - | ppc | pt2 | Ps | PTi | Pxi | PTo | PXxo | xooo0000B B? B6 B5 B4 B3 B2 Bi Bo IPH# Interrupt Priority High | 87H | PPCH | PT2H | PSH | PT1H | PX1H | PTOH | PXOH | x00000008 a7 86 85 a4 83 82 a1 80 Po* Port 0 goH | AD7 | ADs | ADs | aD4 | AD3 | AD2 | ADI | ADO | FFH g7 96 95 94 93 92 91 90 Pit Port 1 90H | CEX4 | CEX3 | CeEx2 | CEx1 | Cexo | EcI | T2EX | T2 | FFH A? AGB AS A4 Ag A2 Al AO P2* Port2 AOH | ADI5 | AD14 | ADI3 | ADI2 | ADit | ADio | ADO | ADs | FFH B? B6 B5 B4 B3 B2 Bi Bo P3* Port 3 BOH RD | wR [ Ti | To | INTT | INTO [ TxD | RxD | FFH PCON#! | Power Control a7H | smopi | smcoo | - | por? | cei | Gro | Pp | IDL | ooxxo000B * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. Reserved bits. 1. Reset value depends on reset source. 2. Bit will not be affected by Reset. 3. LPEP Low Power EPROM operation (OTP/EPROM only) 1997 May 30 12Philips Semiconductors Preliminary specification 8-bit CMOS (low voltage, low power and high speed) microcontroller families 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ Table 2. 8XC51FA/FB/FC, 8XC51RA+/RB+/RC+/RD+ Special Function Registers (Continued) DIRECT BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION RESET SYMBOL DESCRIPTION _| ADDRESS | MSB LSB VALUE D7 D D5 D4 D3 D2 D1 bBo Psw* Program Status Word | DOH cy | ac | Fo | Rsi {| RSo {| ov | - | P__ | oo0000x0B RACAP2H# | Timer 2 Capture High CBH QOH RACAP2L# | Timer 2 Capture Low CAH 00H SADDR# Slave Address ASH 00H SADEN# | Slave Address Mask BSH 00H SBUF Serial Data Buffer 99H XXXXXXXXB 9F 9E 9D 9C 9B 9A 99 98 SCON* | Serial Control 98H |sMore| smi | sm2 | REN | TBs | RB8 | Ti | RI | ooH SP Stack Pointer 81H 07H 8F 8E 8D 8c 8B 8A 89 88 TCON* | Timer Control asH | TFi | TRI | Tro | TRO | IE1 | (71 | IEo | (To JooH CF CE cD cc CB CA cg cE T2CON* Timer 2 Control C8H TF2 EXF2 RCLK TCLK | EXEN2 TR2 CfT2 | CP/RL2 | OOH T2MOD# Timer 2 Mode Control CSH - - - - - - T20E | DCEN | xxxxxx00B THO Timer High 0 8CH 00H TH1 Timer High 1 8DH 00H TH2# Timer High 2 CDH OOH TLO Timer Low 0 8AH OOH TL1 Timer Low 1 8BH 00H TL2# Timer Low 2 CCH 00H TMOD Timer Mode 89H GATE C/T M1 Mo GATE C/T M1 Mo 00H WDTRST | HOW Watchdog OA6H Timer Reset (RX+ only) * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. Reserved bits. OSCILLATOR CHARACTERISTICS RESET XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed. 1997 May 30 13 A reset is accomplished by holding the RST pin high for atleast two machine cycles (24 oscillator periods), while the oscillator is running. To insure a good power-on reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. At power-on, the voltage on Vec and RST must come up at the same time for a proper start-up. Ports 1, 2, and 3 will asynchronously be driven to their reset condition when a voltage above VjH1 (min.)is applied to RESET.Philips Semiconductors Preliminary specification 8-bit CMOS (low voltage, low power and high speed) microcontroller families 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ LOW POWER MODES Stop Clock Mode The static design enables the clock speed to be reduced down to 0 MHz (stopped). When the oscillator is stopped, the RAM and Special Function Registers retain their values. This mode allows step-by-step utilization and permits reduced system power consumption by lowering the clock frequency down to any value. For lowest power consumption the Power Down mode is suggested. Idle Mode In the idle mode (see Table 3), the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mede before the idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset. Power-Down Mode To save even more power, a Power Down mode (see Table 3) can be invoked by software. |n this mode, the oscillator is stopped and the instruction that invoked Power Down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values down to 2.0V and care must be taken to return Veg to the minimum specified operating voltages before the Power Down Mode is terminated. Either a hardware reset or external interrupt can be used to exit from Power Down. Reset redefines all the SFRs but does not change the on-chip RAM. An external interrupt allows both the SFRs and the on-chip RAM to retain their values. To properly terminate Power Down the reset or external interrupt should not be executed before Vec is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10ms). With an external interrupt, INTO and INT1 must be enabled and configured as level-sensitive. Holding the pin low restarts the oscillator but bringing the pin back high completes the exit. Once the interrupt is serviced, the next instruction to be executed after RET! will be the one following the instruction that put the device into Power Down. LPEP When this bit is set = 1 (AUXR1/Bit4), the chip will go into very low power operation for EPROM at less than 4V (Vec < 4V). When Bii4 = 0, the chip will go back to Active mode. POWER OFF FLAG The Power Off Flag (POF) is set by on-chip circuitry when the Vec level on the 8XC51FX/8XC51RX+ rises from 0 to 5V. The POF bit can be set or cleared by software allowing a user to determine if the reset is the result of a power-on or a warm start after powerdown. The Veg level must remain above 3V for the POF to remain unaffected by the Vc level. Design Consideration When the idle mode is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. ONCE Mode The ONCE (On-Circuit Emulation) Mode facilitates testing and debugging of systems without the device having to be removed from the circuit. The ONCE Mode is invoked by: 1. Pull ALE low while the device is in reset and PSENis high; 2. Hold ALE low as RST is deactivated. While the device is in ONCE Mode, the Port 0 pins go into a float state, and the other port pins and ALE and PSEN are weakly pulled high. The oscillator circuit remains active. While the 8XC51FA/FB is in this mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when a nornal reset is applied. Programmable Clock-Out A 50% duty cycle clock can be programmed to come out on P1.0. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed: 1. toinput the external clock for Timer/Counter 2, or 2. to output a 50% duty cycle clock ranging from 61Hz to 4MHz ata 16MHz operating frequency. To configure the Timer/Gounter 2 as a clock generater, bit C/T2 (in T2CON) must be cleared and bit T20E in T@MOD must be set. Bit TR2 (T2CON.2) also must be set to start the timer. The Clock-Out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L) as shown in this equation: Oscillator Frequency 4 x (65536 - RCAP2H, RCAP2L) Where (RCAP2H, RCAP2L) = the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. In the Clock-Out mode Timer 2 roll-overs will not generate an interrupt. This is similar to when itis used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator simultaneously. Note, however, that the baud-rate and the Clock-Out frequency will be the same. Table 3. External Pin Status During Idle and Power-Down Mode MODE PROGRAM MEMORY ALE PSEN PORT 0 PORT 1 PORT 2 PORT 3 Idle Internal 1 1 Data Data Data Data Idle External 1 1 Float Data Address Data Power-down Internal 0 0 Data Data Data Data Power-down External 0 a Float Data Data Data 1997 May 30 14Philips Semiconductors Preliminary specification 8-bit CMOS (low voltage, low power and high speed) microcontroller families 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ TIMER 2 OPERATION Timer 2 Timer 2 is a 16-bit Timer/Counter which can operate as either an event timer or an event counter, as selected by C/T2* in the special function register T2CON (see Figure 1). Timer 2 has three operating modes :Capture, Auto-reload (up or down counting) ,and Baud Rate Generator, which are selected by bits in the T2CON as shown in Table 4. Capture Mode In the capture mode there are two options which are selected by bit EXEN2 in T2CON. If EXEN2=0, then timer 2is a 16-bit timer or counter (as selected by C/T2* in T2CON) which, upon overflowing sets bit TF2, the timer 2 overflow bit. This bit can be used to generate an interrupt (by enabling the Timer 2 interrupt bit in the IE register). If EXEN2= 1, Timer 2 operates as described above, but with the added feature that a 1- to -0 transition at extemal input T2EX causes the current value in the Timer 2 registers, TL2 and Th2, to be captured into registers RCAP2L and RCAP2H, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set, and EXF2 like TF2 can generate an interrupt (which vectors to the same location as Timer 2 overflow interrupt. The Timer 2 interrupt service routine can interrogate TF2 and EXF2 to determine which event caused the interrupt). The capture mode is illustrated in Figure 2 (There is no reload value for TL2 and TH2 in this mode. Even when a capture event occurs from T2EX, the counter keeps on counting T2EX pin transitions or osc/12 pulses.). Auto-Reload Mode (Up or Down Counter) In the 16-bit auto-reload mode, Timer 2 can be configured (as either a timer or counter [C/T2* in T2C-ON)]) then programmed to count up or down. The counting direction is determined by bit DCEN (Down Counter Enable) which is located in the T2MOD register (see Figure 3). When reset is applied the DGEN=0 which means Timer 2 will default to counting up. If DCEN bitis set, Timer 2 can count up or down depending on the value of the T2EX pin. Figure 4 shows Timer 2 which will count up automatically since DBCENS=0. In this mode there are two options selected by bit EXEN2 in T2CON register. If EXEN2=0, then Timer 2 counts up to OFFFFH and sets the TF2 (Overflow Flag) bit upon overflow. This causes the Timer 2 registers to be reloaded with the 16-bit value in RCAP2L and RCAP2H. The values in RCAP2L and RCAP2H are preset by software means. If EXEN2=1, then a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at input T2EX. This transition also sets the EXF2 bit. The Timer 2 interrupt, if enabled, can be generated when either TF2 or EXF2 are 1. In Figure 5 DCEN=1 which enables Timer 2 to count up or down. This mode allows pin T2EX to control the direction of count. When a logic 1 is applied at pin T2EX Timer 2 will count up. Timer 2 will overflow at OFFFFH and set the TF2 flag, which can then generate an interrupt, if the interrupt is enabled. This timer overflow also causes the 16-bit value in RCAP2L and RCAP2H to be reloaded into the timer registers TL2 and TH2. When a logic 0 is applied at pin T2EX this causes Timer 2 to count down. The timer will underflow when TL2 and TH2 become equal to the value stored in RCAP2L and RCAP2H. Timer 2 underflow sets the TF2 flag and causes QFFFFH to be reloaded into the timer registers TL2 and TH2. The external flag EXF2 toggles when Timer 2 underflows or overflows. This EXF2 bit can be used as a 17th bit of resolution if needed. The EXF2 flag does not generate an interrupt in this mode of operation. on Timer 2 overflow. (MSB) (LSB) TF2 EXF2 RCLK TCLK EXEN2 TR2 CfT2 CP/RL2 Symbol Position Name and Significance TF2 T2CON.7 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK or TCLK = 1. EXF2 T2CON.6 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1). RCOLK T2CON.5 Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. TCLK T2CON.4 Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. EXEN2 T2CON.3 Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX. TR2 T2CON.2 = Start/stop control for Timer 2. Alogic 1 starts the timer. c/T2 T2CON.1 Timeror counter select. (Timer 2) 0 = Internal timer (OSC/12) 1 = External event counter (falling edge triggered). CP/RL2 T2CON.0 Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1. When cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T@EX when EXEN@2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload SU00726 Figure 1. Timer/Counter 2 (T2CON) Control Register 1997 May 30Philips Semiconductors Preliminary specification -bi 8XC52/54/58/80C32 6-bit CMOS (low voltage, low Power 8XC51 FA/FB/FC/80C51 FA and high speed) microcontroller families 8XC51RA+/RB+/RC+/RD+/80C51RA+ Table 4. Timer 2 Operating Modes RCLK + TOLK CP/RL2 0 16-bit Auto-reload 16-bit Capture 0 1 Baud rate generator Xx (off) osc mT 12 C/T? =0 st Tle TH2 9 *1 (a-bits) (8-bits) a c= 1 T2 Pin Control TA Capiure Transition Timer 2 Detector Interrupt | RCAP2L RCAP2H T2EX Pin. 1 a oro =| EXF2 Control EXEN2 SU00066 Figure 2. Timer 2 in Capture Mode T2MOD Address = 0C9H Reset Value = XXXX XX00B Not Bit Addressable _ _ _ _ _ _ T20E DCEN Bit 7 6 5 4 3 2 1 0 Symbol Function _ Not implemented, reserved for future use.* T20E Timer 2 Output Enable bit. DCEN Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down counter. * User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bitis indeterminate. suo0729 Figure 3. Timer 2 Mode (T2MOD) Control Register 1997 May 30 16Philips Semiconductors Preliminary specification 8-bit CMOS (low voltage, low power 8XC52/54/58/80C32 te ( vitage, P a: 8XC51FA/FB/FC/80C51 FA and high speed) microcontroller families 8XC51RA+/RB+/RC+/RD+/80C51RA+ osc +12 crT2 =0 To _ TL2 TH2 /@ *) (a.BiTs} (B-BITS} CTE =1 T2 PIN CONTROL pe, TAZ RELOAD TRANSITION DETECTOR RCAP2L RCAP2H | TF2 TIMER 2 INTERRUPT T2EX PIN) 1 a oT". + =| EXF2 CONTROL EXEN? Su00067 Figure 4. Timer 2in Auto-Reload Mode (DCEN = 0) (DOWN COUNTING RELOAD VALUE} FFH FFH TOGGLE x T+ Exr2 osc +12 oT =o OVERFLOW ono Tle TH2 aa e TF2 -* = INTERRUPT Tz PIN _ 4 crT2 =1 CONTROL we COUNT DIRECTION 1=UP 0 =DOWN ACAP2L RCAP2H (UP COUNTING RELOAD VALUE} T2EX PIN suD0730 Figure 5. Timer 2 Auto Reload Mode (DCEN = 1) 1997 May 30 17Philips Semiconductors Preliminary specification 8-bit CMOS (low voltage, low power and high speed) microcontroller families 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ Timer 1 Overilow _ NOTE: OSC. Freq. is divided by 2, not 12. +2 o 1 osc wy 2 C/T? =0 \ ----- SMOD . 4 . TL2 TH2 . } oS (Bits) (B-bits} MTEL. RCLK cz =4 ; T2 Pin Control =] +16 RX Clock TR2 o Reload Ys - ___. TCLK Transition Detector ACAP2L RCAP2H | a ol TX Clock T2EX Pin. - ono a] EXF2 limer2 \ Interrupt \ | Control EXEN2 fo Note availability of additional external interrupt. SU00068 Figure 6. Timer 2in Baud Rate Generator Mode Table 5. Timer 2 Generated Commonly Used Baud Rates Timer 2 Baud Rate Osc Freq RCGAP2H RCGAP2L 375K 12MHz FF FF 9.6K 12MHz FF DS 2.8K 12MHz FF B2 24K 12MHz FF 64 1.2K 12MHz FE cs 300 12MHz FB 1E 110 12MHz F2 AF 300 6MHz FD 8F 110 6MHz Fg 57 Baud Rate Generator Mode Bits TCLK and/or RCLK in T2CON (Table 4) allow the serial port transmit and receive baud rates to be derived from either Timer 1 or Timer 2. When TCLK= 0, Timer 1 is used as the serial port transmit baud rate generator. When TCLK= 1, Timer 2 is used as the serial port transmit baud rate generator. RCLK has the same effect for the serial port receive baud rate. With these two bits, the serial port can have different receive and transmit baud rates one generated by Timer 1, the other by Timer 2. Figure 6 shows the Timer 2 in baud rate generation mode. The baud rate generation mode is like the auto-reload mode,in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. 1997 May 30 18 The baud rates in modes 1 and 3 are determined by Timer 2s overflow rate given below: Modes 1 and 3 Baud Rates = Timer 2 Overflow Rate The timer can be configured for either timer or counter operation. In many applications, it is configured for timer operation (C/T2*=0). Timer operation is different for Timer 2 when it is being used as a baud rate generator. Usually, as a timer it would increment every machine cycle (i.e., 1/12 the oscillator frequency). As a baud rate generator, itincrements every state time (i.e., 1/2 the oscillator frequency). Thus the baud rate formula is as follows: Modes 1 and 3 Baud Rates = Oscillator Frequency [82 x [65536 (RCAP2H, RCAP2L)]] Where: (RCAP2H, RCAP2L)= The content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. The Timer 2 as a baud rate generator mode shown in Figure 6, is valid only if RCLK and/or TCLK = 1 in T2CON register. Note that a rollover in TH2 does not set TF2, and will not generate an interrupt. Thus, the Timer 2 interrupt does not have to be disabled when Timer 2 is in the baud rate generator mode. Also if the EXEN2 (T2 external enable flag) is set, a 1-to-0 transition in T2EX (Timer/counter 2 trigger input) will set EXF2 (T2 external flag) but will not cause a reload from (RCAP2H, ROAP2L) to (TH2,TL2). Therefore when Timer 2is in use as a baud rate generator, T2EX can be used as an additional external interrupt, if needed.Philips Semiconductors Preliminary specification 8-bit CMOS (low voltage, low power and high speed) microcontroller families 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ When Timer 2 is in the baud rate generator mode, one should not try to read or write TH2 and TL2. As a baud rate generator, Timer 2 is incremented every state time (osc/2) or asynchronously from pin T2; under these conditions, a read or write of TH2 or TL2 may not be accurate. The RCAP2 registers may be read, but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers. Table 5 shows commonly used baud rates and how they can be obtained from Timer 2. Summary Of Baud Rate Equations Timer 2 is in baud rate generating mode. If Timer 2 is being clocked through pin T2(P1.0) the baud rate is: Timer 2 Overflow Rate Baud Rate = 16 Table 6. Timer 2 as a Timer If Timer 2 is being clocked internally , the baud rate is: fosc [32 x [65536 (RCAP2H, RCAP2L)]] Baud Rate = Where fosc= Oscillator Frequency To obtain the reload value for RCAP2H and RCAP2L, the above equation can be rewritten as: fose Timer/Counter 2 Set-up Except for the baud rate generator mode, the values given for T2CON do not include the setting of the TR2 bit. Therefore, bit TR2 must be set, separately, to turn the timer on. see Table 6 for set-up of Timer 2 as a timer. Also see Table 7 for set-up of Timer 2 asa counter. T2CON MODE INTERNAL CONTROL EXTERNAL CONTROL (Note 1) (Note 2) 16-bit Auto-Reload 00H 08H 16-bit Capture 01H OSH Baud rate generator receive and transmit same baud rate 34H 36H Receive only 24H 26H Transmit only 14H 16H Table 7. Timer 2 as a Counter TMOD MODE INTERNAL CONTROL EXTERNAL CONTROL (Note 1) (Note 2) 16-bit 02H OAH Auto-Reload 03H OBH NOTES: 1. Capture/reload occurs only on timer/counter overflow. 2. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate generator mode. 1997 May 30 19Philips Semiconductors Preliminary specification 8-bit CMOS (low voltage, low power and high speed) microcontroller families 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ Enhanced UART The UART operates in all of the usual modes that are described in the first section of Data Handbook IC 20, 80C51-Based 8-Bit Microcontrollers. |n addition the UART can perform framing error detect by looking for missing stop bits, and automatic address recognition. The 8XC-51 FA/83C51FB UART also fully supports multiprocessor communication as does the standard 80C51 UART. When used for framing error detect the UART looks for missing stop bits in the communication. A missing bit will set the FE bit in the SCON register. The FE bit shares the SCON.7 bit with SMO and the function of SCON.7 is determined by PCON.6 (SMOD0) (see Figure 7). If SMOD0 is set then SCON.7 functions as FE. SCON.7 functions as SMO when SMOD0 is cleared. When used as FE SCON.7 can only be cleared by software. Refer to Figure 8. Automatic Address Recognition Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. This feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be automatically set when the received byte contains either the Given address or the Broadcast address. The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. Automatic address recognition is shown in Figure 9. The 8 bit mode is called Mode 1. In this mode the RI flag will be set if SM2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a Given or Broadcast address. Mode 0 is the Shift Register mode and SM2 is ignored. Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Two special Function Registers are used to define the slave's address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the SADDR are to b used and which bits are dont care. The SADEN mask can be logically ANDed with the SADDR to create the Given address which the master will use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding others. The following examples will help to show the versatility of this scheme: Slave 0 SADDR = 1100 9000 SADEN = 1441 1104 Given 1100 00X0 1997 May 30 20 Slave 1 SADDR = 1100 9000 SADEN = 11411110 Given = 1100 000x In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a Oin bit 0 and itignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be 1100 0010 since slave 1 requires a Qin bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000. In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: Slave 0 SADDR = 1100 9000 SABDEN = 1111 1001 Given = 1100 OXxXO Slave 1 SABDDR = 1110 9000 SABDEN = 1111 1010 Given = 1110 OxX0x Slave 2 SABDDR = 1110 9000 SABDEN = 1111. 1100 Given = 1110 OOXx In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100, since itis necessary to make bit 2 = 1 to exclude slave 2. The Broadcast Address for each slave is created by taking the logical GR of SADDR and SADEN. Zeros in this result are trended as dont-cares. In most cases, interpreting the dont-cares as ones, the broadcast address will be FF hexadecimal. Upon reset SADDR (SFR address OASH) and SADEN (SFR address OBSH) are leaded with Os. This produces a given address of all dont cares as well as a Broadcast address of all dont cares. This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard 80C51 type UART drivers which do not make use of this feature.Philips Semiconductors Preliminary specification -bi 8XC52/54/58/80C32 8-bit CMOS (low voltage, low Power 8XC51 FA/FB/FC/80C51 FA and high speed) microcontroller families 8XC51RA+/RB+/RC+/RD+/80C51RA+ SCON Address = 98H Reset Value = 0000 0000B Bit Addressable | SMO/FE | SM1 | SM2 | REN | TB8 | RBS | TI | Rl | Bit: 7 6 5 4 3 2 1 0 (SMODo = 0/1)* Symbol Function FE Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit. SMO Serial Port Mode Bit 0, (SMODO must = 0 to access bit SMO) SM1 Serial Port Mode Bit 1 SMO SM1 Mode Description Baud Rate** 0 0 0 shift register fasc/12 Q 1 1 8-bit UART variable 1 0 2 9-bit UART fosc/64 or fosc/32 1 1 3 9-bit UART variable SM2 Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the received 9th data bit (RB8)is 1, indicating an address, and the received byte is a Given or Broadcast Address. In Mode 1, if SM2 = 1 then RI will not be activated unless a valid stop bit was received, and the received byte is a Given or Broadcast Address. In Mode 0, SM2 should be 0. REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception. TBS The Sth data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. RB& In modes 2 and 3, the Sth data bit that was received. In Mode 1, if SM2 = 0, RB@ is the stop bit that was received. In Mode 0, RB8 is not used. Tl Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. Must be cleared by software. Rl Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software. NOTE: *SMODO is located at PCONB. Tosc = oscillator requency su00043 Figure 7. SCON: Serial Port Control Register 1997 May 30 21Philips Semiconductors Preliminary specification 8-bit CMOS (low voltage, low power BXC52/54/58/80C32 . . a: 8XC51 FA/FB/FC/80C51 FA and high speed) microcontroller families 8XC51RA+/RB+/RC+/RD+/80C51RA+ START DATA BYTE ONLY IN STOP BIT MODE2,3 BIT a SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR) o oo} _ Mo TO UART MODE CONTROL SCON SMo/FE | SMI SM2 REN TBS ABS TI Al (oat SMOD1 | SMODO - POF LVF GFO GFi IDL ory 0: SCON.7 = SMO 1: SCON.? = FE Su000s4 Figure 8. UART Framing Error Detection KEKE KE KEKE KEKE KE SCON SMo. SM1 SM2 REN TBS RBS TI Al 8H h 1 1 1 1 x i 0 RECEIVED ADDRESS Do TO D7. PROGRAMMED ADDRESS J_ COMPARATOR IN UART MODE 2 OR MODE 3 AND SM2 = 1: INTERRUPT IF REN=1, RBS=1 AND RECEIVED ADDRESS = PROGRAMMED ADDRESS WHEN OWN ADDRESS RECEIVED, CLEAR SM? TO RECEIVE DATA BYTES WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS. su00045 Figure 9. UART Multiprocessor Communication, Automatic Address Recognition 1997 May 30 22Philips Semiconductors Preliminary specification 8-bit CMOS (low voltage, low power and high speed) microcontroller families 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ Interrupt Priority Structure The 8XC51 FA/FB/FC and 8XC51RA+/RB+/RC+/RD+ have a 7-source four-level interrupt structure (see Table 8). The 80C52/54/58 and 80C32 only have a 6-source four-level interrupt structure because these devices do not havea PCA. There are 3 SFRs associated with the four-level interrupt. They are the IE, IP, and IPH. (See Figures 10, 11, and 12.) The IPH (Interrupt Priority High) register makes the four-level interrupt structure possible. The IPH is located at SFR address B7H. The structure of the IPH register and a description of its bits is shown in Figure 12. The function of the IPH SFR is simple and when combined with the IP SFR determines the priority of each interrupt. The priority of each interrupt is determined as shown in the following table: PRIORITY BITS INTERRUPT PRIORITY LEVEL IPH.x IP.x 0 0 Level 0 (lowest priority) i) 1 Level 1 1 0 Level 2 1 1 Level 3 (highest priority) Table 8 ~s Interrupt Table The priority scheme for servicing the interrupts is the same as that for the 80C51, except there are four interrupt levels rather than two as on the 80051. An interrupt will be serviced as long as an interrupt of equal or higher priority is not already being serviced. If an interrupt of equal or higher level priority is being serviced, the new interrupt will wait until itis finished before being serviced. If a lower priority level interrupt is being serviced, it will be stopped and the new interrupt serviced. When the new interrupt is finished, the lower priority level interrupt that was stopped will be completed. SOURCE POLLING PRIORITY REQUEST BITS HARDWARE CLEAR? VECTOR ADDRESS 03H OBH 13H 1BH 23H 2BH 33H XO 1 TO x1 T1 SP T2 PCA (8XC51FX and BXC51RX+ NOTES: 1. L= Level activated 2. T= Transition activated IEG N (L)! TPO Y T= N (L) TF RI, TI TF2, EXF2 CF, CCFn n=0-4 Y (1? (1) 7 6 5 4 3 2 1 0 IE (OA8H) EA EG ET2 ES ET1 EX1 ETO EXO Enable Bit = 1 enables the interrupt. Enable Bit = 0 disables it. BIT SYMBOL FUNCTION IE.7 EA Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually enabled or disabled by setting or clearing its enable bit. IE.6 EG PCA interrupt enable bit for FX and RX+ only not implemented otherwise. IE.5 ET2 Timer 2 interrupt enable bit. IE.4 ES Serial Port interrupt enable bit. IE.3 ET1 Timer 1 interrupt enable bit. IE.2 EX1 External interrupt 1 enable bit. 1E.14 ETO Timer O interrupt enable bit. IE.0 EXO External interrupt 0 enable bit. suo#so Figure 10. IE Registers 1997 May 30 23Philips Semiconductors 8-bit CMOS (low voltage, low power Preliminary specification 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA and high speed) microcontroller families 8XC51RA+/RB+/RC+/RD+/80C51RA+ T 6 5 4 3 2 1 0 IP (OB8H) PPG PT2 PS PT4 PX1 PTO PXO Priority Bit = 1 assigns high priority Priority Bit = 0 assigns low priority BIT SYMBOL FUNCTION IP.7 _ Not implemented, reserved for future use. IP.6 PPG PCA interrupt priority bit for FX and RX+ only, otherwise not implemented. IP5 PT2 Timer 2 interrupt priority bit. IP.4 PS Serial Port interrupt priority bit. IP.3 PT1 Timer 1 interrupt priority bit. IP.2 PX1 External interrupt 1 priority bit. IP PTO Timer O interrupt priority bit. IP.O PXO External interrupt 0 priority bit. suooes1 Figure 11. IP Registers T 6 5 4 3 2 1 0 IPH (B7H) PPGH | PT2H PSH PT1H | PX1H | PTOH | PXOH Priority Bit = 1 assigns higher priority Priority Bit = 0 assigns lower priority BIT SYMBOL FUNCTION IPH.7 Not implemented, reserved for future use. IPH.6 PPGH PCA interrupt priority bit high for FX and RX+ only, otherwise not implemented. IPH.5 PT2H Timer 2 interrupt priority bit high. IPH.4 PSH Serial Port interrupt priority bit high. IPH.3 PT1H Timer 1 interrupt priority bit high. IPH.2 PX1H External interrupt 1 priority bit high. IPH.1 PTOH Timer O interrupt priority bit high. IPH.0 PXOH External interrupt 0 priority bit high. suoo8e? 1997 May 30 Figure 12. IPH Registers 24.Philips Semiconductors Preliminary specification 8-bit CMOS (low voltage, low power and high speed) microcontroller families 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ Reduced EMI Mode The AO bit (AUXR.O) in the AUXR register when set disables the ALE output. Reduced EMI Mode AUXR (8EH) 7 6 5 4 3 2 1 0 P- | - [| - [| - | - J - fextram | ao AUXR.1 EXTRAM (RX and RX+ only) AUXR.O AO Turns off ALE output. Dual DPTR The dual DPTR structure (see Figure 13) is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1/bitO that allows the program code to switch between them. New Register Name: AUXR1# @ SFR Address: A2H Reset Value: xxxxxxx0B 7 6 5 4 3 2 1 0 L- | - | - [rrr | - | - | - J ors | Where: BPS = AUXR1/bit0 = Switches between DPTRO and DPTR1. Select Reg DPS DPTRO 0 DPTR1 1 The DPS bit status should be saved by software when switching between DPTRO and DPTR1. 1997 May 30 25 ' TT ' DPS 1 ' BITo ' apTap AUXAI ' DPTA1 ' DPTRO DPH | DPL TN (83H) (82H) EXTERNAL DATA MEMORY SUO0745A Figure 13. DPTR Instructions The instructions that refer to DPTR refer to the data pointer thatis currently selected using the AUXR1/bit 0 register. The six instructions that use the DPTR are as follows: INC DPTR MOV DPTR, #data16 MOV A, @ A+DPTR MOvX A, @ DPTR Increments the data pointer by 1 Loads the DPTR with a 16-bit constant Move code byte relative to DPTR to ACG Move external RAM (16-bit address) to ACG Move ACC to external RAM (16-bit address) MOvVX @ DPTR,A JMP @ A+ DPTR Jump indirect relative to DPTR The data pointer can be accessed on a byte-by-byte basis by specifying the low or high byte in an instruction which accesses the SFRs. See application note AN458 for more details.Philips Semiconductors Preliminary specification 8-bit CMOS (low voltage, low power and high speed) microcontroller families 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ (8XC51FX and 8XC51RX+ ONLY) Programmable Counter Array (PCA) (8XC51FX and 8XC51RX+ only) The Programmable Counter Array available on the 8XC51FX and 8XC51 RX-+ is a special 16-bit Timer that has five 16-bit capture/compare modules associated with it. Each of the modules can be programmed to operate in one of four modes: rising and/or falling edge capture, software timer, high-speed output, or pulse width modulator. Each module has a pin associated with it in port 1. Module 0 is connected to P1.3(CEX0), module 1 to P1.4(CEX1), etc. The basic PCA configuration is shown in Figure 14. The PCA timer is a commen time base fer all five modules and can be programmed to run at: 1/12 the oscillator frequency, 1/4 the oscillator frequency, the Timer 0 overflow, or the input on the ECI pin (P1.2). The timer count source is determined from the CPS1 and CPS0 bits in the CMOD SFR as follows (see Figure 17): CPS1 CPSO PCA Timer Count Source 0 Q = 1/12 oscillator frequency 0 1 1/4 oscillator frequency 1 QO Timer 0 overflow 1 1 External Input at ECI pin In the CMOD SFR are three additional bits associated with the PCA. They are CIBL which allows the PCA to stop during idle mode, WDTE which enables or disables the watchdog function on medule 4, and ECF which when set causes an interrupt and the PCA overflow flag CF (in the CCON SFR) to be set when the PCA timer overflows. These functions are shown in Figure 15. The watchdog timer function is implemented in module 4 (see Figure 24). The CGON SFR contains the run control bit for the PCA and the flags for the PCA timer (CF) and each module (refer to Figure 18). To run the PCA the GR bit (CCON.6) must be set by software. The PCA is shut off by clearing this bit. The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be generated if the ECF bit in the CMOD register is set, The CF bit can only be cleared by software. Bits 0 through 4 of the CCON register are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. These flags also can only be cleared by software. The PCA interrupt system shown in Figure 16. Each module in the PCA has a special function register associated with it. These registers are: CCAPMO for module 0, CCAPM1 for module 1, etc. (see Figure 19). The registers contain the bits that control the mode that each module will operate in. The ECCF bit (CCAPMn.0 where n=0, 1, 2, 3, or 4 depending on the module) enables the CCF flag in the CCON SFR to generate an interrupt when a match or compare occurs in the associated module. PWM (CCAPMn.1) enables the pulse width modulation mode. The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to toggle when there is a match between the PCA counter and the medules capture/compare register. The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON register to be set when there is a match between the PCA counter and the modules capture/compare register. The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit enables the positive edge. If both bits are set both edges will be enabled anda capture will occur for either transition. The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function. Figure 20 shows the CCAPMnh settings for the various PCA functions. There are two additional registers associated with each of the PCA modules. They are GCAPnH and GGAPnL and these are the registers that store the 16-bit count when a capture occurs ora compare should occur. When a module is used in the PWM mode these registers are used to control the duty cycle of the output. <a fe [7] P1.3/CEXO <_____t=[7] P1.4/CEX1 +<l ___tm-[7] P1.5/CEX2 +l fem] P1.B/CEX3 eet $$ __fee{T) Pt zicexs [_ 16 BITS + _ MODULE 0 MODULE 1 16 BITS | PCA TIMER/COUNTER MODULE 2 TIME BASE FOR PCA MODULES MODULE 3 MODULE FUNCTIONS: 16-BIT CAPTURE 16-BIT TIMER 16-BIT HIGH SPEED GUTPUT MODULE 4 8-BIT PWM WATCHDOG TIMER (MODULE 4 ONLY} SU00032 Figure 14, Programmable Counter Array (PCA) 1997 May 30 26Philips Semiconductors Preliminary specification -bi 8XC52/54/58/80C32 6-bit CMOS (low voltage, low Power 8XC51 FA/FB/FC/80C51 FA and high speed) microcontroller families 8XC51RA+/RB+/RC+/RD+/80C51RA+ (8XC51FX and 8XC51RX+ ONLY) a TO PCA MODULES OSscH2 OVERFLOW osc INTERRUPT CH cL tot TIMER o 16-BIT UP COUNTER i OVERFLOW EXTERNAL INPUT (P1.2/ECH IDLE CMOD cIbL) | WOTE _ cPSt cPso ECF | (Don) CF cR _ cers | ccrs | ccre | ccri | coro | COON (DSH) SUoc033 Figure 15. PCA Timer/Counter CCON CCF3 CCF2 (Dat) PCA TIMER/COUNTER MODULE 0 IE.6 IE.7 EG EA MODULE 1 : : TO INTERRUPT PRIORITY DECODER MODULE 2 MODULE 3 MODULE 4 CMOD.o! ECF CCAPMn.O | ECCFn SU00034 Figure 16. PCA Interrupt System 1997 May 30 27Philips Semiconductors Preliminary specification 8-bit CMOS (low voltage, low power 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA and high speed) microcontroller families 8XC51RA+/RB+/RC+/RD+/80C51RA+ (8XC51FX and 8XC51RX+ ONLY) CMOD Address = ODSH Reset Value = 00XX X000B Bit Addressable CIDL WDTE - - - CPS1 CPSoO ECF Bit: 7 6 5 4 3 2 1 0 Symbol Function CIBL Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during idle Mode. CIDL = 1 programs it to be gated off during idle. WDTE Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it. - Not implemented, reserved for future use.* CPS1 PCA Gount Pulse Select bit 1. CPSO PCA Count Pulse Select bit 0. CPS1 CPSO = Selected PCA Input** 0 0 0 Internal clock, fogc + 12 0 1 1 Internal clock, fosc +4 1 0 2 Timer 0 overflow 1 1 3 External clock at ECI/P1.2 pin (max. rate = fogc + 8) ECF PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = 0 disables that function of CF. NOTE: * User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In ihat case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. ** fogc = oscillator frequency SU00035 Figure 17. CMOD: PCA Counter Mode Register GCON Address = OD8H Reset Value = 00X0 0000B Bit Addressable CF CR - CCF4 CCF3 CCF2 CCF1 CCFO Bit: 7 6 5 4 3 2 1 0 Symbol Function CF PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software but can only be cleared by software. CR PCA Gounter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA counter off. - Not implemented, reserved for future use*. COF4 PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF3 PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CGF2 PGA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF1 PGA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCFO PGA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. NOTE: * User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In ihat case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. SU00036 1997 May 30 Figure 18. GGCON: PGA Counter Control Register 28Philips Semiconductors Preliminary specification 8-bit CMOS (low voltage, low power and high speed) microcontroller families 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ (8XC51FX and 8XC51RX+ ONLY) CCAPMnh Address CCAPMO ODAH Reset Value = X000 0000B CCAPM1 oDBH CCAPM2 = ODCH CCAPM3 ODDH CCAPM4 ODEH Not Bit Addressable - ECOMn | CAPPn | CAPNn MATn TOGn PWMn | ECCFn Bit: 7 6 5 4 2 1 0 Symbol Function - Not implemented, reserved for future use. ECOMn Enable Comparator. ECOMn = 1 enables the comparator function. CAPPn Capture Positive, CAPPn = 1 enables positive edge capture. CAPNn Capture Negative, CAPNn = 1 enables negative edge capture. MATn Match. When MATn = 1, a match of the PCA counter with this modules compare/capture register causes the CCFn bit in CCON to be set, flagging an interrupt. TOGn Toggle. When TOGn = 1, a match of the PCA counter with this modules compare/capture register causes the CEXn pin to toggle. PWMn Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be used as a pulse width modulated output. ECCFn Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register to generate an interrupt. NOTE: User sotiware should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be O, and its active value will be 1. The value read from a reserved bit is indeterminate. SU00037 Figure 19. CCAPMn: PCA Modules Compare/Capture Registers - ECOMn | GAPPn | CAPNn MATn TOGn PWMn | ECCFn MODULE FUNCTION x i) 0 0 0 0 0 0 No operation x x 1 0 0 0 0 xX 16-bit capture by a positive-edge trigger on CEXn x x 0 1 0 0 0 xX 16-bit capture by a negative trigger on CEXn x x 1 1 0 0 0 x 16-bit capture by a transition on CEXn x 1 0 Q 1 0 0 x 16-bit Software Timer x 1 0 0 1 1 0 Xx 16-bit High Speed Output x 1 0 0 0 0 1 0 8-bit PWM x 1 0 0 1 Xx 0 Xx Watchdog Timer Figure 20. PCA Module Modes (CCAPMn Register) PGA Capture Mode High Speed Output Mode To use one of the PCA modules in the capture mode either one or both of the CCAPM bits CAPN and CAPP for that module must be set. The external CEX input for the module (on port 1) is sampled for a transition. When a valid transition occurs the PCA hardware loads the value of the PCA counter registers (CH and CL) into the module's capture registers (CCAPnL and GCAPnH). If the GCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated. Refer to Figure 21. 16-bit Software Timer Mode The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the modules CCAPMnh register. The PCA timer will be compared toe the modules capture registers and when a match occurs an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set (see Figure 22). 1997 May 30 29 In this mode the CEX output (on port 1) associated with the PCA module will toggle each time a match occurs between the PCA counter and the medules capture registers. To activate this mode the TOG, MAT, and ECOM bits in the modules CCAPMn SFR must be set (see Figure 23). Pulse Width Modulator Mode All of the PCA modules can be used as PWM outputs. Figure 24 shows the PWM function. The frequency of the output depends on the source for the PCA timer. All of the modules will have the same frequency of output because they all share the PCA timer. The duty cycle of each module is independently variable using the modules capture register CCAPLn. When the value of the PCA CL SFRis less than the value in the modules CCAPLn SFR the output will be low, when it is equal to or greater than the output will be high. When CL overflows from FF to 00, CCAPLn is reloaded with the value in CCAPHn. the allows updating the PWM without glitches. The PWM and ECOM bits in the modules CCAPMn register must be set to enable the PWM mode.Philips Semiconductors Preliminary specification -bi 8XC52/54/58/80C32 6-bit CMOS (low voltage, low Power 8XC51 FA/FB/FC/80C51 FA and high speed) microcontroller families 8XC51RA+/RB+/RC+/RD+/80C51RA+ (8XC51FX and 8XC51RX+ ONLY) CCON CF CR _ OCF4 COF3 CCF2 CCF1 CCFO (D8H} PCA INTERRUPT (TO COFn) PCA TIMER/COUNTER cH cL I : | J eae CAPTURE : : | cexn []}-+ ry Ee yi CCAPnH CCAPnL CCAPMn, n= 0 to 4 _ ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn (DAH DEH} SU00749 Figure 21. PCA Capture Mode Cr CR _ COF4 CCF3 COF2 CCF1 CCFO Der WRITE TO CCAPnH RESET PCA INTERRUPT WRITE TO CCAPNH CCAPhL (TO GOFn} CCAPnL 0 4 JL ENABLE 16-BIT COMPARATOR CH cL PCA TIMER/COUNTER CCAPMn, n= 0 to 4 ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn (DAH DEH! 4 0 0 0 a SU0G750 Figure 22. PCA Compare Mode 1997 May 30 30Philips Semiconductors Preliminary specification -bi 8XC52/54/58/80C32 6-bit CMOS (low voltage, low Power 8XC51 FA/FB/FC/80C51 FA and high speed) microcontroller families 8XC51RA+/RB+/RC+/RD+/80C51RA+ (8XC51FX and 8XC51RX+ ONLY) CF cR COF4 CCF3 ccr2 CCF1 CCFo (oer WRITE TO CCAPnH AESET PCA INTERRUPT WAITETO CCAPnH CCAPnL CCAPnL ENABLE MATCH i 16-BIT COMPARATOR H : i hi i i : : TOGGLE CH CL : i PCA TIMER/COUNTER CCAPMh, n: 0.4 ECOMn | CAPPn | CAPNn MATn TOGn PWMn ECCFn (DAH DEH) A a a 1 a SU00751 Figure 23. PCA High Speed Output Mode CCAPnH CCAPnL ENABLE I CL < GCAPnL 8-BIT | COMPARATOR CEXn Tp CL = GCAPnL 1 OVERFLOW CL PCA TIMER/COUNTER CCAPMn, n:0..4 ECOMn |) CAPPn | CAPNn | MATn TOGn PWMn | ECCEn (DAH DEH) 0 a 0 a a S00752 Figure 24. PCA PWM Mcde 1997 May 30 31Philips Semiconductors Preliminary specification 8-bit CMOS (low voltage, low power and high speed) microcontroller families 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ (8XC51FX and 8XC51RX+ ONLY) cMOD cio. | woTe cpst | cPso EOF | orn WRITE TO CCAP4H FET eaceecesttesseteeesntseesneceseresessteseetesseeeteseteesantessneterenetereneeten . WRITE TO CCAP4H CCAPAL MODULE 4 CCAP4L ENABLE MATCH ; 16-BIT COMPARATOR or RESET cH cL PCA TIMERCOUNTER ECOMn | CAPPn | CAPNn | MATn | TOGn | Pwen | EGCFn (OCH) T 0 0 1 x 0 x SLI008 32 Figure 25. PCA Watchdog Timer m(Mcdule 4 only) PCA Watchdog Timer An on-board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count. Watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge. Module 4 is the only PCA medule that can be programmed as a watchdog. However, this medule can still be used for other modes if the watchdog is not needed. Figure 25 shows a diagram of how the watchdog works. The user pre-loads a 16-bit value in the compare registers. Just like the other compare modes, this 16-bit value is compared to the PCA timer value. If a match is allowed to occur, an internal reset will be generated. This will not cause the RST pin to be driven high. In order to hold off the reset, the user has three options: 1. pericdically change the compare value so it will never match the PCA timer, periodically change the PCA timer value so it will never match the compare values, or 3. disable the watchdog by clearing the WDTE bit before a match occurs and then re-enable it. 1997 May 30 32 The first two options are more reliable because the watchdog timer is never disabled as in option #3. If the program counter ever goes astray, a match will eventually occur and cause an internal reset. The second option is also not recommended if other PCA modules are being used. Remember, the PCA timer is the time base for all modules; changing the time base for other modules would not be a good idea. Thus, in most applications the first solution is the best option. Figure 26 shows the code for initializing the watchdog timer. Module 4 can be configured in either compare mode, and the WDTE bitin CMOD must also be set. The users software then must periodically change (CCAP4H,CCAP4L) to keep a match from occurring with the PCA timer (CH,CL). This code is given in the WATCHDOG routine in Figure 26. This routine should not be part of an interrupt service routine, because if the program counter goes astray and gets stuck in an infinite loop, interrupts will still be serviced and the watchdog will keep getting reset. Thus, the purpose of the watchdog would be defeated. Instead, call this subroutine from the main program within 216 count of the PCA timer.Philips Semiconductors Preliminary specification -bi 8XC52/54/58/80C32 6-bit CMOS (low voltage, low Power 8XC51 FA/FB/FC/80C51 FA and high speed) microcontroller families 8XC51RA+/RB+/RC+/RD+/80C51RA+ (8XC51FX and 8XC51RX+ ONLY) INIT_WATCHDOG: MOV CCAPM4, #4CH 7 Module 4 in compare mode MOV CCAP4L, #0FFH 7 Write to low byte first MOV CCAP4H, #0FFH } Before PCA timer counts up tea } FFFF Hex, these compare values } must be changed ORL CMOD, #40H } Set the WDTE bit to enable the ; watchdog timer without changing } the other bits in CMOD ? PRR RK RRR KE KK RR KKK RRR KK KK EK K RR KKK RK RK RK RK RK K RR KKK RK RK KR RRR KK RK RK RK ROKK RK ? } Main program goes here, but CALL WATCHDOG pericdically. ? PR RRR KK RK KKK RR RR K RK KKK RR KKK RK KKK KR KKK RK KKK RR KKK RK KKK RR KKK RK KKK RR KKK KK ? WATCHDOG: CLR EA } Hold off interrupts MOV CCAP4L, #00 ;} Next compare value is within MOV CCAP4H, CH } 255 countts cf the current PCA SETB EA 7 timer value RET Figure 26. PCA Watchdog Timer Initialization Code 1997 May 30 33Philips Semiconductors Preliminary specification 8-bit CMOS (low voltage, low power and high speed) microcontroller families 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ (BXC51RX+ ONLY) Expanded Data RAM Addressing (BXC51RX+ ONLY) The 8XG51RX and 8XC51 RX+ have internal data memory that is mapped into four separate segments: the lower 128 bytes of RAM, upper 128 bytes of RAM, 128 bytes Special Function Register (SFR), and 256 bytes (768 for RD and RD+) expanded RAM (ERAM). The four segments are: 1. The Lower 128 bytes of RAM (addresses OOH to 7FH) are directly and indirectly addressable. The Upper 128 bytes of RAM (addresses 80H to FFH) are indirectly addressable only. The Special Function Registers, SFRs, (addresses 80H to FFH) are directly addressable only. The 256-bytes (768 for RD+) expanded RAM (ERAM, OOH FFH) are indirectly accessed by move external instruction, MOVX, and with the EXTRAM bit cleared, see Figure 27. The Lower 128 bytes can be accessed by either direct or indirect addressing. The Upper 128 bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy the same address space as the SFR. That means they have the same address, but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the GPU knows whether the access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode used in the instruction. Instructions that use direct addressing access SFR space. For example: MOV OAH, #data accesses the SFR at location OAQH (which is P2). Instructions that use indirect addressing access the Upper 128 bytes of data RAM. For example: MOV @R0,#data where RO contains OAGH, accesses the data byte at address OAQH, rather than P2 (whose address is OAQH). The ERAM can be accessed by indirect addressing, with EXTRAM bit cleared and MO'X instructions. This part of memory is physically located on-chip, logically occupies the first 256-bytes (768 for RD and RD+) of external data memory. With EXTRAM = 0, the ERAM is indirectly addressed, using the MOV*X instruction in combination with any of the registers RO, R1 of the selected bank or DPTR. An access to ERAM will not affect ports PO, P3.6 (WR#) and P3.7 (RD#). P2 SFR is cutput during external addressing. For example, with EXTRAM = 0, MOVX @RO0,#data where RO contains OAQH, access the ERAM at address 0AQH rather than external memory. An access to external data memory locations higher than FFH (2FF for RD and RD+) (i.e., 0100H to FFFFH) will be performed with the MOVX DPTR instructions in the same way as in the standard 80C51, so with PO and P2 as data/address bus, and P3.6 and P3.7 as write and read timing signals. Refer to Figure 28. With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard 80C651. MOVX @ Ri will provide an 8-bit address multiplexed with data on Port 0 and any output port pins can be used to output higher order address bits. This is to provide the external paging capability. MOVX @DPTR will generate a 16-bit address. Port 2 outputs the high-order eight address bits (the contents of BPH) while Port 0 multiplexes the low-order eight address bits (DPL) with data. MOVX @Ri and MOVX @DPTR will generate either read or write signals on P3.6 (#WR) and P3.7 (#RD). The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM) internal data memory. The stack may not be located in the ERAM. AUXR Address = 8EH Reset Value = xxxx xx00B Not Bit Addressable _ _ _ _ _ _ EXTRAM AO Bit: 7 6 5 4 3 2 1 0 Symbol Function AO Disable/Enable ALE AO Operating Mode 0 ALE is emitted at a constant rate of 1/6 the oscillator frequency. 1 ALE is active only during a MOVX or MOVC instruction. EXTRAM _Internal/Extermal RAM (QOH FFH) access using MOVX @Ri/@DPTR EXTRAM Operating Mode 0 Internal ERAM (QQH-FFH) (QOH2FFH for RD+) access using MOVX @Ri/@DPTR 1 External data memory access. Not implemented, reserved for future use. NOTE: User software should not write 1s io reserved bits. These bits may be used in future 8051 family products to invoke new features. In ihat case, the reset or inactive value of the new bit will be O, and its active value will be 1. The value read from a reserved bit is indeterminate. SUO0833A Figure 27. AUXR: Auxiliary Register (RX+ only) 1997 May 30 34Philips Semiconductors Preliminary specification 8-bit CMOS (low voltage, low power 8XC52/54/58/80C32 te ( vitage, P a: 8XC51FA/FB/FC/80C51 FA and high speed) microcontroller families 8XC51RA+/RB+/RC+/RD+/80C51RA+ (BXC51RX+ ONLY) 2FF (RD TO AD} FF * a FF FFFF UPPER SPECIAL EXTERNAL 128 BYTES FUNCTION DATA INTERNAL RAM REGISTER MEMORY ERAM 80 80 Le Fe 256 BYTES F LOWER 128 BYTES INTERNAL RAM 300 (RD AND RD+} 1 00 00 00 000 Suoos34 Figure 28. Internal and External Data Memory Address Space with EXTRAM = 0 HARDWARE WATCHDOG TIMER (ONE-TIME ENABLED WITH RESET-OUT FOR 8XC51RX+) The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer reset (WDTRST) SFR. The WDT is disabled at reset. To enable the WDT, user must write 01EH and 0E1Hin sequence to the WDTRST, SFR location 0A6H. When WOT is enabled, it will increment every machine cycle while the oscillatoris running and there is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WOT overflows, it will drive an output reset HIGH pulse at the RST-pin. Using the WDT To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location OAGH. When WDT is enabled, the user needs to service it by writing to 01EH and OE1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when it reaches 16383 (8FFFH) and this will reset the device. When WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycles. To reset the WDT, the user must write 01EH and 0E1H to WDTRST. WDTRST is a write only register. The WOT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the reset pin. The RESET pulse duration is 98 x Tosc, where Tosc = 1/foge. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WOT reset. 1997 May 30 35Philips Semiconductors Preliminary specification 8-bit CMOS (low voliage, low power eee and high speed) microcontroller families 8XC51RA+/RB+/RC+/RD+/80C51RA+ ABSOLUTE MAXIMUM RATINGS? 2: 3 PARAMETER RATING UNIT Operating temperature under bias 0 to +70 or 40 to +85 C Storage temperature range 65 to +150 C Voltage on EA/Vpp pin to Veg 0 to +13.0 Vv Voltage on any other pin to Vg -0.5to +6.5 Vv Maximum lo. per I/O pin 15 mA Power dissipation (based on package heat transfer limitations, not device power consumption) 15 W NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, itis suggested that conventional precautions be taken to avoid applying greater than the rated maximum. 3. Parameters are valid over operating temperature range unless ctherwise specified. All voltages are with respect to Vgg unless otherwise noted. 1997 May 30 36Philips Semiconductors Preliminary specification 8-bit CMOS (low voltage, low power and high speed) microcontroller families 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ DC ELECTRICAL CHARACTERISTICS Tamb = OC to +70C or 40C to +85C, Vere = 2.7V to 5.5V, Veg = OV (16MHz devices) TEST LIMITS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT 4.0V < Voc < 5.5V 0.5 0.2Vec0.1 Vv Vit Input low voltage 2.7V<Vec< 4.0V 05 0.7 v Vin Input high voltage (ports 0, 1, 2, 3, EA) 0.2Vee+0.9 Vect0.5 Vv View Input high voltage, XTAL1, RST 0.7Vec Vect+0.5 Vv Veo =2.7V 8 cc Voi Output low voltage, ports 1, 2, lo = 1.6mA2 0.4 Vv Vv Output low voltage, port 0, ALE, PSEN: 7 Voc = 2.7V 0.4 Vv ou 1 1 , lop = 3.2mA? , Veco =2.7V lon = -20uA Voc -0.7 Vou Output high voltage, ports 1, 2, 33 Voc = 4.5V Ver -0.7 Vv lon = 30pnA co Output high voltage (port O in external bus mode), Veco =2.7V _ Vout ALES, PSEN low = -3.2mA Voc 9.7 V lit Logical 0 input current, ports 1, 2, 3 Vin = 0.4V -1 50 pA AL Logical 1-to-0 transition current, ports 1, 2, 36 Mi letenet 650 pA lu Input leakage current, port 0 0.45 < Vin < Vec -9.3 +10 pA lec Power supply current (see Figure 36): See note 5 Active mode @ 16MHz 15 mA Idle mode @ 18MHz 4 mA Power-down mode or clock stopped (see Figure 40 Tamb = 0C to 70C 3 50 pA for conditions) Tamb = 40C to +85C 75 pA Rrst Intemal reset pull-down resistor 40 225 kQ. Cio Pin capacitance! (except EA) 15 pF NOTES: 1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the Vg,s of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. lq, can exceed these conditions provided that no single output sinks more than 5mA and no more than two outputs exceed the test conditions. 3. Capacitive loading on ports 0 and 2 may cause the Vqy on ALE and PSEN tc momentarily fall below the V0.7 specification when the address bits are stabilizing. 4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when Vjjy is approximately 2V. 5. See Figures 37 through 40 for lec test conditions. Active mode: = Ieg = 0.9 x FREQ. + 1.1mA Idle mode: leg = 0.18 x FREQ. +1.01mA; See Figure 36. This value applies to Tamp = OC to +70C. For Tamp = 40C to +85C, I = 750nA. Load capacitance for port 0, ALE, and PSEN = 100pfF, load capacitance for all other outputs = 80pF. Under steady state (non-transient) conditions, lq, must be externally limited as follows: Maximum le, per port pin: 15mA (*NOTE: This is 85C specification.) Maximum Io. per 8-bit port: 26mA Maximum total Ip for all outputs: 7imA If lo. exceeds the test condition, VoL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 9. ALE is tested to Voy1, except when ALE is off then Voy is the voltage specification. 10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF (except EA is 25pF). ON & 1997 May 30 37Philips Semiconductors Preliminary specification 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ 8-bit CMOS (low voltage, low power and high speed) microcontroller families DC ELECTRICAL CHARACTERISTICS Tamb = 0C to +70C or 40C to +85C, 24MHz and 33MHz devices; 5V +10%; Vgg = OV TEST LIMITS SYMBOL PARAMETER UNIT CONDITIONS MIN TYP! MAX VIL Input low voltage 4.5V<Vec <5.5V 0.5 0.2Vce-0.1 Vv Vin Input high voltage (ports 0, 1, 2,3, EA) 0.2Vece+0.9 Vect0.5 Vint Input high voltage, XTAL1, RST 0.7Vec Vect0.5 Veco = 4.5V 8 cc VoL Output low voltage, ports 1, 2, 3 lop = 1.6mA2 0.4 Vv Vv, Output low voltage, port 0, ALE, PSEN 7: Voc = 4.5V 04 v ou Pp ge, port , , lo. = 3.2mAZ , . Veco =4.5V 3 cc Vou Output high voltage, ports 1, 2, 3 low = -30pA Veco 0.7 Vv Output high voltage (port 0 in external bus mode}, Veco = 4.5V _ Vout ALES, PSEN? lon = -3.2mA Veo-0.7 V lit Logical 0 input current, ports 1, 2, 3 Vin =0.4V -1 -50 WA AL Logical 1-to-0 transition current, ports 1, 2, 36 vin= 2.0V 650 WA lu Input leakage current, port 0 0.45 <Vin< Vee - 0.3 +10 WA lec Power supply current {see Figure 36): See note 5 Active mode (see Note 5) Idle mode (see Note 5) Power-down mode or clock stopped (see Figure 40 Tamb = 0C to 70C 3 50 yA for conditions) Tamb = 40C to 485C 75 A Rrst Internal reset pull-down resistor 40 225 kQ Cio Pin capacitance! (except EA) 15 pF NOTES: 1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the Vo_s of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. lo, can exceed these conditions provided that no single output sinks more than 5mA and no more than two outputs exceed the test conditions. 3. Capacitive loading on ports 0 and 2 may cause the Vgy on ALE and PSEN tc momentarily fall below the Ve0.7 specification when the address bits are stabilizing. 4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when Vjy is approximately 2V. 5. See Figures 37 through 40 for lec test conditions. Active mode: locqmaxy = 9.9 x FREQ. + 1.1mA Idle mode: lecimaxy = 0.18 x FREQ. +1.0mA; See Figure 36. This value applies to Tamb = OC to +70C. For Tamb = 40C to +85C, IL = 750nA. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance fer all other outputs = 80pF. Under steady state (non-transient) conditions, ley must be externally limited as follows: Maximum Ie. per port pin: 15mA (*NOTE: This is 85C specification.) Maximum ley per 8-bit port: 26mA Maximum total Ip. for all outputs: 71imA If lo, exceeds the test condition, Vo, may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 9. ALE is tested to Vou1. except when ALE is off then Voy is the voltage specification. 10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF (except EA is 25pF). ON 1997 May 30 38Philips Semiconductors Preliminary specification 8-bit CMOS (low voltage, low power and high speed) microcontroller families 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ AC ELECTRICAL CHARACTERISTICS Tamb = 0C to +70C or 40C to 485C, Veco = +2.7V to +5.5V, Vgg = OV 23 16MHz CLOCK VARIABLE CLOCK SYMBOL | FIGURE PARAMETER MIN MAX MIN MAX UNIT TAeLeL 29 Oscillator frequency Speed versions :4;5:s 3.5 16 MHz tHe 29 ALE pulse width 85 Zte, cy 40 ns tAVLL 29 Address valid to ALE low 22 te_cL-40 ns tLLAX 29 Address hold after ALE low 32 teLc_-30 ns Loy 29 ALE low to valid instruction in 150 4te, cL -100 ns tLLPL 29 ALE low to PSEN low 32 tec. -30 ns tPLPH 29 PSEN pulse width 142 3te_cL-45 ns tPLiy 29 PSEN low to valid instruction in a2 3te_cL-105 ns tpxix 29 Input instruction hold after PSEN Q Q ns tpxiz 29 Input instruction float after PSEN 37 ter cl-25 ns tayviy 4 29 Address to valid instruction in 207 5te_c. -105 ns tPLAZ 29 PSEN low to address float 10 10 ns Data Memory tRLRH 30,31 | AD pulse width 275 6Btey c.-100 ns twhwH 30,31 | WR pulse width 275 Bte_ c_-100 ns tRLDv 30,31 | RD low to valid data in 147 5tc_c_-165 ns tRHDx 30,31 | Data hold after RD Q Q ns trHDz 30,31 Data float after RD 65 Ate. 60 ns tLupy 30, 31 ALE low to valid data in 350 8te_c .-150 ns tayvpy 30, 31 Address to valid data in 397 Ste_c_-165 ns LOWE 30,31 | ALE low to RD or WR low 137 239 3te_c -80 3te, cL +50 ns bAVWL 30,31 | Address valid to WH low or RD low 122 4ter cp -130 ns tovwx 30,31 | Data valid to WR transition 13 tei, -50 ns twHox 30,31 | Data hold after WR 13 tei cp -50 ns toywH 31 Data valid to WR high 287 7te_cL-150 ns teLaz 30,31 | AD low to address float Q Q ns tWHLH 30,31 | RDor WRhigh to ALE high 23 103 te_c, 40 tere +40 ns External Clock tenex 33 High time 20 20 tere-ctetex ns teLex 33 Low time 20 20 tecer-tcHex ns teLcH 33 Rise time 20 20 ns teHeL 33 Fall time 20 20 ns Shift Register bee xt 32 Serial port clock cycle time 750 12teceL ns toyxH 32 Output data setup to clock rising edge 492 10te_ .-133 ns tyHoX 32 Output data hold after clock rising edge 8 2te_ci-117 ns tyHpx 32 Input data hold after clock rising edge 0 0 ns txHDV 32 Clock rising edge to input data valid 492 10te tc _133 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the microcontroller to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. See application note AN457 for external memory interface. 5. Parts are guaranteed to operate down to OHz. 1997 May 30Philips Semiconductors Preliminary specification -bi 8XC52/54/58/80C32 6-bit CMOS (low voltage, low Power 8XC51 FA/FB/FC/80C51 FA and high speed) microcontroller families 8XC51RA+/RB+/RC+/RD+/80C51RA+ AC ELECTRICAL CHARACTERISTICS Tamb = 0G to +70C or 40C to 485C, Veg = 5V 410%, Vgg = 0V12 3 24MHz CLOCK VARIABLE CLOCK4 33MHz CLOCK SYMBOL | FIGURE PARAMETER MIN MAX MIN MAX MIN MAX | UNIT Teter 29 Oscillator frequency 3.5 33 Speed versions: A;B;T (24MHz) 3.5 24 MHz : I;J;U (33MHz) 3.5 33 tHLL 29 ALE pulse width 43 Ate. cy, 40 21 ns taVLL. 29 Address valid to ALE low 17 tee 25 5 ns tLLAX 29 Address hold after ALE low 17 tote. 25 ns Luv 29 ALE low te valid instruction in 102 4te_e_-65 55 ns {LLPL 29 ALE low to PSEN low 17 teLe_-25 5 ns tp, pH 29 PSEN pulse width 80 Step . 45 45 ns tPLiy 29 PSEN low to valid instruction in 65 3te_ c_-60 30 ns tex 29 Input instruction hold after PSEN 0 4) a ns tpxiz 29 Inputinstruction float after PSEN 17 tee. -25 5 ns taviy 29 Address to valid instruction in 128 Ste, ce, -80 70 ns tpLaz 29 PSEN low to address float 10 10 10 ns Data Memory tRLRH 30, 31 RD pulse width 150 BteLe_100 82 ns tWwLWH 30, 31 WR pulse width 150 BteLe_-100 82 ns tripy 30, 31 RD low to valid data in 118 Ste, e_-90 60 ns tRHpx 30, 31 Data hold after RD 0 a) a ns tRupz 30, 31 Data float after RD 55 2te, c.-28 32 ns tLLDy 30, 31 ALE low to valid data in 183 8te_cL-150 90 ns tayDV 30, 31 Address to valid data in 210 Ste_eL-165 105 ns {LLWL 30, 31 ALE low to RD or WR low 75 175 Ste_cL 50 Ste_cL+50 40 140 ns tAVWL 30,31 | Address valid to WR low or RD low 92 4te. cL -75 45 ns tovwx 30, 31 Data valid to WR transition 12 tetc L390 0 ns twHoXx 30, 31 Data hold after WR 17 tere -25 5 ns tovwH 31 Data valid to WR high 162 7te_, -130 80 ns teLaz 30,31 | RD low to address float 0 Q 0 ns tWHLH 30,31 | RD or WR high to ALE high 17 67 teLe_ 25 tee +25 5 55 ns External Clock teHex 33 High time 17 17 tere_teLex ns teLex 33 Low time 17 17 tece_-teHex ns teLcH 33 Rise time 5 5 ns teHeL 33 Fall time 5 5 ns Shift Register ixLxL 32 Serial port clock cycle time 505 12tcLeL 360 ns tovxH 32 Output data setup to clock rising edge 283 10te_e_-133 167 ns txHOX 32 Output data hold after clock rising edge 3 2te_cL-80 ns tyHDpXx 32 Input data hold after clock rising edge 0 0 0 ns tyHpy 32 Clock rising edge to input data valid 283 10tey ,-133 167 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the microcontroller to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. Variable clock is specified for oscillator frequencies greater than 16MHz to 33MHz. For frequencies equal or less than 16MHz, see 16MHz AC Electrical Characteristics, page 39. 5. Parts are guaranteed to operate down to OHz. 1997 May 30 40Philips Semiconductors Preliminary specification 8-bit CMOS (low voltage, low power and high speed) microcontroller families 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ EXPLANATION OF THE AC SYMBOLS Each timing symbol has five characters. The first character is always t (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are: A Address CG - Clock D Input data H Logic level high | Instruction (program memory contents) L Logic level low, or ALE P PSEN Q- Output data R RD signal t Time V - Valid W- WR signal X No longer a valid logic level Z Float Examples: tay), = Time for address valid to ALE low. tuLpL =Time for ALE low to PSEN low. LHL ALE _tavin | tipe | 1 tpl mK SN tpxix PORTO | INSTR IN AG-A? _ PORT 2 A0-A15 _ >< x AS-AIS Xx SU0G006 Figure 29. External Pr ogram Memory Read Cycle ALE / \ hr twHLH > tLLbv * << tLUOWL et tRLRH * AD NN rd ee 4 tLLAX _ tRHDZ taviL [<> trrpy | * tRLAZ, trupx >| z= AO-A7 io PORT 0 __ > FROM Fl OR DPL < DATA IN > AO-A7 FHOM PCL Csi <_ tAVWL all tavov PORT a 2 P2.0-P2.7 OR A84A15 FROM DPF AO-A15 FROM PCH N Suez Figure 30. External 1997 May 30 Data Memory Read Cycle 4Philips Semiconductors Preliminary specification 8-bit CMOS (low voltage, low power BXC52/54/58/80C32 t ( tage, p 8XC51FA/EB/EC/80C51 FA and high speed) microcontroller families 8XC51RA+/RB+/RC+/RD+/80C51RA+ ALE ie rm tWHLH mA \ @ tower et twLWwH * WH Y | tLLax tavLL [<> tovwx > twHax e<_ _ tavwu | / PORT a f oy ote DATA OUT AQ-A7 FROM PCL INSTR IN FROM RIOR DPL AQ < taywL * / PORT 2 x P2.0-P2.7 OR A8-A15 FROM DPF x AQ-A15 FROM PCH N SLI00026 Figure 31. External Data Memory Write Cycle INSTRUCTION || 0 | 1 | 2 | 3 | 4 | 5 | B | 7 | 8 | cook LJ LI LJ LI LILI LI Lo OUTPUT DATA WAITE TO SBUF A | txHDX txHDV INPUT DATA Ud CLEAR RI SET RI SUG0027 Figure 32. Shift Register Mode Timing VeeO5 - 7 7 7 ce avec 0.45 0.2Vv60C-0.1 Stioceag Figure 33. External Clock Drive 1997 May 30 42Philips Semiconductors Preliminary specification -bi 8XC52/54/58/80C32 6-bit CMOS (low voltage, low Power 8XC51 FA/FB/FC/80C51 FA and high speed) microcontroller families 8XC51RA+/RB+/RC+/RD+/80C51RA+ TIMING VoOH-O.1 REFERENCE ~ POINTS = ay Veco0.5 x O.2VEC109 x VLOAD+0.1 VLOAD' o4sV OVvec-0.1 VLOAD-O.1 VoOL+o.1 NOTE: NOTE: AC inputs during testing are driven at Voc 0.5 for a logic 1 and 0.45 for a logic 0. For timing purposes, a port is no longer floating when a 100m change trom Timing measurements are made at V\4 min for a logic 1 and _ max for a logic o. load voltage occurs, and begins to float when a 100m change from the loaded Vou oc level occurs. Iolo. = +20MA. SU00717 SU00718 Figure 34, AC Testing Input/Output Figure 35. Float Waveform 90.00 80.00 70.00 MAX ACTIVE MODE = +1. 60.00 50.00 IocimA} 40.00 TYP ACTIVE MODE 30.00 20.00 MAX IDLE MODE 10.00 1 0.00 TYP IDLE MODE | 0 4 8 12 15 20 24 28 32 36 FREQ AT XTAL1 (MH2} SUO0837A Figure 36. Icg vs. FREQ Valid only within frequency specifications of the device under test 1997 May 30 43Philips Semiconductors Preliminary specification 8XC52/54/58/80C32 8-bit CMOS (low voltage, low power aXC51 FAIRR/EGIB0CS1 EA and high speed) microcontroller families 8XC51RA+/RB+/RC+/RD+/80C51RA+ Moc Voc loc lec Voc Yoo Voc Mes RST Yoo Po K Po | RST NJ NM EA = ER (NC} XTAL2 (NC} XTAL2 CLOCK SIGNAL w] XTAL1 CLOCK SIGNAL _-] XTAL1 = ab _ = suos7ig 7 su0720 Figure 37. leg Test Condition, Active Mode Figure 38. Igg Test Condition, Idle Mode All other pins are disconnected All other pins are disconnected Voe-O5 - > > = Ooo 0.45V o-vVvec0.1 SUocoeg Figure 39. Clock Signal Waveform for Icc Tests in Active and Idle Modes teicH = tcHeL = 5ns Voc loc Voc AST Voo Pa | = _| \ EA (NC) XTAL2 XTALI = Vss = SUO0016 Figure 40. lec Test Condition, Power Down Mode All other pins are disconnected. Veg = 2V to 5.5V 1997 May 30 44Philips Semiconductors Preliminary specification 8-bit CMOS (low voltage, low power and high speed) microcontroller families 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ EPROM CHARACTERISTICS All these devices can be programmed by using a modified Improved Quick-Pulse Programming algorithm. It differs from older methods in the value used for Vpp (programming supply voltage) and in the width and number of the ALE/PROG pulses. The family contains two signature bytes that can be read and used by an EPROM programming system to identify the device. The signature bytes identify the device as being manufactured by Philips. Table 9 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the security bits. The circuit configuration and waveforms for quick-pulse programming are shown in Figures 41 and 42. Figure 43 shows the circuit configuration for normal program memory verification. Quick-Pulse Programming The setup for microcontroller quick-pulse programming is shown in Figure 41. Note that the device is running with a 4 to BMHz oscillator. The reason the oscillator needs to be running is that the device is executing internal address and program data transfers. The address of the EPROM location to be programmed is applied to ports 1 and 2, as shown in Figure 41. The code byte to be programmed into that location is applied to port 0. RST, PSEN and pins of ports 2 and 3 specified in Table 9 are held at the Program Code Data levels indicated in Table 9. The ALE/PROG is pulsed low 5 times as shown in Figure 42. To program the encryption table, repeat the 5 pulse programming sequence for addresses 0 through 1FH, using the Pgm Encryption Table levels. Do not forget that after the encryption table is programmed, verification cycles will produce only encrypted data. To program the security bits, repeat the 5 pulse programming sequence using the Pgm Security Bit levels. After one security bit is programmed, further programming of the code memory and encryption table is disabled. However, the other security bits can still be programmed. Note that the EA/Vpp pin must not be allowed to go above the maximum specified Vpp level for any amount of time. Even a narrow glitch above that voltage can cause permanent damage to the device. The Vpp source should be well regulated and free of glitches and overshoot. Program Verification If security bits 2 and 3 have not been programmed, the on-chip program memory can be read out for program verification. The address of the program memory locations to be read is applied to ports 1 and 2 as shown in Figure 43. The other pins are held at the Verify Code Data levels indicated in Table 9. The contents of the address location will be emitted on port 0. External pull-ups are required on port 0 for this operation. If the 64 byte encryption table has been programmed, the data presented at port 0 will be the exclusive NOR of the program byte with one of the encryption bytes. The user will have to know the encryption table contents in order to correctly decode the verification data. The encryption table itself cannot be read out. Trademark phrase of Intel Corporation. 1997 May 30 45 Reading the Signature Bytes The signature bytes are read by the same procedure as a normal verification of locations 030H and 031H, except that P3.6 and P3.7 need to be pulled to a logic low. The values are: (030H)= 15H indicates manufactured by Philips (031H)= 97H indicates 87C52 BBH indicates 87C54 BDH indicates 87C58 BiH indicates 87C51FA B2H indicates 87C51FB B3H indicates 87C51FC CAH indicates 87C51RA+ CBH indicates 87C51RB+ CCH indicates 87C51RC+ CDH indicates 87C51RD+ FAH indicates 87C51FA FBH indicates 87C51FB FCH indicates 87C51 FC COH indicates 87C51RA+ Ci1H indicates 87C51RB+ C@H indicates 87C51RC+ C3H indicates 87C51RD+ (060H) = Program/Verify Algorithms Any algorithm in agreement with the conditions listed in Table 9, and which satisfies the timing specifications, is suitable. Erasure Characteristics Erasure of the EPROM begins to occur when the chipis exposed to light with wavelengths shorter than approximately 4,000 angstroms. Since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in room level fluorescent lighting) could cause inadvertent erasure. For this and secondary effects, it is recommended that an opaque label be placed over the window. For elevated temperature or environments where solvents are being used, apply Kapton tape Fluorglas part number 2345-5, or equivalent. The recommended erasure procedure is exposure to ultraviolet light (at 2537 angstroms) to an integrated dose of at least BOW-s/cm2. Exposing the EPROM to an ultraviolet lamp of 12,000uW/crn? rating for 90 to 120 minutes, at a distance of about 1 inch, should be sufficient. Erasure leaves the array in an all 1s state. Security Bits With none of the security bits programmed the code in the program memory can be verified. If the encryption table is programmed, the code will be encrypted when verified. When only security bit 1 (see Table 10) is programmed, MOYVC instructions executed from external program memory are disabled from fetching code bytes from the internal memory, EA is latched on Reset and all further programming of the EPROM is disabled. When security bits 1 and 2 are programmed, in addition to the above, verify mode is disabled. When all three security bits are programmed, all of the conditions above apply and all external program memory execution is disabled. Encryption Array 64 bytes of encryption array are initially unprogrammed (all 1s).Philips Semiconductors Preliminary specification 8-bit CMOS (low voltage, low power 8XC52/54/58/80C32 and high speed) microcontroller families 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ Table 9. EPROM Programming Modes MODE RST PSEN ALE/PROG | EA/Vpp P2.7 P2.6 P3.7 P3.6 Read signature 1 0 1 1 0 0 0 0 Program code data 1 0 o* Vpp 1 0 1 1 Verify code data 1 0 1 1 0 0 1 1 Pgm encryption table 1 0 o* Vpp 1 0 1 0 Pgm security bit 1 1 Qa Q* Vpp 1 1 1 1 Pgm security bit 2 1 0 o* Vpp 1 1 0 0 Pgm security bit 3 1 a0 a* Vpp ) 1 a0 1 NOTES: 1. 0 = Valid low for that pin, 1 = valid high for that pin. 2. Vpp = 12.75V +0.25V. 3. Vee = 5V+10% during programming and verification. * ALE/PROG receives 5 programming pulses for code data (also for user array; 5 pulses for encryption or security bits) while Vpp is held at 12.75V. Each programming pulse is low for 100us (+1018) and high for a minimum of 10s. Table 10. Program Security Bits for EPROM Devices PROGRAM LOCK BITS!:2 SB1 SB2 SB3 | PROTECTION DESCRIPTION 1 U U U No Program Security features enabled. (Code verify will still be encrypted by the Encryption Array if programmed.) 2 P U U MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on Reset, and further programming of the EPROM is disabled. 3 P P U Same as 2, also verify is disabled. 4 P P Same as 3, external execution is disabled. NOTES: 1. P-programmed. U- unprogrammed. 2. Any other combination of the security bits is not defined. 1997 May 30 46Philips Semiconductors Preliminary specification 8-bit CMOS (low voltage, low power and high speed) microcontroller families 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ +5 AGA? API Voc /\ Po K PGM DATA 1 _] AST 1 yl P36 EAVpp #*___ +12.75V 1 _f p37 ALE-PROG '*__. PULSES TO GROUND EPROM/OTP PSEN ft__ 0 , i] XTAL2 P27 }*_ 1 4emHz _ P26 f__ 0 TL Tr XTAL1 P2zoPp25 Kk AS-AI3 Vss P34 ___ Al4 A8A15 are programming addresses _ P3.5 Je _ A15(RD+ ONLY} {not external memory addresses per - device pin out} SUOOB38A Figure 41. Programming Configuration lt 5 PULSES | 1 ALE/PHOG: a 1 2 3 4 2 ee SEE eX BELOW igHaL = 10s MIN TeLGH = 100p1st10ps 1 ALE/PROG: o | 1 SUO08 75 Figure 42. PROG Waveform +5V Voc AQ-AT 1 PA Po PGM DATA 1 | _] RST EAVpp [*_ 1 1 _#] P3.6 1 a 1 x] p37 ALEPROG EPROM/OTP PSEN }*___ 0 ff, i XTAL2 p27 }#__ 9 ENABIE 46MHz C2 P26 f*___ 9 TL Tr XTAL1 P? O-P25 AB-A13. Vss P34 *___ Ala AS-A15 are programming addresses = p35 fe. 415 (RD+ ONLY} (not external memory addresses per - device pin out} su0870 Figure 43. Program Verification 1997 May 30 47Philips Semiconductors Preliminary specification -bi 8XC52/54/58/80C32 6-bit CMOS (low voltage, low Power 8XC51 FA/FB/FC/80C51 FA and high speed) microcontroller families 8XC51RA+/RB+/RC+/RD+/80C51RA+ EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS Tamb = 21C to +27C, Veg = 5V+10%, Vgs = OV (See Figure 44) SYMBOL PARAMETER MIN MAX UNIT Vpp Programming supply voltage 12.5 13.0 Vv Ipp Programming supply current 50 1 mA Ttere Oscillator frequency 4 6 MHz tAVGL Address setup to PROG low 48tcLcL tGHax Address hold after PROG 48tcLeL toveL Data setup to PROG low 48tcLeL teHDx Data hold after PROG 48tcLcL tEHSH P2.7 (ENABLE) high to Vpp 48tei cL tsHeL Vpp setup to PROG low 10 us tGHsL Vpp hold after PROG 10 Ls tGLGH PROG width go 110 us tavay Address to data valid 48tcicL teLoz ENABLE low to data valid 48tcLcoL teHOz Data float after ENABLE 0 48teLcL tGHEL PROG high to PROG low 10 us NOTE: 1. Not tested. PROGRAMMING* VERIFICATION* P1.0-P17 ADDRESS P2.0-P2.5 P34 (AOA14) M tavoy PORTO $$$$$= _( DATA OUT >_- P0.0 PO.7 n, / (Do - D7) tGHDx tGHAX ALE/PROG tGHSL LOGIC 1 LOGIC 1 EANpp LOGIC o tEHSH tELav teHaz P2.7 SLI008 77 NOTES: * FOR PROGRAMMING CONFIGURATION SEE FIGURE 41. FOR VERIFICATION CONDITIONS SEE FIGURE 43. "SEE TABLE 9. Figure 44. EPROM Programming and Verification 1997 May 30 48Philips Semiconductors Preliminary specification -bi 8XC52/54/58/80C32 6-bit CMOS (low voltage, low Power 8XC51 FA/FB/FC/80C51 FA and high speed) microcontroller families 8XC51RA+/RB+/RC+/RD+/80C51RA+ MASK ROM DEVICES Security Bits intemal memory, EA is latched on Reset and all further programming With none of the security bits programmed the code in the program of the EPROM is disabled. When security bits 1 and 2 are memory can be verified. If the encryption table is programmed, the programmed, in addition to the above, verify mode is disabled. code will be encrypted when verified. When only security bit 1 (see Table 11) is programmed, MOVC instructions executed from external program memory are disabled from fetching code bytes from the Encryption Array 64 bytes of encryption array are initially unprogrammed (all 1s). Table 11. Program Security Bits PROGRAM LOCK BITS1: 2 SBI SB2_ | PROTECTION DESCRIPTION 1 U U No Program Security features enabled. (Code verify will still be encrypted by the Encryption Array if programmed.) 2 P U MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on Reset, and further programming of the EPROM is disabled. NOTES: 1. P-programmed. U unprogrammed. 2. Any other combination of the security bits is not defined. ROM CODE SUBMISSION FOR 8K ROM DEVICES (80052, 83C51FA, AND 83C51RA+) When submitting ROM code for the 8k ROM devices, the following must be specified: 1. 8k byte user ROM data 2. 64 byte ROM encryption key 3. ROM security bits. ADDRESS CONTENT BIT(S) COMMENT Q000H to 1FFFH DATA 70 User ROM Data 2000H to 201FH KEY 7:0 ROM Encryption Key FFH = no encryption 2020H SEG 0 ROM Security Bit 1 0 = enable security 1 = disable security 2020H SEC 1 ROM Security Bit 2 0 = enable security 1 = disable security Security Bit1: When programmed, this bit has two effects on masked ROM parts: 1. External MOVC is disabled, and 2. EA is latched on Reset. Security Bit 2: When programmed, this bit inhibits Verify User ROM. NOTE: Security Bit 2 cannot be enabled unless Security Bit 1 is enabled. If the ROM Code file does not include the options, the following information must be included with the ROM code. For each of the following, check the appropriate box, and send to Philips along with the code: Security Bit #1: OU Enabled OU Disabled Security Bit #2: OU Enabled OU Disabled Encryption: O No O Yes If Yes, must send key file. 1997 May 30 49Philips Semiconductors Preliminary specification -bi 8XC52/54/58/80C32 6-bit CMOS (low voltage, low Power 8XC51 FA/FB/FC/80C51 FA and high speed) microcontroller families 8XC51RA+/RB+/RC+/RD+/80C51RA+ ROM CODE SUBMISSION FOR 16K ROM DEVICES (80054, 83C51FB AND 83051RB+) When submitting ROM code for the 16K ROM devices, the following must be specified: 1. 16k byte user ROM data 2. 64 byte ROM encryption key 3. ROM security bits. ADDRESS CONTENT BIT(S) COMMENT Q000H to 3FFFH DATA 7:0 User ROM Data 4000H to 401FH KEY 7:0 ROM Encryption Key FFH = no encryption 4020H SEC i) ROM Security Bit 1 0 = enable security 1 = disable security 4020H SEC 1 ROM Security Bit 2 0 = enable security 1 = disable security Security Bit 1: When programmed, this bit has two effects on masked ROM parts: 1. External MOVC is disabled, and 2. EAis latched on Reset. Security Bit 2: When programmed, this bit inhibits Verify User ROM. NOTE: Security Bit 2 cannot be enabled unless Security Bit 1 is enabled. If the ROM Code file does not include the options, the following information must be included with the ROM code. For each of the following, check the appropriate box, and send to Philips along with the code: Security Bit #1: QO Enabled QO) Disabled Security Bit #2: 1 Enabled UO) Disabled Encryption: O No O Yes If Yes, must send key file. 1997 May 30 50Philips Semiconductors Preliminary specification 8-bit CMOS (low voltage, low power and high speed) microcontroller families 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ ROM CODE SUBMISSION FOR 32K ROM DEVICES (80C58, 83C51FC, AND 83C51RC+) When submitting ROM code for the 32K ROM devices, the following must be specified: 1. 32k byte user ROM data 2. 64 byte ROM encryption key 3. ROM security bits. ADDRESS CONTENT BIT(S) COMMENT Q000H to 7FFFH DATA 7:0 User ROM Data 8000H to 801FH KEY 7:0 ROM Encryption Key FFH = no encryption 8020H SEG 0 ROM Security Bit 1 0 = enable security 1 = disable security 8020H SEG 1 ROM Security Bit 2 0 = enable security 1 = disable security Security Bit 1: When programmed, this bit has two effects on masked ROM parts: 1. External MOVC is disabled, and 2. EA is latched on Reset. Security Bit 2: When programmed, this bit inhibits Verify User ROM. NOTE: Security Bit 2 cannot be enabled unless Security Bit 1 is enabled. If the ROM Code file does not include the options, the following information must be included with the ROM code. For each of the following, check the appropriate box, and send to Philips along with the code: Security Bit #1: QO Enabled Security Bit #2: 1 Enabled Encryptisquare O No 1997 May 30 D Disabled U Disabled DO Yes 51 lf Yes, must send key file.Philips Semiconductors Preliminary specification 8-bit CMOS (low voltage, low power and high speed) microcontroller families 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ ROM CODE SUBMISSION FOR 64K ROM DEVICE (8351RD+) When submitting ROM code for the 64K ROM devices, the following must be specified: 1. 64k byte user ROM data 2. 64 byte ROM encryption key 3. ROM security bits. ADDRESS CONTENT BIT(S) COMMENT 0000H to FFFFH DATA 7:0 User ROM Data 10000H to 1001FH KEY 7:0 ROM Encryption Key FFH = no encryption 108020H SEG 0 ROM Security Bit 1 0 = enable security 1 = disable security 10020H SEG 1 ROM Security Bit 2 0 = enable security 1 = disable security Security Bit 1: When programmed, this bit has two effects on masked ROM parts: 1. External MOVC is disabled, and 2. EAis latched on Reset. Security Bit 2: When programmed, this bit inhibits Verify User ROM. NOTE: Security Bit 2 cannot be enabled unless Security Bit 1 is enabled. If the ROM Code file does not include the options, the following information must be included with the ROM code. For each of the following, check the appropriate box, and send to Philips along with the code: Security Bit #1: QO Enabled QO) Disabled Security Bit #2: 1 Enabled UO) Disabled Encryption: O No O Yes If Yes, must send key file. 1997 May 30 52Philips Semiconductors 8-bit CMOS (low voltage, low power and high speed) microcontroller families DIP40: plastic dual in-line package; 40 leads (600 mil) Preliminary specification 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ $OT129-1 + seating plane 40 21 My | . . ff pin 1 index if x I si F | i A i ; i y 1 20 0 5 10mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) A A A 4 1 zi) UNIT | vax | omh. | maz b by c pM) eM e ey L Me My wolf 1.70 0.53 0.36 52.50 14.1 3.60 15.80 | 17.42 mm a7 7 O81 | 40 | 44a | 038 | 023 | 51.50] 13.7 | 254 | 741 sos | 15.24 | 15.90 | 2754 | 225 . 0.067 6.021 0.014 2.067 0.56 0.14 0.62 0.69 inches 0.19 0.020 0.16 0.045 0.015 | 0.009 2.028 054 0.16 0.60 0.12 0.60 0.63 0.01 0.089 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES VERSION PROJECTION | 'SSUEDATE IEC JEDEC ElAJd 92-44-47 $O7T129-1 051G08 MO-015AJ E =} 95-01-14 1997 May 30 53Preliminary specification 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51 FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ 40-PIN (600 mils wide) CERAMIC DUAL IN-LINE (F) PACKAGE (WITH WINDOW (FA) PACKAGE) 8-bit CMOS (low voltage, low power and high speed) microcontroller families Philips Semiconductors 0590B (roa) cog (s2z0) 010" - - (9E0) GLoo (go's 1) S690 (y SLON) (va) 0090 | asd \ (190) ozoo (orb) sg0'0 (896) Gel (Gey) GAL oO ( SLON) (eer 1) cago (g2'Gh) ozoa s}onpodd WOU dj 40} UOITe30] MOPUIM Sse]ouEq * do] ay} Woy PSMAIA LAU OF# Ul 0] asivoja0/7e1UNCS ANUIJUGS PU | # Uld UM LETS SuSqUUNU Ul * | aueld o} sejnaipuadiad ag 0] pauresjsuos SPES| SU] UIIM PSINSESLU SUCISUBLUIP eseu| * YOYELUSILU ASE O} pl] pue eu [ees ay) UC SNOSIUAW PUP UNWSAO sse|b Jo] BIUeBMO]/e apNjaul pue Apog au} uo suNyep aouauajad aye 4, puB .d, 1, 286 L-INS PLA ISNY Jed Bulouess|o} pue Ud!sualUig sasayjuazed Ul UMOYs ase SJAAUUII[I|| SSU9U] :UOISUBLUIp Bulljouju05 XW (24-9) Gez0 S L SALON @rsz0) 0100] a] 3 | 1 [|] | ANV1d ONILWAS o8d (paz) oo 0 | f \ > ae \ | / PM MM MM TT I vA yYYrvryYYywy Ww rrr aw ror ry 1. Tee | 853-0590B 06688 1997 May 30Philips Semiconductors Preliminary specification 8-bit CMOS (low voltage, low power and high speed) microcontroller families 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ PLCC44: plastic leaded chip carrier; 44 leads $OT187-2 39 2g L OO Oo = 7 Z a og EF 40] | oF q | L] 44[ N sotQt ---L---th- ge te U Y pin 1 index 1 ] c | 5 [el . | A ih ; [18 ky [| ik SS s t ty ' 7 17 T 4 detail X ~ [=v @] A + D - B Hp ==" @/ 5] 0 5 10mm scale DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) Ay Ag ay) et k, Zp) 76 UNIT) A min. Ag max. bp b, D E e ep | ec | Hp | He k max. Lp v Ww max.| max. p 4.57 0.53 | 6.81 | 16.68] 16.86 16.00 | 16.00| 17.85] 17.65] 1.22 1.44 mm | gig | O81 | 025) 305) 6551 aes | 16.51/18.51| 12" 4499/1499] 17.40] 17.40] 1.07 | O84] 10g | O78) O18) O10) 216) 216 ; 45 . 0.180 0.024 | 0.082] 0.854] 0.656 0.680 | 0.630] 0.695] 0.495 | 0.048 0.057 inches) 9 465] 0920] 0.01 | 0.12 | 'Sralc.o26 | o.650| 0.650] 99 |o.s90/ 0.590] 0.685] 0.685] 0.042] 92| 9. cag] 2-007] 0.007 | 0.004) 0.086 | 0.085 Note 1. Plastic or metal protrusions of 0.01 inches maximum per side are not included, REFERENCES VERSION PROJECTION | SUE DATE IEC JEDEC EIAJ Oe SOT187-2 112E10 MO-047AC os 95-0025 1997 May 30 55Philips Semiconductors Preliminary specification 8-bit CMOS (low voltage, low power BXCS2/54/58/80C32 t ( lage, P . 8XC51FA/FB/FC/80C51FA and high speed) microcontroller families 8XC51RA+/RB+/RC+/RD+/80C51RA+ QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2 cS Pu ae c / - aly | 7 [A] MBAABA ABA A yf = | a | co 1 Soe E He A Ag ; (Aa) o | =D [pis | UAT I le EY Do [pape pin 1 index C1 44 | O= ri i _ GUAeHTSHEE HE | ea ol! cho | Eo D [B] Hp SOE) DIMENSIONS (mm are the ariginal dimensions) A UNIT | Jax | At | 42 | As | Bp | | DM | EM) e | Hp | He] L | bp | @ v w y | Zp) ze) 0 0.25 | 1.85 0.40 | 0.25 | 10.1 | 10.4 12.9 | 12.9 0.95 | 0.85 1.2 | 1.2 | 10 mm 1219) gos] 1.65| o2a0}os} 99 | 99 | OF J aza] aaa} 4 | oss}o7s | Ot) %1 | OT | ag | oa | oe Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN VERSION IEC JEDEC ElAd PROJECTION SOTSO7-2 = 95-02-04 ISSUE DATE 1997 May 30 56