K7Q161862B-FC16 - Samsung Electronics

512Kx36 & 1Mx18 QDRTM b2 SRAM

- 1 - Rev 1.0

Mar. 2004

K7Q163662B

K7Q161862B

Document Title

512Kx36-bit, 1Mx18-bit QDRTM SRAM

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electron ics CO., LTD. reserve th e right to change th e

specifications. SAMSUNG Elect ronics will evaluate and reply to your requests an d questions on the parameters of this device. If you have any que s-

tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

Revision History

Rev. No.

0.0

1.0

Remark

Advance

Final

History

1. Initial document.

1. Final spec release

Draft Date

Jan. 27, 2004

Mar. 18, 2004

512Kx36 & 1Mx18 QDRTM b2 SRAM

- 2 - Rev 1.0

Mar. 2004

K7Q163662B

K7Q161862B

512Kx36-bit, 1Mx18-bit QDRTM SRAM

FEATURES

FUNCTIONAL BLOCK DIAGRAM

• 1.8V/2.5V +0.1V/-0.1 V Power Supply.

• I/O Supply Volt age 1.5V +0.1V/-0.1V for 1.5V I/O,

1.8V+0.1V/-0.1V for 1.8V I/O.

• Separate independent read and write data ports

with concurrent read and write operation

• HSTL I/ O.

• Full data coherency, providing most current data .

• Synchronous pipeline read with self timed early write.

• Registered address, control and data input/output.

• DDR(Double Data Rate) Interface on read and write ports.

• Fixed 2-bit burst for both read and write operation.

• Clock-stop supports to reduce current.

• Two input clocks(K and K) for accurate DDR timing at clock

rising edges only.

• Two Input clocks for output data(C and C) to minimiz e

clock-skew and flight-time mismatches.

• Single address bus.

• Byte writable function.

• Sepatate read/write control pin(R and W)

• Simple depth expansion with no data contention.

• Programmab le output impedance.

• JTAG 1149.1 compatible test access port.

• 165FBGA(11x15 ball aray FBGA) with body size of 13x15mm

ADDRESS

D(Data in)

ADD

REG

DATA

REG

CLK

GEN

CTRL

LOGIC

512Kx36

1Mx18

MEMORY

ARRAY

WRIT E DR I VER

BWX

36 (or 18)

4(or 2)

Organization Part

Number Cycle

Time Access

Time Unit

X36 K7Q163662B-FC16 6.0 2.5 ns

X18 K7Q161862B-FC16 6.0 2.5 ns

SELECT OUTPUT CONTROL

SENSE AMPS

WRITE/READ DECODE

OUTPUT REG

OUTPUT SELECT

OUTPUT DRIVER

Notes: 1. Numbers in ( ) are for x18 device.

18 (or 19)18 (or 19)

36 (or 18)

Q(Data Ou t)

QDR SRAM and Quad Data Rate comprise a new family of products developed by Cypress, Hitachi, IDT, Micron, NEC and Samsung technology.

36 (or 18) 36 (or 18)

(or 36) (or 36)

512Kx36 & 1Mx18 QDRTM b2 SRAM

- 3 - Rev 1.0

Mar. 2004

K7Q163662B

K7Q161862B

PIN CONFIGURATIONS(TOP VIEW) K7Q161862B(1Mx18)

Notes: 1. * Checked pins are reserved for higher density address

2. BW0 controls write to D0:D8 and BW1 controls write to D9:D17.

12345678910 11

ANC VSS NC W BW1KNC R SA VSS NC

BNC Q9 D9 SA NC K BW0SA NC NC Q8

CNC NC D10 VSS SA SA SA VSS NC Q7 D8

DNC D11 Q10 VSS VSS VSS VSS VSS NC NC D7

ENC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6

FNC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5

GNC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5

HNC VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ

JNC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4

KNC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3

LNC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2

MNC NC D16 VSS VSS VSS VSS VSS NC Q1 D2

NNC D17 Q16 VSS SA SA SA VSS NC NC D1

PNC NC Q17 SA SA C SA SA NC D0 Q0

RTDO TCK SA SA SA C SA SA SA TMS TDI

PIN NAME

Notes: 1. C, C, K or K cann ot be set to VREF voltage.

2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it

cannot be connected to ground or left unconnected

3. Not connected to chip pad internally.

SYMBOL PIN NUMBERS DESCRIPTION NOTE

K, K 6B, 6 A Inp u t C l o ck

C, C 6P, 6R Input Clocks for Output data 1

SA 9A,4B,8B,5C-7C,5N-7N, 4P,5P,7P,8P,3R-5R,7R-9R Address Inputs

D0-17 10P,11N,11M,10K,11J,11G,10E,11D,11C,3B,3C,2D,

3F,2G,3J,3L,3M,2N Data Inputs

Q0-17 11P,10M,11L,11K,10J,11F,11E,10C,11B,2B,3D,3E,

2F,3G,3K,2L,3N,3P Data Ou tputs

W4A Write Control

R8A Read Control

BW0, BW17B, 5A Byte Write Control Pin

VREF 2H,10H Input Reference Voltage

ZQ 11H Output Driver Impedance Control Input 2

VDD 5F,7F,5G,7G,5H,7H,5J,7J,5K,7K Power Supply ( 2.5V )

VDDQ 4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L Output Power Supply ( 1.5V or 1.8V )

VSS 2A,10A,4C,8C,4D-8D,5E-7E,

6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N Ground

TMS 10R JTAG Test Mode Select

TDI 11R JTAG Te s t Data Input

TCK 2R JTAG Test Clock

TDO 1R JTAG Test Data Output

NC 3A,7A,1B,5B,9B,10B,1C,2C,9C,1D,9D,

10D,1E,2E,9E,1F,9F,10F,1G,9G,10G,1H,1J,2J,9J,1K,

2K,9J,1L,9L,10L,1M,2M,9M,1N,9N,10N,1P,2P,9P No Connect 3

512Kx36 & 1Mx18 QDRTM b2 SRAM

- 4 - Rev 1.0

Mar. 2004

K7Q163662B

K7Q161862B

PIN CONFIGURATIONS(TOP VIEW) K7Q163662B(512Kx36)

Notes : 1. * Checked pins are reserved for higher density address

2. BW0 controls write to D0:D8, BW1 controls write to D9:D17, BW2 controls write to D18:D26 and BW3 controls w rite to D27: D35.

12345678910 11

ANC VSS NC W BW2KBW1RNC VSS NC

BQ27 Q18 D18 SA BW3KBW0SA D17 Q17 Q8

CD27 Q28 D19 VSS SA SA SA VSS D16 Q7 D8

DD28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7

EQ29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6

FQ30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5

GD30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q13 D13 D5

HNC VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ

JD31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4 D4

KQ32 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 Q3

LQ33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2

MD33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2

ND34 D26 Q25 VSS SA SA SA VSS Q10 D9 D1

PQ35 D35 Q26 SA SA C SA SA Q9 D0 Q0

RTDO TCK SA SA SA C SA SA SA TMS TDI

PIN NAME

Notes: 1. C, C, K or K cannot be set to VREF voltage.

2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it

cannot be connected to ground or left unconnected

3. Not connected to chip pad internally.

SYMBOL P IN NUMBERS DESCRIPTION NOTES

K, K 6B, 6A Input Clock

C, C 6P, 6R Input Clocks for Output data 1

SA 4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R Address Inputs

D0-35 10P,11N,11M,10K,11J,11G,10E,11D,11C,10N,9M,9L

9J,10G,9F,10D,9C,9B,3B,3C,2D,3F,2G,3J,3L,3M,2N

1C,1D,2E,1G,1J,2K,1M,1N,2P Data Inputs

Q0-35 11P,10M,11L,11K,10J,11F,11E,10C,11B,9P,9N,10L

9K,9G,10F,9E,9D,10B,2B,3D,3E,2F,3G,3K,2L,3N

3P,1B,2C,1E,1F,2J,1K,1L,2M,1P Data Outputs

W4A Write Control Pin

R8A Read Control Pin

BW0,BW1,BW2,BW37B,7A,5A,5B Byte Write Control Pin

VREF 2H,10H Input Reference Voltage

ZQ 11H Output Driver Impedance Control Input 2

VDD 5F,7F,5G,7G,5H,7H,5J,7J,5K,7K Power Supply ( 2.5V )

VDDQ 4E,8E,4F,8F,4G, 8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L Output Power Supply ( 1.5V or 1.8V )

VSS 2A,10A,4C,8C,4D-8D,5E-7E,

6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N Ground

TMS 10R JTAG Test Mode Select

TDI 11R JTAG Test Data Input

TCK 2R JTAG Test Clock

TDO 1R JTAG Test Data Output

NC 3A,9A,1H No Connect 3

512Kx36 & 1Mx18 QDRTM b2 SRAM

- 5 - Rev 1.0

Mar. 2004

K7Q163662B

K7Q161862B

The K7Q163662B and K7Q161862B are 18,874,368-bits QDR(Quad Data Rate) Synchronous Pipelined Burst SRAM s.

They are organized as 524,288 words by 36bits for K7Q163662B and 1,048,576 words by 18 bits for K7Q161862B.

The QDR operation is possible by supporting DDR read and write operations through separate data output and input ports

with the same cycle. Memory bandwidth is maxmized as data can be transfered into sram

on every rising edge of K and K, and transfered out of sram on every rising edge of C and C.

And totally independent read and write ports eliminate the need for high speed bus turn around.

Address, data inputs, and all control signals are synchronized to the input clock ( K or K ).

Normally data outputs are synchronized to output clocks ( C and C ), but when C and C are tied high,

the data outputs are synchronized to the input clocks ( K and K ).

Read address is registered on rising edges of the input K clocks, and write address is

registered on rising edges of the input K clocks.

Common address bus is used to access address both for read and write operations.

The internal burst counter is fiexd to 2-bit sequential for both read and write operations.

Synchronous pipeline read and early write enable high speed operations.

Simple depth expansion is accomplished by using R and W for port selection.

Byte write operation is supported with BW0 and BW1 ( BW2 and BW3 ) pins.

IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoriing package pads attachment status with system.

The K7Q163662B and K7Q161862B are implemented with SAMSUNG's high performance 6T CMOS technology and is available

in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.

GENERAL DESCRIPTION

Read Operations

Read cycles are initiated by activating R at the rising edge of the positive input clock K.

Address is presented and stored in the read address register synchronized with K clock.

For 2-bit burst DDR operation, it will access two 36-bit or 18-bit data words with each read command.

The first pipelined data is transfered out of the device triggered by C clock following next K clock rising edge.

Next burst data is triggered by the rising edge of following C clock rising edge.

Continuous read operations are initiated with K clock rising edge.

And pipelined data are transferred out of device on every rising edge of both C and C clocks.

In case C and C tied to high, output data are triggered by K and K instead of C and C.

When the R is disabled after a read operation, the K7Q163662B and K7Q161862B will first complete burst read operation

before entering into deselect mode at the next K clock rising edge.

Then output drivers disabled automatically to high impedance state.

512Kx36 & 1Mx18 QDRTM b2 SRAM

- 6 - Rev 1.0

Mar. 2004

K7Q163662B

K7Q161862B

Write cycles are initiated by activating W at the rising edge of the positive input clock K.

Address is presented and stored in the write address register synchronized with following K clock.

For 2-bit burst DDR operation, it will write two 36-bit or 18-bit data words with each write command.

The first "early" data is transfered and registered in to the device synchronous with same K clock rising edge with W presented.

Next burst data is transfered and registered synchronous with following K clock rising edge.

Continuous write operations are initiated with K rising edge.

And "early writed" dat a is presented to the device on every rising edge of both K and K clocks.

When the W is disabled, the K7Q163662B and K7Q161862B will enter into deselect mode.

The device disregards input data presented on the same cycle W disabled.

The K7Q163662B and K7Q161862B support byte write operations.

With activating BW0 or BW1 ( BW2 or BW3 ) in write cycle, only one byte of input data is presented.

In K7Q161862B, BW0 controls write operation to D0:D8, BW1 controls write operation to D9:D17.

And in K7Q163662B BW2 controls write operation to D18:D26, BW3 controls write operation to D27:D35.

Write Operations

Programmable Impedance Output Buffer Operation

Single Clock Mode

Depth Expansion

The designer can program the SRAM's output buffer impedance by terminating the ZQ pin to VSS through a precision resistor(RQ).

The value of RQ (within 15%) is five times the output impedance desired.

For example, 250Ω resistor will give an output impedance of 50Ω.

Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles.

In all cases impedance updates are transparent to the user and do not produce access time "push-outs"

or other anomalous behavior in the SRAM.

There are no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up,

the SRAM needs 1024 non-read cycles.

The K7Q163662B and K7Q161862B can be used with the single clock pair K and K.

In this mode, C and C must be tied high during power up and this single clock pair control both the input and output registers.

C and C cannot be tied high during operation.

System flight time and clock skew could not be compensated in single clock mode.

Separate input and output ports enables easy depth expansion.

Each port can be selected and deselected independently

and read and write operation do not affect each other.

Before chip deselected, all read and write pending operations are completed.

512Kx36 & 1Mx18 QDRTM b2 SRAM

- 7 - Rev 1.0

Mar. 2004

K7Q163662B

K7Q161862B

READ

DDR READ DDR WRITE

READ NOP

POWER-UP

WRITE NOP

LOAD NEW

WRITE ADDRESS

LOAD NEW

READ ADDRESS

ALWAYS

(FIXED)

WRITE

STATE DIAGRAM

Notes: 1. Internal burst counter is fixed as 2-bit linear, i.e. when first address is A0+0, next internal burst address is A0+1.

2. "READ" refers to read active status with R=Low, "READ" refers to read inactive status with R=high. "WRITE" and "WRITE" are t h e sa me ca s e .

3. Read and write state machine can be active simultaneously.

4. State machine control timing sequence is controlled by K.

ALWAYS

(FIXED)

READ WRITE

512Kx36 & 1Mx18 QDRTM b2 SRAM

- 8 - Rev 1.0

Mar. 2004

K7Q163662B

K7Q161862B

TRUTH TABLES

SYNCHRONOUS TRUTH TABLE

Notes: 1. X means "Don′t Care".

2. The rising edge of clock is symbolized by ( ↑ ).

3. Before enter into clock stop status, all pending read and write operations will be completed.

K R W D Q OPERATION

D(A0) D(A1) Q(A0) Q(A1)

Stopped X X Previous state Previous state Previous state Previous state Clock S top

↑H H X X High-Z High-Z No Operation

↑LX X X D

OUT at C(t+1) DOUT at C(t+1) Read

↑X L Din at K(t) Din at K(t) X X Write

WRITE TRUTH TABLE(x18)

Notes: 1. X means "Don′t Care".

2. All inputs in this table must meet setup and hold time around the rising edge of CLK( ↑ ).

K K W BW0BW1OPERATION

↑H X X READ/NOP

↑L L L WRITE ALL BYTEs ( K↑ )

↑LLH WRITE BYTE 0 ( K↑ )

↑LLH WRITE BYTE 0 ( K

↑ )

↑LHL WRITE BYTE 1 ( K↑ )

↑LHL WRITE BYTE 1 ( K

↑ )

↑L H H WRITE NOTHING ( K↑ )

WRITE TRUTH TABLE(x36)

Notes: 1. X means "Don′t Care".

2. All inputs in this table must meet setup and hold time around the rising edge of CLK( ↑ ).

K K W BW0BW1BW2BW3OPERATION

↑HXXXX READ/NOP

↑LLLLL WRITE ALL BYTEs ( K↑ )

↑LLLLL WRITE ALL BYTEs ( K

↑ )

↑LLHHH WRITE BYTE 0 ( K↑ )

↑LLHHH WRITE BYTE 0 ( K

↑ )

↑LHLHH WRITE BYTE 1 ( K↑ )

↑LHLHH WRITE BYTE 1 ( K

↑ )

↑L H H L L WRITE BYTE 2 and BYTE 3 ( K↑ )

↑LHHHH WRITE NOTHING ( K↑ )

↑LHHHH WRITE NOTHING ( K

↑ )

512Kx36 & 1Mx18 QDRTM b2 SRAM

- 9 - Rev 1.0

Mar. 2004

K7Q163662B

K7Q161862B

DC ELECTRICAL CHARACTERISTICS

Notes: 1. Minimum cycle. IOUT=0mA.

2. |IOH|=(VDDQ/2)/(RQ/5)±15% @V OH=VDDQ/2 for 175Ω ≤ RQ ≤ 350Ω.

3. |IOL|=(VDDQ/2)/(RQ/5)±15% @VOL=VDDQ/2 fo r 175Ω ≤ RQ ≤ 350Ω.

4. Minimum Impedance Mode when ZQ pin is connected to VDD.

5. Operating current is calculated with 50% read cycles and 50% write cycles.

6. Standby Current is only after all pending read and write burst opeactions are completed.

7. Programmable Impedance Mode.

8. These are DC test criteria. DC design criteria is VREF±50mV. The AC V IH/VIL levels are defined separately for measuring

timing parameters.

9. VIL (Mi n )DC =-0.3V, VIL (Min)AC=-1.5V(pulse width ≤ 3ns).

10. VIH (Max)DC =VDDQ+0.3, VIH (Max)AC=VDDQ+0.85V(pulse width ≤ 3ns).

PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNIT NOTES

Input Leakage Current IIL VDD=Max ; VIN=VSS to VDDQ -2 +2 µA

Output Leakage Current IOL Output Disabled, -2 +2 µA

Operating Current (x18) : DDR ICC VDD=Max , IOUT=0mA

Cycle T ime ≥ tKHKH Min -16 - 400 mA 1,5

Operating Current (x36) : DDR ICC VDD=Max , IOUT=0mA

Cycle T ime ≥ tKHKH Min -16 - 500 mA 1,5

Standby Current(NOP) : DDR ISB1

Device deselected, IOUT=0mA,

f=Max,

All Inputs≤0.2V or ≥ VDD-0.2V -16 - 240 mA 1,6

Output High Voltage VOH1 VDDQ/2 VDDQ V2,7

Output Low Voltage VOL1 VSS VDDQ/2 V 3,7

Output High Voltage VOH2 IOH=-1.0mA VDDQ-0.2 VDDQ V4

Output Low Voltage VOL2 IOL=1.0mA VSS 0.2 V 4

Input Low Voltage VIL -0.3 VREF-0.1 V 8,9

Input High Voltage VIH VREF+0.1 VDDQ+0.3 V 8,10

ABSOLUTE MAXIMUM RATINGS*

*Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating

only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification

is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. VDDQ must not exceed VDD during normal op eration.

PARAMETER SYMBOL RATING UNIT

Voltage on VDD Supply Relative to VSS VDD -0.5 to 3.6 V

Voltage on VDDQ Supply Relative to VSS VDDQ -0.5 to VDD V

Voltage on Input Pin Relative to VSS VIN -0.5 to VDD+0.3 V

Storage Temperature TSTG -65 to 150 °C

Operating Temperatur e TOPR 0 to 70 °C

Storage Temperature Range Under Bias TBIAS -10 to 85 °C

512Kx36 & 1Mx18 QDRTM b2 SRAM

- 10 - Rev 1.0

Mar. 2004

K7Q163662B

K7Q161862B

AC TIMING CHARACTERISTICS

Notes: 1. All address inputs must meet the specified setup and hold times for all latching clock edges.

2. Control signals are R, W,BW0,BW1 and (BW2, BW3, also for x36)

3. If C,C are tied high, K ,K become the references for C,C timing parameters.

4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ.

The specs as shown do not imply bus contention beacuse tCHQX1 is a MIN parameter that is worst case at totally different test conditions

(0°C, 2.6V) than tCHQZ, which i s a MAX parameter( worst case at 70°C, 2.4V)

It is not possible for two SRAMs on the same board to be at such different voltage and temperature.

PARAMETER SYMBOL -16 UNITS NOTES

MIN MAX

Clock

Clock Cycle Time(K, K, C, C)tKHKH 6.0 ns

Clock HIGH time (K, K, C, C)tKHKL 2.4 ns

Cloc k Low time ( K, K, C, C)tKLKH 2.4 ns

Clock to clock (K↑ → K↑, C↑ → C↑)tKHKH2.7 3.3 ns

Clock to data clock (K↑ → C↑, K↑→ C↑)tKHCH 0.0 2.0 ns

Output Times

C, C High to Output Valid tCHQV 2.5 ns 3

C, C High to Output Hold tCHQX 1.2 ns 3

C High to Output High-Z tCHQZ 2.5 ns 3

C High to Output Low-Z tCHQX1 1.2 ns 3

Setup Times

Address valid to K rising edge tAVKH 0.7 ns

Control inputs valid to K rising edge tIVKH 0.7 ns 2

Data-in valid to K, K rising edge tDVKH 0.7 ns

Hold Times

K rising edge to address hold tKHAX 0.7 v

K rising edge to control inputs hold tKHIX 0.7 ns

K, K rising edge to data-in hold tKHDX 0.7 ns

RECOMMENDED DC OPERATING CONDITIONS (0°C ≤ TA ≤ 70°C)

PARAMETER SYMBOL MIN TYP MAX UNIT

Supply Voltage VDD 1.7 2.5 2.6 V

VDDQ 1.4 1.5 1.9 V

Reference Voltage VREF 0.68 0.75 0.95 V

Ground VSS 000V

VDDQ

VIL

VDDQ+0.7V 20% tKHKH(MIN)

VSS

VIH

VSS-0.7V 20% tKHKH(MIN)

Undershoot TimingOverershoot Timing

VDDQ+0.35V

VSS-0.35V

512Kx36 & 1Mx18 QDRTM b2 SRAM

- 11 - Rev 1.0

Mar. 2004

K7Q163662B

K7Q161862B

APPLICATION INFORMATION

PIN CAPACITANCE

Note: 1. Parameters are tested with RQ=250Ω and VDDQ=1.5V.

2. Periodically sampled and not 100% tested.

PRMETER SYMBOL TESTCONDITION TYP MAX Unit NOTES

Address Control Input Capacitance CIN VIN=0V 4 5 pF

Input and Output Capacitance COUT VOUT=0V 6 7 pF

Clock Capacitance CCLK -56pF

1Mx18

SRAM#1

D0-17

SA RWBW0Q0-17

SRAM#4

R=50Ω Vt=VREF

R=250ΩR=250Ω

BW1KD0-17

SA RWBW0Q0-17

CCBW1K

Data In

Data Out

Address

BW0-7

Return CLK

Source CLK

Return CLK

Source CLK

MEMORY

CONTROLLER

VDDQ/2

50Ω

SRAM Zo=50Ω

0.75V

VREF

ZQ 250Ω

AC TEST OUTPUT LOAD

AC TEST CONDITIONS

Note: Parameters are tested with RQ=250Ω

Parameter Symbol Value Unit

Core Power Supply Voltage VDD 1.7~2.6 V

Output Power Supply Voltage VDDQ 1.4~1.9 V

Input High/Low Level VIH/VIL 1.25/0.25 V

Input Reference Level VREF 0.75 V

Input Rise/Fall Time TR/TF0.3/0.3 ns

Output Timing Reference Level VDDQ/2 V

512Kx36 & 1Mx18 QDRTM b2 SRAM

- 12 - Rev 1.0

Mar. 2004

K7Q163662B

K7Q161862B

Q1-1 Q1-2 Q2-1 Q2-2 Q3-1 Q3-2

tKLKH

tKHKH

tKHKL

tAVKH tKHAX

tIVKH tKHIX

tCHQX1

tKHCH

tCHQV

tCHQX

Q(Da ta Out)

Note: 1. Q1-1 refers to output from address A1+0, Q1-2 refers to output from address A1+1 i.e. the next internal burst address following A1+0.

2. Outputs are disabled(High-Z) one cycle after a NOP.

A1 A2 A3

TIMING WAVE FORMS OF READ AND NOP

Don′t Care Undefined

tCHQZ

D1-1 D1-2 D2-1 D2-2 D3-1 D3-2

D(Data In)

tKLKH

tKHKH

tKHKL

tAVKH tKHAX

tIVKH

tKHIX

A1 A2 A3

tDVKH tKHDX

tKHIX

TIMING WAVE FORMS OF WRITE AND NOP

READ READ NOP READ

WRITE WRITE NOP WRITE NOP

512Kx36 & 1Mx18 QDRTM b2 SRAM

- 13 - Rev 1.0

Mar. 2004

K7Q163662B

K7Q161862B

Q1-1 Q1-2 Q3-1 Q3-2 Q5-1 Q5-2

TIMING WAVE FORMS OF READ, WRITE AND NOP

D(Data In)

Q(Data Out)

A1 A2 A3 A4 A5 A6 A7

D2-1 D2-2 D4-1 D4-2 D7-1 D7-2D6-1 D6-2

Don′t Care Undefined

Note: 1. Q1-1 refers to output from address A1+0, Q1-2 refers to output from address A1+1 i.e. the next internal burst address following A1+0.

2. Outputs are disabled(High-Z) one cycle after a NOP.

3. If address A1=A2, data Q1-1=D2-1, data Q1-2=D2-2. Write data is forwarded immediately as read results.

4. BWx are assumed active.

READ WRITE NOP WRITEREAD WRITE READ WRITE

512Kx36 & 1Mx18 QDRTM b2 SRAM

- 14 - Rev 1.0

Mar. 2004

K7Q163662B

K7Q161862B

IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG

This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan

circuitry when in test mode. This is to suppor t connectivity testing dur ing manufacturing and system diagnostics. I nternal data is not

driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Reg-

ister, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up,

therefore, TRST signal is not required. It is possible to use t his device without utilizing the TAP. To disab le the TAP controller without

interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an

undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be

tied to V DD through a resistor. TDO should be left unconnected.

TAP Controller State Diagram

Test Logic Reset

Run Test Idle

011

Select DR

Capture DR

Shift DR

Exit1 DR

Pause DR

Exit2 DR

Update DR

Select IR

Capture IR

Shift IR

Exit1 IR

Pause IR

Exit2 IR

Update IR

JTAG Block Diagram JTAG Instruction Coding

NOTE :

1. Places DQs in Hi-Z in order to sample all input data regardless of other

SRAM inputs. This instruction is not IEEE 1149.1 compliant.

2. Places DQs in Hi-Z in order to sample all input data regardless of other

SRAM inputs.

3. TDI is sampled a s an input to the firs t ID reg i ster to allow for th e ser ial shift

of the external TDI data.

4. Bypass register is initiated to VSS when BYPASS instruction is invoked. The

Bypass Register also holds serially loaded T DI when exiting the Shift D R

states.

5. SAMPLE instruction dose not places DQs in Hi-Z.

6. This instruction is reserved for future use.

IR2 IR1 IR0 Instruction TDO Output Notes

0 0 0 EXTEST Boundary Scan Register 1

0 0 1 IDCODE Identification Register 3

0 1 0 SAMPLE-Z Boundary Scan Register 2

0 1 1 RESERV ED Do Not Use 6

1 0 0 SAMPLE Boundary Scan Register 5

1 0 1 RESERV ED Do Not Use 6

1 1 0 RESERV ED Do Not Use 6

1 1 1 BYPASS Bypass Register 4

SRAM

CORE

BYPASS Reg.

Identification Reg.

Instruction Reg.

Control Signals

TAP Controller

TDO

TDI

TMS

TCK

K,K

C,C

A,D

512Kx36 & 1Mx18 QDRTM b2 SRAM

- 15 - Rev 1.0

Mar. 2004

K7Q163662B

K7Q161862B

ID REGISTER DEFINITION

Note : Part C onfiguration

/def=001 for 16Mb, /wx=11 for x36, 10 for x18.

/t=Don’t Care. /q=1 for QDR, 0 for DDR /b=1 for 4Bit Burst, 0 for 2Bit Burst /s=1 for Separate I/O, 0 for Common I/O

Part Revision Number

(31:29) Part Configuration

(28:12) Samsung JEDEC Code

(11: 1) Start Bit(0)

512Kx36 000 00def0wx0t0q0b0s0 00001001110 1

1Mx18 000 00def0wx0t0q0b0s0 00001001110 1

SCAN REGISTER DEFINITION

Part In str uction Register Bypass Register ID Register Boundar y Scan

512Kx36 3 bits 1 bit 32 bits 107 bits

1Mx18 3 bits 1 bit 32 bits 107 bits

Note: 1. NC pins are read as "X" ( i.e. don′t care.)

ORDER PIN ID

37 10D

38 9E

39 10C

40 11D

41 9C

42 9D

43 11B

44 11C

45 9B

46 10B

47 11A

48 Internal

49 9A

50 8B

51 7C

52 6C

53 8A

54 7A

55 7B

56 6B

57 6A

58 5B

59 5A

60 4A

61 5C

62 4B

63 3A

64 1H

65 1A

66 2B

67 3B

68 1C

69 1B

70 3D

71 3C

72 1D

ORDER PIN ID

73 2C

74 3E

75 2D

76 2E

77 1E

78 2F

79 3F

80 1G

81 1F

82 3G

83 2G

84 1J

85 2J

86 3K

87 3J

88 2K

89 1K

90 2L

91 3L

92 1M

93 1L

94 3N

95 3M

96 1N

97 2M

98 3P

99 2N

100 2P

101 1P

102 3R

103 4R

104 4P

105 5P

106 5N

107 5R

ORDER PIN ID

16R

26P

36N

47P

57N

67R

78R

88P

99R

10 11P

11 10P

12 10N

13 9P

14 10M

15 11N

16 9M

17 9N

18 11L

19 11M

20 9L

21 10L

22 11K

23 10K

24 9J

25 9K

26 10J

27 11J

28 11H

29 10G

30 9G

31 11F

32 11G

33 9F

34 10F

35 11E

36 10E

BOUNDARY SCAN EXIT ORDER

512Kx36 & 1Mx18 QDRTM b2 SRAM

- 16 - Rev 1.0

Mar. 2004

K7Q163662B

K7Q161862B

JTAG DC OPERATING CONDITIONS

Note: 1. The input level of SRAM pin is to follow the SRAM DC specification.

Parameter Symbol Min Typ Max Unit Note

Power Supply Voltage VDD 1.7 2.5 2.6 V

Input High Level VIH 0.7*VDD -VDD+0.3 V

Input Low Level VIL -0.3 - 0.3*VDD V

Output High Voltage(IOH=-2mA) VOH 0.75*VDD -VDD V

Output Low Voltage(IOL=2mA) VOL VSS - 0.25*VDD V

JTAG TIMING DIAGRAM

JTAG AC Characteristics

Parameter Symbol Min Max Unit Note

TCK Cycle Time tCHCH 50 - ns

TCK Hig h Pulse Width tCHCL 20 - ns

TCK Low Pulse Width tCLCH 20 - ns

TMS Input Setup Time tMVCH 5-ns

TMS Input Hold Time tCHMX 5-ns

TDI Input Setup Time tDVCH 5-ns

TDI Input Hold Time tCHDX 5-ns

SRAM Input Setup Time tSVCH 5-ns

SRAM Input Hold Tim e tCHSX 5-ns

Clock Low to Output Valid tCLQV 010ns

JTAG AC TEST CONDITIONS

Note: 1. See SRAM AC test output load on page 11.

Parameter Symbol Min Unit Note

Input High/Low Level VIH/VIL VDD/0.0 V

Input Rise/Fall Time TR/TF 1.0/1.0 ns

Input and Output Timing Reference Level VDD/2 V 1

TCK

TMS

TDI

tCHCH

tMVCH tCHMX

tCHCL tCLCH

tDVCH tCHDX

tCLQV

TDO

(SRAM)

tSVCH tCHSX

512Kx36 & 1Mx18 QDRTM b2 SRAM

- 17 - Rev 1.0

Mar. 2004

K7Q163662B

K7Q161862B

165 FBGA PACKAGE DIMENSIONS

Side View

13mm x 15mm Body, 1.0mm Bump Pitch, 11x15 Ball Array

Bottom View

Top Vi e w

Symbol Value Units Note Symbol Value Units Note

A13 ± 0.1 mm E1.0 mm

B15 ± 0.1 mm F14.0 mm

C1.3 ± 0.1 mm G10.0 mm

D0.35 ± 0.05 mm H0.5 ± 0.05 mm

∅ H