DS07-13701-8E
FUJITSU SEMICONDUCTOR
DATA SHEET
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90570 Series
MB90573/574/574C/F574/F574A/V570/V570A
■
■■
■DESCRIPTION
The MB90570 series is a general-purpose 16-bit microcontroller developed and designed by Fujitsu for process
control applications in consumer products that require high-speed real time processing. It contains an I2C*2 bus
interface that allows inter-equipment communication to be implemented readily. This product is well adapted to
car audio equipment, VTR systems, and other equipment and systems.
The instruction set of F2MC-16LX CPU core inher its AT architecture of F2MC*1 family with additional instr uction
sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and en-
hanced bit manipulation instructions. The microcontroller has a 32-bit accumulator f or processing long word data.
The MB90570 series has peripher al resources of an 8/10-bit A/D con verter, an 8-bit D/A converter, UART (SCI),
an e xtended I/O serial interface , an 8/16-bit up/down counter/timer, an 8/16-bit PPG timer , I/O timer (a 16-bit free
run timer, an input capture (ICU), an output compare (OCU)).
*1:F2MC stands for FUJITSU Flexible Microcontroller.
*2:Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use these
components in an I2C system, provided that the system conforms to the I2C Standard Specification as
defined by Philips.
■
■■
■PACKAGE
120-pin plastic LQFP
(FPT-120P-M05) (FPT-120P-M13)
120-pin plastic QFP 120-pin plastic LQFP
(FPT-120P-M21)
MB90570 Series
2
■
■■
■FEATURES
•Clock
Embedded PLL clock multiplication circuit
Operating clock (PLL clock) can be selected from 1/2 to 4× oscillation (at oscillation of 4 MHz, 4 MHz to 16 MHz).
Minimum instruction e xecution time: 62.5 ns (at oscillation of 4 MHz, 4× PLL clock, operation at VCC of 5.0 V)
• Maximum memory space
16 Mbytes
• Instruction set optimized for controller applications
Rich data types (bit, byte, word, long word)
Rich addressing mode (23 types)
Enhanced signed multiplication/division instruction and RETI instruction functions
Enhanced precision calculation realized by the 32-bit accumulator
• Instruction set designed for high level language (C) and multi-task operations
Adoption of system stack pointer
Enhanced pointer indirect instructions
Barrel shift instructions
• Progr am patch function (for two address pointers)
• Enhanced execution speed
4-byte instruction queue
• Enhanced interrupt function
8 levels, 34 factors
• Automatic data transmission function independent of CPU operation
Extended intelligent I/O service function (EI2OS): Up to 16 channels
• Embedded ROM size and types
Mask ROM: 128 kbytes/256 kbytes
Flash ROM: 256 kbytes
Embedded RAM size:6 kbytes/10 kbytes (mask ROM)
10 kbytes (flash memory)
10 kbytes (evaluation device)
• Low-power consumption (standby) mode
Sleep mode (mode in which CPU operating clock is stopped)
Stop mode (mode in which oscillation is stopped)
CPU intermittent operation mode
Hardware standby mode
•Process
CMOS technology
• I/O port
General-pur pose I/O ports (CMOS): 63 ports
General-purpose I/O ports (with pull-up resistors): 24 ports
General-purpose I/O ports (open-drain): 10 ports
Total: 97 ports
•Timer
Timebase timer/watchdog timer: 1 channel
8/16-bit PPG timer: 8-bit × 2 channels or 16-bit × 1 channel
• 8/16-bit up/down counter/timer: 1 channel (8-bit × 2 channels)
(Continued)
MB90570 Series
3
(Continued)
• 16-bit I/O timer
16-bit free run timer: 1 channel
Input capture (ICU): Generates an interrupt request by latching a 16-bit free run timer counter v alue upon
detection of an edge input to the pin.
Output compare (OCU):Generates an interrupt request and reverse the output level upon detection of a match
between the 16-bit free run timer counter value and the compare setting value.
• Extended I/O serial interface: 3 channels
•I
2C interface (1 channel)
Serial I/O port for supporting Inter IC BUS
• UART0 (SCI), UART1 (SCI)
With full-duplex double buffer
Clock asynchronized or clock synchronized transmission can be selectively used.
• DTP/external interrupt circuit (8 channels)
A module for starting extended intelligent I/O service (EI2OS) and generating an exter nal interr upt tr iggered
by an external input.
• Delayed interrupt generation module
Generates an interrupt request for switching tasks.
• 8/10-bit A/D converter (8 channels)
8/10-bit resolution
Starting by an external trigger input.
Conversion time: 26.3 µs
• 8-bit D/A converter (based on the R-2R system)
8-bit resolution: 2 channels (independent)
Setup time: 12.5 µs
• Clock timer: 1 channel
• Chip select output (8 channels)
An active level can be set.
• Clock output function
MB90570 Series
4
■
■■
■PRODUCT LINEUP
(Continued)
Part number
Item MB90573 MB90574/C MB90F574/A MB90V570/A
Classification Mask ROM products Flash ROM products Evaluation product
ROM size 128 kbytes 256 kbytes None
RAM size 6 kbytes 10 kbytes
CPU functions
The number of instructions: 340
Instruction bit length: 8 bits, 16 bits
Instruction length: 1 byte to 7 bytes
Data bit length: 1 bit, 8 bits, 16 bits
Minimum execution time: 62.5 ns (at machine clock of 16 MHz)
Interrupt processing time: 1.5 µs (at machine clock of 16 MHz, minimum value)
Ports
General-purpose I/O ports (CMOS output): 63
General-purpose I/O ports (with pull-up resistor): 24
General-purpose I/O ports (N-ch open-drain output): 10
Total: 97
UART0 (SCI), UART1 (SCI)
Clock synchronized transmission (62.5 kbps to 1 Mbps)
Clock asynchronized transmission (1202 bps to 9615 bps)
Transmission can be performed by bi-directional serial transmission or by
master/slave connection.
8/10-bit A/D converter
Resolution: 8/10-bit
Number of inputs: 8
One-shot conversion mode (converts selected channel only once)
Scan conversion mode (converts two or more successive channels and can
program up to 8 channels.)
Continuous conversion mode (converts selected channel continuously)
Stop conversion mode (converts selected channel and stop operation repeatedly)
8/16-bit PPG timer
Number of channels: 1 (or 8-bit × 2 channels)
PPG operation of 8-bit or 16-bit
A pulse wave of given intervals and given duty ratios can be output.
Pulse interval: 62.5 ns to 1 µs (at oscillation of 4 MHz, machine clock of 16 MHz)
8/16-bit up/down counter/
timer
Number of channels: 1 (or 8-bit × 2 channels)
Event input: 6 channels
8-bit up/down counter/timer used: 2 channels
8-bit re-load/compare function supported: 1 channel
16-bit
I/O timer
16-bit
free run timer Number of channel: 1
Overflow interrupts
Output
compare
(OCU)
Number of channels: 4
Pin input factor: A match signal of compare register
Input
capture
(ICU)
Number of channels: 2
Rewriting a register value upon a pin input (rising, falling, or both edges)
MB90570 Series
5
(Continued)
* : Varies with conditions such as the operating frequency. (See section “■ ELECTRICAL CHARACTERISTICS.”)
Assurance for the MB90V570/A is given only for operation with a tool at a power voltage of 4.5 V to 5.5 V, an
operating temperature of 0 °C to +25 °C, and an operating frequency of 1 MHz to 16 MHz.
■
■■
■PACKAGE AND CORRESPONDING PRODUCTS
: Available ×: Not available
Note : For more information about each package, see section “■ PACKAGE DIMENSIONS.”
Part number
Item MB90573 MB90574/C MB90F574/A MB90V570/A
DTP/external interrupt
circuit
Number of inputs: 8
Started by a rising edge, a falling edge, an “H” level input, or an “L” level input.
External interrupt circuit or extended intelligent I/O service (EI2OS) can be used.
Delayed interrupt
generation module An interrupt generation module for switching tasks used in real time operating
systems.
Extended I/O serial interface Clock synchronized transmission (3125 bps to 1 Mbps)
LSB first/MSB first
I2C interface Serial I/O port for supporting Inter IC BUS
Timebase timer 18-bit counter
Interrupt interval: 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms
(at oscillation of 4 MHz)
8-bit D/A converter 8-bit resolution
Number of channels: 2 channels
Based on the R-2R system
Watchdog timer Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms
(at oscillation of 4 MHz, minimum value)
Low-power consumption
(standby) mode Sleep/stop/CPU intermittent operation/clock timer/hardware standby
Process CMOS
Power supply voltage for
operation* 4.5 V to 5.5 V
Package MB90573 MB90574 MB90F574/A MB90574C
FPT-120P-M05 ×
FPT-120P-M13
FPT-120P-M21 × ×
MB90570 Series
6
■
■■
■DIFFERENCES AMONG PRODUCTS
Memory Size
In evaluation with an evaluation product, note the difference between the evaluation product and the product
actually used. The following items must be taken into consideration.
• The MB90V570/A does not have an inter nal ROM, however, operations equivalent to chips with an inter nal
R OM can be evaluated by using a dedicated de velopment tool, enabling selection of ROM size by settings of
the development tool.
• In the MB90V570/A, images from FF4000H to FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH to
mapped to bank FE and FF only. (This setting can be changed by configuring the development tool.)
• In the MB90F574/574/573/F574A/574C, images from FF4000H to FFFFFFH are mapped to bank 00, and
FF0000H to FF3FFFH to bank FF only.
• The products designated with /A or /C are diff erent from those without /A or /C in that they are DTP/e xternally-
interrupted types which return from standby mode at the ch.0 to ch.1 edge request.
MB90570 Series
7
■
■■
■PIN ASSIGNMENT
P30/ALE
VSS
P27/A23
P26/A22
P25/A21
P24/A20
P23/A19
P22/A18
P21/A17
P20/A16
P17/AD15
P16/AD14
P15/AD13
P14/AD12
P13/AD11
P12/AD10
P11/AD09
P10/AD08
P07/AD07
P06/AD06
P05/AD05
P04/AD04
P03/AD03
P02/AD02
P01/AD01
P00/AD00
VCC
X1
X0
VSS
P66/OUT2
P67/OUT3
VSS
C
P70
P71
P72
DVCC
DVSS
P73/DA0
P74/DA1
AVCC
AVRH
AVRL
AVSS
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
P86/AN6
P87/AN7
VCC
P90/CS0
P91/CS1
P92/CS2
P93/CS3
P94/CS4
P95/CS5
(Top view)
(FPT-120P-M05)
(FPT-120P-M13)
(FPT-120P-M21)
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
P31/RD
P32/WRL
P33/WRH
P34/HRQ
P35/HAK
P36/RDY
P37/CLK
VCC
P40/SIN0
P41/SOT0
P42/SCK0
P43/SIN1
P44/SOT1
P45/SCK1
P46/PPG0
P47/PPG1
P50/SIN2
P51/SOT2
P52/SCK2
P53/SIN3
P54/SOT3
P55/SCK3
P56/IN0
P57/IN1
P60/SIN4
P61/SOT4
P62/SCK4
P63/CKOT
P64/OUT0
P65/OUT1
RST
MD0
MD1
MD2
HST
PC3
PC2
PC1
PC0
PB7
PB6/ADTG
PB5/IRQ5
PB4/IRQ4
PB3/IRQ3
PB2/IRQ2
PB1/IRQ1
X0A
X1A
PB0/IRQ0
PA7/SCL
PA6/SDA
PA5/ZIN1
PA4/BIN1
PA3/AIN1/IRQ7
PA2/ZIN0
PA1/BIN0
PA0/AIN0/IRQ6
VSS
P97/CS7
P96/CS6
MB90570 Series
8
■
■■
■PIN DESCRIPTION
(Continued)
*1 : FPT-120P-M05
*2 : FPT-120P-M13, FPT-120P-M21
Pin no. Pin name Circuit
type Function
LQFP-120 *1
QFP-120 *2
92,93 X0,X1 A High speed oscillator pins
74,73 X0A,X1A B Low speed oscillator pins
89 to 87 MD0 to MD2 C These are input pins used to designate the operating mode. They
should be connected directly to Vcc or Vss.
90 RST C Reset input pin
86 HST C Hardware standby input pin
95 to 102 P00 to P07 D
In single chip mode, these are general purpose I/O pins. When set for
input, they can be set by the pull-up resistance setting register
(RDR0). When set for output, this setting will be invalid.
AD00 toAD07 In external bus mode, these pins function as address low output/data
low I/O pins.
103 to 110 P10 to P17 D
In single chip mode, these are general purpose I/O pins. When set for
input, they can be set by the pull-up resistance setting register
(RDR1). When set for output, the setting will be invalid.
AD08 toAD15 In external bus mode, these pins function as address middle output/
data high I/O pins.
111 to 118 P20 to P27 EIn single chip mode this is a general-purpose I/O port.
A16 to A23 In external bus mode, these pins function as address high output
pins.
120 P30 EIn single chip mode this is a general-purpose I/O port.
ALE In external bus mode, this pin functions as the address latch enable
signal output pin.
1P31 EIn single chip mode this is a general-purpose I/O port.
RD In external bus mode, this pin functions as the read strobe signal out-
put pin.
2P32 EIn single chip mode this is a general-purpose I/O port.
WRL In external bus mode, this pin functions as the data bus lower 8-bit
write strobe signal output pin.
3P33 EIn single chip mode this is a general-purpose I/O port.
WRH In external bus mode, this pin functions as the data bus upper 8-bit
write strobe signal output pin.
4P34 EIn single chip mode this is a general-purpose I/O port.
HRQ In external bus mode, this pin functions as the hold request signal in-
put pin.
5P35 EIn single chip mode this is a general-purpose I/O port.
HAK In external bus mode, this pin functions as the hold acknowledge sig-
nal output pin.
6P36 EIn single chip mode this is a general-purpose I/O port.
RDY In external bus mode, this pin functions as the ready signal input pin.
MB90570 Series
9
(Continued)
*1 : FPT-120P-M05
*2 : FPT-120P-M13, FPT-120P-M21
Pin no. Pin name Circ uit
type Function
LQFP-120 *1
QFP-120 *2
7P37 EIn single chip mode this is a general-purpose I/O port.
CLK In external bus mode, this pin functions as the clock (CLK) signal out-
put pin.
9
P40
F
In single chip mode this is a general-purpose I/O port. It can be set to
open drain by the ODR4 register.
SIN0
This is also the UART ch.0 serial data input pin. While UART ch.0 is
in input operation, this input signal is in continuous use, and therefore
the output function should only be used when needed. If shared by
output from other functions, this pin should be output disabled during
SIN operation.
10 P41 F
In single chip mode this is a general-purpose I/O port. It can be set to
open drain by the ODR4 register.
SOT0 This is also the UART ch.0 serial data output pin. This function is valid
when UART ch.0 is enabled for data output.
11 P42 F
In single chip mode this is a general-purpose I/O port. It can be set to
open drain by the ODR4 register.
SCK0 This is also the UART ch.0 serial clock I/O pin. This function is valid
when UART ch.0 is enabled for clock output.
12
P43
F
In single chip mode this is a general-purpose I/O port. It can be set to
open-drain by the ODR4 register.
SIN1
This is also the UART ch.1 serial data input pin. While UART ch.1 is
in input operation, this input signal is in continuous use, and therefore
the output function should only be used when needed. If shared by
output from other functions, this pin should be output disabled during
SIN operation.
13 P44 F
In single chip mode this is a general-purpose I/O port. It can be set to
opendrain by the ODR4 register.
SOT1 This is also the UART ch.1 serial data output pin. This function is valid
when UART ch.1 is enabled for data output.
14 P45 F
In single chip mode this is a general-purpose I/O port. It can be set to
open drain by the ODR4 register.
SCK1 This is also the UART ch.1 serial clock I/O pin. This function is valid
when UART ch.1 is enabled for clock output.
15,16 P46,P47 F
In single chip mode this is a general-purpose I/O port. It can be set to
open drain by the ODR4 register.
PPG0,PPG1 These are also the PPG0, 1 output pins. This function is valid when
PPG0, 1 output is enabled.
17
P50
E
In single chip mode this is a general-purpose I/O port.
SIN2 This is also the I/O serial ch.0 data input pin. During serial data input,
this input signal is in continuous use, and therefore the output function
should only be used when needed.
MB90570 Series
10
(Continued)
*1 : FPT-120P-M05
*2 : FPT-120P-M13, FPT-120P-M21
Pin no. Pin name Circuit
type Function
LQFP-120 *1
QFP-120 *2
18 P51 EIn single chip mode this is a general-purpose I/O port.
SOT2 This is also the I/O serial ch.0 data output pin. This function is valid
when serial ch.0 is enabled for serial data output.
19 P52 EIn single chip mode this is a general-purpose I/O port.
SCK2 This is also the I/O serial ch.0 clock I/O pin. This function is valid when
serial ch.0 is enabled for serial data output.
20
P53
E
In single chip mode this is a general-purpose I/O port.
SIN3 This is also the I/O serial ch.1 data input pin. During serial data input,
this input signal is in continuous use, and therefore the output function
should only be used when needed.
21 P54 EIn single chip mode this is a general-purpose I/O port.
SOT3 This is also the I/O serial ch.1 data output pin. This function is valid
when serial ch.1 is enabled for serial data output.
22 P55 EIn single chip mode this is a general-purpose I/O port.
SCK3 This is also the I/O serial ch.1 clock I/O pin. This function is valid when
serial ch.1 is enabled for serial data output.
23,24
P56,P57
E
In single chip mode this is a general-purpose I/O port.
IN0,IN1 These are also the input capture ch.0/1 trigger input pins. During input
capture signal input on ch.0/1 this function is in continuous use, and
therefore the output function should only be used when needed.
25
P60
F
In single chip mode this is a general-purpose I/O port. When set for
input it can be set by the pull-up resistance register (RDR6). When set
for output this setting will be invalid.
SIN4 This is also the I/O serial ch.2 data input pin. During serial data input
this function is in continuous use, and therefore the output function
should only be used when needed.
26 P61 F
In single chip mode this is a general-purpose I/O port. When set for
input it can be set by the pull-up resistance register (RDR6). When set
for output this setting will be invalid.
SOT4 This is also the I/O serial ch.2 data output pin. This function is valid
when serial ch.2 is enabled for serial data output.
27 P62 F
In single chip mode this is a general-purpose I/O port. When set for
input it can be set by the pull-up resistance register (RDR6). When set
for output this setting will be invalid.
SCK4 This is also the I/O serial ch.2 serial clock I/O pin. This function is valid
when serial ch.2 is enabled for serial data output.
28 P63 F
In single chip mode this is a general-purpose I/O port. When set for
input it can be set by the pull-up resistance register (RDR6). When set
for output this setting will be invalid.
CKOT This is also the clock monitor output pin. This function is valid when
clock monitor output is enabled.
MB90570 Series
11
(Continued)
*1 : FPT-120P-M05
*2 : FPT-120P-M13, FPT-120P-M21
Pin no. Pin name Circuit
type Function
LQFP-120 *1
QFP-120 *2
29 to 32
P64 to P67
F
In single chip mode these are general-purpose I/O ports. When set for
input they can be set by the pull-up resistance register (RDR6). When
set for output this setting will be invalid.
OUT0 to
OUT3
These are also the output compare ch.0 to ch.3 event output pins.
This function is valid when the respective channel(s) are enabled for
output.
35 to 37 P70 to P72 E These are general purpose I/O ports.
40,41 P73,P74 IThese are general purpose I/O ports.
DA0,DA1 These are also the D/A converter ch.0,1 analog signal output pins.
46 to 53 P80 to P87 KThese are general purpose I/O ports.
AN0 to AN7 These are also A/D converter analog input pins. This function is valid
when analog input is enabled.
55 to 62 P90 to P97 EThese are general purpose I/O ports.
CS0 to CS7 These are also chip select signal output pins. This function is valid
when chip select signal output is enabled.
34 C G This is the power supply stabilization capacitor pin. It should be
connected externally to an 0.1 µF ceramic capacitor. Note that this is
not required on the FLASH model (MB90F574/A) and MB90574C.
64
PA0
E
This is a general purpose I/O port.
AIN0 This pin is also used as count clock A input for 8/16-bit up-down
counter ch.0.
IRQ6 This pin can also be used as interrupt request input ch. 6.
65 PA1 EThis is a general purpose I/O port.
BIN0 This pin is also used as count clock B input for 8/16-bit up-down
counter ch.0.
66 PA2 EThis is a general purpose I/O port.
ZIN0 This pin is also used as count clock Z input for 8/16-bit up-down
counter ch.0.
67
PA3
E
This is a general purpose I/O port.
AIN1 This pin is also used as count clock A input for 8/16-bit up-down
counter ch.1.
IRQ7 This pin can also be used as interrupt request input ch.7.
68 PA4 EThis is a general purpose I/O port.
BIN1 This pin is also used as count clock B input for 8/16-bit up-down
counter ch.1.
69 PA5 EThis is a general purpose I/O port.
ZIN1 This pin is also used as count clock Z input for 8/16-bit up-down
counter ch.1.
MB90570 Series
12
(Continued)
*1 : FPT-120P-M05
*2 : FPT-120P-M13, FPT-120P-M21
Pin no. Pin name Circuit
type Function
LQFP-120 *1
QFP-120 *2
70
PA6
L
This is a general purpose I/O port.
SDA
This pin is also used as the data I/O pin for the I2C interface. This
function is valid when the I2C interface is enabled for operation. While
the I2C interface is operating, this port should be set to the input level
(DDRA: bit6 = 0).
71
PA7
L
This is a general purpose I/O port.
SCL
This pin is also used as the clock I/O pin for the I2C interface. This
function is valid when the I2C interface is enabled for operation. While
the I2C interface is operating, this port should be set to the input level
(DDRA: bit7 = 0).
72,
75 to 79
PB0,
PB1 to PB5
E
These are general-purpose I/O ports.
IRQ0,
IRQ1 to IRQ5
These pins are also the external interrupt input pins. IRQ0, 1 are en-
abled for both rising and falling edge detection, and therefore cannot
be used for recovery from STOP status for MB90V570, MB90F574,
MB90573 and MB90574. However, IRQ0, 1 can be used for recovery
from STOP status for MB90V570A, MB90F574A and MB90574C.
80
PB6
E
This is a general purpose I/O port.
ADTG This is also the A/D converter external trigger input pin. While the A/D
converter is in input operation, this input signal is in continuous use,
and therefore the output function should only be used when needed.
81 PB7 E This is a general purpose I/O port.
82 to 85 PC0 to PC3 E These are general purpose I/O ports.
8,54,94 VCC Power
supply These are power supply (5V) input pins.
33,63,
91,119 VSS Power
supply These are power supply (0V) input pins.
42 AVCC H This is the analog macro (D/A, A/D etc.) Vcc power supply input pin.
43 AVRH J This is the A/D converter Vref+ input pin. The input voltage should not
exceed Vcc.
44 AVRL H This is the A/D converter Vref- input pin. The input voltage should not
less than Vss.
45 AVSS H This is the analog macro (D/A, A/D etc.) Vss power supply input pin.
38 DVCC HThis is the D/A converter Vref input pin. The input voltage should not
exceed Vcc.
39 DVSS HThis is the D/A converter GND power supply pin. It should be set to
Vss equivalent potential.
MB90570 Series
13
■
■■
■I/O CIRCUIT TYPE
(Continued)
Type Circuit Remarks
A
• Oscillator circuit
Oscillator recovery resistance for high
speed = approx. 1 MΩ
B
• Oscillator circuit
Oscillator recovery resistance for low
speed = approx. 10 MΩ
C
• Hysteresis input pin
Resistance value = approx. 50 kΩ (typ.)
D
• CMOS hysteresis input pin with input
pull-up control
• CMOS level output.
• CMOS hysteresis input
(Includes input shut down standby
control function)
• Pull-up resistance value =
approx. 50 kΩ(typ.)
IOL = 4mA
X1
X0
Standby control signal
X1A
X0A
Standby control signal
Hysteresis input
R
RHysteresis input
Selective signal either
with a pull-up resistor or
without it.
IOL = 4 mA
Standby control for input interruption
VCC
VCC
P-ch
P-ch
N-ch
MB90570 Series
14
(Continued)
Type Circuit Remarks
E
• CMOS hysteresis input/output pin.
• CMOS level output
• CMOS hysteresis input
(Includes input shut down standby
control function)
IOL = 4 mA
F
• CMOS hysteresis input/output pin.
• CMOS level output
• CMOS hysteresis input
(Includes input shut down standby
control function)
IOL = 10 mA (Large current port)
G
• C pin output
(capacitance connector pin).
On the MB90F574 this pin is not
connected (NC).
H
• Analog power supply protector
circuit.
I
• CMOS hysteresis input/output
• Analog output/CMOS output
dual-function pin (CMOS output is not
available during analog output.)
(Analog output priority: DAE = 1)
• Includes input shut down standby
control function.
IOL = 4mA
VCC
IOL = 4 mA
RHysteresis input
Standby control for input interruption
P-ch
N-ch
Hysteresis input
R
IOL = 10 mA
VCC
Standby control for input interruption
P-ch
N-ch
VCC
N-ch
P-ch
AVP
VCC
P-ch
N-ch
R
IOL = 4 mA
Hysteresis input
DAO
Standby control for input interruption
VCC
P-ch
N-ch
MB90570 Series
15
(Continued)
Type Circuit Remarks
J
• A/D conver ter ref+ power supply input
pin(AVRH), with power supply
protector circuit.
K
• CMOS hysteresis input /analog input
dual-function pin.
• CMOS output
• Includes input shut down function at
input shut down standby.
L
• Hysteresis input
• N-ch open-drain output
• Includes input shut down standby
control function.
IOL= 4mA
ANE
ANE
AVR
VCC
P-ch
N-ch
N-ch
P-ch
Hysteresis input
R
IOL = 4 mA Analog input
Standby control for input interruption
VCC
N-ch
P-ch
Hysteresis input
R
IOL = 4 mA Standby control for input interruption
VCC N-ch
N-ch
MB90570 Series
16
■
■■
■HANDLING DEVICES
1. Preventing Latchup
CMOS ICs may cause latchup in the following situations:
• When a voltage higher than Vcc or lower than Vss is applied to input or output pins.
• When a voltage exceeding the rating is applied between Vcc and Vss.
• When AVcc power is supplied prior to the Vcc voltage.
In turning on/turning off the analog pow er supply, make sure the analog po wer v oltage (AVCC, AVRH, DVCC)and
analog input voltages not exceed the digital voltage (VCC).
2. Treatment of unused pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the
device. Therefor they must be tied to VCC or Ground through resistors. In this case those resistors should be
more than 2 kΩ.
Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above
described connection.
3. Notes on Using External Clock
In using the external clock, drive X0 pin only and leave X1 pin unconnected.
4. Unused Sub Clock Mode
If sub clock modes are not used, the oscillator should be connected to the X01A pin and X1A pin
5. Power Supply Pins (VCC/VSS)
In products with multiple VCC or VSS pins, the pins of a same potential are intern ally connected in the device to
avoid abnormal operations including latch-up. However, connect the pins external power and ground lines to
lower the electro-magnetic emission level, to prevent abnor mal operation of strobe signals caused by the r ise
in the ground level, and to conform to the total current rating.
Make sure to connect VCC and VSS pins via lowest impedance to power lines.
•
••
• Using external clock MB90570 series
X0
X1
Open
MB90570 Series
17
It is recommended to provide a bypass capacitor of around 0.1 µF between VCC and VSS pin near the device.
6. Crystal Oscillator Circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass
capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines , and
make sure, to the utmost effort, that lines of oscillation circuit do not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with an grand
area for stabilizing the operation.
7. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply, D/A converter power supply (A VCC, A VRH, AVRL, DVCC,DVSS)
and analog inputs (AN0 to AN7) after turning-on the digital power supply (VCC).
Turn-off the digital power after tur ning off the A/D converter supply and analog inputs. In this case, make sure
that the vo ltage does not exceed AVRH or AVCC (tur ning on/off the analog and digital power supplies simulta-
neously is acceptable).
8. Connection of Unused Pins of A/D Converter
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = DVCC = VSS.
9. N.C. Pins
The N.C. (internally connected) pins must be opened for use.
10. Notes on Energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50
or more µs (0.2 V to 2.7 V).
11. Indeterminate outputs from ports 0 and 1
The outputs from ports 0 and 1 become indeterminate during oscillation setting time of step-down circuit (during
a power-on reset) after the power is turned on. (MB90573, MB90574, MB90V570, MB90V570A)
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
•
••
• Using power supply pins
MB90570 series
MB90570 Series
18
The series without built-in step-down circuit have no oscillation setting time of step-down circuit, so outputs
should not become indeterminate. (MB90F574,MB90F574A,MB90574C)
12. Initialization
In the de vice, there are internal registers which are initialized only by a po wer-on reset. Turn on the power again
to initialize these registers.
13. Return from standby state
If the powe r-supply voltage goes below the standby RAM holding voltage in the standby state, the device may
fail to return from the standby state. In this case, reset the device via the e xternal reset pin to return to the normal
state.
14. Precautions for Use of ’DIV A, Ri,’ and ’DIVW A, Ri’ Instructions
The signed multiplication-division instructions ’DIV A, Ri,’ and ’DIVW A, RWi’ should be used when the corre-
sponding bank registers (DTB, ADB , USB, SSB) are set to v alue ’00h.’ If the corresponding bank registers (DTB ,
ADB, USB, SSB) are set to a value other than ’00h,’ then the remainder obtained after the execution of the
instruction will not be placed in the instruction operand register.
15. Precautions for Use of REALOS
Extended intelligent I/O service (EI2OS) cannot be used, when REALOS is used.
16. Caution on PLL Clock Mode
If the PLL clock mode is selected, the microcontroller attempt to be w orking with the self-oscillating circuit e ven
when there is no external oscillator or external clock input is stopped. Performance of this operation, however,
cannot be guaranteed.
Oscillation setting time *2
VCC (power-supply pin)
PONR (power-on reset) signal
RST (external asynchronous reset) signal
RST (internal reset) signal
Oscillation clock signal
KA (internal operating clock A) signal
KB (internal operating clock B) signal
PORT (port output) signal
Step-down circuit setting time *1
Period of indeterminate
*1: Step-down circuit setting time217/oscillation clock frequency (oscillation cloc k frequency of 16 MHz: 8.19 ms)
*2: Oscillation setting time 218/oscillation clock frequency (oscillation clock frequency of 16 MHz: 16.38 ms)
Timing chart of indeterminate outputs from ports 0 and 1
MB90570 Series
19
■
■■
■BLOCK DIAGRAM
Port 0, 1, 2
F2MC–16LX
CPU
Clock control
block
(including timebase
timer)
External bus
interface
UART0
(SCI),
UART1
(SCI)
16-bit free run timer
Interrupt controller
8-bit
D/A
converter
× 2 ch.
Internal data bus
DTP/
external
interrupt
circuit
× 8 ch.
Input capture
(ICU)
X0, X1
P00/AD00 to P07/AD07
DVSS
Port 3
Port 4
8/16-bit
PPG timer
ch.0
Port 5
SIO × 2 ch
Output
compare
(OCU)
Port 6
Clock output
X0A, X1A
RST
HST
P10/AD08 to P17/AD15
P20/A16 to P27/A23
P30/ALE
P31/RD
P32/WRL
P33/WRH
P36/RDY
P35/HAK
P34/HRQ
P37/CLK
P40/SIN0
P41/SOT0
P42/SCK0
P43/SIN1
P44/SOT1
P45/SCK1
P46/PPG0
P47/PPG1
P50/SIN2
P51/SOT2
P52/SCK2
P53/SIN3
P54/SOT3
P55/SCK3
P56/IN0
P57/IN1
P64/OUT0 to P67/OUT3
P60/SIN4
P61/SOT4
P62/SCK4
P63/CKOT
Port 7
Port 9
I2C bus
Port A
Chip select
output
Port B
Port C
RAM
P70 to P72
P73/DA0
P74/DA1
DVCC
PA1/BIN0
PA2/ZIN0
PA3/AIN1/IRQ7
PA4/BIN1
PA5/ZIN1
SIO × 1 ch. ROM
PA6/SDA
PA7/SCL
PB7
PB6/ADTG
PC0 to PC3
4
88
8
P00 to P07 (8 ports): Provided with a register optional input pull-up resistor
P10 to P17 (8 ports): Provided with a register optional input pull-up resistor
P40 to P47 (8 ports): Heavy-current (IOL = 10 mA) port
P60 to P67 (8 ports): Provided with a register optional input pull-up resistor
MD0 to MD2,
C, VCC, VSS
Other pins
Main clock
Sub clock
8/16-bit up/down
counter/timer
8
16
2
6
2
2
2
2
2
2
2
4
3
2
88
2
6
66
8
8/10-bit
A/D converter
× 8 ch.
Port 8
P90/CS0 to P97/CS7
PA0/AIN0/IRQ6
PB0/IRQ0 to
PB5/IRQ5
AVRL
AVRH
AVSS
AVCC
P80/AN0 to
P87/AN7
4
8
MB90570 Series
20
■
■■
■MEMORY MAP
Note : The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C
compiler small model. The low er 16-bit of bank FF and the lower 16-bit of bank 00 is assigned to the same
address, enabling reference of the table on the ROM without stating “far”.
For example, if an attempt has been made to access 00C000H, the contents of the ROM at FFC000H are
accessed actually . Since the ROM area of the FF bank exceeds 48 kbytes, the whole area cannot be reflected
in the image f or the 00 bank. The ROM data at FF4000H to FFFFFFH looks , theref ore, as if it were the image
f or 00400H to 00FFFFH. Thus , it is recommended that the ROM data table be stored in the area of FF4000H
to FFFFFFH.
Part number Address #1* Address #2 * Address #3 *
MB90573 FE0000H004000H001800H
MB90574/C FC0000H004000H002900H
MB90F574/A FC0000H004000H002900H
FFFFFFH
Address #1
FC0000H
010000H
Address #2
Address #3
000100H
0000C0H
000000H
ROM area ROM area
ROM area
(image of
bank FF)
ROM area
(image of
bank FF)
RAM RAM RAM
Register Register Register
PeripheralPeripheral Peripheral
Internal ROM
external bus mode
A mirror function
is supported. External ROM
external bus mode
: Internal access memory
: External access memory
*: Addresses #1, #2 and #3 are unique to the product type.
: Inhibited area
004000H
Single chip mode
A mirror function is
supported.
MB90570 Series
21
■
■■
■F2MC-16LX CPU PROGRAMMING MODEL
•Dedicated registers
:Accumulator (A)
Dual 16-bit register used for storing results of calculation etc. The two
16-bit registers can be combined to be used as a 32-bit register.
:Additional data bank register (ADB)
The 8-bit register indicating the additional data space.
:User stack pointer (USP)
The 16-bit pointer indicating a user stack address.
:User stack bank register (USB)
The 8-bit register indicating the user stack space.
:System stack pointer (SSP)
The 16-bit pointer indicating the status of the system stack address.
:Processor status (PS)
The 16-bit register indicating the system status.
:Program bank register (PCB)
The 8-bit register indicating the program space.
:Data bank register (DTB)
The 8-bit register indicating the data space.
:Program counter (PC)
The 16-bit register indicating storing location of the current instruction
code.
:Direct page register (DPR)
The 8-bit register indicating bit 8 through 15 of the operand address
in the short direct addressing mode.
:System stack bank register (SSB)
The 8-bit register indicating the system stack space.
AH AL
USP
SSP
DPR
PCB
DTB
USB
SSB
ADB
PS
PC
8-bit
16-bit
32-bit
MB90570 Series
22
•General-purpose registers
•Processor status (PS)
Maximum of 32 banks
000180H + (RP × 10H)
R7
R5
R3
R1
R6
R4
R2
R0
RW7
RW6
RW5
RW4
RL3
RL2
RL1
RL0
RW3
RW2
RW1
RW0
16-bit
ILM RP CCR
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
ILM2 B4ILM1 ILM0 B3 B2 B1 B0 — I S T N Z V C
00 000 000 10XXXXX
—
PS
Initial value
—: Reserved
X: Undefined
MB90570 Series
23
■
■■
■I/O MAP
(Continued)
Address Abbreviated
register
name Register name Read/
write Resource name Initial value
000000HPDR0 Port 0 data register R/W Port 0 XXXXXXXXB
000001HPDR1 Port 1 data register R/W Port 1 XXXXXXXXB
000002HPDR2 Port 2 data register R/W Port 2 XXXXXXXXB
000003HPDR3 Port 3 data register R/W Port 3 XXXXXXXXB
000004HPDR4 Port 4 data register R/W Port 4 XXXXXXXXB
000005HPDR5 Port 5 data register R/W Port 5 XXXXXXXXB
000006HPDR6 Port 6 data register R/W Port 6 XXXXXXXXB
000007HPDR7 Port 7 data register R/W Port 7 XXXXXXXXB
000008HPDR8 Port 8 data register R/W Port 8 XXXXXXXXB
000009HPDR9 Port 9 data register R/W Port 9 XXXXXXXXB
00000AHPDRA Port A data register R/W Port A XXXXXXXXB
00000BHPDRB Port B data register R/W Port B XXXXXXXXB
00000CHPDRC Port C data register R/W Port C XXXXXXXXB
00000DH
to
00000FH(Disabled)
000010HDDR0 Port 0 direction register R/W Port 0 0 0 0 0 0 0 0 0B
000011HDDR1 Port 1 direction register R/W Port 1 0 0 0 0 0 0 0 0B
000012HDDR2 Port 2 direction register R/W Port 2 0 0 0 0 0 0 0 0B
000013HDDR3 Port 3 direction register R/W Port 3 0 0 0 0 0 0 0 0B
000014HDDR4 Port 4 direction register R/W Port 4 0 0 0 0 0 0 0 0B
000015HDDR5 Port 5 direction register R/W Port 5 0 0 0 0 0 0 0 0B
000016HDDR6 Port 6 direction register R/W Port 6 0 0 0 0 0 0 0 0B
000017HDDR7 Port 7 direction register R/W Port 7 – – – 0 0 0 0 0B
000018HDDR8 Port 8 direction register R/W Port 8 0 0 0 0 0 0 0 0B
000019HDDR9 Port 9 direction register R/W Port 9 0 0 0 0 0 0 0 0B
00001AHDDRA Port A direction register R/W Port A 0 0 0 0 0 0 0 0B
00001BHDDRB Port B direction register R/W Port B 0 0 0 0 0 0 0 0B
00001CHDDRC Port C direction register R/W Port C 0 0 0 0 0 0 0 0B
00001DHODR4 Port 4 output pin register R/W Port 4 0 0 0 0 0 0 0 0B
00001EHADER Analog input enable register R/W Port 8,
8/10-bit
A/D converter 11111111B
00001FH(Disabled)
000020HSMR0 Serial mode register 0 R/W UART0
(SCI) 00000000B
000021HSCR0 Serial control register 0 R/W 0 0 0 0 0 1 0 0B
MB90570 Series
24
(Continued)
Address Abbreviated
register
name Register name Read/
write Resour ce
name Initial value
000022HSIDR0/
SODR0 Serial input data register 0/
serial output data register 0 R/W UART0
(SCI) XXXXXXXXB
000023HSSR0 Serial status register 0 R/W 00001–00B
000024HSMR1 Serial mode register 1 R/W
UART1
(SCI)
00000000B
000025HSCR1 Serial control register 1 R/W 0 0 0 0 0 1 0 0B
000026HSIDR1/
SODR1 Serial input data register 1/
serial output data register 1 R/W XXXXXXXXB
000027HSSR1 Serial status register 1 R/W 00001–00B
000028HCDCR0 Communications prescaler control
register 0 R/W
Communica-
tions
prescaler
register 0
0–––1111B
000029H(Disabled)
00002AHCDCR1 Communications prescaler control
register 1 R/W
Communica-
tions
prescaler
register 0
0–––1111B
00002BH
to
00002FH(Disabled)
000030HENIR DTP/interrupt enable register R/W DTP/external
interrupt circuit
00000000B
000031HEIRR DTP/interrupt factor register R/W XXXXXXXXB
000032HELVR Request level setting register R/W 00000000
B
000033H00000000B
000034H(Disabled)
000035H
000036HADCS1 A/D control status register lower
digits R/W
8/10-bit A/D
converter
00000000B
000037HADCS2 A/D control status register upper
digits R/W or W 00000000B
000038HADCR1 A/D data register lower digits R XXXXXXXXB
000039HADCR2 A/D data register upper digits W 0 0 0 0 1 – XXB
00003AHDADR0 D/A converter data register ch.0 R/W 8-bit D/A
converter
XXXXXXXXB
00003BHDADR1 D/A converter data register ch.1 R/W XXXXXXXXB
00003CHDACR0 D/A control register 0 R/W – – – – – – – 0B
00003DHDACR1 D/A control register 1 R/W – – – – – – – 0B
00003EHCLKR Clock output enable register R/W Clock monitor
function ––––0000B
00003FH(Disabled)
000040HPRLL0 PPG0 reload register L ch.0 R/W 8/16-bit PPG
timer 0 XXXXXXXXB
000041HPRLH0 PPG0 reload register H ch.0 R/W XXXXXXXXB
MB90570 Series
25
(Continued)
Address Abbreviated
register
name Register name Read/
write Resource name Initial value
000042HPRLL1 PPG1 reload register L ch.1 R/W 8/16-bit PPG
timer 1 XXXXXXXXB
000043HPRLH1 PPG1 reload register H ch.1 R/W XXXXXXXXB
000044HPPGC0 PPG0 operating mode control
register ch.0 R/W 8/16-bit PPG
timer 0 0X000XX1B
000045HPPGC1 PPG1 operating mode control
register ch.1 R/W 8/16-bit PPG
timer 1 0X000001B
000046HPPGOE PPG0 and 1 output control registers
ch.0 and ch.1 R/W 8/16-bit PPG
timer 0, 1 000000XXB
000047H(Disabled)
000048HSMCSL0 Serial mode control lower status
register 0 R/W Extended I/O
serial interface 0
––––0000
B
000049HSMCSH0 Serial mode control upper status
register 0 R/W 00000010B
00004AHSDR0 Serial data register 0 R/W XXXXXXXXB
00004BH(Disabled)
00004CHSMCSL1 Serial mode control lower status
register 1 R/W Extended I/O
serial interface 1
––––0000
B
00004DHSMCSH1 Serial mode control upper status
register 1 R/W 00000010B
00004EHSDR1 Serial data register 1 R/W XXXXXXXXB
00004FH(Disabled)
000050HIPCP0 ICU data register ch.0 R 16-bit I/O timer
(input capture
(ICU) section)
XXXXXXXXB
000051HXXXXXXXXB
000052HIPCP1 ICU data register ch.1 R XXXXXXXXB
000053HXXXXXXXXB
000054HICS01 ICU control status register R/W 0 0 0 0 0 0 0 0B
000055H(Disabled)
000056HTCDT Free run timer data register R/W 16-bit I/O timer
(16-bit free run
timer section)
00000000
B
000057H00000000B
000058HTCCS Free run timer control status register R/W 0 0 0 0 0 0 0 0B
000059H(Disabled)
00005AHOCCP0 OCU compare register ch.0 R/W
16-bit I/O timer
(output compare
(OCU) section)
XXXXXXXXB
00005BHXXXXXXXXB
00005CHOCCP1 OCU compare register ch.1 R/W XXXXXXXXB
00005DHXXXXXXXXB
00005EHOCCP2 OCU compare register ch.2 R/W XXXXXXXXB
00005FHXXXXXXXXB
MB90570 Series
26
(Continued)
Address Abbreviated
register
name Register name Read/
write Resource name Initial value
000060HOCCP3 OCU compare register ch.3 R/W
16-bit I/O timer
(output compare
(OCU) section)
XXXXXXXXB
000061HXXXXXXXXB
000062HOCS0 OCU control status register ch.0 R/W 0 0 0 0 – – 0 0B
000063HOCS1 OCU control status register ch.1 R/W – – – 0 0 0 0 0B
000064HOCS2 OCU control status register ch.2 R/W 0 0 0 0 – – 0 0B
000065HOCS3 OCU control status register ch.3 R/W – – – 0 0 0 0 0B
000066H(Disabled)
000067H
000068HIBSR I2C bus status register R
I2C interface
00000000
B
000069HIBCR I2C bus control register R/W 0 0 0 0 0 0 0 0B
00006AHICCR I2C bus clock control register R/W – – 0 XXXXXB
00006BHIADR I2C bus address register R/W – XXXXXXXB
00006CHIDAR I2C bus data register R/W XXXXXXXXB
00006DH(Disabled)
00006EH
00006FHROMM ROM mirroring function selection
register WROM mirroring
function
selection module –––––––1B
000070HUDCR0 Up/down count register 0 R
8/16-bit up/down
counter/timer
00000000B
000071HUDCR1 Up/down count register 1 R 0 0 0 0 0 0 0 0B
000072HRCR0 Reload compare register 0 W 0 0 0 0 0 0 0 0B
000073HRCR1 Reload compare register 1 W 0 0 0 0 0 0 0 0B
000074HCSR0 Counter status register 0 R/W 0 0 0 0 0 0 0 0B
000075H(Reserved area)*3
000076HCCRL0 Counter control register 0 R/W 8/16-bit up/down
counter/timer
–0000000
B
000077HCCRH0 00000000B
000078HCSR1 Counter status register 1 R/W 0 0 0 0 0 0 0 0B
000079H(Reserved area)*3
00007AHCCRL1 Counter control register 1 R/W 8/16-bit up/down
counter/timer –0000000B
00007BHCCRH1 –0000000B
00007CHSMCSL2 Serial mode control lower status
register 2 R/W Extended I/O
serial interface 2
––––0000B
00007DHSMCSH2 Serial mode control higher status
register 2 R/W 00000010B
00007EHSDR2 Serial data register 2 R/W XXXXXXXXB
00007FH(Disabled)
MB90570 Series
27
(Continued)
Address Abbreviated
register
name Register name Read/
write Resource name Initial value
000080HCSCR0 Chip selection control register 0 R/W
Chip select
output
––––0000B
000081HCSCR1 Chip selection control register 1 R/W – – – – 0 0 0 0B
000082HCSCR2 Chip selection control register 2 R/W – – – – 0 0 0 0B
000083HCSCR3 Chip selection control register 3 R/W – – – – 0 0 0 0B
000084HCSCR4 Chip selection control register 4 R/W – – – – 0 0 0 0B
000085HCSCR5 Chip selection control register 5 R/W – – – – 0 0 0 0B
000086HCSCR6 Chip selection control register 6 R/W – – – – 0 0 0 0B
000087H
to
00008BH(Disabled)
00008CHRDR0 Port 0 input pull-up resistor setup
register R/W Port 0 00000000B
00008DHRDR1 Port 1 input pull-up resistor setup
register R/W Port 1 00000000B
00008EHRDR6 Port 6 input pull-up resistor setup
register R/W Port 6 00000000B
00008FH
to
00009DH(Disabled)
00009EHPACSR Program address detection control
status register R/W Address match
detection
function 00000000B
00009FHDIRR Delayed interrupt factor generation/
cancellation register R/W
Delayed
interrupt
generation
module
–––––––0B
0000A0HLPMCR Low-power consumption mode
control register R/W Low-power
consumption
(standby) mode
00011000
B
0000A1HCKSCR Clock select register R/W 1 1 1 1 1 1 0 0B
0000A2H
to
0000A4H(Disabled)
0000A5HARSR Automatic ready function select
register W
External bus pin
0011––00B
0000A6HHACR Upper address control register W 0 0 0 0 0 0 0 0B
0000A7HECSR Bus control signal select register W 0 0 0 0 0 0 0 0B
0000A8HWDTC Watchdog timer control register R/W Watchdog timer XXXXXXXXB
0000A9HTBTC Timebase timer control register R/W Timebase timer 1 – – 0 0 1 0 0B
0000AAHWTC C lock timer control register R/W Clock timer 1 X0 0 0 0 0 0B
MB90570 Series
28
(Continued)
Address Abbreviated
register
name Register name Read/
write Resource name Initial value
0000ABH
to
0000ADH(Disabled)
0000AEHFMCS Flash control register R/W Flash interface 0 0 0 X0 XX0B
0000AFH(Disabled)
0000B0HICR00 Interrupt control register 00 R/W
Interrupt
controller
00000111B
0000B1HICR01 Interrupt control register 01 R/W 0 0 0 0 0 1 1 1B
0000B2HICR02 Interrupt control register 02 R/W 0 0 0 0 0 1 1 1B
0000B3HICR03 Interrupt control register 03 R/W 0 0 0 0 0 1 1 1B
0000B4HICR04 Interrupt control register 04 R/W 0 0 0 0 0 1 1 1B
0000B5HICR05 Interrupt control register 05 R/W 0 0 0 0 0 1 1 1B
0000B6HICR06 Interrupt control register 06 R/W 0 0 0 0 0 1 1 1B
0000B7HICR07 Interrupt control register 07 R/W 0 0 0 0 0 1 1 1B
0000B8HICR08 Interrupt control register 08 R/W 0 0 0 0 0 1 1 1B
0000B9HICR09 Interrupt control register 09 R/W 0 0 0 0 0 1 1 1B
0000BAHICR10 Interrupt control register 10 R/W 0 0 0 0 0 1 1 1B
0000BBHICR11 Interrupt control register 11 R/W 0 0 0 0 0 1 1 1B
0000BCHICR12 Interrupt control register 12 R/W 0 0 0 0 0 1 1 1B
0000BDHICR13 Interrupt control register 13 R/W 0 0 0 0 0 1 1 1B
0000BEHICR14 Interrupt control register 14 R/W 0 0 0 0 0 1 1 1B
0000BFHICR15 Interrupt control register 15 R/W 0 0 0 0 0 1 1 1B
0000C0H
to
0000FFH(External area)*1
000100H
to
000###H(RAM area)*2
000###H
to
001FEFH(Reserved area)*3
001FF0H
PADR0 Program address detection register 0 R/W
Address match
detection
function
XXXXXXXXB
001FF1HProgram address detection register 1 R/W XXXXXXXXB
001FF2HProgram address detection register 2 R/W XXXXXXXXB
001FF3H
PADR1 Program address detection register 3 R/W XXXXXXXXB
001FF4HProgram address detection register 4 R/W XXXXXXXXB
001FF5HProgram address detection register 5 R/W XXXXXXXXB
001FF6H
to
001FFFH(Reserved area)
MB90570 Series
29
Descriptions for read/write
R/W : Readable and writable
R : Read only
W : Write only
Descriptions for initial value
0 : The initial value of this bit is “0”.
1 : The initial value of this bit is “1”.
X : The initial value of this bit is undefined.
– : This bit is unused. The initial value is undefined.
*1 : This area is the only e xternal access area having an address of 0000FFH or low er. An access operation to this
area is handled as that to external I/O area.
*2 : For details of the RAM area, see “■ MEMORY MAP”.
*3 : The reserved area is disabled because it is used in the system.
Notes : • For bits that is initialized by an reset operation, the initial value set by the reset operation is listed as an
initial value. Note that the values are different from reading results.
For LPMCR/CKSCR/WDTC, there are cases where initialization is performed or not performed, depending
on the types of the reset. However initial value for resets that initializes the value are listed.
• The addresses following 0000FFH are reserved. No external bus access signal is generated.
• Boundary ####H between the RAM area and the reserved area varies with the product model.
MB90570 Series
30
■
■■
■INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
(Continued)
Interrupt source EI2OS
support Interrupt vector Interrupt contr ol register Priority
Number Address ICR Address
Reset ×# 08 FFFFDCH——High
INT9 instruction ×# 09 FFFFD8H——
Exception ×# 10 FFFFD4H——
8/10-bit A/D converter # 11 FFFFD0HICR00 0000B0H
Input capture 0 (ICU) include # 12 FFFFCCH
DTP0 (external interrupt 0) # 13 FFFFC8HICR01 0000B1H
Input capture 1 (ICU) include # 14 FFFFC4 H
Output compare 0 (OCU) match # 15 FFFFC0HICR02 0000B2H
Output compare 1 (OCU) match # 16 FFFFBCH
Output compare 2 (OCU) match # 17 FFFFB8HICR03 0000B3H
Output compare 3 (OCU) match # 18 FFFFB4H
Extended I/O serial interface 0 # 19 FFFFB0HICR04 0000B4H
16-bit free run timer ×# 20 FFFFACH
Extended I/O serial interface 1 # 21 FFFFA8HICR05 0000B5H
Clock timer ×# 22 FFFFA4H
Extended I/O serial interface 2 # 23 FFFFA0HICR06 0000B6H
DTP1 (external interrupt 1) # 24 FFFF9CH
DTP2/DTP3 (external interrupt 2/
external interrupt 3) # 25 FFFF98HICR07 0000B7H
8/16-bit PPG timer 0 counter borrow ×# 26 FFFF94H
DTP4/DTP5 (external interrupt 4/
external interrupt 5) # 27 FFFF90HICR08 0000B8H
8/16-bit PPG timer 1 counter borrow ×# 28 FFFF8CH
8/16-bit up/down counter/timer 0
borrow/overflow/inversion # 29 FFFF88HICR09 0000B9H
8/16-bit up/down counter/timer 0
compare match # 30 FFFF84H
8/16-bit up/down counter/timer 1
borrow/overflow/inversion # 31 FFFF80HICR10 0000BAH
8/16-bit up/down counter/timer 1
compare match # 32 FFFF7CH0000BAH
DTP6 (external interrupt 6) # 33 FFFF78HICR11 0000BBH
Timebase timer ×# 34 FFFF74HLow
MB90570 Series
31
(Continued)
:Can be used
:Can not be used
:Can be used. With EI2OS stop function.
Interrupt source EI2OS
support Interrupt vector Interrupt control register Priority
Number Address ICR Address
DTP7 (external interrupt 7) # 35 FFFF70HICR12 0000BCHHigh
Low
I2C interface ×# 36 FFFF6CH
UART1 (SCI) reception complete # 37 FFFF68HICR13 0000BDH
UART1 (SCI) transmission
complete # 38 FFFF64H
UART0 (SCI) reception complete # 39 FFFF60HICR14 0000BEH
UART0 (SCI) transmission
complete # 40 FFFF5CH
Flash memory ×# 41 FFFF58HICR15 0000BFH
Delayed interrupt generation
module ×# 42 FFFF54H
×
MB90570 Series
32
■
■■
■PERIPHERALS
1. I/O Port
(1) Input/output Port
Port 0 through 4, 6, 8, A and B are general-pur pose I/O por ts having a combined function as an exter nal bus
pin and a resource input. P ort 0 to P ort 3 hav e a general-purpose I/O ports function only in the single-chip mode.
• Operation as output port
The pin is configured as an output port by setting the corresponding bit of the DDR register to “1”.
Writing data to PDR register when the port is configured as output, the data is retained in the output latch in
the PDR and directly output to the pin.
The v alue of the pin (the same v alue retained in the output latch of PDR) can be read out b y reading the PDR
register.
Note : When a read-modify-write instruction (e.g. bit set instruction) is performed to the port data register, the
destination bit of the operation is set to the specified value, not affecting the bits configured by the DDR
register for output, however, values of bits configured by the DDR register as inputs are changed because
input values to the pins are written into the output latch. To avoid this situation, configure the pins by the DDR
register as output after writing output data to the PDR register when configuring the bit used as input as
outputs.
• Operation as input port
The pin is configured as an input by setting the corresponding bit of the DDR register to “0”.
When the pin is configured as an input, the output buff er is turned-off and the pin is put into a high-impedance
status.
When a data is written into the PDR register , the data is retained in the output latch of the PDR, but pin outputs
are unaffected.
Reading the PDR register reads out the pin level (“0” or “1”).
MB90570 Series
33
(2) Register Configuration
(Continued)
• Port 0 data register (PDR0)
• Port 1 data register (PDR1)
Address
000000H
bit 15 bit 8
P07 P06 P05 P04 P03 P02 P01 P00
(PDR1)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
............
XXXXXXXXB
bit 7 bit 0bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............
R/W R/W R/W R/W R/W R/W R/W R/W
(PDR0)
Address
000001H
Initial value
XXXXXXXXB
Initial value
P17 P16 P15 P14 P13 P12 P11 P10
• Port 2 data register (PDR2)
• Port 3 data register (PDR3)
Address
000002H
bit 15 bit 8
P27 P26 P25 P24 P23 P22 P21 P20(PDR3)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
............
XXXXXXXXB
bit 7 bit 0bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............
R/W R/W R/W R/W R/W R/W R/W R/W (PDR2)
Address
000003H
Initial value
XXXXXXXXB
Initial value
P37 P36 P35 P34 P33 P32 P31 P30
• Port 4 data register (PDR4)
• Port 5 data register (PDR5)
Address
000004H
bit 15 bit 8
P47 P46 P45 P44 P43 P42 P41 P40(PDR5)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
............
XXXXXXXXB
bit 7 bit 0bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............
R/W R/W R/W R/W R/W R/W R/W R/W
(PDR4)
Address
000005H
Initial value
XXXXXXXXB
Initial value
P57 P56 P55 P54 P53 P52 P51 P50
• Port 6 data register (PDR6)
• Port 7 data register (PDR7)
Address
000006H
bit 15 bit 8
P67 P66 P65 P64 P63 P62 P61 P60(PDR7)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
............
XXXXXXXXB
bit 7 bit 0bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............
— — — R/W R/W R/W R/W R/W
(PDR6)
Address
000007H
Initial value
- - -XXXXXB
Initial value
— — — P74 P73 P72 P71 P70
• Port 8 data register (PDR8)
Address
000008H
bit 15 bit 8
P87 P86 P85 P84 P83 P82 P81 P80(PDR9)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
............
XXXXXXXXB
Initial value
MB90570 Series
34
(Continued)
• Port A data register (PDRA)
• Port 9 data register (PDR9)
Address
00000AH
bit 15 bit 8
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
(PDRB)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
............
XXXXXXXXB
bit 7 bit 0bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............
R/W R/W R/W R/W R/W R/W R/W R/W (PDR8)
Initial value
XXXXXXXXB
Initial value
P97 P96 P95 P94 P93 P92 P91 P90
Address
000009H
• Port B data register (PDRB)
Address
00000BH
bit 15 bit 8
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
(PDRA)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
............
XXXXXXXXB
Initial value
• Port C data register (PDRC)
Address
00000CH
bit 15 bit 8
— — — — PC3 PC2 PC1 PC0
(Disabled)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
————R/WR/WR/WR/W
............
XXXXXXXXB
Initial value
• Port 0 direction register (DDR0)
Address
000010H
bit 15 bit 8
D07 D06 D05 D04 D03 D02 D01 D00
(DDR1)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
............
00000000B
Initial value
• Port 2 direction register (DDR2)
Address
000012H
bit 15 bit 8
D27 D26 D25 D24 D23 D22 D21 D20
(DDR3)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
............
00000000B
Initial value
• Port 4 direction register (DDR4)
Address
000014H
bit 15 bit 8
D47 D46 D45 D44 D43 D42 D41 D40
(DDR5)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
............
00000000B
Initial value
• Port 1 direction register (DDR1) bit 7 bit 0bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............
R/W R/W R/W R/W R/W R/W R/W R/W (DDR0) 00000000B
Initial value
D17 D16 D15 D14 D13 D12 D11 D10
• Port 3 direction register (DDR3) bit 7 bit 0bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............
R/W R/W R/W R/W R/W R/W R/W R/W (DDR2) 00000000B
Initial value
D37 D36 D35 D34 D33 D32 D31 D30
Address
000011H
Address
000013H
MB90570 Series
35
(Continued)
• Port 6 direction register (DDR6)
• Port 5 direction register (DDR5)
Address
000016H
bit 15 bit 8
D67 D66 D65 D64 D63 D62 D61 D60
(DDR7)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
............
00000000B
bit 7 bit 0bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............
R/W R/W R/W R/W R/W R/W R/W R/W
(DDR4)
Initial value
00000000B
Initial value
D57 D56 D55 D54 D53 D52 D51 D50
Address
000015H
• Port 8 direction register (DDR8)
Address
000018H
bit 15 bit 8
D87 D86 D85 D84 D83 D82 D81 D80
(DDR9)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
............
00000000B
Initial value
• Port C direction register (DDRC)
Address
00001CH
bit 15 bit 8
— — — — DC3 DC2 DC1 DC0
(ODR4)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
————R/WR/WR/WR/W
............
00000000B
Initial value
• Port 0 input pull-up resistor setup register (RDR0)
Address
00008CH
bit 15 bit 8
RD07 RD06 RD05 RD04 RD03 RD02 RD01 RD00
(RDR1)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
............
00000000B
Initial value
• Port 9 direction register (DDR9) bit 7 bit 0bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............
R/W R/W R/W R/W R/W R/W R/W R/W
(DDR8) 00000000B
Initial value
D97 D96 D95 D94 D93 D92 D91 D90
Address
000019H
• Port 7 direction register (DDR7) bit 7 bit 0bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............
— — — R/W R/W R/W R/W R/W
(DDR6) - - -00000B
Initial value
— — — D74 D73 D72 D71 D70
Address
000017H
• Port 4 output pin register (ODR4)
Address
00001DH
bit 15 bit 8
OD47 OD46 OD45 OD44 OD43 OD42 OD41 OD40
(DDRC)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
............
00000000B
Initial value
• Port A direction register (DDRA)
Address
00001AH
bit 15 bit 8
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
(DDRB) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
............
00000000B
Initial value
• Port B direction register (DDRB)
Address
00001BH
bit 15 bit 8
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0(DDRA)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
............
00000000B
Initial value
MB90570 Series
36
(Continued)
• Port 6 input pull-up resistor setup register (RDR6)
• Port 1 input pull-up resistor setup register (RDR1)
Address
00008EH
bit 15 bit 8
RD67 RD66 RD65 RD64 RD63 RD62 RD61 RD60
(Disabled)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
............
00000000B
bit 7 bit 0bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............
R/W R/W R/W R/W R/W R/W R/W R/W
(RDR0)
Initial value
00000000B
Initial value
RD17 RD16 RD15 RD14 RD13 RD12 RD11 RD10
Address
00008DH
• Analog input enable register (ADER)
11111111B
Initial value
(Disabled) ADE7 ADE6 ADE5 ADE4 ADE3
Address
00001EH
R/W:Readable and writable
—:Reserved
X:Undefined
bit 15 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
............
ADE2 ADE1 ADE0
R/W R/W R/W R/W R/W R/W R/W R/W
MB90570 Series
37
(3) Block Diagram
• Input/output port
PDR (port data register)
DDR (port direction register)
PDR read
PDR write
DDR write
DDR read
Direction latch
Output latch
Internal data bus
Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode
Standby control (SPL=1)
P-ch
N-ch
Pin
• Output pin register (ODR) To resource input
DDR (port direction register)
PDR read
PDR write
DDR write
DDR read
Direction latch
Output latch
Internal data bus
Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode
Standby control
(SPL=1)
P-ch
N-ch
Pin
ODR (output pin register)
ODR write
ODR read
ODR latch
PDR (port data register) From resource output
Resource output enable
MB90570 Series
38
• Input pull-up resistor setup register (RDR) To resource input
DDR (port direction register)
PDR read
PDR write
DDR write
DDR read
Direction latch
Output latch
Internal data bus
Standby control: Stop, timebase timer mode and SPL=1
Standby control
(SPL=1)
P-ch
N-ch
Pin
RDR
(input pull-up resistor setup register)
RDR write
RDR read
RDR latch
PDR (port data register)
Pull-up resistor
About 5.0 kΩ
(5.0 V)
P-ch
• Analog input enable register (ADER)
PDR (port data register)
ADER read
ADER write
PDR write
PDR read
ADER latch
Internal data bus
Standby control
(SPL=1)
P-ch
N-ch
Pin
DDR write
DDR read
Direction latch
ADER (analog input enable register)
To analog input
Output latch
RMW
(read-modify-write
type instruction)
Standby control: Stop, timebase timer mode and SPL=1
DDR (port direction register)
MB90570 Series
39
2. Timebase Timer
The timebase timer is a 18-bit free run counter (timebase counter) for counting up in synchronization to the
internal count clock (divided-b y-2 of oscillation) with an interval timer function f or selecting an interval time from
four types of 212/HCLK, 214/HCLK, 216/HCLK, and 219/HCLK.
The timebase timer also has a function for supplying operating clocks for the timer output for the oscillation
stabilization time or the watchdog timer etc.
(1) Register Configuration
(2) Block Diagram
. . . . . . . . . . . .
• Timebase timer control register (TBTC)
RESV —
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 0
— — — R/W R/W W R/W R/W
(WDTC) Initial value
1--00100B
Address
0000A9H—TBIE TBOF TBR TBC1 TBC0
R/W:Readable and writable
W:Write only
—:Unused
RESV: Reserved bit
. . . . . .
To 8/16-bit PPG timer
Timebase timer counter
Divided-by-2
of HCLK
Power-on reset
Start stop mode
CKSCR: MCS = 1→0*1
Counter
clear circuit Interval
timer selector
Clear TBOF Set TBOF
Timebase timer control register
(TBTC)
Timebase timer
interrupt signal
#34*2
OF: Overflow
HCLK: Oscillation clock
*1: Switch machine clock from oscillation clock to PLL clock
*2: Interrupt signal
RESV ——
TBIE TBRTBOF TBC1 TBC0
To oscillation stabilization
time selector of clock control block
To watchdog timer
OF OF
OF OF
× 21× 22× 23× 28× 29× 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
MB90570 Series
40
3. Watchdog Timer
The watchdog timer is a 2-bit counter oper ating with an output of the timebase timer and resets the CPU when
the counter is not cleared for a preset period of time.
(1) Register Configuration
(2) Block Diagram
• Watchdog timer control register (WDTC)
Address
0000A8H
bit 15 bit 8
PONR STBR WRST ERST SRST WTE WT1 WT0(TBTC)
R:Read only
W:Write only
X:Indeterminate
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
RRRRRWWW
............ Initial value
XXXXXXXXB
HCLK: Oscillation clock
PONR STBR WRST ERST SRST WTE WT1 WT0
Watchdog timer control register (WDTC)
Start sleep mode
Start hold status
Start stop mode
CLR and start
Watchdog timer
Overflow
To internal reset
generation circuit
Counter clear
control circuit Count clock
selector 2-bit
counter
Watchdog timer
reset generation
circuit
Clear
Divided-by-2
of HCLK
(Timebase timer counter)
× 21× 22... × 28× 29× 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
CLR
2
4
CLR
MB90570 Series
41
4. 8/16-bit PPG Timer
The 8/16-bit PPG timer is a 2-CH reload timer module f or outputting pulse ha ving given frequencies/duty r atios.
The two modules performs the following operation by combining functions.
• 8-bit PPG output 2-CH independent operation mode
This is a mode for operating independent 2-CH 8-bit PPG timer, in which PPG0 and PPG1 pins correspond
to outputs from PPG0 and PPG1 respectively.
• 16-bit PPG timer output operation mode
In this mode, PPG0 and PPG1 are combined to be oper ated as a 1-CH 8/16-bit PPG timer operating as a 16-
bit timer. Because PPG0 and PPG1 outputs are reversed by an underflow from PPG1 outputting the same
output pulses from PPG0 and PPG1 pins.
• 8 + 8-bit PPG timer output operation mode
In this mode, PPG0 is oper ated as an 8-bit communications prescaler, in which an underflow output of PPG0
is used as a clock source for PPG1. A toggle output of PPG0 and PPG output of PPG1 are output from PPG0
and PPG1 respectively.
• PPG output operation
A pulse wave with any per iod/duty ratio is output. The module can also be used as a D/A conver ter with an
external add-on circuit.
MB90570 Series
42
(1) Register Configuration
• PPG0, 1 output control register ch.0, ch.1(PPGOE)
• PPG0 reload register H ch.0 (PRLH0)
Address
000046H
bit 15 bit 8
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 — —(Disabled)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W R/W R/W R/W R/W R/W — —
............
bit 7 bit 0bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............
(PRLH0)
R/W R/W R/W R/W R/W R/W R/W R/W
000000XXB
bit 7 bit 0bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
............
R/W R/W R/W R/W R/W R/W R/W R/W
(PRLL1)
Address
000041H
• PPG1 reload register H ch.1 (PRLH1)
Address
000043H
• PPG0 reload register L ch.0 (PRLL0)
• PPG1 reload register L ch.1 (PRLL1)
Address
000040Hbit 15 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
............
(PRLH1)
R/W R/W R/W R/W R/W R/W R/W R/W
Address
000042Hbit 15 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
............
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
XXXXXXXXB
Initial value
XXXXXXXXB
Initial value
• PPG0 operating mode control register ch.0 (PPGC0)
Address
000044HPEN0 — PE00 PIE0 PUF0 — — RESV(PPGC1) 0X000XX1B
Initial value
bit 15 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
............
R/W — R/W R/W R/W — — —
bit 7 bit 0bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............
R/W R/W R/W R/W R/W R/W R/W R/W
(PPGC0)
Address
000045H0X000001B
Initial value
PEN1 — PEI0 PIE1 PUF1 MD1 MD0 RESV
• PPG1 operating mode control register ch.1 (PPGC1)
R/W:Readable and writable
—:Reserved
X:Undefined
RESV: Reserved bit
(PRLL0)
XXXXXXXXB
Initial value
XXXXXXXXB
Initial value
MB90570 Series
43
(2) Block Diagram
•Block diagram of 8/16-bit PPG timer (ch.0)
PRLH0
Timebase timer output (512/HCLK)
PEN0
Data bus for “H” digits
— PE00 PIE0 PUF0 — — RESV
Data bus for “L” digits
PPG0 operating mode
control register ch.0 (PPGC0)
PPG0 reload
register
PRLL0
Temporary buffer
(PRLBH0)
Reload register
(L/H selector)
Down counter
(PCNT0)
Count value
Clear
CLK
2
Select signal
Re-load
Underflow Pulse selector
PPG0
output latch
Reverse
PPG output
control circuit
Mode control signal
Pin
P46/PPG0
Count
clock
selector
PPG1 underflow
PPG0 underflow
(to PPG1)
Select signal
*:Interrupt number
HCLK:Oscillation clock
φ:Machine clock frequency
3
R
SQ Interrupt request
#26*
PCM2 PCM1 PCM0
Peripheral clock (16/φ)
Peripheral clock (8/φ)
Peripheral clock (4/φ)
Peripheral clock (2/φ)
Peripheral clock (1/φ)
PPG0 output
control register
ch.0 (PPGOE0)
MB90570 Series
44
•Block diagram of 8/16-bit PPG timer (ch.1)
*:Interrupt number
HCLK:Oscillation clock
φ:Machine clock frequency
PEN1
Data bus for “H” digits
Data bus for “L” digits
PPG1 operating mode
control register ch.1 (PPGC1)
PPG1
output latch
2
Reverse
Count clock selector
Select signal
PPG0 underflow
Interrupt request
#28*
Timebase timer output (512/HCLK)
Peripheral clock (16/φ)
Peripheral clock (8/φ)
Peripheral clock (4/φ)
Peripheral clock (2/φ)
Peripheral clock (1/φ)
—PEI0 PIE1 PUF1 MD1 MD0 RESV PCS2PCS1 PCS0
PPG1 output control
register ch.1 (PPGOE1)
PPG1 underflow
(to PPG0)
PRLH1 PRLL1
Temporary buffer
(PRLBH1)
Reload selector
(L/H selector)
Down counter
(PCNT1) Pin
Count value Clear
Select signal
Re-load
Underflow
PPG output control circuit P47/PPG1
PPG1 reload
register
Operating mode
control signal
CLK MD0
R
SQ
MB90570 Series
45
5. 16-bit I/O timer
The 16-bit I/O timer module consists of one 16-bit free run timer, two input capture circuits, and four output
comparators. This module allows two independent wavefo rms to be output on the basis of the 16-bit free r un
timer. Input pulse width and external clock periods can, therefore, be measured.
•Bloc k Diagram
Internal data bus
Input capture 16-bit
free run timer Output compare
Dedicated
bus Dedicated
bus
MB90570 Series
46
(1) 16-bit free run Timer
The 16-bit free run timer consists of a 16-bit up counter, a control register, and a communications prescaler
register. The value output from the timer counter is used as basic timer (base timer) f or input capture (ICU) and
output compare (OCU).
• A counter operation clock can be selected from four internal clocks (φ/4, φ/16, φ/32 and φ/64).
• An interrupt can be generated by overflow of counter value or compare match with OCU compare register 0.
(Compare match requires mode setup.)
• The counter value can be initialized to “0000H” by a reset, software clear or compare match with OCU compare
register 0.
•Register Configuration
•Bloc k Diagram
• free run timer data register (TCDT)
bit 15 bit 8
• free run timer control status register (TCCS)
IVFRESV
(Disabled)
R/W R/W R/W R/W R/W R/W R/W R/W
bit 7 bit 6 bit 5 bit 4 Initial value
00000000B
STOPIVFE CLRMODE CLK0CLK1
............. bit 3 bit 2 bit 1 bit 0
R/W: Readable and writable
RESV: Reserved bit
Address
000058H
Address
000056H
000057H
bit 15 Initial value
00000000B
bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
T15 T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0
free run timer data register (TCDT)
16-bit free run timer
interrupt request
#20*
*:Interrupt number
φ:Machine clock frequency
OF:Overflow
2
OF
free run timer
control status register
(TCCS)
φ
16-bit counter
STOPCLK CLR
Communications
prescaler register
RESV IVF IVFE STOP MODE CLR CLK1 CLK0
OCU compare register
ch.0 match signal
Internal data bus
Count value output
to ICO and OCU
MB90570 Series
47
(2) Input Capture (ICU)
The input capture (ICU) generates an interrupt request to the CPU simultaneously with a storing operation of
current counter v alue of the 16-bit free run timer to the ICU data register (IPCP) upon an input of a trigger edge
to the external pin.
There are f our sets (f our channels) of the input capture external pins and ICU data registers, enab ling measure-
ments of maximum of four events.
• The input capture has two sets of external input pins (IN0, IN1) and ICU registers (IPCP), enabling measure-
ments of maximum of four events.
• A trigger edge direction can be selected from rising/falling/both edges.
• The input capture can be set to generate an interrupt request at the storage timing of the counter v alue of the
16-bit free run timer to the ICU data register (IPCP).
• The input compare conforms to the extended intelligent I/O service (EI2OS).
• The input capture (ICU) function is suited for measurements of intervals (frequencies) and pulse widths.
•Register Configuration
• ICU data register ch.0, ch.1 (IPCP0, IPCP1)
Address Initial value
XXXXXXXXB
CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 (IPCP0 low, IPCP1 low)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 0
.............
RR RRRR RR
Address
CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00
(IPCP0 high, IPCP1 high)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0bit 15 bit 8
............
RR RRRR RR
• ICU control status register (ICS01)
R/W:Readable and writable
R:Read only
X:Undefined
000051H
000053H
Address
000054H
Initial value
00000000B
ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00
(Disabled)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0bit 15 bit 8
............
R/W R/W R/W R/W R/W R/W R/W R/W
000050H
000052H
Note: This register holds a 16-bit free run timer value when the valid edge of the corresponding external pin input waveform is
detected. (You can word-access this register, but you cannot program it.)
Initial value
XXXXXXXXB
IPCP0(low):
IPCP1(low):
IPCP0(high):
IPCP1(high):
MB90570 Series
48
•Bloc k Diagram
Internal data bus
Edge detection circuit
Data latch signal
Latch
signal
Output latch ICU data register (IPCP)
IPCP0H IPCP0L 16
16 16-bit free run
2
2
P56/IN0
Pin
Pin
Interrupt request
#12*
ICP1
P57/IN1
IPCP1H IPCP1L
ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00
Interrupt request
#14*
*: Interrupt number
ICU control status register (ICS01)
MB90570 Series
49
(3) Output Compare (OCU)
The output compare (OCU) is two sets of compare units consisting of four-channel OCU compare registers, a
comparator and a control register.
An interrupt request can be generated for each channel upon a match detection by performing time-division
comparison between the OCU compare data register setting value and the counter value of the 16-bit free run
timer.
The OUT pin can be used as a wavefor m output pin for reversing output upon a match detection or a general-
purpose output port for directly outputting the setting value of the CMOD bit.
•Register Configuration
— — — CMOD OTE1 OTE0 OTD1 OTD0 (OCS0, OCS2)
• OCU control status register ch.1, ch.3 (OCS1, OCS3)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 0
— — — R/W R/W R/W R/W R/W
Address Initial value
- - -00000B
.............
ICP1 ICP0 ICE1 ICE0 — — CST1 CST0(OCS1, OCS3)
• OCU control status register ch.0, ch.2 (OCS0, OCS2)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0bit 15 bit 8
R/W R/W R/W R/W — — R/W R/W
............
C15 C14 C13 C12 C11 C10 C09 C08
• OCU compare register ch.0 to ch.3 (OCCP0 to OCCP3)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
XXXXXXXXB
C07 C06 C05 C04 C03 C02 C01 C00
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
R/W:Readable and writable
—:Reserved
X:Undefined
000063H
000065H
Initial value
0000- -00B
Address
000062H
000064H
Initial value
XXXXXXXXB
Address
OCCP0 (high order address): 00005BH
OCCP1 (high order address): 00005DH
OCCP2 (high order address): 00005FH
OCCP3 (high order address): 000061H
Address
OCCP0 (low order address): 00005AH
OCCP1 (low order address): 00005CH
OCCP2 (low order address): 00005EH
OCCP3 (low order address): 000060H
MB90570 Series
50
•Bloc k diagram
OCU control
status register ch.0, ch.1 (OCS0, OCS1)
16-bit free run timer
—
Compare control circuit 3
OCCP3
#18*
#17* Output compare
interrupt request
Output
control circuit 3 Pin
P67/OUT3
*: Interrupt number
22
— — CMOD OTE1 OTE0 OTD1 OTD0 ICP1 ICP0 ICE1 ICE0 — — CST1 CST0
OCU compare register ch.3
Compare control circuit 2
OCCP2
OCU compare register ch.2
Compare control circuit 1
OCU compare register ch.1
Compare control circuit 0
OCU compare register ch.0
OCCP1
OCCP0
Internal data bus
OCU control status register
ch.2, ch.3 (OCS2, OCS3)
— — — CMOD OTE1 OTE0 OTD1 OTD0 ICP1 ICP0 ICE1 ICE0 — — CST1 CST0
#16*
#15*
Output compare
interrupt request
Output
control circuit 2
Output
control circuit 1
Output
control circuit 0
Pin
P65/OUT1
Pin
P66/OUT2
Pin
P64/OUT0
22
MB90570 Series
51
6. 8/16-bit up/down counter/timer
The 8/16-bit up/down counter/timer consists of six event input pins, two 8-bit up/down counters, two 8-bit
reload compare registers, and their controllers.
(1) Register configuration
000076H
00007AH
• Up/down count register 1 (UDCR1) bit 7 bit 0
Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............. Initial value
00000000B
D17 D16 D15 D14 D13 D12 D11 D10 (UDCR0)
RRRRRRRR
• Up/down count register 0 (UDCR0)
bit 15 bit 8
Address
D06D07
(UDCR1)
RRRRRRRR
bit 7 bit 6 bit 5 bit 4
D04D05 D02D03 D00D01
............ bit 3 bit 2 bit 1 bit 0
000070H
Initial value
00000000B
000071H
• Reload compare register 1 (RCR1) bit 7 bit 0
Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............. Initial value
00000000B
D17 D16 D15 D14 D13 D12 D11 D10 (RCR0)
WWWWWWWW
• Reload compare register 0 (RCR0)
bit 15 bit 8
Address
D06D07
(RCR1)
WWWWWWWW
bit 7 bit 6 bit 5 bit 4
D04D05 D02D03 D00D01
............ bit 3 bit 2 bit 1 bit 0
000072H
Initial value
00000000B
000073H
• Counter status register 0, 1 (CSR0, CSR1)
bit 15 bit 8
Address
CITECSTR
(Reserved area)
R/W R/W R/W R/W R/W R/W R R
bit 7 bit 6 bit 5 bit 4
CMPFUDIE UDFFOVFF UDF0UDF1
............ bit 3 bit 2 bit 1 bit 0
000074H
000078H
Initial value
00000000B
• Counter control register 0, 1 (CCRL0, CCRL1)
bit 15 bit 8
Address
CTUT
—
(CCRH0, CCRH1)
—R/W R/W R/W R/W R/W R/W R/W
bit 7 bit 6 bit 5 bit 4
RLDEUCRE CGSCUDCC CGE0CGE1
............ bit 3 bit 2 bit 1 bit 0 Initial value
-0000000B
• Counter control register 0 (CCRH0) bit 7 bit 0
Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............. Initial value
00000000B
M16E CDCF CFIE CLKS CMS1 CMS0 CES1 CES0 (CCRL0)
R/W R/W R/W R/W R/W R/W R/W R/W
000077H
• Counter control register 1 (CCRH1) bit 7 bit 0
Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............. Initial value
-0000000B
—CDCF CFIE CLKS CMS1 CMS0 CES1 CES0 (CCRL1)
—R/W R/W R/W R/W R/W R/W R/W
00007BH
R/W:Readable and writable
R:Read only
W:Write only
—:Undefined
MB90570 Series
52
(2) Block Diagram
•Block diagram of 8/16-bit up/down counter/timer 0
Internal data bus
RCR0
Reload compare register 0 Re-load
control
circuit
Up/down count register 0
UDCR0 CARRY/
BORRW
Counter control
register 0 (CCRL0)
—CTUT CGE1 CGE0UCRE UDCCRLDE CGSC
PA2/ZIN0
Pin Edge/level
detection circuit
Counter clear
circuit
Overflow
Underflow
Compare
control circuit
Prescaler
PA0/AIN0/IRQ6
Pin
Pin
PA1/BIN0
UP/down count
clock selector
Counter status
register 0 (CSR0)
Count clock
CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0
M16E CDCF CES1 CES0CFIE CMS1CLKS CMS0
Interrupt request
#29*
Interrupt request
#30*
Counter control register 0 (CCRH0) M16E
(to channel 1)
(to channel 1)
*:Interrupt number
φ:Machine clock frequency
φ
MB90570 Series
53
•Block diagram of 8/16-bit up/down counter/timer 1
Internal data bus
RCR1
Reload compare register 1
Re-load
control
circuit
Up/down count register 1
UDCR1
Counter control
register 1 (CCRL1)
—CTUT CGE1 CGE0UCRE UDCCRLDE CGSC
PA5/ZIN1
Pin Edge/level
detection circuit
Counter clear
circuit
Overflow
Underflow
Compare
control circuit
φ
PA3/AIN1/IRQ7
Pin
Pin
PA4/BIN1
CARRY/BORRW
(from channel 0)
UP/down count
clock selector
Counter status
register 1 (CSR1)
Count clock
CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0
—CDCF CES1 CES0CFIE CMS1CLKS CMS0
Interrupt request
#31*
Interrupt request
#32*
Counter control register 1 (CCRH1)
(from channel 1)
*:Interrupt number
φ:Machine clock frequency
M16E
Prescaler
MB90570 Series
54
7. Extended I/O serial interface
The extended I/O serial interface transfers data using a clock synchronization system having an 8-bit x 1 channel
configuration.
For data transfer, you can select LSB first/MSB first.
(1) Register Configuration
• Serial mode control upper status register 0 to 2 (SMCSH0 to SMCSH2)
• Serial mode control lower status register 0 to 2 (SMCSL0 to SMCSL2)
• Serial data register 0 to 2 (SDR0 to SDR2)
bit 7 bit 0
Address
SMCSH0: 000049H
SMCSH1: 00004DH
SMCSH2: 00007DH
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............. Initial value
00000010B
SMD2 SMD1 SMD0 SIE SIR BUSY STOP STRT (SMCSL)
R/W R/W R/W R/W R/W R R/W R/W
bit 15 bit 8
Address
——
(SMCSH) ————
R/W R/W R/W R/W
bit 7 bit 6 bit 5 bit 4
—— BDSMODE SCOESOE
............ bit 3 bit 2 bit 1 bit 0
SMCSL0: 000048H
SMCSL1: 00004CH
SMCSL2: 00007CH
Initial value
- - - -0000B
bit 15 bit 8
Address
D6D7
(Disabled)
R/W R/W R/W R/W R/W R/W R/W R/W
bit 7 bit 6 bit 5 bit 4
D4D5 D2D3 D0D1
............ bit 3 bit 2 bit 1 bit 0
SDR0: 00004AH
SDR1: 00004EH
SDR2: 00007EH
Initial value
XXXXXXXXB
R/W:Readable and writable
R:Read only
—:Reserved
X:Undefined
MB90570 Series
55
(2) Block Diagram
Internal data bus
Pin
(MSB first) D0 to D7 D7 to D0 (LSB first)
Transfer direction selection
Serial data register
(SDR)
Read
Write
Shift clock counter
P44/SOT1
P51/SOT2
Pin
P43/SIN1
P50/SIN2
Pin
Pin
Pin
P45/SCK1
P52/SCK2
Pin
Control circuit
Internal clock
210
SMD2 SMD1 SMD0 SIE SIR BUSY STOP STRT ————
MODE BDS SOE SCOE
Interrupt request
#19 (SMCS0)*
#21 (SMCS1)*
#23 (SMCS2)*
*: Interrupt number
Serial mode control
status register (SMCS)
Pin
P42/SCK0
Pin
P40/SIN0
P41/SOT0
Pin
MB90570 Series
56
8. I2C Interface
The I2C interface is a serial I/O port supporting Inter IC BUS operating as master/slave devices on I2C bus.
The MB90570/A series contains one channel of an I2C interface, having the following features.
• Master/sla ve transmission/reception
• Arbitration function
• Clock synchronization function
• Slave address/general call address detection function
• Transmission direction detection function
• Repeated generation function start condition and detection function
• Bus error detection function
(1) Register Configuration
. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . . . . .
•I
2C b us status register (IBSR)
bit 15 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
(IBCR)
BER BEIE SCC MSS ACK GCAA INTE INT
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 0
RRRRRRRR
R/W R/W R/W R/W R/W R/W R/W R/W
BB RSC AL LRB TRX AAS GCA FBT
(IBSR)
Initial value
00000000B
Address
000068H
Address
000069H
Initial value
00000000B
bit 15 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
(IADR)
——R/W
— — EN CS4 CS3 CS2 CS1 CS0
Initial value
--0XXXXXB
Address
00006AH
R/W R/WR/W R/W R/W
•I
2C bus control register (IBCR)
•I
2C bus clock control register (ICCR)
—A6A5A4A3A2A1A0
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 0
— R/W R/W R/W R/W R/W R/W R/W
(ICCR)
Address
00006BH
Initial value
-XXXXXXXB
bit 15 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
(Disabled) D7
Initial value
XXXXXXXXB
Address
00006CH
R/W R/WR/W R/W R/W
D6 D5 D4 D3 D2 D1 D0
R/WR/WR/W
R/W: Readable and writable
R: Read only
—: Reserved
X: Indeterminate
•I
2C bus address register (IADR)
•I
2C bus data register (IDAR)
MB90570 Series
57
(2) Block Diagram
Internal data bus
I2C bus control register
(IBCR) I2C bus status register
(IBSR)
BER BEIE SCC MSS ACK
GCAA INTE
INT BB RSC AL LRB TRX AAS GCA FBT
Error
Start
Master
ACK enable
GC-ACK enable
Interrupt enable
Transmission
complete flag
Bus busy
Repeat start
Last bit
Transmit/receive
Slave
General call
Detection of first byte
Number of
interrupt
request
generated
Start stop condition
generation circuit Start stop condition
detection circuit
Interrupt request signal
#36*
SDA line
SCL line Pin
Pin
PA7/SCL
I2C enable
IDAR register
Slave address
comparison circuit
IADR register
Arbitration lost
detection circuit
Clock control block
4
φ
Clock
divider 1
(1/5 to
1/8)
Count
clock
selector 1
Clock
divider 2
Count
clock
selector 2
Shift clock
generation
circuit
Sync
8
I2C enable
— — EN CS4 CS3 CS2 CS1 CS0
I2C bus clock control register
(ICCR)
φ:Machine clock frequency
*:Interrupt number
PA6/SDA
MB90570 Series
58
9. UART0 (SCI), UART1 (SCI)
UART0 (SCI) and UART 1 (SCI) are general-pur pose ser ial data communication interfaces for performing syn-
chronous or asynchronous communication (start-stop synchronization system).
• Data buffer: Full-duplex double buffer
• Transfer mode: Clock synchronized (with start and stop bit)
Clock asynchronized (start-stop synchronization system)
• Baud rate: Embedded dedicated baud rate generator
External clock input possible
Internal clock (a clock supplied from 8-bit PPG timer ch1 or 16-bit PPG timer can be used.)
• Data length: 7 bit to 9 bit selectiv e (without a parity bit)
6 bit to 8 bit selective (with a parity bit)
• Signal format: NRZ (Non Return to Zero) system
• Reception error detection:Framing error
Overrun error
Par ity error (multi-processor mode is supported, enabling setup of any baud rate
by an external clock.)
• Interrupt request:Receive interrupt (receive complete, receive error detection)
Transmit interrupt (transmission complete)
Transmit/receive conforms to extended intelligent I/O service (EI2OS)
Asynchronization 9615 bps/31250 bps/4808 bps/2404 bps/1202 bps
CLK synchronization 1 Mbps/500 kbps/250 kbps/125 kbps/62.5 kbps}Internal machine clock
For 6 MHz, 8 MHz, 10 MHz
12 MHz and 16 MHz
MB90570 Series
59
(1) Register Configuration
• Serial control register 0,1 (SCR0, SCR1)
PEN P SBL CL A/D REC RXE TXE
Address
000021H
000025H(SMR0, SMR1)
bit 7 bit 0
.............
• Serial mode register 0, 1 (SMR0, SMR1)
MD1 MD0 CS2 CS1 CS0 RESV SCKE SOE
Address
000020H
000024H(SCR0, SCR1)
bit 15 bit 8
............
• Serial status register 0,1 (SSR0, SSR1)
Address
000023H
000027H
• Serial input data register 0,1 (SIDR0, SIDR1)
Address
000022H
000026H
• Serial output data register 0,1 (SODR0, SODR1)
Address
000022H
000026H
R/W R/W R/W R/W R/W W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
PE ORE FRE RDRF TRDE — RIE TIE
bit 7 bit 0
.............
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
(SIDR0, SIDR1/SODR0,SODR1)
RR RRR—R/WR/W
D7 D6 D5 D4 D3 D2 D1 D0(SSR0, SSR1)
bit 15 bit 8
............
RRRRRRRR
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
D7 D6 D5 D4 D3 D2 D1 D0(SSR0, SSR1)
bit 15 bit 8
............
WWWWWWWW
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
MD — — — DIV3 DIV2 DIV1 DIV0(Disabled)
bit 15 bit 8
............
R/W — — — R/W R/W R/W R/W
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
• Communications prescaler control register 0,1 (CDCR0, CDCR1)
Address
000028H
00002AH
Initial value
00000100B
Initial value
00000000B
Initial value
00001-00B
Initial value
XXXXXXXXB
Initial value
XXXXXXXXB
Initial value
0- - -1111B
R/W :Readable and writable
R :Read only
W :Write only
—:Reserved
X :Undefined
RESV: Reserved bit
MB90570 Series
60
(2) Block Diagram
•UART0 (SCI)
Clock
selector
Dedicated baud
rate generator
8/16-bit PPG
timer 1 (upper)
External clock
P42/SCK0
Pin
P40/SIN0
Receive condition
decision circuit
SMR0
register SCR0
register SSR0
register
Receive
clock Receive
control circuit
Start bit
detection circuit
Receive bit
counter
Receive parity
counter
Shift register for
reception
SIDR0 SODR0
Transmit
clock
Transmit
control circuit
Transmit start
circuit
Transmit bit
counter
Transmit parity
counter
Shift register for
transmission
Receive
interrupt signal
#39*
Transmit
interrupt signal
#40*
P41/SOT0
Start transmission
To I2C reception
error generation
signal (to CPU)
Internal data bus
MD1
MD0
CS2
CS1
CS0
SCKE
SOE
PEN
P
SBL
CL
A/D
REC
RXE
TXE
PE
FRE
RDRF
TDRE
RIE
TIE
*: Interrupt number
Control bus
Reception
complete
ORE
Pin
Pin
MB90570 Series
61
•UART1 (SCI)
Clock
selector
Dedicated baud
rate generator
8/16-bit PPG
timer 1 (upper)
P45/SCK1
Pin
P43/SIN1
Receive condition
decision circuit
SMR1
register SCR1
register SSR1
register
Receive
clock Receive
control circuit
Start bit
detection circuit
Receive bit
counter
Receive parity
counter
Shift register for
reception
SIDR1 SODR1
Transmit
clock
Transmit
control circuit
Transmit start
circuit
Transmit bit
counter
Transmit parity
counter
Shift register for
transmission
Receive
interrupt signal
#37*
Transmit
interrupt signal
#38*
P44/SOT1
Start transmission
To EI2OS reception
error generation
signal (to CPU)
Internal data bus
MD1
MD0
CS2
CS1
CS0
SCKE
SOE
PEN
P
SBL
CL
A/D
REC
RXE
TXE
PE
FRE
RDRF
TDRE
RIE
TIE
*: Interrupt number
Control bus
Reception
complete
ORE
Pin
Pin
MB90570 Series
62
10. DTP/External Interrupt Circuit
DTP (Data Transfer Peripheral), which is located between the peripheral circuit outside the device and the
F2MC-16LX CPU , receiv es an interrupt request or DMA request generated by the e xternal peripheral circuit* f or
transmission to the F2MC-16LX CPU. DTP is used to activate the intelligent I/O service or interrupt processing.
As request le vels f or IRQ2 to IRQ7, two types of “H” and “L” can be selected f or the intelligent I/O service. Rising
and falling edges as well as “H” and “L” can be selected for an external interrupt request. For IRQ0 and IRQ1,
a request by a level cannot be entered, but both edges can be entered.
* : The external peripheral circuit is connected outside the MB90570/A series device.
Note : IRQ0 and IRQ1 cannot be used for the intelligent I/O service and return from an interrupt.
(1) Register Configuration
• DTP/interrupt factor register (EIRR)
Address
000031H
bit 7 bit 0
ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............
(ENIR) Initial value
XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
Address
000030H
bit 15 bit 8
EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0(EIRR)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
............
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
00000000B
Address
Low order address 000032H
bit 15 bit 8
LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0(ELVR upper)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
............
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
00000000B
• DTP/interrupt enable register (ENIR)
R/W:Readable and writable
X:Undefined
Address
High order address 000033HLB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 (ELVR lower) Initial value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
• Request level setting register (ELVR)
bit 7 bit 0bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............
MB90570 Series
63
(2) Block Diagram
Request level setting register (ELVR)
LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0
2222
22
Level edge
selector 7 Level edge
selector 5 Level edge
selector 3 Level edge
selector 1
Level edge
selector 6 Level edge
selector 4 Level edge
selector 2 Level edge
selector 0
DTP/external interrupt
input detection circuit
ER7 ER0ER6ER5ER4ER3ER2ER1
EN7 EN0EN6EN5EN4EN3EN2EN1
DTP/interrupt factor register (EIRR)
Interrupt request signal
#35*
#33*
#27*
#25*
#24*
#13*
DTP/interrupt enable register (ENIR)
22
Internal data bus
Pin
PA3/AIN1/IRQ7
Pin
PA0/AIN0/IRQ6
Pin
PB5/IRQ5
Pin
PB4/IRQ4
Pin
PB3/IRQ3
Pin
PB2/IRQ2
Pin
PB1/IRQ1
Pin
PB0/IRQ0
*: Interrupt number
MB90570 Series
64
11. Delayed Interrupt Generation Module
The dela yed interrupt generation module generates interrupts for s witching tasks for de velopment on a real-time
operating system (REALOS series). The module can be used to generate softwarewise generates hardware
interrupt requests to the CPU and cancel the interrupts.
This module does not conform to the extended intelligent I/O service (EI2OS).
(1) Register Configuration
The DIRR is the register used to control delay interrupt request generation/cancellation. Programming this
register with “1” generates a dela y interrupt request. Programming this register with “0” cancels a dela y interrupt
request. Upon a reset, an interrupt is canceled. The reserv ed bit area can be programmed with either “0” or “1”.
For future extension, however, it is recommended that bit set and clear instructions be used to access this register.
(2) Block Diagram
• Delayed interrupt factor generation/cancellation register (DIRR)
Address
00009FH
bit 7 bit 0
———————R0
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............
(PACSR)
———————R/W
Initial value
-------0B
R/W:Readable and writable
—:Reserved
Note: Upon a reset, an interrupt is canceled.
Delayed interrupt factor generation/
cancellation register (DIRR)
*: Interrupt number
—S factor
R latch
——————R0
Internal data bus
Interrupt request signal
#42*
MB90570 Series
65
12. 8/10-bit A/D Converter
The 8/10-bit A/D converter has a function of converting analog voltage input to the analog input pins (input
voltage) to digital values (A/D conversion) and has the following features.
• Minimum conversion time: 26.3 µs (at machine clock of 16 MHz, including sampling time)
• Minimum sampling time: 4 µs/256 µs (at machine clock of 16 MHz)
• Compare time: 176/352 machine cycles per channel (176 machine cycles are used for a machine cloc k below
8 MHz.)
• Conversion method: RC successive approximation method with a sample and hold circuit.
• 8-bit or 10-bit resolution
• Analog input pins: Selectable from eight channels by software
Single conversion mode: Selects and converts one channel.
Scan conversion mode:Converts two or more successive channels. Up to eight channels can be programmed.
Continuous conversion mode: Repeatedly converts specified channels.
Stop conversion mode:Stops conversion after completing a conversion for one channel and wait for the next
activation (conversion can be started synchronously.)
• Interrupt requests can be generated and the e xtended intelligent I/O service (EI2OS) can be started after the
end of A/D conversion. Furthermore, A/D conversion result data can be transferred to the memory, enabling
efficient continuous processing.
• When interrupts are enabled, there is no loss of data even in continuous operations because the conversion
data protection function is in effect.
• Starting factors for conversion: Selected from software activation, and external trigger (falling edge).
MB90570 Series
66
(1) Register Configuration
• A/D control status register upper digits (ADCS2)
Address
000037H
bit 7 bit 0
BUSY INT INTE PAUS STS1 STS0 STRT RESV
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............
(ADCS1)
R/W R/W R/W R/W R/W R/W W R/W
Address
000036H
bit 15 bit 8
MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0(ADCS2)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
............
R/W:Readable and writable
R :Read only
W :Write only
—:Reserved
X:Undefined
RESV: Reserved bit
• A/D control status register lower digits (ADCS1)
• A/D data register upper digits (ADCR2)
Initial value
00000000B
Initial value
00000000B
Address
000039H
bit 7 bit 0
DSEL ST1 ST0 CT1 XCT0 — D9 D8
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............
(ADCR1)
WWWWW———
Address
000038H
bit 15 bit 8
D7 D6 D5 D4 D3 D2 D1 D0(ADCR2)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
RRRRRRRR
............
• A/D data register lower digits (ADCR1)
Initial value
XXXXXXXXB
Initial value
00001-XXB
MB90570 Series
67
(2) Block Diagram
φ:Machine clock frequency
TO:8/16-bit PPG timer channel 1 output
*:Interrupt number
Interrupt request #11*
Clock selector Decoder
Sample hold
circuit Control circuit
8-bit D/A converter
Analog
channel
selector
Comparator
A/D data register
(ADCR)
AVRH, AVRL
AVCC
AVSS
PB6/ADTG
TO
A/D control status
register (ADCS)
BUSY INT INTE PAUS STS1 STS0 STRT DA MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
RESV ST1ST0CT1CT0—D9D8D7D6D5D4D3D2D1D0
P87/AN7
P86/AN6
P85/AN5
P84/AN4
P83/AN3
P82/AN2
P81/AN1
P80/AN0
2
6
φ
Internal data bus
MB90570 Series
68
13. 8-bit D/A Converter
The 8-bit D/A conver ter, which is based on the R-2R system, suppor ts 8-bit resolution mode. It contains two
channels each of which can be controlled in terms of output by the D/A control register.
(1) Register Configuration
bit 7 bit 0bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............
bit 15 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
............
bit 7 bit 0bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............
bit 15 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
............
• D/A converter data register ch.0 (DADR0)
Address
00003AH
DA17 DA16 DA15 DA14 DA13 DA12 DA11 DA10 (DADR0)
R/W R/W R/W R/W R/W R/W R/W R/W
Address
00003BH
DA07 DA06 DA05 DA04 DA03 DA02 DA01 DA00(DADR1)
R/W R/W R/W R/W R/W R/W R/W R/W
R/W:Readable and writable
—:Reserved
X:Undefined
• D/A converter data register ch.1 (DADR1)
• D/A control register 0 (DACR0)
Initial value
XXXXXXXXB
Initial value
XXXXXXXXB
Address
00003CH
Address
00003DH
• D/A control register 1 (DACR1)
Initial value
-------0B
Initial value
-------0B
— — — — — — — DAE0(DACR1)
———————DAE1 (DACR0)
———————R/W
———————R/W
MB90570 Series
69
(2) Block Diagram
DA17
Internal data bus
Internal data bus
D/A converter data register ch.1 (DADR1) D/A converter data register ch.0 (DADR0)
DA16 DA15 DA14 DA13 DA12 DA11 DA10 DA07 DA06 DA05 DA04 DA03 DA02 DA01 DA00
D/A converter 1 D/A converter 0
DA17
DA16
DA15
DA14
DA13
DA12
DA11
DA10
DA07
DA06
DA05
DA04
DA03
DA02
DA01
DA00
DVRH DVRL
2R R
2R R
2R R
2R R
2R R
2R R
2R R
2R2R
DVSS
2R R
2R R
2R R
2R R
2R R
2R R
2R R
DVSS
Pin
P74/DA1 Pin
P73/DA0
Standby control
D/A control register 1 (DACR1)
Standby control
D/A control register 0 (DACR0)
———————
DAE1
———————
DAE0
2R2R
MB90570 Series
70
14. Clock Timer
The clock timer control register (WTC) controls operation of the clock timer, and time for an interval interrupt.
(1) Register Configuration
(2) Block Diagram
• Clock timer control register (WTC)
Address
0000AAH
bit 15 bit 8
WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0(Disabled)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W R R/W R/W R/W R R/W R/W
............
R/W:Readable and writable
R:Read only
X:Undefined
Initial value
1X000000B
Clock counter
LCLK
Power-on reset
Shift to a hardware standby
Shift to stop mode
Counter
clear circuit
Interval
timer selector
Clock timer interrupt request
#22*
Clock timer control register (WTC)
WDCS
To sub-clock oscillation stabilization
time controller
To watchdog timer
× 21× 22× 23× 24× 25× 26× 27× 28× 29× 210 × 211 × 212 × 213 × 214 × 215
OF OF OF OF OF OF OF
SCE WTIE WTOF WTR WTC2 WTC1 WTC0
*:Interrupt number
OF:Overflow
LCLK:Oscillation sub-clock frequency
MB90570 Series
71
15. Chip Select Output
This module generates a chip select signal f or f acilitating a memory and I/O unit, and is provided with eight chip
select output pins. When access to an address is detected with a hardw are-set area set for each pin register, a
select signal is output from the pin.
(1) Register Configuration
• Chip selection control register 1, 3, 5, 7 (CSCR1, CSCR3, CSCR5, CSCR7)
Address
CSCR1: 000081H
CSCR3: 000083H
CSCR5: 000085H
CSCR7: 000087H
bit 7 bit 0
— — — — ACTL OPEL CSA1 CSA0
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............
(CSCR0, CSCR2, CSCR4, CSCR6)
— — — — R/W R/W R/W R/W
bit 15 bit 8
(CSCR1, CSCR3, CSCR 5, CSCR7)
bit 7 bit 6 bit 5 b it 4 bit 3 bit 2 bit 1 bit 0
............
R/W:Readable and writable
—:Reserved
• Chip selection control register 0, 2, 4, 6 (CSCR0, CSCR2, CSCR4, CSCR6)
Initial value
----0000B
Initial value
----0000B
— — — — R/W R/W R/W R/W
— — — — ACTL OPEL CSA1 CSA0
Address
CSCR0: 000080H
CSCR2: 000082H
CSCR4: 000084H
CSCR6: 000086H
MB90570 Series
72
(2) Block Diagram
A23 A22 ⋅ ⋅ ⋅ ⋅ ⋅ A17 A16
Address decoder
A15 A14 ⋅ ⋅ ⋅ ⋅ ⋅ A01 A00
2
Address decoder
Decode signal
Decode
Program area
Chip selection control register 0 (CSCR0)
P90/CS0
(Program ROM area application)
P91/CS1
P92/CS2
P93/CS3
P94/CS4
P95/CS5
P96/CS6
P97/CS7
Selector
Selector
Selector
Selector
Selector
Selector
Selector
Selector
Select and set
Select and set
Select and set
Select and set
Select and set
Select and set
Select and set
Chip selection control register 1 (CSCR1)
Chip selection control register 2 (CSCR2)
Chip selection control register 3 (CSCR3)
Chip selection control register 4 (CSCR4)
Chip selection control register 5 (CSCR5)
Chip selection control register 6 (CSCR6)
Chip selection control register 7 (CSCR7)
From address (CPU)
Select and set
MB90570 Series
73
(3) Decode Address Spaces
Pin
name CSA Decode space Number of
area bytes Remarks
10
CS0
0 0 F00000H to FFFFFFH1 Mbyte
Becomes active when the program ROM
area or the program vector is fetched.
0 1 F80000H to FFFFFFH512 kbyte
1 0 FE0000H to FFFFFFH128 kbyte
11 — Disabled
CS1
0 0 E00000H to EFFFFFH1 Mbyte Adapted to the data ROM and RAM areas,
and external circuit connection applica-
tions.
0 1 F00000H to F7FFFFH512 kbyte
1 0 FC0000H to FDFFFFH128 kbyte
1 1 68FF80H to 68FFFFH128 byte
CS2
0 0 003000H to 003FFFH4 kbyte Adapted to the data ROM and RAM areas,
and external circuit connection applica-
tions.
0 1 FA0000H to FBFFFFH128 kbyte
1 0 68FF80H to 68FFFFH128 byte
1 1 68FF00H to 68FF7FH128 byte
CS3
0 0 F80000H to F9FFFFH128 kbyte Adapted to the data ROM and RAM areas,
and external circuit connection applica-
tions.
0 1 68FF00H to 68FF7FH128 byte
1 0 68FE80H to 68FEFFH128 byte
11 — Disabled
CS4
0 0 002800H to 002FFFH2 kbyte Adapted to the data ROM and RAM areas,
and external circuit connection applica-
tions.
0 1 68FE80H to 68FEFFH128 byte
10 — Disabled
11 — Disabled
CS5
0 0 68FF80H to 68FFFFH128 byte Adapted to the data ROM and RAM areas,
and external circuit connection applica-
tions.
01 — Disabled
10 — Disabled
11 — Disabled
CS6
0 0 68FF00H to 68FF7FH128 byte Adapted to the data ROM and RAM areas,
and external circuit connection applica-
tions.
01 — Disabled
10 — Disabled
11 — Disabled
CS7 — — — Disabled Disabled
MB90570 Series
74
16. Communications Prescaler Register
This register controls machine clock division.
Output from the communications prescaler register is used for UART0 (SCI), UART1 (SCI), and extended I/O
serial interface.
The communications prescaler register is so designed that a constant baud rate may be acquired for var ious
machine clocks.
(1) Register Configuration
• Communications prescaler control register 0,1 (CDCR0, CDCR1)
Address bit 15 bit 8
MD — — — DIV3 DIV2 DIV1 DIV0(Disabled)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W — — — R/W R/W R/W R/W
............
R/W:Readable and writable
—:Reserved
Initial value
0- - -1111B
000028H
00002AH
MB90570 Series
75
17. Address Match Detection Function
When the address is equal to a value set in the address detection register, the instruction code loaded into the
CPU is replaced forcibly with the INT9 instruction code (01H). As a result, when the CPU executes a set
instruction, the INT9 instruction is executed. Processing by the INT#9 interrupt routine allows the program
patching function to be implemented.
Two address detection registers are supported. An interrupt enable bit is prepared f or each register. If the value
set in the address detection register matches an address and if the interrupt enable bit is set at “1”, the instruction
code loaded into the CPU is replaced forcibly with the INT9 instruction code.
(1) Register Configuration
• Program address detection register 0 to 2 (PADR0)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value
XXXXXXXXB
R/W:Readable and writable
X :Undefined
RESV:Reserved bit
Address
PADR0 (Low order address): 001FF0H
R/W R/W R/W R/W R/W R/W R/W R/W
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value
XXXXXXXXB
Address
PADR0 (Middle order address): 001FF1H
R/W R/W R/W R/W R/W R/W R/W R/W
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value
XXXXXXXXB
Address
PADR0 (High order address): 001FF2H
R/W R/W R/W R/W R/W R/W R/W R/W
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value
XXXXXXXXB
Address
PADR1 (Low order address): 001FF3H
R/W R/W R/W R/W R/W R/W R/W R/W
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value
XXXXXXXXB
Address
PADR1 (Middle order address): 001FF4H
R/W R/W R/W R/W R/W R/W R/W R/W
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value
XXXXXXXXB
Address
PADR1 (High order address): 001FF5H
R/W R/W R/W R/W R/W R/W R/W R/W
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value
00000000B
Address
00009EH
R/W R/W R/W R/W R/W R/W R/W R/W
• Program address detection register 3 to 5 (PADR1)
• Program address detection control status register (PACSR)
RESV RESV RESV RESV AD1E RESV AD0E RESV
MB90570 Series
76
(2) Block Diagram
Internal data bus
Address latch
Enable bit
F2MC-16LX
CPU core
Address detection
register
Compare
INT9
instruction
MB90570 Series
77
18. ROM Mirroring Function Selection Module
The ROM mirroring function selection module can select what the FF bank allocated the R OM sees through the
00 bank according to register settings.
(1) Register Configuration
Note : Do not access this register during operation at addresses 004000H to 00FFFFH.
(2) Block Diagram
• ROM mirroring function selection register (ROMM)
Address
00006FH
bit 7 bit 0
———————MI
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............
(Disabled)
W:Write only
—:Reserved
Initial value
-------1B
———————W
ROM mirroring function selection
register (ROMM)
Address area
FF bank 00 bank
ROM
Data
Internal data bus
Address
MB90570 Series
78
19. Low-power Consumption (Standby) Mode
The F2MC-16LX has the f ollo wing CPU operating mode configured b y selection of an opera ting clock and cloc k
operation control.
•Clock mode
PLL clock mode: A mode in which the CPU and peripheral equipment are driven b y PLL-multiplied oscillation
clock (HCLK).
Main clock mode:A mode in which the CPU and peripheral equipment are driven by divided-by-2 of the oscil
lation clock (HCLK).
The PLL multiplication circuits stops in the main clock mode.
• CPU intermittent operation mode
The CPU intermittent operation mode is a mode for reducing power consumption by operating the CPU
intermittently while external bus and peripheral functions are operated at a high-speed.
•Hardware standby mode
The hardware standb y mode is a mode for reducing pow er consumption b y stopping cloc k supply to the CPU
by the low-power consumption control circuit, stopping clock supplies to the CPU and peripheral functions
(timebase timer mode), and stopping oscillation cloc k (stop mode, hardware standb y mode). Of these modes,
modes other than the PLL clock mode are power consumption modes.
(1) Register Configuration
• Clock select register (CKSCR)
Address
0000A1H
bit 7 bit 0
SCM MCM WS1 WS0 SCS MCS CS1 CS0
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............
(LPMCR)
R R R/W R/W R/W R/W R/W R/W
Address
0000A0H
bit 15 bit 8
STP SLP SPL RST TMD CG1 CG0 SSR(CKSCR)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
W W R/W W R/W W R/W R/W
............
R/W:Readable and writable
R:Read only
W:Write only
• Low-power consumption mode control register (LPMCR)
Initial value
00011000B
Initial value
11111100B
MB90570 Series
79
(2) Block Diagram
STP
Standby control circuit
SLP SPL RST TMD CG1 CG0 SSR
Low-power consumption mode control register
(LPMCR)
Hardware
standby
Reset
Interrupt
SQ
R
SQ
R
SQ
R
SQ
R
2
2
2
CPU intermittent
operation cycle
selector
CPU clock
control circuit
Peripheral clock
control circuit
CPU operation
clock
Peripheral function
operation clock
Clock mode
Sleep signal
Stop signal
Machine clock
Clock selector
PLL multiplication
circuit Clock select register (CKSCR)
SCM
MCM WS1 WS0 SCS MCS CS1 CS0
Timebase timer To watchdog timer
Clock timer
Sub-clock oscillator
Oscillation
sub-clock
Oscillation
clock
Clock oscillator
Main
clock
1/2 1/2048 1/4 1/4 1/8
1/1024 1/8 1/2 1/2
Oscillation
stabilization
time selector
PinX0
Pin
X1
PinX0A
Pin
X1A
S: Set
R: Reset
Q: Output
MB90570 Series
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■
■■
■ELECTRICAL CHARACTERISTICS
1. Absolute Maximu m Ratings (AVSS = VSS = 0.0 V)
*1 : Care must be taken that AVCC, AVRH, AVRL, and DVRH do not exceed VCC. Also, care must be taken that
AVRH and AVRL do not exceed AVCC, and AVRL does not exceed AVRH.
*2 : VI and VO shall never exceed VCC + 0.3 V.
*3 : The maximum output current is a peak value for a corresponding pin.
*4 : Average output current is an average current value observed for a 100 ms period for a corresponding pin.
*5 : Total average current is an average current value observed for a 100 ms period for all corresponding pins.
Note : Average output current = operating × operating efficiency
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Parameter Symbol Value Unit Remarks
Min Max
Power supply voltage
VCC VSS – 0.3 VSS + 6.0 V
AVCC VSS – 0.3 VSS + 6.0 V *1
AVRH,
AVRL VSS – 0.3 VSS + 6.0 V *1
DVRH VSS – 0.3 VSS + 6.0 V *1
Input voltage VIVSS – 0.3 VSS + 6.0 V *2
Output voltage VOVSS – 0.3 VSS + 6.0 V *2
“L” level maximum output current IOL 15 mA *3
“L” level average output current IOLAV 4mA*4
“L” level total maximum output current ΣIOL 100 mA
“L” level total average output current ΣIOLAV 50 mA *5
“H” level maximum output current IOH –15 mA *3
“H” level average output current IOHAV –4 mA *4
“H” level total maximum output current ΣIOH –100 mA
“H” level total average output current ΣIOHAV –50 mA *5
Power consumption PD
300 mW MB90573/4
MB90V570/A
500 mW MB90574C
800 mW MB90F574/A
Operating temperature TA–40 +85 °C
Storage temperature Tstg –55 +150 °C
MB90570 Series
81
2. Recommended Operating Conditions (AVSS = VSS = 0.0 V)
* : Use a ceramic capacitor or a capacitor with equiv alent frequency characteristics. The smoothing capacitor to be
connected to the VCC pin must have a capacitance value higher than CS.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
Parameter Symbol Value Unit Remarks
Min Max
Power supply voltage
VCC 3.0 5.5 V Normal operation (MB90574/C)
VCC 4.5 5.5 V Normal operation (MB90F574/A)
VCC 3.0 5.5 V Retains status at the time of operation
stop
Smoothing capacitor CS0.1 1.0 µF*
Operating temperature TA–40 +85 °C
•
••
• C pin connection circuit
C
CS
MB90570 Series
82
3. DC Characteristics (AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
(Continued)
Parameter Symbol Pin name Condition Value Unit Remarks
Min Typ Max
“H” level input
voltage VIHS CMOS
hysteresis
input pin VCC = 3.0 V to 5.5 V
(MB90573)
(MB90574)
VCC = 4.5 V to 5.5 V
(MB90F574)
0.8 VCC —VCC + 0.3 V
VIHM MD pin input VCC – 0.3 — VCC + 0.3 V
“L” level input
voltage VILS CMOS
hysteresis
input pin VSS – 0.3 — 0.2 VCC V
VILM MD pin input VSS – 0.3 — VSS + 0.3 V
“H” level output
voltage VOH Other than
PA6 and
PA7
VCC = 4.5 V
IOH = –2.0 mA VCC – 0.5 — — V
“L” level output
voltage VOL All output
pins VCC = 4.5 V
IOL = 2.0 mA ——0.4V
Open-drain
output leakage
current Ileak PA6, PA7 — — 0.1 5 µA
Input leakage
current IIL Other than
PA6 and
PA7
VCC = 5.5 V
VSS < VI < VCC –5 — 5 µA
Pull-up
resistance RUP
P00 to P07,
P10 to P17,
P60 to P67,
RST, MD0,
MD1
—1530100kΩ
Pull-down
resistance RDOWN MD0 to MD2 — 15 30 100 kΩ
Power supply
current
ICC VCC Internal operation
at 16 MHz
VCC at 5.0 V
Normal operation
— 30 40 mA MB90574
ICC VCC — 85 130 mA MB90F574/A
ICC VCC — 50 80 mA MB90574C
ICC VCC Internal operation
at 16 MHz
VCC at 5.0 V
A/D converter
operation
— 35 45 mA MB90574
ICC VCC — 90 140 mA MB90F574/A
ICC VCC — 55 85 mA MB90574C
ICC VCC Internal operation
at 16 MHz
VCC at 5.0 V
D/A converter
operation
— 40 50 mA MB90574
ICC VCC — 95 145 mA MB90F574/A
ICC VCC — 65 85 mA MB90574C
MB90570 Series
83
(Continued)
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter Symbol Pin name Condition Value Unit Remarks
Min Typ Max
Power supply
current
ICC VCC
When data written
in flash mode
programming of
erasing
— 95 140 mA MB90F574/A
ICCS VCC Internal operation
at 16 MHz
VCC = 5.0 V
In sleep mode
— 7 12 mA MB90574
ICCS VCC — 5 10 mA MB90F574/A
ICCS VCC — 15 20 mA MB90574C
ICCL VCC Internal operation
at 8 kHz
VCC = 5.0 V
TA = +25°C
Subsystem
operation
— 0.1 1.0 mA MB90574
ICCL VCC — 4 7 mA MB90F574/A
ICCL VCC — 0.03 1 mA MB90574C
ICCLS VCC Internal operation
at 8 kHz
VCC = 5.0 V
TA = +25°C
In subsleep mode
—3050µA MB90574
ICCLS VCC — 0.1 1 mA MB90F574/A
ICCLS VCC —1050µA MB90574C
ICCT VCC Internal operation
at 8 kHz
VCC = 5.0 V
TA = +25°C
In clock mode
—1530µA MB90574
ICCT VCC —3050µA MB90F574/A
ICCT VCC —1.030µA MB90574C
ICCH VCC TA = +25°C
In stop mode
—520µA MB90574
ICCH VCC —0.110µAMB90F574/A
MB90574C
Input
capacitance CIN
Other than
AVCC,
AVSS, VCC,
VSS
— — 10 80 pF
MB90570 Series
84
4. AC Characteristics
(1) Reset, Hardware Standby Input Timing
(AVCC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
* : Oscillation time of oscillator is time that the amplitude reached the 90 %.
In the crystal oscillator, the oscillation time is between several ms to tens ms. In FAR/ceramic oscillator, the
oscillation time is between hundreds of µs to several ms. In the external clock, the oscillation time is 0 ms.
Note : For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
Parameter Symbol Pin
name Condition Value Unit Remarks
Min Max
Reset input time tRSTL RST —
4 tCP —ns
Under normal
operation
Oscillation time of
oscillator * + 4 tCP — ms In stop mode
Hardware standby input time tHSTL HST 4 tCP —ns
0.2 VCC
tRSTL, tHSTL
RST
HST 0.2 VCC
Under Normal operation
In Stop Mode
90 % of
amplitude
Oscillation time
of oscillator Oscillation setting time Instruction execution
0.2 VCC 0.2 VCC
RST
X0
tRSTL
4 tCP
Internal operation clock
Internal reset
• Measurement conditions for AC characteristics
Pin
CL
CL is a load capacitance connected to a pin under test.
Capacitors of CL = 30 pF must be connected to CLK and ALE pins, while CL of 80 pF must
be connected to address data bus (AD15 to AD00), RD, WRL, and WRH pins.
MB90570 Series
85
(2) Specification for Power-on Reset (AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
* : VCC must be kept lower than 0.2 V before power-on.
Note : • The above ratings are values for causing a power-on reset.
• There are internal registers which can be initialized only by a power-on reset.
Apply power according to this rating to ensure initialization of the registers.
Parameter Symbol Pin name Condi-
tion Value Unit Remarks
Min Max
Power supply rising time tRVCC —0.05 30 ms *
Power supply cut-off time tOFF VCC 4—ms
Due to repeated
operations
VCC
tOFF
0.2 V
2.7 V 0.2 V 0.2 V
tR
VSS
Sudden changes in the power supply voltage may cause a power-on reset.
To change the power supply voltage while the device is in operation, it is recommended to raise the voltage
smoothly to suppress fluctuations as shown below.
In this case, change the supply voltage with the PLL clock not used. If the voltage drop is 1 V/s or fewer per sec-
ond, however, you can use the PLL clock.
VCC
3.0 V It is recommended to keep the rising
speed of the supply voltage at 50 mV/ms
or slower.
MB90570 Series
86
(3) Clock Timings (AVCC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
* : The frequency fluctuation rate is the maximum de viation r ate of the preset center frequency when the multiplied
PLL signal is loc ked.
The PLL frequency de viation changes periodically from the preset frequency “(about CLK × (1CYC to 50 CYC)”,
thus minimizing the chance of worst values to be repeated (errors are minimal and negligible for pulses with
long intervals).
Parameter Symbol Pin name Condi-
tion Value Unit Remarks
Min Typ Max
Clock frequency FCX0, X1
—
3—16MHz
FCL X0A, X1A — 32.768 — kHz
Clock cycle time tHCYL X0, X1 62.5 — 333 ns
tLCYL X0A, X1A — 30.5 — µs
Input clock pulse width
PWH,
PWL X0 10 — — ns Recommend
duty ratio of
30% to 70%
PWLH,
PWLL X0A — 15.2 — µs
Input clock rising/falling time tCR,
tCF X0, X0A — — 5 ns External clock
operation
Internal operating clock fre-
quency
fCP —1.5—16MHz
Main clock op-
eration
fLCP — — 8.192 — kHz Subclock oper-
ation
Internal operating clock cycle
time
tCP — 62.5 — 333 ns External clock
operation
tLCP — — 122.1 — µsSubclock oper-
ation
Frequency fluctuation rate
locked ∆f— ——5%*
| α |
fO
+
–
+ α
fO
– α
∆f = × 100 (%) Center frequency
MB90570 Series
87
• X0, X1 clock timing
PWH
0.2 VCC
0.8 VCC 0.8 VCC 0.8 VCC
PWL
tCF tCR
tHCYL
0.2 VCC
• X0A, X1A clock timing
PWLH
0.2 VCC
0.8 VCC 0.8 VCC 0.8 VCC
PWLL
tCF tCR
tLCYL
0.2 VCC
X0
X0A
5.5
4.5
3.3
3.0
16
12
9
8
4
34 8 16
1.5 3 8 12 16
6 12
6
2
3
1.5
• PLL operation guarantee range
Relationship between internal operating clock
frequency and power supply voltage
(MHz)
Internal clock fCP
Power supply voltage V
CC
(V) Operation guarantee range (MB90F574/A)
PLL operation
guarantee range
Relationship between oscillating frequency, internal
operating clock frequency, and power supply voltage
(MHz) Multiplied-
by-4 Multiplied-
by-3
Not multiplied
Multiplied-by-2 Multiplied-by-1
Internal clock f
CP
Oscillation clock FC
(MHz)
Operation guarantee range MB90574C
Operation guarantee range
MB90V570/A
Operation guarantee range
MB90573/4
MB90570 Series
88
The AC ratings are measured for the following measurement reference voltages.
(4) Recommended Resonator Manufacturers
(Continued)
• Input signal waveform • Output signal waveform
0.8 VCC
0.2 VCC
Hystheresis input pin
0.7 VCC
0.3 VCC
Pins other than hystheresis input/MD input
Hystheresis input pin
2.4 VCC
0.8 VCC
•Mask ROM product (MB90574)
Resonator
manufacturer* Resonator Frequency (MHz) C1 (pF) C1 (pF) R
Murata Mfg. Co., Ltd.
CSA2.00MG040 2.00 100 100 No required
CSA4.00MG040 4.00 100 100 No required
CSA8.00MTZ 8.00 30 30 No required
CSA16.00MXZ040 16.00 15 15 No required
CSA32.00MXZ040 32.00 5 5 No required
TDK Corporation
CCR3.52MC3 to
CCR6.96MC3 3.52 to 6.96 Built-in Built-in No required
CCR7.0MC5 to
CCR12.0MC5 7.00 to 12.00 Built-in Built-in No required
CCR20.0MSC6 to
CCR32.0MSC6 20.00 to 32.00 Built-in Built-in No required
•Sample application of ceramic resonator
X0 X1
R
C1C2
*
MB90570 Series
89
(Continued)
(5) Clock Output Timing (AVCC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter Symbol Pin name Condition Value Unit Remarks
Min Max
Cycle time tCYC CLK —62.5 — ns
CLK ↑ → CLK ↓tCHCL CLK 20 — ns
• Flash product (MB90F574)
Inquiry:Murata Mfg. Co., Ltd.
•Murata Electronics North America, Inc.: TEL 1-404-436-1300
•Murata Europe Management GmbH: TEL 49-911-66870
•Murata Electronics Singapore (Pte.): TEL 65-758-4233
TDK Corporation
•TDK Corporation of America
Chicago Regional Office: TEL 1-708-803-6100
•TDK Electronics Europe GmbH
Components Division: TEL 49-2102-9450
•TDK Singapore (PTE) Ltd.: TEL 65-273-5022
•TDK Hongkong Co., Ltd.: TEL: 852-736-2238
•Korea Branch, TDK Corporation: TEL 82-2-554-6636
Resonator
manufacturer* Resonator Frequency (MHz) C1 (pF) C2 (pF) R
Murata Mfg. Co., Ltd.
CSA2.00MG040 2.00 100 100 No required
CSA4.00MG040 4.00 100 100 No required
CSA8.00MTZ 8.00 30 30 No required
CSA16.00MXZ040 16.00 15 15 No required
CSA32.00MXZ040 32.00 5 5 No required
TDK Corporation
CCR3.52MC3 to
CCR6.96MC3 3.52 to 6.96 Built-in Built-in No required
CCR7.0MC5 to
CCR12.0MC5 7.00 to 12.00 Built-in Built-in No required
CCR20.0MSC6 to
CCR32.0MSC6 20.00 to 32.00 Built-in Built-in No required
2.4 V 0.8 V
tCYC
tCHCL
2.4 V
CLK
MB90570 Series
90
(6) Bus Read Timing (AVCC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
Parameter Symbol Pin name Condition Value Unit Remarks
Min Max
ALE pulse width tLHLL ALE
—
1 tCP*/2 – 20 — ns
Effective address →
ALE ↓ time tAVLL ALE,
A23 to A16,
AD15 to AD00 1 tCP*/2 – 20 — ns
ALE ↓ → address
effective time tLLAX ALE,
AD15 to AD00 1 tCP*/2 – 15 — ns
Effective address →
RD ↓ time tAVRL RD,
A23 to A16,
AD15 to AD00 1 tCP* – 15 — ns
Effective address →
valid data input tAVDV A23 to A16,
AD15 to AD00 —5 tCP*/2 – 60 ns
RD pulse width tRLRH RD 3 tCP*/2 – 20 — ns
RD ↓ → valid data input tRLDV RD,
AD15 to AD00 —3 tCP*/2 – 60 ns
RD ↑ → data hold time tRHDX RD,
AD15 to AD00 0—ns
RD ↑ → ALE ↑ time tRHLH ALE, RD 1 tCP*/2 – 15 — ns
RD ↑ → address
effective time tRHAX ALE,
A23 to A16 1 tCP*/2 – 10 — ns
Effective address →
CLK ↑ time tAVCH CLK,
A23 to A16,
AD15 to AD00 1 tCP*/2 – 20 — ns
RD ↓ → CLK ↑ time tRLCH CLK, RD 1 tCP*/2 – 20 — ns
ALE ↓ → RD ↓ time tALRL ALE, RD 1 tCP*/2 – 15 — ns
MB90570 Series
91
CLK 2.4 V
tAVCH
ALE
RD
AD23 to AD16
0.8 VCC
0.2 VCC
AD15 to AD00 Address Read data
2.4 V
2.4 V
0.8 V 2.4 V
0.8 V 2.4 V
2.4 V
0.8 V 2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V 0.8 VCC
0.2 VCC
tRLCH
tRHLH
tLHLL
tAVLL tLLAX tRLRH
tAVRL tRLDV tRHAX
tAVDV tRHDX
2.4 V
MB90570 Series
92
(7) Bus Write Timing (AVCC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
Parameter Symbol Pin name Condition Value Unit Remarks
Min Max
Effective address →
WR ↓ time tAVWL WRL, WRH,
A23 to A16,
AD15 to AD00
—
1 tCP – 15 — ns
WR pulse width tWLWH WRL, WRH 3 tCP*/2 – 20 — ns
Write data → WR ↑ time tDVWH WRL, WRH,
AD15 to AD00 3 tCP*/2 – 20 — ns
WR ↑ → data hold time tWHDX WRL, WRH,
AD15 to AD00 20 — ns
WR ↑ → address
effective time tWHAX WRL, WRH,
A23 to A16 1 tCP*/2 – 10 — ns
WR ↑ → ALE ↑ time tWHLH ALE, WRL 1 tCP*/2 – 15 — ns
WR ↓ → CLK ↑ time tWLCH CLK, WRH 1 tCP*/2 – 20 — ns
CLK
2.4 V
tWLCH
ALE
WRL, WRH
A23 to A16
2.4 V
0.8 V
AD15 to AD00 Address Write data
tWHLH
tAVWL tWLWH
tDVWH tWHDX
tWHAX
2.4 V
2.4 V
0.8 V 2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
2.4 V
0.8 V 0.8 V
MB90570 Series
93
(8) Ready Input Timing (AVCC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Note : Use the automatic ready function when the setup time f or the rising edge of the RDY signal is not sufficient.
(9) Hold Timing (AVCC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
Note : More than 1 machine cycle is needed before HAK changes after HRQ pin is fetched.
Parameter Symbol Pin name Condition Value Unit Remarks
Min Max
RDY setup time tRYHS RDY —45 — ns
RDY hold time tRYHH RDY 0 — ns
Parameter Symbol Pin name Condition Value Unit Remarks
Min Max
Pins in floating status →
HAK ↓ time tXHAL HAK —30 1 tCP*ns
HAK ↑ → pin valid time tHAHV HAK 1 tCP*2 tCP*ns
CLK 2.4 V
0.8 VCC
tRYHS
ALE
RD/WRL, RD/WRH
RDY
(wait inserted)
RDY
(wait not inserted)
2.4 V
tRYHS
0.2 VCC 0.2 VCC
0.8 VCC
tRYHH
Pins
HAK
High-Z
tXHAL
2.4 V
0.8 V
2.4 V
0.8 V
tHAHV
0.8 V 2.4 V
MB90570 Series
94
(10) UART0 (SCI), UART1 (SCI) Timing (AVCC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
Notes : • These are AC ratings in the CLK synchronous mode.
• CL is the load capacitance value connected to pins while testing.
Parameter Symbol Pin name Condition Value Unit Remarks
Min Max
Serial clock cycle time tSCYC SCK0 to SCK4
Internal shift clock
mode
CL = 80 pF
+ 1 TTL for an
output pin
8 tCP*—ns
SCK ↓ → SOT delay
time tSLOV SCK0 to SCK4,
SOT0 to SOT4 – 80 80 ns
Valid SIN → SCK ↑ tIVSH SCK0 to SCK4,
SIN0 to SIN4 100 — ns
SCK ↑ → valid SIN hold
time tSHIX SCK0 to SCK4,
SIN0 to SIN4 60 — ns
Serial clock “H” pulse
width tSHSL SCK0 to SCK4
External shift
clock mode
CL = 80 pF
+ 1 TTL for an
output pin
4 tCP*—ns
Serial clock “L” pulse
width tSLSH SCK0 to SCK4 4 tCP*—ns
SCK ↓ → SOT delay
time tSLOV SCK0 to SCK4,
SOT0 to SOT4 — 150 ns
Valid SIN → SCK ↑ tIVSH SCK0 to SCK4,
SIN0 to SIN4 60 — ns
SCK ↑ → valid SIN hold
time tSHIX SCK0 to SCK4,
SIN0 to SIN4 60 — ns
MB90570 Series
95
•
Internal shift clock mode
• External shift clock mode
SCK0 to SCK4 2.4 V
0.8 V
SOT0 to SOT4
SIN0 to SIN4
SCK0 to SCK4
SOT0 to SOT4
SIN0 to SIN4
0.8 V
2.4 V
0.2 V
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
2.4 V
0.8 V
0.8 VCC
0.2 VCC
0.2 VCC
0.8 VCC
0.2 VCC
0.8 VCC
tSCYC
tIVSH tSHIX
tSLOV
tSLSH tSHSL
tIVSH tSHIX
tSLOV
MB90570 Series
96
(11) Timer Input Timing (AVCC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
(12) Timer Output Timing (AVCC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter Symbol Pin name Condition Value Unit Remarks
Min Max
Input pulse width tTIWH,
tTIWL IN0, IN1 — 4 tCP*—ns
Parameter Symbol Pin name Condition Value Unit Remarks
Min Max
CLK ↑ → TOUT
transition time tTO OUT0 to OUT3,
PPG0, PPG1 —30—ns
tTIWH
0.8 VCC
0.2 VCC
tTIWL
0.8 VCC
0.2 VCC
IN0, IN1
CLK
tTO
2.4 V
TOUT 2.4 V
0.8 V
MB90570 Series
97
(13) Trigger Input Timing (AVCC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
Parameter Symbol Pin name Condition Value Unit Remarks
Min Max
Input pulse width tTRGH
tTRGL
IRQ0 to IRQ7,
ADTG, IN0, IN1 —5 tCP *—ns
Under normal
operation
IRQ0 to IRQ5 1 — µs In stop mode
0.2 VCC
0.8 VCC
tTRGH
0.8 VCC
0.2 VCC
IRQ0 to IRQ7
ADTG, IN0, IN1 tTRGL
MB90570 Series
98
(14) Chip Select Output Timing (AVCC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
Parameter Symbol Pin name Condition Value Unit Remarks
Min Max
Valid chip select output
→ Valid data input time tSVDV CS0 to CS7,
AD15 to AD00
—
—5 tCP*/2 – 60 ns
RD ↑ → chip select
output effective time tRHSV RD,
CS0 to CS7 1 tCP*/2 – 10 — ns
WR ↑ → chip select
output effective time tWHSV CS0 to CS7,
WRL, WRH 1 tCP*/2 – 10 — ns
Valid chip select output
→ CLK ↑ time tSVCH CLK,
CS0 to CS7 1 tCP*/2 – 20 — ns
CLK 2.4 V
Read data
2.4 V
0.8 V
tSVCH
2.4 V
2.4 V
2.4 V
Write data
0.8 V
A23 to A16
CS0 to CS7
AD15 to AD00
WRL, WRH
AD15 to AD00
RD
tRHSV
tSVDV
tWHSV
MB90570 Series
99
(15) I2C Timing (AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Notes : • “m” and “n” in the above table represent the values of shift clock frequency setting bits (CS4-CS0) in
the clock control register “ICCR”. For details, refer to the register description in the hardware manual.
• tDOSUO represents the minimum value when the interrupt period is equal to or greater than the SCL “L” width.
• The SDA and SCL output values indicate that rise time is 0 ns.
• For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
Parameter Symbol Pin name Condition Value Unit Remarks
Min Max
Internal clock cycle time tCP —
—
62.5 666 ns All products
Start condition output tSTAO
SDA,SCL
tCP×m×n/2-20 tCP×m×n/2+20 ns Only as master
Stop condition output tSTOO tCP(m×n/
2+4)-20 tCP(m×n/
2+4)+20 ns
Start condition detection tSTAI 3tCP+40 — ns Only as slave
Stop condition detection tSTOI 3tCP+40 — ns
SCL output “L” width tLOWO SCL tCP×m×n/2-20 tCP×m×n/2+20 ns Only as master
SCL output “H” width tHIGHO tCP(m×n/
2+4)-20 tCP(m×n/
2+4)+20 ns
SDA output delay time tDOO SDA,SCL 2tCP-20 2tCP+20 ns
Setup after SDA output
interrupt period tDOSUO 4tCP-20 — ns
SCL input “L” width tLOWI SCL 3tCP+40 — ns
SCL input “H” width tHIGHI tCP+40 — ns
SDA input setup time tSUI SDA,SCL 40 — ns
SDA input hold time tHOI 0—ns
MB90570 Series
100
SCL
SDA
SCL
SDA
tSTAO tDOO tDOO tDOSUOtSUI
tSUI tHOI tDOO tDOO tDOSUO tSTOI
tHOI
0.2 VCC
0.2 VCC0.2 VCC0.2 VCC0.2 VCC
0.2 VCC
0.8 VCC
0.8 VCC 0.8 VCC 0.8 VCC
0.8 VCC 0.8 VCC 0.8 VCC 0.8 VCC
1
67 8 9
89
ACK
ACK
tLOWO tHIGHO
tHIGHI tLOWI
•I
2C interface [data transmitter (master/slave)]
•I
2C interface [data receiver (master/slave)]
MB90570 Series
101
(16) Pulse Width on External Interrupt Pin at Return from STOP Mode
(AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
Parameter Symbol Pin name Condition Value Unit Remarks
Min Max
Input pulse width tIRQWH
tIRQWL IRQ2 to IRQ7 6tCP *ns
IRQ2 ∼ IRQ7
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
tIRQWH tIRQWL
IRQ2 ∼ IRQ7
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
tIRQWH tIRQWL
MB90570 Series
102
5. A/D Converter Electrical Characteristics
(AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, 2.7 V AVRH – AVRL, TA = –40°C to +85°C)
Parameter Symbol Pin name Condition Value Unit
Min Typ Max
Resolution — —
—
—8/10—bit
Total error — — — — ±5.0 LSB
Non-linear error — — — — ±2.5 LSB
Differential
linearity error —— ——±1.9 LSB
Zero transition
voltage VOT AN0 to
AN7 –3.5 LSB +0.5 LSB +4.5 LSB mV
Full-scale
transition voltage VFST AN0 to
AN7 AVRH
–6.5 LSB AVRH
–1.5 LSB AVRH
+1.5 LSB mV
A/D conversion
time ——
VCC = 5.0 V ±10%
at machine clock of 16 MHz 416tCP ——µs
Sampling period — — VCC = 5.0 V ±10% at machine
clock of 6 MHz 64tCP ——µs
Analog port
input current IAIN AN0 to
AN7
—
——10µA
Analog input
voltage VAIN AN0 to
AN7 AVRL — AVRH V
Reference
voltage
—AVRH AVRL
+3.0 —AV
CC V
—AVRL 0 — AVRH
–3.0 V
Power supply
current
IAAVCC —5—mA
IAH AVCC CPU stopped and 8/10-bit
A/D converter not in operation
(VCC = AVCC = AVRH = 5.0 V) —— 5µA
Reference
voltage supply
current
IRAVRH — — 400 — µA
IRH AVRH CPU stopped and 8/10-bit
A/D converter not in operation
(VCC = AVCC = AVRH = 5.0 V) —— 5µA
Offset between
channels —AN0 to
AN7 ———4LSB
≤
MB90570 Series
103
6. A/D Converter Glossary
Resolution: Analog changes that are identifiable with the A/D converter
Linearity error:The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000
0001”) with the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual con-
version characteristics
Differential linearity error:The deviation of input voltage needed to change the output code by 1 LSB from the
theoretical value
Total error :The total error is defined as a difference between the actual value and the theoretical va lue, which
includes zero-transition error/full-scale transition error and linearity error.
(Continued)
Total error
3FF
3FE
3FD
004
003
002
001
Analog inputAVRL AVRH
Actual conversion
value
Digital output
VNT
(measured value)
0.5 LSB
Actual conversion
characteristics
Theoretical
characteristics
0.5 LSB
{1 LSB × (N – 1) + 0.5 LSB}
[V]
AVRH – AVRL
1024
1 LSB = (Theoretical value)
VOT (Theoretical value) = AVRL + 0.5 LSB[V]
VFST (Theoretical value) = AVRH – 1.5 LSB[V]
Total error for digital output N [LSB]
VNT – {1 LSB × (N – 1) + 0.5 LSB}
1 LSB
=
VNT: Voltage at a transition of digital output from (N – 1) to N
MB90570 Series
104
(Continued)
Linearity error
N + 1
N
N – 1
N – 2
3FF
3FE
3FD
004
003
002
001
Analog inputAVRL AVRH Analog inputAVRL AVRH
Actual conversion
characteristics
VOT (measured value)
VFST
(measured value)
Actual conversion
value
VNT
{1 LSB × (N – 1)+ VOT}
Theoretical
characteristics
Digital output
Digital output
Differential linearity error
Theoretical characteristics
V(N + 1)T
(measured value)
Actual conversion
value
VNT (measured value)
Actual conversion value
Linearity error of
digital output N
VOT:Voltage at transition of digital output from “000H” to “001H”
VFST:Voltage at transition of digital output from “3FEH” to “3FFH”
[LSB]
VNT – {1 LSB × (N – 1) + VOT}
1 LSB
=
[V]
VFST – VOT
1022
=
1 LSB
– 1 LSB [LSB]
V(N + 1)T – VNT
1 LSB
=
Differential linearity error
of digital N
MB90570 Series
105
7. Notes on Using A/D Converter
Select the output impedance value for the external circuit of analog input according to the f ollowing conditions.
Output impedance values of the external circuit MB90V570/V570A/573/574 are 5 kΩ or lower , MB90F574/574A/
574C are 10 kΩ or lower are recommended.
When capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor
value is recommended to minimized the effect of voltage distribution between the e xternal capacitor and internal
capacitor.
When the output impedance of the external circuit is too high, the sampling period f or analog voltages ma y not
be sufficient (sampling period = 4.00 µs @machine clock of 16 MHz).
•Error
The smaller the | AVRH – AVRL |, the greater the error would become relatively.
•
••
• Equipment of analog input circuit model
Note : Listed values must be considered as standards.
Comparator
Analog input C0
C1MB90573/4, MB90V570/A R ≅ 3.2 kΩ, C ≅ 30 pF
MB90F574/A R ≅ 7.1 kΩ, C ≅ 48.3 pF
MB90574C R ≅ 2.2 kΩ, C ≅ 45 pF
MB90570 Series
106
8. D/A Converter Electrical Characteristics
(AVCC = VCC = DVCC = 5.0 V ±10%, AVSS = VSS = DVSS = 0.0 V, TA = –40°C to +85°C)
9. Flash Memory Program/Erase Characteristics
Parameter Symbol Pin name Value Unit Remarks
Min Typ Max
Resolution — — — 8 — bit
Differential linearity
error —— ——±0.9 LSB
Absolute accuracy — — — — ±1.2 %
Linearity error — — — — ±1.5 LSB
Conversion time — — — 10 20 µs Load capacitance: 20 pF
Analog reference
voltage —DV
CC VSS + 3.0 — AVCC V
Reference voltage
supply current IDVR DVCC — 120 300 µAConversion under
no load
IDVRS DVCC ——10µA In sleep mode
Analog output
impedance —— —20—kΩ
Parameter Condition Value Unit Remarks
Min Typ Max
Sector erase time
TA = + 25°C
VCC = 5.0 V
—1.530s
Except for the write time before
internal erase operation
Chip erase time — 13.5 — s Except for the write time before
internal erase operation
Word (16bit width)
programming time — 32 1,000 µsExcept for the over head time of
the system
Program/Erase time — 10,000 — — cycle
Data hold time — 100,000 — — h
MB90570 Series
107
■
■■
■EXAMPLE CHARACTERISTICS
(1) Power Supply Current (MB90574)
(Continued)
ICC - VCC
Fc = 16 MHz
ICC (mA)
35
30
25
20
15
10
5
3.0 4.0 5.0 6.0
VCC (V)
TA = +25°C
Fc = 12.5 MHz
Fc = 10 MHz
Fc = 8 MHz
Fc = 5 MHz
Fc = 4 MHz
Fc = 2 MHz
ICC - TA
Fc = 16 MHz
ICC (mA)
35
30
25
20
15
10
5
–20 +10 +40 +70 TA (°C)
VCC = 5.0 V
Fc = 12.5 MHz
Fc = 10 MHz
Fc = 8 MHz
Fc = 5 MHz
Fc = 4 MHz
Fc = 2 MHz
+100
ICCL - VCC
Fc = 8 kHz
ICCL (µA)
160
140
120
100
80
60
40
20
3.0 4.0 5.0 6.0
VCC (V)
TA = +25°C
ICCS - VCC
Fc = 16 MHz
ICCS (mA)
10
9
8
7
6
5
4
3
2
1
3.0 4.0 5.0 6.0
VCC (V)
TA = +25°C
Fc = 12.5 MHz
Fc = 10 MHz
Fc = 8 MHz
Fc = 5 MHz
Fc = 4 MHz
Fc = 2 MHz
ICCS - TA
Fc = 16 MHz
ICCS (mA)
10
9
8
7
6
5
4
3
2
1
–20 +10 +40 +70 TA (°C)
VCC = 5.0 V
Fc = 12.5 MHz
Fc = 10 MHz
Fc = 8 MHz
Fc = 5 MHz
Fc = 4 MHz
Fc = 2 MHz
+100
ICCLS - VCC
Fc = 8 kHz
ICCLS (mA)
70
60
50
40
30
20
10
3.0 4.0 5.0 6.0
VCC (V)
TA = +25°C
MB90570 Series
108
(Continued)
ICC - Fc
ICC (mA)
VCC = 2.5 V
VCC = 3.0 V
VCC = 3.5 V
VCC = 4.0 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
VCC = 6.0 V
35
30
25
20
15
10
5
4.0 6.0 8.0 12.0 16.0
TA = +25°C
ICCS - Fc
ICCS (mA)
VCC = 2.5 V
VCC = 3.0 V
VCC = 3.5 V
VCC = 4.0 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
VCC = 6.0 V
TA = +25°C
10
9
8
7
6
5
4
3
2
1
Fc (MHz) 4.0 6.0 8.0 12.0 16.0
Fc (MHz)
ICCT - VCC
ICCT (µA)
20
18
16
14
12
10
8
6
4
2
TA = +25°C
3.0 4.0 5.0 6.0
VCC (V) 3.0 4.0 5.0 6.0
VCC (V)
Fc = 8 kHz
ICCH - VCC
ICCH (µA)
10
9
8
7
6
5
4
3
2
1
TA = +25°C
ICCLH - TA
ICCLH (µA)
10
9
8
7
6
5
4
3
2
1
–20 +10 +40 +70 +100
TA (°C)
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
VCC = 2.5 V
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
VCC = 2.5 V
–20 +10 +40 +70 +100
TA (°C)
ICCT - TA
ICCT (µA)
10
9
8
7
6
5
4
3
2
1
MB90570 Series
109
(Continued)
20
18
16
14
12
10
8
6
4
2
ICCL - TA
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
VCC = 2.5 V
–20 +10 +40 +70 +100
TA (°C)
14
12
10
8
6
4
2
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
VCC = 2.5 V
ICCL (µA) ICCLS - TA
ICCLS (µA)
–20 +10 +40 +70 +100
TA (°C)
MB90570 Series
110
(2) Power Supply Current (MB90F574)
(Continued)
140
120
100
80
60
40
20
ICC - TA
ICC (mA)
Fc = 16 MHz
Fc = 12.5 MHz
Fc = 10 MHz
Fc = 8 MHz
Fc = 5 MHz
Fc = 4 MHz
Fc = 2 MHz
3.0 4.0 5.0 6.0
TA = +25°C
VCC (V)
ICCS - VCC
ICCS (mA)
40
35
30
25
20
15
10
5
3.0 4.0 5.0 6.0
VCC (V)
Fc = 16 MHz
Fc = 12.5 MHz
Fc = 10 MHz
Fc = 8 MHz
Fc = 5 MHz
Fc = 4 MHz
Fc = 2 MHz
TA = +25°C
ICC - VCC
ICC (mA)
120
100
80
60
40
20
Fc = 16 MHz
Fc = 12.5 MHz
Fc = 10 MHz
Fc = 8 MHz
Fc = 5 MHz
Fc = 4 MHz
Fc = 2 MHz
40
35
30
25
20
15
10
5
Fc = 16 MHz
Fc = 12.5 MHz
Fc = 10 MHz
Fc = 8 MHz
Fc = 5 MHz
Fc = 4 MHz
Fc = 2 MHz
ICCS - TA
ICCS (mA)
VCC = 5.0 V VCC = 5.0 V
–20 +10 +40 +70 +100
TA (°C)
–20 +10 +40 +70 +100
TA (°C)
MB90570 Series
111
(Continued)
50
40
30
20
10
3456
ICCT (µA)
VCC (V)
ICCT - VCC
TA = +25°C
ICCH (µA) ICCH -VCC
FC = 8 kHZ
10
9
8
7
6
5
4
3
2
1
3.0 4.0 5.0 6.0
VCC (V)
120
100
80
60
40
20
4.0 8.0 12.0
ICC (mA)
FC (MHZ)
ICC - FC
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
VCC = 2.5 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 6.0 V
16.0
VCC = 5.5 V 35
30
20
15
10
5
4.0 8.0 12.0
ICCS (mA)
FC (MHZ)
ICCS - FC
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
VCC = 2.5 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 6.0 V
16.0
VCC = 5.5 V
25
40
140
120
100
80
60
40
20
3.0 4.0 5.0 6.0
ICCLS (µA)
VCC (V)
ICCLS - VCC
TA = +25°C
FC = 8 kHz
160
180
200
TA = +25°CTA = +25°C
TA = +25°C
MB90570 Series
112
(Continued)
ICCH (µA) ICCH - TA
10
9
5
4
3
2
1
-20 +10 +70 +100
ICCT (µA)
TA (°C)
ICCT - TA
6
7
8
+40
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
VCC = 2.5 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 6.0 V
VCC = 5.5 V
10
9
5
4
3
2
1
-20 +10 +70 +100
TA (°C)
6
7
8
+40
20
18
10
8
6
4
2
-20 +10 +70 +100
ICCLS (µA)
TA (°C)
12
14
16
+40
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
VCC = 2.5 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 6.0 V
VCC = 5.5 V
ICCLS - TA
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
VCC = 2.5 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 6.0 V
VCC = 5.5 V
MB90570 Series
113
(3) Power Supply Current (MB90574C)
(Continued)
50
45
40
35
30
25
20
15
10
5
0
−50 −20 10 40 70 100
FC = 16 MHz
FC = 12 MHz
FC = 10 MHz
FC = 8 MHz
FC = 5 MHz
FC = 4 MHz
FC = 2 MHz
ICC (mA) VCC = 5.0 VICC - TA
TA (°C)
0
10
20
30
40
50
60
70
246810 14
12 16
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
ICC (mA) TA = +25 °CICC - FC
FC (MHz)
0
2
4
6
8
10
12
14
16
18
3.000 3.500 4.000 4.500 5.000 5.500 6.000
FC = 16 MHz
FC = 12 MHz
FC = 10 MHz
FC = 8 MHz
FC = 5 MHz
FC = 4 MHz
FC = 2 MHz
ICCS (mA) TA = +25 °CICCS - VCC
VCC (V)
0
2
6
4
8
12
10
14
16
18
−50 −20 10 40 70 100
FC = 16 MHz
FC = 12 MHz
FC = 10 MHz
FC = 8 MHz
FC = 4 MHz
FC = 2 MHz
ICCS (mA) VCC = 5 VICCS - TA
TA (°C)
0
10
20
30
40
50
60
70
3.0 3.5 4.0 4.5 5.0 5.5 6.0
FC = 16 MHz
FC = 12 MHz
FC = 10 MHz
FC = 8 MHz
FC = 5 MHz
FC = 4 MHz
FC = 2 MHz
ICC (mA) TA = +25 °CICC - VCC
VCC (V)
18
16
14
12
10
8
6
4
2
02 4 6 8 10 12 14 16
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
ICCS (mA) TA = +25 °CICCS - FC
FC (MHz)
MB90570 Series
114
(Continued)
10
9
8
7
6
5
4
3
2
1
0
3.000 3.500 4.000 4.500 5.000 5.500 6.000
VCC (V)
ICCH (µA) ICCH - VCC TA = +25 °C
10
9
8
7
6
5
4
3
2
1
0
3.000 3.500 4.000 4.500 5.000 5.500 6.000
VCC (V)
ICCT (µA) ICCT - VCC TA = +25 °C
FC = 8 kHz
10
9
8
7
6
5
4
3
2
1
0
−50 −20 10 40 70 100
TA (°C)
ICCT (µA) ICCT - TA
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
10
9
8
7
6
5
4
3
2
1
0
−50 −20 10 40 70 100
TA (°C)
ICCH (µA) ICCH - TA
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
70
60
50
40
30
20
10
0
3.000 3.500 4.000 4.500 5.000 5.500 6.000
VCC (V)
ICCL (µA) ICCL - VCC TA = +25 °C
FC = 8 kHz
70
60
50
40
30
20
10
0
−50 −20 10 40 70 100
TA (°C)
ICCL (µA) ICCL - TA
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
MB90570 Series
115
(Continued)
25
20
15
10
5
0
3.000 3.500 4.000 4.500 5.000 5.500 6.000
VCC (V)
ICCLS (µA) ICCLS - VCC TA = +25 °C
FC = 8 kHz
25
20
15
10
5
0
−50 −20 10 40 70 100
TA (°C)
ICCLS (µA) ICCLS - TA
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
MB90570 Series
116
■
■■
■ORDERING INFORMATION
Part number Pac kage Remarks
MB90573PFF
MB90574PFF
MB90F574PFF
MB90F574APFF
120-pin Plastic LQFP
(FPT-120P-M05)
MB90573PFV
MB90574PFV
MB90574CPFV
MB90F574PFV
MB90F574APFV
120-pin Plastic QFP
(FPT-120P-M13)
MB90574CPMT
MB90F574APMT 120-pin Plastic LQFP
(FPT-120P-M21)
MB90570 Series
117
■
■■
■PACKAGE DIMENSIONS
(Continued)
120-pin plastic LQFP
(FPT-120P-M05)
Dimensions in mm (inches)
C
1998 FUJITSU LIMITED F120006S-3C-4
0.07(.003)
M
INDEX
16.00±0.20(.630±.008)SQ
14.00±0.10(.551±.004)SQ
130
31
6091
120
6190
LEAD No.
(Stand off)
0.10±0.10
(.004±.004)
0.25(.010)
(.018/.030)
0.45/0.75
(.020±.008)
0.50±0.20
(Mounting height)
0~8°
Details of "A" part
1.50
+0.20
–0.10
+.008
–.004
.059
"A"
0.40(.016) 0.16±0.03
(.006±.001) 0.145±0.055
(.006±.002)
0.08(.003)
MB90570 Series
118
(Continued)
120-pin plastic QFP
(FPT-120P-M13)
Dimensions in mm (inches)
C
2000 FUJITSU LIMITED F120013S-c-3-5
0°~8°
.139 –.008
+.013
–0.20
+0.32
3.53
.008 –.006
+.004
–0.15
+0.10
0.20
(Stand off)
0.25(.010)
Details of "A" part
6190
60
31
301
LEAD No.
91
120
20.00±0.10(.787±.004)SQ
22.60±0.20(.890±.008)SQ
0.50(.020) 0.22±0.05
(.009±.002) 0.08(.003) M
"A"
0.08(.003)
(.006±.002)
0.145±0.055
INDEX
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
(Mouting height)
MB90570 Series
119
(Continued)
120-pin plastic LQFP
(FPT-120P-M21)
Dimensions in mm (inches)
C
2001 FUJITSU LIMITED F120033S-c-3-3
1 30
60
31
90 61
120
91
16.00±0.10(.630±.004)SQ
18.00±0.20(.709±.008)SQ
0.50(.020) 0.22±0.05
(.009±.002) M
0.08(.003)
INDEX
.006 –.001
+.002
–0.03
+0.05
0.145
"A"
0.08(.003)
LEAD No.
.059 –.004
+.008
–0.10
+0.20
1.50
Details of "A" part
0~8°
(Mounting height)
0.60±0.15
(.024±.006) 0.25(.010)
(.004±.002)
0.10±0.05
(Stand off)
MB90570 Series
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0111
FUJITSU LIMITED Printed in Japan
