Revised June 2005 74LVT16374 * 74LVTH16374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs General Description Features The LVT16374 and LVTH16374 contain sixteen non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock (CP) and Output Enable (OE) are common to each byte and can be shorted together for full 16-bit operation. The LVTH16374 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. Input and output interface capability to systems at 5V VCC These flip-flops are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT16374 and LVTH16374 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation. Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH16374), also available without bushold feature (74LVT16374) Live insertion/extraction permitted Power Up/Power Down high impedance provides glitch-free bus loading Outputs source/sink 32 mA/64 mA Functionally compatible with the 74 series 16374 Latch-up performance exceeds 500 mA ESD performance: Human-body model ! 2000V Machine model ! 200V Charged-device model ! 1000V Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) Ordering Code: Order Number Package Number 74LVT16374G (Note 1)(Note 2) BGA54A (Preliminary) Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 74LVT16374MEA (Note 2) MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 74LVT16374MTD (Note 2) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 74LVTH16374G (Note 1)(Note 2) BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 74LVTH16374MEA (Note 2) MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 74LVTH16374MTD (Note 2) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Note 1: Ordering code "G" indicates Trays. Note 2: Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code. Logic Symbol (c) 2005 Fairchild Semiconductor Corporation DS012022 www.fairchildsemi.com 74LVT16374 * 74LVTH16374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs January 1999 74LVT16374 * 74LVTH16374 Connection Diagrams Pin Descriptions Pin Assignment for SSOP and TSSOP Pin Names Description OEn Output Enable Input (Active LOW) CPn Clock Pulse Input I0-I15 Inputs O0-O15 3-STATE Outputs NC No Connect FBGA Pin Assignments 1 2 3 4 5 6 A O0 NC OE1 CP1 NC I0 B O2 O1 NC NC I1 I2 C O4 O3 VCC VCC I3 I4 D O6 O5 GND GND I5 I6 E O8 O7 GND GND I7 I8 F O10 O9 GND GND I9 I10 I12 G O12 O11 VCC VCC I11 H O14 O13 NC NC I13 I14 J O15 NC OE2 CP2 NC I15 Truth Tables Inputs Pin Assignment for FBGA Outputs OE1 I0-I7 O0-O7 L H H L L L L L X Oo X H X Z CP1 Inputs CP2 (Top Thru View) H L X Z Oo Outputs OE2 I8-I15 O8-O15 L H H L L L L L X Oo X H X Z HIGH Voltage Level LOW Voltage Level Immaterial HIGH Impedance Previous Oo before HIGH to LOW of CP Functional Description Each flip-flop will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CPn) transition. With the Output Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operation of the OEn input does not affect the state of the flip-flops. The LVT16374 and LVTH16374 consist of sixteen edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Each byte has a buffered clock and buffered Output Enable common to all flip-flops within that byte. The description which follows applies to each byte. www.fairchildsemi.com 2 74LVT16374 * 74LVTH16374 Logic Diagrams Byte 1 (0:7) Byte 2 (8:15) Please note that these diagrams are provided for the understanding of logic operation and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74LVT16374 * 74LVTH16374 Absolute Maximum Ratings(Note 3) Symbol Parameter VCC Supply Voltage VI DC Input Voltage VO DC Output Voltage Value IIK DC Input Diode Current IOK DC Output Diode Current IO DC Output Current Conditions 0.5 to 4.6 0.5 to 7.0 0.5 to 7.0 0.5 to 7.0 50 50 ICC DC Supply Current per Supply Pin IGND DC Ground Current per Ground Pin TSTG Storage Temperature Units V V Output in 3-STATE V Output in High or Low State (Note 4) VI GND mA VO GND mA 64 VO ! VCC Output at High State 128 VO ! VCC Output at Low State mA r64 r128 65 to 150 mA mA qC Recommended Operating Conditions Symbol Parameter VCC Supply Voltage VI Input Voltage Min Max 2.7 3.6 Units V 0 5.5 V IOH High-Level Output Current 32 mA IOL Low-Level Output Current 64 mA TA Free-Air Operating Temperature 't/'V Input Edge Rate, VIN 0.8V-2.0V, VCC 3.0V 40 85 qC 0 10 ns/V Note 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 4: IO Absolute Maximum Rating must be observed. DC Electrical Characteristics Symbol TA VCC Parameter (V) 40qC to 85qC Min Input Clamp Diode Voltage VIH Input HIGH Voltage 2.7-3.6 VIL Input LOW Voltage 2.7-3.6 VOH Output HIGH Voltage 2.7-3.6 VCC 0.2 2.7 2.4 3.0 2.0 VOL II(HOLD) 2.7 Output LOW Voltage Bushold Input Minimum Drive II(OD) Bushold Input Over-Drive (Note 5) Current to Change State II Input Current Data Pins IOFF Power Off Leakage Current IPU/PD Power Up/Down 3-STATE Output Current 0.8 Units V V V 0.2 Conditions II VO d 0.1V or IOH 100 PA IOH 8 mA IOH 32 mA IOL 100 PA IOL 24 mA IOL 16 mA 32 mA 2.7 0.5 0.4 3.0 0.5 IOL 3.0 0.55 IOL 75 V PA 75 500 PA 500 18 mA VO t VCC 0.1V 3.0 3.0 Control Pins 2.0 2.7 3.0 (Note 5) Max 1.2 VIK 64 mA VI 0.8V VI 2.0V (Note 6) (Note 7) 3.6 10 VI 5.5V 3.6 r1 VI 0V or VCC VI 0V VI VCC 5 3.6 PA 1 0 r100 PA 0-1.5V r100 PA 0V d VI or VO d 5.5V VO VI 0.5V to 3.0V GND or VCC IOZL 3-STATE Output Leakage Current 3.6 5 PA VO 0.5V IOZH 3-STATE Output Leakage Current 3.6 5 PA VO 3.0V IOZH 3-STATE Output Leakage Current 3.6 10 PA VCC VO d 5.5V www.fairchildsemi.com 4 Symbol (Continued) VCC Parameter 40qC to 85qC TA (V) Min Units Conditions Max ICCH Power Supply Current 3.6 0.19 mA Outputs HIGH ICCL Power Supply Current 3.6 5 mA Outputs LOW ICCZ Power Supply Current 3.6 0.19 mA Outputs Disabled ICCZ Power Supply Current 3.6 0.19 mA VCC d V O d 5.5V, 'ICC Increase in Power Supply Current 3.6 0.2 mA One Input at VCC 0.6V Outputs Disabled Other Inputs at VCC or GND (Note 8) Note 5: Applies to bushold versions only (74LVTH16374). Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. Dynamic Switching Characteristics Symbol (Note 9) (V) 25qC TA VCC Parameter Min Typ Max Conditions Units CL 500: 50 pF, RL VOLP Quiet Output Maximum Dynamic VOL 3.3 0.8 V (Note 10) VOLV Quiet Output Minimum Dynamic VOL 3.3 0.8 V (Note 10) Note 9: Characterized in SSOP package. Guaranteed parameter, but not tested. Note 10: Max number of outputs defined as (n). n1 data inputs are driven 0V to 3V. Output under test held LOW. AC Electrical Characteristics TA Symbol Parameter VCC 40qC to 85qC, CL 50 pF, RL 3.3V r 0.3V Min Max VCC 500: 2.7V Min Units Max fMAX Maximum Clock Frequency 160 tPHL Propagation Delay 1.9 4.3 1.9 4.6 tPLH CP to On 1.6 4.5 1.6 5.2 tPZL Output Enable Time 1.3 4.4 1.3 5.0 1.0 4.5 1.0 5.4 1.5 4.6 1.5 4.8 2.0 5.0 2.0 5.4 tPZH tPLZ Output Disable Time tPHZ 160 MHz ns ns ns tS Setup Time 1.8 2.0 tH Hold Time 0.8 0.1 ns tW Pulse Width 3.0 3.0 ns tOSHL Output to Output Skew (Note 11) tOSLH ns 1.0 1.0 1.0 1.0 ns Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Capacitance (Note 12) Conditions Typical Units CIN Symbol Input Capacitance Parameter VCC Open, VI 0V or VCC 4 pF COUT Output Capacitance VCC 3.0V, VO 0V or VCC 8 pF Note 12: Capacitance is measured at frequency f 1 MHz, per MIL-STD-883, Method 3012. 5 www.fairchildsemi.com 74LVT16374 * 74LVTH16374 DC Electrical Characteristics 74LVT16374 * 74LVTH16374 Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A www.fairchildsemi.com 6 74LVT16374 * 74LVTH16374 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A 7 www.fairchildsemi.com 74LVT16374 * 74LVTH16374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8