74LVT16374MTDX_NL - Fairchild Semiconductor

January 1999

Revised June 2005

74LVT16374 • 74LVTH16374 Low Voltage 16-Bit D-Type Flip-F lop with 3-STATE Outputs

74LVT16374 • 74LVTH16374

Low Voltage 16-Bit D-Type Flip-Flop

with 3-STATE Outputs

General Descript ion

The LVT16374 and LVTH16374 contain sixteen non-invert-

ing D-type flip-flops with 3-STATE outputs and is intended

for bus oriented applications. The dev ice is byte controlled .

A buffered clock (CP) and Output Enable (OE) are com-

mon to each byte and can be shorted together for full 16-bit

operation.

The LVTH16374 data inputs include bushold, eliminating

the need for external pull-up resistors to hold unused

inputs.

These flip-flops are designed for low-voltage (3.3V) VCC

applications, bu t with the capability to provide a TTL inte r-

face to a 5V envir onmen t. The LVT16374 an d LVTH16374

are fabricated with an advanced BiCMOS technology to

achieve high speed operation similar to 5V ABT while

maintaining a low power dissipation.

Features

■Input and output interface capability to systems at

5V VCC

■Bushold data inputs eliminate the need for external

pull-up resistors to hold unused inputs (74LVTH16374),

also availabl e wit ho ut bush old feat ure (74LVT16374)

■Live insertion /extracti on per mitt ed

■Power Up/Power Down high impedance provides

glitch-fr ee bus load i ng

■Outputs source/sink



32 mA/



64 mA

■Functionally compatible with the 74 series 16374

■Latch-up per for man c e exce eds 500 mA

■ESD performa nce :

Human-body model

2000V

Machine model

200V

Charged-device model

1000V

■Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA)

Ordering Code:

Note 1: Order ing code “G” indicat es T r a ys.

Note 2: Device also av ailable in Tape and R eel. Specify by ap pending su ffix le tter “X” to the ordering code.

Logic Symbol

Order Num b er Packag e Num b er Packa ge Des cri pt io n

74LVT16374G

(Note 1)( Note 2) BGA54A

(Preliminary) 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

74LVT16374MEA

(Note 2) MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

74LVT16374MTD

(Note 2) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

74LVTH16374G

(Note 1)( Note 2) BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

74LVTH16374MEA

(Note 2) MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

74LVTH16374MTD

(Note 2) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

www.fairchildsemi.com 2

74LVT16374 • 74LVTH16374

Connection Diagrams

Pin Assignment for SSOP and TSSOP

Pin Assignment for FBGA

(Top Thru Vi ew)

Pin Descriptions

FBGA Pin Assignments

Truth Tables

HIGH Voltag e Level

LOW Voltage Le ve l

Immaterial

HIGH Im pedance

Previ ous Oo before HIGH to LOW of CP

Functional Description

The LVT16374 and LVTH16374 consist of sixteen

edge-triggered flip-flops with individual D-type inputs and

3-STATE true outputs. The device is byte controlled with

each byte functioning identically, but independent of the

other. The control pins can be shorted together to obtain

full 16-bit operation. Each byte has a buffered clock and

buffered Output Enable common to all flip-flops within that

byte. The description which follows applies to each byte.

Each flip-flop will store the state of their individual D-type

inputs that meet the setup and hold time requirements on

the LOW-to-HIGH Clock (CPn) transition. With the Output

Enable ( OEn) LOW, the contents of the flip-flops are avail-

able at the outputs. When OEn is HIG H, the outputs go to

the high impe dan ce state . Ope rat i on o f the OEn in put does

not affect the state of the flip-flops.

Pin Names Description

OEn Output Enable Input (Active LOW)

CPnClock Pulse Input

I0–I15 Inputs

O0–O15 3-STATE Outputs

NC No Connect

123456

AO0NC OE1CP1NC I0

BO2O1NC NC I1I2

CO4O3VCC VCC I3I4

DO6O5GND GND I5I6

EO8O7GND GND I7I8

FO10 O9GND GND I9I10

GO12 O11 VCC VCC I11 I12

HO14 O13 NC NC I13 I14

JO15 NC OE2CP2NC I15

Inputs Outputs

CP1OE1I0–I7O0–O7



LH H



LL L

LL X O

XH X Z

Inputs Outputs

CP2OE2I8–I15 O8–O15



LH H



LL L

LL X O

XH X Z

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74LVT16374 • 74LVTH16374

Logic Diagrams

Byte 1 (0:7)

Byte 2 (8:15)

Please not e t hat thes e diagrams are provided for the understanding of logic operat ion and s hould no t be us ed to estim at e propagation delays.

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74LVT16374 • 74LVTH16374

Absolute Maximum Ratings(Note 3)

Recommended Operating Conditions

Note 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions

beyo nd those in dic ated may adver s ely affec t device rel iability. Fun c tio nal opera ti on under ab s olute maximum rated con dit ions is not implied.

Note 4: IO Absolute Maximum Rating must be observed.

DC Electrical Characteristics

Symbol Parameter Value Conditions Units

VCC Supply Voltage



0.5 to



4.6 V

VIDC Input Voltage



0.5 to



7.0 V

VODC Output Volta ge



0.5 to



7.0 Output in 3-STATE V



0.5 to



7.0 Output in High or Low State (Note 4)

IIK DC Input Diode Current



50 VI



GND mA

IOK DC Output Diode Current



50 VO



GND mA

IODC Output Current 64 VO

VCC Output at High State mA

128 VO

VCC Output at Low State

ICC DC Supply Current per Supply Pin

64 mA

IGND DC Ground Current per Ground Pin

128 mA

TSTG Storage Temperature



65 to



150

Symbol Parameter Min Max Units

VCC Supply Voltage 2.7 3.6 V

VIInput Voltage 0 5.5 V

IOH High-Level Output Current



32 mA

IOL Low-Level Output Current 64 mA

TAFree-Air Operating Temperature



40 85

V Input Edge Rate, VIN

0.8V–2.0V, VCC

3.0V 0 10 ns/V

Symbol Parameter VCC T A



C to



CUnits Conditions

(V) Min Max

VIK Input Clamp Diode Voltage 2.7



1.2 V II



18 m A

VIH Input HIGH Voltage 2.7–3.6 2.0 VVO

0.1V or

VIL Input LOW Voltage 2.7–3.6 0.8 VO

VCC



0.1V

VOH Output HIGH Voltage 2.7–3.6 VCC



0.2 VIOH



100

2.7 2.4 IOH



8 mA

3.0 2.0 IOH



32 mA

VOL Output LOW Voltage 2 .7 0.2

IOL

100

2.7 0.5 IOL

24 mA

3.0 0.4 IOL

16 mA

3.0 0.5 IOL

32 mA

3.0 0.55 IOL

64 mA

II(HOLD) Bushold Input Minimum Drive 3.0 75

AVI

0.8V

(Note 5)



75 VI

2.0V

II(OD) Bushold Input Over-Drive 3.0 500

A(Note 6)

(Note 5) Current to Change State



500 (Note 7)

IIInput Current 3.6 10

5.5V

Control Pins 3.6

0V or VCC

Data Pins 3.6



VCC

IOFF Power Off Leakage Current 0

100

A0V

VI or VO

5.5V

IPU/PD Power Up/Down 3-STATE 0–1.5V

100

AVO

0.5V to 3.0V

Output Current VI

GND or VCC

IOZL 3-STATE Output Leakage Current 3.6



0.5V

IOZH 3-STATE Output Leakage Current 3.6 5

3.0V

IOZH



3-STATE Output Leakage Current 3.6 10



5.5V

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74LVT16374 • 74LVTH16374

DC Electrical Characteristics (Continued)

Note 5: Applies to bus hold versions only (74LVTH16374).

Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH.

Note 7: An external driver mus t s ink at least the s pec if ied current to switc h f rom HIG H -t o-LOW.

Note 8: This is the incr eas e in sup ply c urrent for eac h input tha t is at t he specified voltage lev el rather th an VCC or GND.

Dynamic Switching Characteristics (Note 9)

Note 9: Characterized in SSOP packa ge. Guaranteed parameter, but not te sted.

Note 10: M ax number of out put s d ef ined as (n). n



1 data inp uts are driven 0V to 3V. Output under tes t held LOW.

AC Electrical Characteristics

Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The

specification applies to any outputs switching in the same direction, either HIGH-to- LOW (tOSHL) or LOW- to -H I GH (t OSLH).

Capacitance (Note 12)

Note 12: C apacitanc e is m easured at fr equency f

1 MHz, per MIL-STD -883, M et hod 3012.

Symbol Parameter VCC T A



C to



CUnits Conditions

(V) Min Max

ICCH Power Supply Current 3.6 0.19 mA Outputs HIGH

ICCL Power Supply Current 3.6 5 mA Outputs LOW

ICCZ Power Supply Current 3.6 0.19 mA Outputs Disabled

ICCZ



Power Supply Current 3.6 0.19 mA VCC

5.5V,

Outputs Disabled

ICC Increase in Power Supply Current 3.6 0.2 mA One Input at VCC



0.6V

(Note 8) Other Inputs at VCC or GND

Symbol Parameter VCC TA

CUnits Conditions

(V) Min Typ Max CL

50 pF, RL

500

VOLP Quiet Output Maximum Dynamic VOL 3.3 0.8 V (Note 10)

VOLV Quiet Output Minimum Dynamic VOL 3.3



0.8 V (Note 10)

Symbol Parameter



C to



C, CL

50 pF, RL

500

UnitsVCC

3.3V

0.3V VCC

2.7V

Min Max Min Max

fMAX Maximum Clock Frequency 160 160 MHz

tPHL Propagation Delay 1.9 4.3 1.9 4.6 ns

tPLH CP to On1.6 4.5 1.6 5.2

tPZL Output Enable Time 1.3 4.4 1.3 5.0 ns

tPZH 1.0 4.5 1.0 5.4

tPLZ Output Disable Time 1.5 4.6 1.5 4.8 ns

tPHZ 2.0 5.0 2.0 5.4

tSSetup Time 1.8 2.0 ns

tHHold Time 0.8 0.1 ns

tWPulse W idth 3.0 3.0 ns

tOSHL Output to Output Skew (Note 11) 1.0 1.0 ns

tOSLH 1.0 1.0

Symbol Parameter Conditions Typical Units

CIN Input Capaci tance VCC

Open, VI

0V or VCC 4pF

COUT Output Capacitance VCC

3.0V, VO

0V or VCC 8pF

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74LVT16374 • 74LVTH16374

Physical Dimensions inches (millimeters) unless otherwise noted

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

Packag e Num b er BGA5 4A

7 www.fairchildsemi.com

74LVT16374 • 74LVTH16374

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

Package Number MS48A

www.fairchildsemi.com 8

74LVT16374 • 74LVTH16374 Low Volt age 16-Bit D-Type Flip-Flop with 3-STATE Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Package Number MTD48

Fairchild does no t assume any responsibility for use of any circui try described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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user.

2. A critical compon ent i n any compon ent of a lif e supp ort

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