NJU8753
PRELIMINAR
Y
-1-
Ver.2009-03-10
Analog Signal Input Class-D Amplifier
with DC-DC Converter for Piezo Speaker
GENERAL DESCRIPTION
The NJU8753 is an analog signal input monaural
class D power amplifier with DC-DC converter for
Piezo speaker. Input part operates on 2.85V(typ) and
a built-in DC-DC converter generates variable output
voltage(up to 12V) with input voltage(2.6 to 4.2V).
Therefore, it drives Piezo speaker with louder sound
and high efficiency.
The NJU8753 incorporates BTL amplifier, which
eliminate AC coupling capacitors, capable of driving
Piezo speaker with simple external LC low-pass
filters.
Class D operation achieves lower power operation
for Piezo speaker, thus the NJU8753 is suited for
battery- powered applications.
FEATURES
Operating Voltage :2.6 to 3.6V(VDD, VREG)
:2.6 to 4.2V(VBAT)
Output voltage :8Vrms(Typ.) @VDDO=10.0V
Piezo Speaker Driving
1-channel Analog Signal Input, 1-channel BTL output
Standby(Hi-Z),
Built-in DC-DC Converter
Built-in Low Voltage Detector
Built-in Short Protector
CMOS Technology
Package Outline :QFN28
TERMINAL CONFIGURATION
PACKAGE OUTLINE
NJU8753KN1
TEST1
TEST3
VREG
FB
VSS
VSS1
VSS1
L
X
L
X
VOUT
VR
EN2
NC
VDDO
VDD
VSS
IN
COM
EN1
TEST2
VDDO
VDDO
OUTP
VSS
NC
VSS
OUTN
VDDO
28
1
QFN28
NJU8753
- 2 - Ver.2009-03-10
BLOCK DIAGRAM
Pulse
Width
Modulator
Short
Protector
VDD
Control Logic Low Voltage
Detecto
r
Soft Start
VSS
+
-
+
-
IN
COM
EN1
VDDO
OUTP
VSS
VDDO
OUTN
VSS
Switching
Regulator
EN2 FB VR Lx VOUT VREG
VSS1
TEST1
TEST2
TEST3
RIN
RFB
20k
70k
x5
NJU3555NJU8753
-3-
Ver.2009-03-10
TERMINAL DESCRIPTION
No. SYMBOL I/O Function
1,
2,
23
TEST1
TEST3
TEST2
I Maker test
These terminals must be connected to GND.
3 VREG − Switching regulator Power Supply : VREG=2.85V
4 FB I Switching regulator Feedback resistor connection
5, 17,
19, 27 VSS − Power GND : VSS=0V
6,7 VSS1 − Switching regulator Power GND: VSS1=0V
8,9 Lx I Switching regulator coil connection
10 VOUT − Switching regulator Power Supply : VOUT=10.0V
11 VR O Switching regulator step-up voltage setting resistor connection
12 EN2 I
Switching regulator Standby Control
High : Step-up ON Low : Standby ON
This terminal must be connected to VREG when step-up ON.
13, 18 NC − Non connection
14, 15,
21, 22 VDDO − Output Power supply
16 OUTN O Negative Output
20 OUTP O Positive Output
24 EN1 I
Power Amplifier Standby Control
High : Standby OFF Low : Standby ON
This terminal must be connected to VDD when Standby OFF.
25 COM − Analog common
26 IN I Audio Signal Input
28 VDD − Power Supply: VDD=2.85V
* VSS terminals(pins 5 and 17 and 19 and 27), VSS1 terminals(pins 6 and 7) should be connected at the
nearest point to the IC.
* VDDO terminals(pins 14 and 15 and 21 and 22) should be connected at the nearest point to the IC.
* OUTP terminal(pin 20), OUTN terminal(pin 16) require Schottky barrier diodes. (Refer to the “TYPICAL
APPLICATION CIRCUIT”)
* Lx terminals(pins 8 and 9) require caution to the extraneous noise including the ESD(electrical static
discharge) because the ESD protection can't be designed as well as other terminals.
Require extra caution when the input voltage (VBAT: Refer to the “TYPICAL APPLICATION CIRCUIT”)
to the Lx terminal is supplied directly from the external because the extraneous noise including
the ESD appears easily.
NJU8753
- 4 - Ver.2009-03-10
FUNCTIONAL DESCRIPTION
(1) Input signal
The amount of current passing through a capacitive load increases proportionately with frequency of audio
signal. Input filters should be put in the input line to reduce load current at high frequency-band.
The 1st–order RC type HPF(High Pass Filter) and the 1st-order RC type LPF(Low Pass Filter) are
composed of input filters.
fCH1(Cut-off frequency of HPF) and fCL1(Cut-off frequency of LPF) are determined by input resistance(RIN),
resistor for LPF(RLPF), capacitor for LPF(CLPF) and AC coupling capacitor(CC). (RLPF, CLPF, CC: Refer to the
“TYPICAL APPLICATION CIRCUIT”)
When RIN=20k, RLPF=2.4k and CLPF=0.022µF, CC=2.2µF, fCH1 and fCL1 are roughly calculated as
following expressions.
When SBDs are added between OUTP and VSS, OUTN and VSS, the fCL1(Cut-off frequency of LPF) must be
less than 7KHz. When SBDs are not added, the fCL1 must be less than 3KHz.
Input amplitude impressed to IN terminal of IC (VIC) must be less than VDD[Vpp].
When VDD=2.85V, RLPF=2.4k , Audio signal maximum input level VINMAX for considering as VIC<=VDD
[Vpp] VINMAX are roughly calculated as following expressions.
(2) Output signal
The OUTP and OUTN generate PWM output signals, which will be converted to analog signal via external
2nd-order or higher LC filter.
LC type LPF is composed of the coil (L) and Piezo Speaker (CL).
The dump resistance (RDAMP) is connected between the OUTN terminal and the coil between the OUTP
terminal and the coil to reduce the cut off frequency (fc) of LPF consumption electric current neighborhood
signal input.
Set it up so that the value of L, CL and RDAMP may become Gain(Q) <1 of LPF in (L, CL, COUT, RDAMP :
Refer to the “TYPICAL APPLICATION CIRCUIT”)
When L=47µH, CL=2.0µF, C OUT=0.1µF, RDAMP =4.7, RDCR=0.2, LPF(fc) and Q are roughly calculated
as following expressions.
(3) Power Amplifier Standby
By setting the EN1 terminal to “L”, the standby mode is enabled. In the standby mode, the entire functions of
the NJU8753 enter a low-power state, and the output terminals (OUTP and OUTN) are high impedance.
(4) Low Voltage Detector
When the power supply voltage drops down to below VDD(MIN), the internal oscillation is halted for
prevention to generate unwanted frequency, and the output terminals (OUTP, OUTN) become in high
impedance.
Hz][5
102.2)104.21020(3.142 1
)(2 16-33
CH1 ≅
×××+×××
=
+
=
CLPFIN CRR
f
π
[kHz]3
10022.0)104.2//1020(3.142 1
)//(2 16-33
CL1 ≅
××××××
==
LPFLPFIN CRR
f
π
(
)
(
)
][1.3
1020 85.21020104.2
RVRR 3
33
IN
ICINLPF
INMAX VppV ≅
×
××+×
=
×+
=
()
()
[kHz]11
101.0100.2210473.142
1
22
1
c6-6-6- ≅
×+××××××
=
+
=
OUTL CCL
f
π
()()()
()
.70
101.0100.22 1074
2.07.4 1
2
1
Q6-6-
-6
≅
×+××
×
×
+
=
++
=
OUTLDCRDAMP CC L
RR
NJU3555NJU8753
-5-
Ver.2009-03-10
(5) Step-up switching regulator
The switching regulator is used as power supply(VDDO) for power amplifier of class-D. The PFM controlled
switching regulator works with external components, which are coil, capacitor, Schottky barrier diode and
step-up voltage setting resistance.
By setting the EN2 terminal to “H”, the step-up operation is enabled, and in case of “L”, standby mode is
enabled.
Step-up voltage is set by internal reference voltage(VREG / 2) and external resistors.
The step-up voltage can be calculated by the following methods:
<Calculation of the step-up voltage>
The step-up voltage is determined by internal reference voltage(VREF), R1 and R2. (See Figure.2)
example: VDD=2.85V, Internal reference voltage(VREF) = VREG / 2=1.425[V], R1=2M, R2=330k”
Step-up voltage[V] = VREF×((R1+R2)/R2) = 1.425×((2M + 330k)/330k) = 10.06[V] ”
Note)
*1 Apply VREG first, next VBAT. Otherwise, the voltage stress may cause a permanent damage to the IC.
*2 The kickback voltage by the step-up voltage operation varies with the fixed number of the external
components and the PCB patterns. Output power supply(VDDO) must not exceed the absolute
maximum rating.
(6) Short Circuit Protection
The short protector, which protects the NJU8753 against high short-circuit current, turns off the output
driver. After about 5 seconds from the protection, the NJU8753 returns to normal operation. The short
protector functions at the following accidents.
-Short between OUTP and OUTN
-Short between OUTP and VSS
-Short between OUTN and VSS
Note)
*1 The detectable current and the period for the protection depend on the power supply voltage, chip
temperature and ambient temperature.
*2 The short protector is not effective for a long term short-circuit current but for an instantaneous
accident. Continuous high-current may cause permanent damage to the NJU8753.
NJU8753
- 6 - Ver.2009-03-10
ABSOLUTE MAXIMUM RATINGS
(Ta=25°C)
PARAMETER SYMBOL CONDITIONS RATING UNIT Note
VDD -0.3 to +4.0 V
VREG -0.3 to +4.0 V
With SBDs -0.3 to +14.0
Supply Voltage
VDDO Without SBDs -0.3 to +9.5 V 6
With SBDs -0.3 to +14.0
LX Input Voltage VLX Without SBDs. -0.3 to +9.5 V 6
FB Input Voltage VFB -0.3 to +4.0 V
Input Voltage Vin -0.3 to VDD+0.3 V
Operating
Temperature Topr -40 to +85 °C
Storage
Temperature Tstg -40 to +125 °C
Power
Dissipation PD 640 * mW
* : Mounted on two-layer board of based on the JEDEC.
Note 1) All voltage are relative to “VSS= 0V” reference.
Note 2) The LSI must be used inside of the “Absolute maximum ratings”. Otherwise, a stress may cause
permanent damage to the LSI.
NJU3555NJU8753
-7-
Ver.2009-03-10
ELECTRICAL CHARACTERISTIC
(Ta=25°C, VDD=VREG=2.85V, VBAT=3.7V, VDDO=10V, VSS=VSS1=0V,
TEST1=TEST2=TEST3=0V, EN1=EN2=2.85V,
Input Signal=1kHz, Input Signal Level=150mVrms,Frequency Band=20Hz to 20kHz,
Load Impedance=2.0µF, 2nd-order 11kHz LC Filter(Q=0.7),
When the SBDs are connected between OUTP and VSS, OUTN and VSS.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Note
VDD Supply Voltage VDD 2.6 2.85 3.6 V
VREG Supply Voltage VREG 2.6 2.85 3.6 V
VBAT Input Voltage VBAT 2.6 3.7 4.2 V
With SBDs 6.5 10.0 12.0
VDDO Supply Voltage VDDO Without SBDs. 6.5 7.5 8.5 V 6
Input Impedance ZIN IN terminal - 20 - K
Voltage Gain AV - 31 - dB
THD+N THD Input Signal Level =200mVrms - 0.05 0.08 % 4
Maximum Output Vo Output THD+N=10% - 8.0 - Vrms
S/N SN A weight - 80 - dB 4
Operating Current(Standby) IST EN1=EN2=0V - - 1 µA
Operating Current
(No signal input) ISS No-load operating
No Signal Input - 10 15 mA
VIH EN1, EN2 terminals 0.7VDD - VDD V
Input Voltage VIL EN1, EN2 terminals 0 - 0.3VDD V
Input Leakage Current ILK EN1, EN2 terminals - - ±1.0 µA
Switching regulator
Oscillating Frequency fOSC 220 300 380 kHz
Switching regulator
Maximum Load Current IOUT Step-up Voltage =10.0V
VOUT= 10.0V X 95% 50 - - mA
Switching regulator
Load Stability VOUT Step-up Voltage =10.0V
IOUT =10mA to 50mA - 100 - mV
*The LSI must be used within the “Absolute maximum ratings”. Otherwise, a stress may cause permanent
damage to the LSI.
Note 3) Test system of the THD+N and S/N
The THD+N and S/N are tested in the system shown in Figure 1, where a 2nd-order LC LPF and
another filter incorporated in an audio analyzer are used.
2nd-order LC LPF : Refer to “Typical Application Circuit”
Filters : 22Hz HPF + 20kHz LPF(AES17)
(with the A-Weight filter for S/N test)
Input Signal
THD
Measuring
Apparatus
Filter
20kHz
(AES17)
2nd-order
LC LPF
NJU8753 Test Board Audio Analyzer
Figure 1. Output THD+N and S/N Test System
NJU8753
NJU8753
- 8 - Ver.2009-03-10
TYPICAL APPLICATION CIRCUIT
Note 4) De-coupling capacitors must be connected between each power supply terminal and GND.
Note 5) The LC filter and the schottky barrier diodes should be laid out nearest to the IC.
OUTP terminal(pin 20), OUTN terminal(pin 16) require schottky barrier diodes for terminal protection.
When SBDs is not used, the VDDO supply voltage maximum is 8.5V. (SBD: When Tj=125°C, IR=less
than 10mA at reverse voltage12V*1. When Tj=25°C, Forward voltage (VF) =0.45V, Forward current (IF)
=more than1A at more than 12V)
*1 Absolute maximum ratings is more than 20V.
Note 6) The LSI must be used inside of the following ratings. Otherwise, a stress may cause permanent
damage to the regulator.
SBDs are added No SBDs
VDDO (Supply Voltage) MAX=12V MAX=8.5V
Input cut-off frequency MAX=7kHz MAX=3kHz
Output cut-off frequency MAX=15kHz
Q (The gain of LPFat MAX=1
Piezo Speaker MAX=2.2µF
The capacitor between VDDO and VSS MAX=22µF
The coil for Lx terminal MIN=22µH
Input voltage MAX=VDD[Vpp]
Note 7) The transition time for EN1 and EN2 signals must be less than 100µs. Otherwise, a malfunction may
be occurred.
Figure 2. Application Circuit example
Piezo Speaker
NJU8753
OUTP(20)
OUTN(16)
VDD(28)
VSS(27)
0.1µF
10µF
VDD
IN(26)
COM(25)
EN1(24)
10µF
47µH
CL:2µF
47uH
4.7
4.7
IN 0.1µF
0.22µF
2.4k
VDDO(14,15)
VOUT(10)
VBAT
VSS(17,19)
FB(4)
Lx(8,9)
TEST1(1)
TEST2
(
23
)
VDDO(21,22)
SBD
R1
R2
2M
330k
0.1µF10µF
TEST
3
(
2
)
EN2(12)
VREG(3)
VSS(5)
0.1µF
10µF
VDD
0.1µF
0.1µF
22µH(DCR=0.5)
22µF
VR(11)
VSS1(6,7)
0.1µF
SBD
SBD
RDUMP L
COUT
RDUMP L
COUT
CIN
RLPF
CLPF
NJU3555NJU8753
-9-
Ver.2009-03-10
Note 8) Apply VREG first, next VBAT. Otherwise, the voltage stress may cause a permanent damage to the IC.
The VDDO is not able to accept from external power supply. Therefore use the DC-DC converter of the
NJU8753.
Note 9) The Lx terminals require caution to the extraneous noise including the ESD(electrical static
discharge) because the ESD protection can't be designed as well as other terminals.
Require extra caution when the input voltage (VBAT) to the Lx terminal is supplied directly from the
external because the extraneous noise including the ESD appears easily.
Note 10) The kickback voltage by the step-up voltage operation varies with the fixed number of the external
components and the PCB patterns. Output power supply(VDDO) must not exceed the absolute
maximum rating.
Note 11) The above circuit shows only application example and does not guarantee the any electrical
characteristics. Therefore, please test the circuit carefully to fit your application.
The cut off frequency of the LC filter influences the quality of sound.
The Q factor of the LC filter must be less than “1”. Otherwise, the operating current increase when
the frequency of input signal is closed to the cut off frequency.
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
