SP706SEN-L/TR - Exar - Datasheet.Live

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June 2010 Rev. 2.0.0

Exar Corporation www.exar.com

48720 Kato Road, Fremont CA 94538, USA Tel. +1 510 668-7000 – Fax. +1 510 668-7001

GENERAL DESCRIPTION

The SP706R/S/T and SP708R/S/T series is a

family of microprocessor (µP) supervisory

circuits that integrate myriad components

involved in discrete solutions which monitor

power-supply and battery in µP and digital

systems.

The SP706R/S/T and SP708R/S/T series will

significantly improve system reliability and

operational efficiency when compared to

solutions obtained with discrete components.

The features of the SP706R/S/T and

SP708R/S/T series include a watchdog timer, a

µP reset, a Power Fail Comparator, and a

manual-reset input.

The SP706R/S/T and SP708R/S/T series is

ideal for 3.0V or 3.3V applications in

automotive systems, computers, controllers,

and intelligent instruments. The SP706R/S/T

and SP708R/S/T series is an ideal solution for

systems in which critical monitoring of the

power supply to the µP and related digital

components is demanded.

APPLICATIONS

• Processors & DSPs Based Systems

• Industrial & Medical Instruments

FEATURES

• Precision Low Voltage Monitor

− SP706R/SP708R: +2.63V

− SP706S/SP708S: +2.93V

− SP706T/SP708T: +3.08V

• 200ms RESET Pulse Width

− SP706R/S/T: Active Low

− SP708R/S/T: Active High and Active Low

• Independent Watchdog Timer

− 1.6s Timeout (SP706R/S/T)

− Enable/Disable Function

• 40µA Maximum Supply Current

• Debounced TTL/CMOS Manual Reset

Input

• RESET Asserted Down to V

CC

=1V

• V

CC

Glitch Immunity

• Voltage Monitor for Power Failure or

Low Battery Warning

• 8-Pin NSOIC and MSOP Packages

• Pin Compatible with Industry

Standards 706R/S/T and 708R/S/T

Part Number RESET Threshold RESET Active Manual RESET Watchdog PFI Accuracy

SP706R 2.63V Low Yes

Yes 4%

SP706S 2.93V Low Yes

Yes 4%

SP706T 3.08V Low Yes

Yes 4%

SP708R 2.63V Low and High Yes No 4%

SP708S 2.93V Low and High Yes No 4%

SP708T 3.08V Low and High Yes No 4%

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3.

.0

0V

V/

/3

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.3

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ABSOLUTE MAXIMUM RATINGS

These are stress ratings only and functional operation of

the device at these ratings or any other above those

indicated in the operation sections of the specifications

below is not implied. Exposure to absolute maximum

rating conditions for extended periods of time may affect

reliability.

V

CC

.......................................................... -0.3V to 6.0V

All Other Inputs (Note 1) ................... -0.3V to (V

CC

+0.3V)

Input Current

VCC ................................................................. 20mA

GND ................................................................ 20mA

Output Current (All outputs) ............................... 20mA

ESD Rating (HBM - Human Body Model) .................... 2kV

Continuous Power Dissipation

SO (derate 5.88mW/°C above +70°C) ...............471mW

Mini SO (derate 4.10mW/°C above +70°C) ........330mW

Storage Temperature .............................. -65°C to 160°C

Lead Temperature (Soldering, 10 sec) ....................300°C

ELECTRICAL SPECIFICATIONS

Unless otherwise indicated, V

CC

= 2.7V to 5.5V (SP70xR), V

CC

= 3.15V to 5.5V (SP70xS), V

CC

= 3.0V to 5.5V (SP70xT), T

A

=

T

MIN

to T

MAX

, typical at 25°C.

Parameter Min. Typ. Max. Units Conditions

Operating Voltage Range V

CC

1.0 5.5 V

Supply Current I

SUPPLY

25 40 µA

MR=V

CC

or floating, WDI floating

Reset Threshold

2.55 2.63 2.70

V

SP706R. SP708R

2.85 2.93 3.00 SP706S. SP708S

3.00 3.08 3.15 SP706T. SP708T

Reset Threshold Hysteresis 20 mV

Note 2

Reset Pulse Width t

RS

140 200 280 ms

Note 2

RESET Output Voltage

V

OH

0.8xV

CC

V

RST(MAX)

<V

CC

<3.6V, I

SOURCE

=500µA

V

OL

0.3 V

RST(MAX)

<V

CC

<3.6V, I

SINK

=1.2mA

V

OH

V

CC

-1.5 4.5V<V

CC

<5.5V, I

SOURCE

=800µA

V

OL

0.4 4.5V<V

CC

<5.5V, I

SINK

=3.2mA

RESET Output Voltage

V

OH

V

CC

-0.6 V

RST(MAX)

<V

CC

<3.6V, I

SOURCE

=215µA

V

OL

0.3 V

RST(MAX)

<V

CC

<3.6V, I

SOURCE

=1.2mA

V

OH

V

CC

-1.5 4.5V<V

CC

<5.5V, I

SOURCE

=800µA

V

OL

0.4 4.5V<V

CC

<5.5V, I

SOURCE

=3.2mA

Watchdog Timeout Period t

WD

1.00 1.60 2.25 s V

CC

<3.6V

WDI Pulse Width t

WP

(note 1) 50 ns

V

IL

=0.4V, V

IH

=0.8xV

CC

WDI Input Threshold

V

IL

0.6 V

RST(MAX)

<V

CC

<3.6V

V

IH

0.7xV

CC

V

RST(MAX)

<V

CC

<3.6V

V

IL

0.8 V

CC

=5V

V

IH

3.5 V

CC

=5V

WDI Input Current -1 0.02 1 µA

WDI=0V or WDI=V

CC

WDO Output Voltage

V

IL

0.8xV

CC

V

RST(MAX)

<V

CC

<3.6V, I

SOURCE

=500µA

V

IH

0.3 V

RST(MAX)

<V

CC

<3.6V, I

SINK

=1.2mA

V

IL

V

CC

-1.5 4.5V<V

CC

<5.5V, I

SOURCE

=800µA

V

IH

0.4 4.5V<V

CC

<5.5V, I

SINK

=3.2mA

MR Pull-up Current 25 70 250 µA MR = 0V, V

RST(MAX)

<V

CC

<3.6V

100 250 600 MR = 0V, 4.5V<V

CC

<5.5V

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Parameter Min. Typ. Max. Units Conditions

MR Pulse Width t

MR

500

ns V

RST(MAX)

<V

CC

<3.6V

150 4.5V<V

CC

<5.5V

MR Input Threshold

V

IL

0.6 V

RST(MAX)

<V

CC

<3.6V

V

IH

0.7xV

CC

V

RST(MAX)

<V

CC

<3.6V

V

IL

0.8 4.5V<V

CC

<5.5V

V

IH

2.0 4.5V<V

CC

<5.5V

MR to Reset Out Delay t

MD

750

ns V

RST(MAX)

<V

CC

<3.6V

250 4.5V<V

CC

<5.5V

PFI Input Threshold 1.20 1.25 1.30 V V

CC

=3.0V - SP70xR, PFI falling

V

CC

=3.3V - SP70xS/T, PFI falling

PFI Input Current -25.00 0.01 25.00 nA

PFO Output Voltage

V

IL

0.8xV

CC

V

RST(MAX)

<V

CC

<3.6V, I

SOURCE

=500µA

V

IH

0.3 V

RST(MAX)

<V

CC

<3.6V, I

SINK

=1.2mA

V

IL

V

CC

-1.5 4.5V<V

CC

<5.5V, I

SOURCE

=800µA

V

IH

0.4 4.5V<V

CC

<5.5V, I

SINK

=3.2mA

Note 1:WDI minimum rise /fall time is 1µs.

BLOCK DIAGRAM

Fig. 1: SP706R/S/T Block Diagram

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SP

P7

70

06

6R

R/

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S/

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S

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P7

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3

3.

.0

0V

V/

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.3

3V

V

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Fig. 2: SP708R/S/T Block Diagram

PIN ASSIGNMENT

Fig. 3: Pin Assignment

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3.

.0

0V

V/

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.3

3V

V

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PIN DESCRIPTION

Name

Pin Number

Description

SP706R/S/T SP708R/S/T

SOIC MSOP SOIC MSOP

MR 1 3 1 3

Manual Reset

This input triggers a reset pulse when pulled below 0.8V. This active

LOW input has an internal 70µA pull-up current. It can be driven

from a TTL or CMOS logic line or shorted to ground with a switch.

V

CC

2 4 2 4

Voltage Input

GND 3 5 3 5

Ground reference for all signals

PFI 4 6 4 6

Power-Fail Input

When this voltage monitor input is less than 1.25V, PFO goes LOW.

Connect PFI to ground or V

CC

when not in use.

PFO 5 7 5 7

Power-Fail Output

This output is LOW until PFI is less then 1.25V

WDI 6 8 - -

Watchdog Input

If this input remains HIGH or LOW for 1.6s, the internal watchdog

timer times out and WDO goes LOW. Floating WDI or connecting WDI

to a high-impedance tri-state buffer disables the watchdog feature.

The internal watchdog timer clears whenever RESET is asserted, WDI

is tri-stated, or whenever WDI sees a rising or falling edge.

N.C. - - 6 8

No Connect

RESET 7 1 7 1

Active-LOW RESET Output

This output pulses LOW for 200ms when triggered and stays LOW

whenever V

CC

is below the reset threshold. It remains LOW for 200ms

after V

cc

rises above the reset threshold or MR goes from LOW to

HIGH. A watchdog timeout will not trigger RESET unless WDO is

connected to MR.

WDO 8 2 - -

Watchdog Output

This output pulls LOW when the internal watchdog timer finishes its

1.6s count and does not go HIGH again until the watchdog is cleared.

WDO also goes LOW during low-line conditions. Whenever V

CC

is

below the reset threshold, WDO stays LOW. However, unlike RESET,

WDO does not have a minimum pulse width. As soon as V

CC

is above

the reset threshold, WDO goes HIGH with no delay.

RESET - - 8 2

Active-HIGH RESET Output

This output is the complement of RESET. Whenever RESET is HIGH,

RESET is LOW and vice-versa. Note that the SP708R/S/T has a reset

output only.

ORDERING INFORMATION

Part Number Temperature

Range Marking Package Packing

Quantity Note 1 Note 2

SP706RCN-L 0°C≤T

A

≤+70°C

SP706RC

YYWWL

X

8-pin NSOIC Bulk Lead Free

SP706RCN-L/TR 0°C≤T

A

≤+70°C 8-pin NSOIC 2.5K/Tape & Reel Lead Free

SP706RCU-L 0°C≤T

A

≤+70°C

706R

CXXX

YWW

8-pin MSOP Bulk Lead Free

SP706RCU-L/TR 0°C≤T

A

≤+70°C 8-pin MSOP 2.5K/Tape & Reel Lead Free

SP706REN-L -40°C≤T

A

≤+85°C

SP706RE

YYWWL

X

8-pin NSOIC Bulk Lead Free

SP706REN-L/TR -40°C≤T

A

≤+85°C 8-pin NSOIC 2.5K/Tape & Reel Lead Free

SP706REU-L -40°C≤T

A

≤+85°C

706R

EXXX

YWW

8-pin MSOP Bulk Lead Free

SP706REU-L/TR -40°C≤T

A

≤+85°C 8-pin MSOP 2.5K/Tape & Reel Lead Free

SP706SCN-L 0°C≤T

A

≤+70°C

SP706SC

YYWWL

X

8-pin NSOIC Bulk Lead Free

SP706SCN-L/TR 0°C≤T

A

≤+70°C 8-pin NSOIC 2.5K/Tape & Reel Lead Free

SP706SCU-L 0°C≤T

A

≤+70°C

706S

CXXX

YWW

8-pin MSOP Bulk Lead Free

SP706SCU-L/TR 0°C≤T

A

≤+70°C 8-pin MSOP 2.5K/Tape & Reel Lead Free

S

SP

P7

70

06

6R

R/

/S

S/

/T

T

-

S

SP

P7

70

08

8R

R/

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S/

/

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3

3.

.0

0V

V/

/3

3.

.3

3V

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Part Number Temperature

Range Marking Package Packing

Quantity Note 1 Note 2

SP706SEN-L -40°C≤T

A

≤+85°C

SP706SE

YYWWL

X

8-pin NSOIC Bulk Lead Free

SP706SEN-L/TR -40°C≤T

A

≤+85°C 8-pin NSOIC 2.5K/Tape & Reel Lead Free

SP706SEU-L -40°C≤T

A

≤+85°C

706S

EXXX

YWW

8-pin MSOP Bulk Lead Free

SP706SEU-L/TR -40°C≤T

A

≤+85°C 8-pin MSOP 2.5K/Tape & Reel Lead Free

SP706TCN-L 0°C≤T

A

≤+70°C

SP706TC

YYWWL

X

8-pin NSOIC Bulk Lead Free

SP706TCN-L/TR 0°C≤T

A

≤+70°C 8-pin NSOIC 2.5K/Tape & Reel Lead Free

SP706TCU-L 0°C≤T

A

≤+70°C

706T

CXXX

YWW

8-pin MSOP Bulk Lead Free

SP706TCU-L/TR 0°C≤T

A

≤+70°C 8-pin MSOP 2.5K/Tape & Reel Lead Free

SP706TEN-L -40°C≤T

A

≤+85°C

SP706TE

YYWWL

X

8-pin NSOIC Bulk Lead Free

SP706TEN-L/TR -40°C≤T

A

≤+85°C 8-pin NSOIC 2.5K/Tape & Reel Lead Free

SP706TEU-L -40°C≤T

A

≤+85°C

706T

EXXX

YWW

8-pin MSOP Bulk Lead Free

SP706TEU-L/TR -40°C≤T

A

≤+85°C 8-pin MSOP 2.5K/Tape & Reel Lead Free

SP708REN-L -40°C≤T

A

≤+85°C

SP708RE

YYWWL

X

8-pin NSOIC Bulk Lead Free

SP708REN-L/TR -40°C≤T

A

≤+85°C 8-pin NSOIC 2.5K/Tape & Reel Lead Free

SP708SCN-L 0°C≤T

A

≤+70°C

SP708SC

YYWWL

X

8-pin NSOIC Bulk Lead Free

SP708SCN-L/TR 0°C≤T

A

≤+70°C 8-pin NSOIC 2.5K/Tape & Reel Lead Free

SP708SCU-L 0°C≤T

A

≤+70°C

708S

UXXX

YWW

8-pin MSOP Bulk Lead Free

SP708SCU-L/TR 0°C≤T

A

≤+70°C 8-pin MSOP 2.5K/Tape & Reel Lead Free

SP708SEN-L -40°C≤T

A

≤+85°C

SP708SE

YYWWL

X

8-pin NSOIC Bulk Lead Free

SP708SEN-L/TR -40°C≤T

A

≤+85°C 8-pin NSOIC 2.5K/Tape & Reel Lead Free

SP708TCN-L 0°C≤T

A

≤+70°C

SP708TC

YYWWL

X

8-pin NSOIC Bulk Lead Free

SP708TCN-L/TR 0°C≤T

A

≤+70°C 8-pin NSOIC 2.5K/Tape & Reel Lead Free

SP708TEN-L -40°C≤T

A

≤+85°C

SP706TE

YYWWL

X

8-pin NSOIC Bulk Lead Free

SP708TEN-L/TR -40°C≤T

A

≤+85°C 8-pin NSOIC 2.5K/Tape & Reel Lead Free

“YY” = Year – “WW” = Work Week – “X” = Lot Number

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R/

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S/

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S

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P7

70

08

8R

R/

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3

3.

.0

0V

V/

/3

3.

.3

3V

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TYPICAL PERFORMANCE CHARACTERISTICS

All data taken at V

CC

= 2.7V to 5.5V (SP70xR), V

CC

= 3.15V to 5.5V (SP70xS), V

CC

= 3.0V to 5.5V (SP70xT), T

A

= 25°C,

unless otherwise indicated.

Fig. 4: Power-Fail Comparator

De-Assertion Response Time

Fig. 5: Power-Fail Comparator

De-Assertion Response Time Circuit

Fig. 6: Power-Fail Comparator

Assertion Response Time

Fig. 7: Power-Fail Comparator

Assertion Response Time Circuit

Fig. 8: SP706 RESET Output Voltage

vs. Supply Voltage

Fig. 9: SP706 RESET Output Voltage

vs. Supply Voltage Circuit

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70

06

6R

R/

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S

SP

P7

70

08

8R

R/

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S/

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3

3.

.0

0V

V/

/3

3.

.3

3V

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Fig. 10: SP706 RESET Response Time

Fig. 11: SP706 RESET Response Time Circuit

Fig. 12: SP708 RESET and RESET Assertion

Fig. 13: SP708 RESET and RESET De-Assertion

Fig. 14: SP708 RESET and RESET Assertion and De-Assertion Circuit

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SP

P7

70

06

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R/

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S/

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S

SP

P7

70

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8R

R/

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3

3.

.0

0V

V/

/3

3.

.3

3V

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Fig. 15: SP708 RESET Output Voltage

vs. Supply Voltage

Fig. 16: SP708 RESET Response Time

Fig. 17: SP708 RESET Output Voltage vs. Supply Voltage

and SP813L RESET Response Time Circuit

S

SP

P7

70

06

6R

R/

/S

S/

/T

T

-

S

SP

P7

70

08

8R

R/

/S

S/

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3

3.

.0

0V

V/

/3

3.

.3

3V

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FEATURES

The SP706R/S/T and SP708R/S/T series

provides four

key functions:

1. A reset output during power-up, power-

down

and brownout conditions.

2. An independent watchdog output that goes

LOW if the watchdog input has not been

toggled

within 1.6 seconds.

3. A 1.25V threshold detector for power-fail

warning, low battery detection, or monitoring

a

power supply other than +3.3V/+3.0V.

4. An active-LOW manual-reset that allows

RESET to be triggered by a pushbutton switch.

The SP706R/S/T devices are the same as the

SP708R/S/T devices except for the active-

HIGH

RESET substitution of the watchdog

timer.

THEORY OF OPERATION

The SP706R/S/T-SP708R/S/T series is a

microprocessor (µP) supervisory circuit that

monitors the power supplied to digital circuits

such as microprocessors, microcontrollers, or

memory. The series is an ideal solution for

portable, battery-powered equipment that

requires power supply monitoring.

Implementing this series will reduce the

number of components and overall complexity.

The watchdog functions of this product family

will continuously oversee the operational

status of a system. The operational features

and benefits of the SP706R/S/T-SP708R/S/T

series are described in more detail below.

RESET OUTPUT

A microprocessor's reset input starts the µP in

a known state. The SP706R/S/T-SP708R/S/T

series asserts reset during power-up and

prevents code execution errors during power

down or brownout conditions.

On power-up, once V

CC

reaches 1V, RESET is a

guaranteed logic LOW of 0.4V or less. As V

CC

rises, RESET stays LOW. When V

CC

rises above

the reset threshold, an internal timer releases

RESET after 200ms. RESET pulses LOW

whenever V

CC

dips below the reset threshold,

such as in a brownout condition. When a

brownout condition occurs in the middle of a

previously initiated reset pulse, the pulse

continues for at least another 140ms. On

power down, once V

CC

falls below the reset

threshold, RESET stays LOW and is

guaranteed to be 0.4V or less until V

CC

drops

below 1V.

The active-HIGH RESET output is simply the

complement of the RESET output and is

guaranteed to be valid with V

CC

down to 1.1V.

Some µPs, such as Intel's 80C51, require an

active-HIGH reset pulse.

WATCHDOG TIMER

The SP706R/S/T-SP708R/S/T watchdog circuit

monitors the µP's activity. If the µP does not

toggle the watchdog input (WDI) within 1.6

seconds and WDI is not tri-stated, WDO goes

LOW. As long as RESET is asserted or the WDI

input is tri-stated, the watchdog timer will stay

cleared and will not count. As soon as RESET

is released and WDI is driven HIGH or LOW,

the timer will start counting. Pulses as short as

50ns can be detected.

Typically, WDO will be connected to the non-

maskable interrupt input (NMI) of a µP. When

V

CC

drops below the reset threshold, WDO will

go LOW whether or not the watchdog timer

had timed out. Normally this would trigger an

NMI but RESET goes LOW simultaneously and

thus overrides the NMI.

If WDI is left unconnected, WDO can be used

as a low-line output. Since floating WDI

disables the internal timer, WDO goes LOW

only when V

CC

falls below the reset threshold,

thus functioning as a low-line output.

Fig. 18: Watchdog Timing Waveforms

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Fig. 19: Timing Diagrams with WDI tri-stated.

P

OWER-FAIL COMPARATOR

The power-fail comparator can be used for

various purposes because its output and non

inverting input are not internally connected.

The inverting input is internally connected to a

1.25V reference.

To build an early-warning circuit for power

failure, connect the PFI pin to a voltage divider

as shown in Figure 20. Choose the voltage

divider ratio so that the voltage at PFI falls

below 1.25V just before the +5V regulator

drops out. Use PFO to interrupt the µP so it

can prepare for an orderly power-down.

Fig. 20: Typical Operating Circuit

MANUAL RESET

The manual-reset input (MR) allows RESET to

be triggered by a pushbutton switch. The

switch is effectively debounced by the 140ms

minimum RESET pulse width. MR is TTL/CMOS

logic compatible, so it can be driven by an

external logic line. MR can be used to force a

watchdog timeout to generate a RESET pulse

in the SP706R/S/T-SP708R/S/T. Simply

connect WDO to MR.

Ensuring a Valid Reset Output Down to

V

CC

=0V

When V

CC

falls below 1V, the RESET output no

longer sinks current, it becomes an open

circuit. High-impedance CMOS logic inputs can

drift to undetermined voltages if left undriven.

If a pull-down resistor is added to the RESET

pin, any stray charge or leakage currents will

be shunted to ground, holding RESET LOW.

The resistor value is not critical. It should be

about 100KΩ, large enough not to load RESET

and small enough to pull RESET to ground.

MONITORING VOLTAGES OTHER THAN THE

UNREGULATED DC INPUT

Monitor voltages other than the unregulated

DC by connecting a voltage divider to PFI and

adjusting the ratio appropriately. If required,

add hysteresis by connecting a resistor (with a

value approximately 10 times the sum of the

two resistors in the potential divider network)

between PFI and PFO. A capacitor between PFI

and GND will reduce the power-fail circuit's

sensitivity to high-frequency noise on the line

being monitored. RESET can be used to

monitor voltages other than the +3.3V/+3.0V

V

CC

line. Connect PFO to MR to initiate a

RESET pulse when PFI drops below 1.25V.

Figure 21 shows the SP706R/S/T-SP708R/S/T

series configured to assert RESET when the

+3.3V/3.0V supply falls below the RESET

threshold, or when the +12V supply falls

below approximately 11V.

MONITORING A NEGATIVE VOLTAGE SUPPLY

The power-fail comparator can also monitor a

negative supply rail, shown in Figure 22. When

the negative rail is good (a negative voltage of

large magnitude), PFO is LOW. By adding the

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resistors and transistor as shown, a HIGH PFO

triggers RESET. As long as PFO remains HIGH,

the SP706R/S/T-SP708R/S/T series will keep

RESET asserted (where RESET = LOW and

RESET = HIGH). Note that this circuit's

accuracy depends on the PFI threshold

tolerance, the V

CC

line, and the resistors.

Fig. 21: Monitoring +3.3V/+3.0V and +12V Power

Supplies

Fig. 22: Monitoring a Negative Voltage Supply

I

NTERFACING TO µPS WITH BIDIRECTIONAL

RESET PINS

µPs with bidirectional RESET pins, such as the

Motorola 68HC11 series, can contend with the

SP705/706/707/708 RESET output. If, for

example, the RESET output is driven HIGH and

the µP wants to pull it LOW, indeterminate

logic levels may result. To correct this,

connect a 4.7KΩ resistor between the RESET

output and the µP reset I/O, as shown if

Figure 23. Buffer the RESET output to other

system components.

Fig. 23: Interfacing to Microprocessors

with Bidirectional RESET I/O (SP706)

N

EGATIVE-GOING V

CC

TRANSIENT

While issuing resets to the μP during power-

up, power-down, and brownout conditions,

these supervisors are relatively immune to

short duration negative-going VCC transients

(glitches). It is usually undesirable to reset the

μP when V

CC

experiences only small glitches.

Figure 24 shows maximum transient duration

vs. reset-comparator overdrive, for which

reset pulses are not generated. The data was

generated using negative-going V

CC

pulses,

starting at 3.3V and ending below the reset

threshold by the magnitude indicated (reset

comparator overdrive). The graph shows the

maximum pulse width a negative-going V

CC

transient may typically have without causing a

reset pulse to be issued. As the amplitude of

the transient increases (i.e. goes farther below

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the reset threshold), the maximum allowable

pulse width decreases. Typically, a V

CC

transient that goes 100mV below the reset

threshold and lasts for 40μs or less will not

cause a reset pulse to be issued. A 100nF

bypass capacitor mounted close to the VCC pin

provides additional transient immunity.

Fig. 24: Maximum Transient Duration without Causing a

Reset Pulse vs. Reset Comparator Overdrive

APPLICATIONS

The SP706P/R/S/T-SP708R/S/T series offers

unmatched performance and the lowest power

consumption for these industry standard

devices. Refer to Figures 25 and 26 for supply

current performance characteristics rated

against temperature and supply voltages.

Fig. 25: Supply Current vs. Temperature

Fig. 26: Supply Current vs. Supply Voltage

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PACKAGE SPECIFICATION

8-PIN NSOIC

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8-PIN MSOP

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REVISION HISTORY

Revision Date Description

2.0.0 06/04/2010 Reformat of datasheet

FOR FURTHER ASSISTANCE

Email: customersupport@exar.com

Exar Technical Documentation: http://www.exar.com/TechDoc/default.aspx?

E

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design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein,

conveys no license under any patent or other right, and makes no representation that the circuits are free of patent

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user’s specific application. While the information in this publication has been carefully checked; no responsibility, however,

is assumed for inaccuracies.

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