ee November 1988 FAIRCHILD Revised December 1998 eer pepe SEMICONDUCTOR 74AC175 74ACT175 Quad D-Type Flip-Flop General Description Features The AC/ACT175 is a high-speed quad D-type flip-flop. The lB loc reduced by 50% device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D-type inputs is stored during the LOW-to-HIGH clock tran- sition. Both true and complemented outputs of each flip- Mf Asynchronous common reset flop are provided. A Master Reset input resets all flip-flops, Mf True and complement output independent of the Clock or D-type inputs, when LOW. lf Edge-triggered D-type inputs lf Buffered positive edge-triggered clock Hi Outputs source/sink 24 mA @ ACT175 has TTL-compatible inputs Ordering Code: Order Number | Package Number Package Description 74AC175SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Body 74AC175SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE Il, 5.8mm Wide 74AC175MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74AC175PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 74ACT175SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Body 74ACT175SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE Il, 5.8mm Wide 74ACT175MTGC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACT175PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering code. Logic Symbols Connection Diagram | | | | Pin Assignment for DIP and SOIC Dg Dy D2 Ds m4 is Veg Oj wr Q-42 15-0; 3 14-0; D.-45 12d, us 11f-O, IEEE/EC a7 10a, mS) eR cnD+48 afc cp c1 7 Cc Pin Descriptions Do 1D = % Pin Names Description r Do-D3 Data Inputs Q 0 cP Clock Pulse Input i 0, a 2 NG, MR Master Reset Input iH a; Qo-Q3, True Outputs - = P 05 Qo-G3 Complement Outputs FACT is a trademark of Fairchild Semiconductor Corporation. 1999 Fairchild Semiconductor Corporation DS009936.prf www.fairchildsemi.com doj4-dijg edAL-g pend SZLLOVPZ SZLOWPZ74AC175 - 74ACT175 Functional Description Truth Table The AC/ACT175 consists of four edge-triggered D-type flip- flops with individual D inputs and Q and Q outputs. The Inputs Outputs Clock and Master Reset are common. The four flip-flops @t,, MR=H @ tat will store the state of their individual D inputs on the LOW- Y|z 9 a ol a to-HIGH clock (CP) transition, causing individual Q and Q outputs to follow. A LOW input on the Master Reset (MR) will force all Q outputs LOW and Q outputs HIGH indepen- dent of Clock or Data inputs. The AC/ACT175 is useful for oe oe - 2 general logic applications where a common Master Reset and Clock are acceptable. H = HIGH Voltage Level L = LOW Voltage Level t, = Bit Time before Clock Pulse toi = Bit Time after Clock Pulse Logic Diagram wR Dg Dy Dy Dy D | L | L | cP Q cP Q ocp Q cP Q cD cD cD cD | | I J Qs Qs Qp Q Q) a Q Q% Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. eoO @O) eoO No www.fairchildsemi.comAbsolute Maximum Ratingsinote 1) Supply Voltage (Vcc) DC Input Diode Current (I),) Vv, =-0.5V Vi = Veco + 0.5V DC Input Voltage (V)) DC Output Diode Current (lox) Vo =-0.5V Vo= Voc + 0.5V DC Output Voltage (Vo) DC Output Source or Sink Current (lo) DC Vee or Ground Current per Output Pin (leg or lenp) Storage Temperature (Tstq) Junction Temperature (Ty) PDIP 0.5V to +7.0V -20 mA +20 mA -0.5V to Vec +0.5V -20 mA +20 mA -0.5V to Vec +0.5V +50 mA +50 mA -65C to +150C 140C DC Electrical Characteristics for AC Recommended Operating Conditions Supply Voltage (Vcc) AC ACT Input Voltage (Vj) Output Voltage (Vo) Operating Temperature (Ta) Minimum Input Edge Rate (AV/At) AC Devices Vin from 30% to 70% of Veco Veco @ 3.3, 4.5V, 5.5V Minimum Input Edge Rate (AV/At) ACT Devices Vin from 0.8V to 2.0V Voc @ 4.5V, 5.5V Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, with- out exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications 2.0V to 6.0V 4.5V to 5.5V OV to Voc OV to Voc 40C to +85C 125 mV/ns 125 mV/ns Symbol Parameter Veco Ta = 425C Ta =40C to +85C Units Conditions (V) Typ Guaranteed Limits Vin Minimum HIGH Level 3.0 1.5 2.1 24 Vout =0.1V Input Voltage 4.5 2.25 3.15 3.15 v or Voc 0.1V 5.5 2.75 3.85 3.85 Vit Maximum LOW Level 3.0 1.5 0.9 0.9 Vout =0.1V Input Voltage 4.5 2.25 1.35 1.35 v or Voc 0.1V 5.5 2.75 1.65 1.65 Vou Minimum HIGH Level 3.0 2.99 29 29 lout = 50 pA Output Voltage 45 4.49 44 44 Vv 5.5 5.49 54 5.4 Vin = Vit or Vin 3.0 2.56 2.46 lon =12 mA 45 3.86 3.76 Vv lon =24 mA 5.5 4.86 4.76 lou = 24 mA (Note 2) VoL Maximum LOW Level 3.0 0.002 0.1 0.1 lout = 50 pA Output Voltage 45 0.001 0.1 0.1 Vv 5.5 0.001 0.1 0.1 Vin = Vit or Vin 3.0 0.36 0.44 lol = 12 mA 45 0.36 0.44 Vv lot = 24 mA 5.5 0.36 0.44 lot = 24 mA (Note 2) lI Maximum Input 5.5 +0.1 +1.0 BPA |Vi=Voec, GND (Note 4) Leakage Current lop Minimum Dynamic 5.5 75 mA | Vo_p = 1.65V Max loup Output Current (Note 3) 5.5 15 mA | Voup = 3.85V Min loc Maximum Quiescent 5.5 4.0 40.0 BA | Vin=Voec or GND (Note 4) Supply Current Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: |, and Ig @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V Vg. www.fairchildsemi.com GZILLOVPZ SLLOVPZ74AC175 - 74ACT175 DC Electrical Characteristics for ACT Symbol Parameter Veco Ta = +28C Ta =40C to +85C Units Conditions (V) Typ Guaranteed Limits Vin Minimum HIGH Level 45 1.5 2.0 2.0 Vv Vout =0.1V Input Voltage 5.5 1.5 2.0 2.0 or Veg 0.1V Vit Maximum LOW Level 45 1.5 0.8 0.8 Vv Vout =0.1V Input Voltage 5.5 1.5 0.8 0.8 or Veg 0.1V Vou Minimum HIGH Level 45 4.49 44 44 Vv lout =50 pA Output Voltage 5.5 5.49 54 54 Vin = Vit or Vin 45 3.86 3.76 Vv lou =-24 mA 5.5 4.86 4.76 lou =24 mA (Note 5) VoL Maximum LOW Level 45 0.001 0.1 0.1 Vv lout = 50 pA Output Voltage 5.5 0.001 O11 O11 Vin = Vit or Vin 45 0.36 0.44 Vv lo =24 mA 5.5 0.36 0.44 lo. = 24 mA (Note 5) lI Maximum Input 5.5 +0.1 +1.0 pA Vi=Vec, GND Leakage Current loct Maximum 5.5 0.6 15 mA |[Vi=Veg -2.1V Io/Input lotp Minimum Dynamic 5.5 75 mA Vo_p = 1.65V Max lonp Output Current(Note 6) 5.5 75 MA | Vonp = 3.85V Min loc Maximum Quiescent 5.5 4.0 40.0 pA Vin=Vec Supply Current or GND Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. www.fairchildsemi.comAC Electrical Characteristics for AC Veco Ta =+25C Ta =40C to +85C Symbol Parameter (V) C_ =50 pF C_ = 50 pF Units (Note 7) Min Typ Max Min Max fmax Maximum Clock 3.3 149 214 139 MHz Frequency 5.0 187 244 187 teLH Propagation Delay 3.3 2.0 9.5 12.0 2.0 13.5 ns CP to Q, or G, 5.0 1.5 7.0 9.0 1.0 9.5 tPHL Propagation Delay 3.3 2.5 8.5 13.0 2.0 14.5 ns CP toQ, or Q, 5.0 1.5 6.0 95 1.5 10.5 tpLy Propagation Delay 3.3 3.0 7.5 12.5 2.5 13.5 ns MR to G, 5.0 2.0 5.5 9.0 1.5 10.0 tPHL Propagation Delay 3.3 3.0 8.5 11.0 2.5 12.5 ns MR to Q, 5.0 2.0 6.0 85 1.5 9.0 Note 7: Voltage Range 3.3 is 3.3V +0.3V Voltage Range 5.0 is 5.0V +0.5V AC Operating Requirements for AC Vee Ta =+28C Ta =40C to +85C Symbol Parameter (V) C, = 50 pF C,_ = 50 pF Units (Note 8) Typ Guaranteed Minimum ts Setup Time, HIGH or LOW 3.3 2.0 45 45 ns D, to CP 5.0 1.0 3.0 3.0 ty Hold Time, HIGH or LOW 3.3 1.0 1.0 1.0 ns D, to CP 5.0 1.0 1.0 1.0 tw CP Pulse Width 3.3 2.5 45 4.5 ns HIGH or LOW 5.0 2.0 3.5 3.5 tw MR Pulse Width, LOW 3.3 2.5 45 5.0 ns 5.0 2.0 3.5 3.5 trec Recovery Time 3.3 2.0 0 0 ns MR to CP 5.0 -1.0 0 0 Note 8: Voltage Range 3.3 is 3.3V 10.3V Voltage Range 5.0 is 5.0V +0.5V 5 www.fairchildsemi.com GZILLOVPZ SLLOVPZ74AC175 - 74ACT175 AC Electrical Characteristics for ACT Vee Ta =+28C Ta =40C to +85C Symbol Parameter (V) C, =50 pF C, = 50 pF Units (Note 9) Min Typ Max Min Max fmax Maximum Clock 5.0 175 236 145 MHz Frequency tpLH Propagation Delay 5.0 2.0 6.0 10.0 1.5 11.0 ns CP to Q, or Q, tpuL Propagation Delay 5.0 2.0 7.0 11.0 1.5 12.0 ns CP to Q, or Q, tpLH Propagation Delay 5.0 2.0 6.0 9.5 1.5 10.5 ns MR to Q, teu Propagation Delay 5.0 2.0 5.5 9.5 1.5 10.5 ns MR to Q, Note 9: Voltage Range 5.0 is 5.0V +0.5V AC Operating Requirements for ACT Veco Ta = 428C Ta =40C to +85C Symbol Parameter (V) C,_=50 pF C, = 50 pF Units (Note 10) Typ Guaranteed Minimum tg (H) Setup Time 5.0 3.0 2.0 2.0 ns ts (L) D, to CP 3.0 25 25 ty Hold Time, HIGH or LOW 5.0 0 1.0 1.0 ns D, to CP tw CP Pulse Width 5.0 4.0 3.0 3.5 ns HIGH or LOW tw MR Pulse Width, LOW 5.0 4.0 3.0 4.0 ns trec Recovery Time, MR to CP 5.0 0 0 0 ns Note 10: Voltage Range 5.0 is 5.0V +0.5V Capacitance Symbol Parameter Typ Units Conditions Cn Input Capacitance 4.5 pF Voc = OPEN Cpp Power Dissipation Capacitance 45.0 pF Voc =5.0V www.fairchildsemi.comPhysical DimensiONS inches (millimeters) unless otherwise noted 0.386 -0.394 igao410.0) | 16 % 1413 12 1 110 9 0.280.244 30: (5.791 6.198) Tye lo my veAO NOt 192 3 4 5 & 7 6 IDENT ond MAX (0.254) 0.1500.157 (3.810 3.968) o.o1o.020 |, 0.053 9.069 10.254 0.508) | |* {1.346 1.753) 0.004 0.010 B MAX TYP 40.102 0.254) ALL LEADS Tl 7 1 f= hh 4 +__ fea SSS scans 4 > A PLANE 0.008 0.010 f 6 oe 0.060 0.014 ~0.020 typ 008 0. 16 . 014-0. {0.203 0.254) | fae 250.050 (0-356) 71.270) 10.355 0.508) TYP ALL LEADS (0-406- 1.270) TYP 0.004 TYP ALL LEADS pelle 2.008 yp (0.102) 10.203) wma EY M1 ALL LEAD TIPS. 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Body Package Number M16A 16 9 0.295-0.319 (7.5-8.1) 0.205-0.213 (5.2-5.4) 1 TT 0.394-0.402 071 ; reo (Te ses818 1p 1 = = = = = = \ 0.067-0.085 o_R0 (.7-2.1) 9-8 TYP 0.006 (0.15) \ 5 SEATING PLANE 0.000-0.010 (0-0.25) 0.014-0.020 {0.35-0.50) TYP >| [ y M16D (REV B) 0.049 (Gg5y TYP) 0.016-0.031 (0.4-0.8) Tye 16-Lead Small Outline Package (SOP), EIAJ TYPE Il, 5.3mm Wide Package Number M16D www.fairchildsemi.com GZILLOVPZ SLLOVPZ74AC175 - 74ACT175 Physical DimensiONS inches (millimeters) unless otherwise noted (Continued) (00000007 DIMENSIONS METRIC ONLY | se (M00 | 16 * 9 0.42 TYP ld | LULL ER EO | LAND PATTERN RECOMMENDATION GAGE PLANE ~~ 4.16 TYP. fee SLE | \ \\ sean ave T 0-8 \~1- 0.6 + 0.1 emu aL [ea] 0.2 [cB] A] TYPICAL, SCALE: 40X PIN #1 IDENT. ALL LEAD TIPS SEE DETAIL A vos p& 90) . / ao a si | A ve TYP | 7 a [eT F Tee 0.65 TYP Lo. 10 + 0.05 TYP 9.09-0.20 TYP J H 0.19 - 0.3 0 TYP 0.13 A/B c 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 www.fairchildsemi.com 8Physical DimensiONS inches (millimeters) unless otherwise noted (Continued) 0.740 - 0.780 0.080 18.80 - 19.81 0.090_ ( ) >| (2.286) 9] INDEX AREA 0.25040.010 (6.3504 0.254) PIN NO. 1 PIN NO. 1 went LY 2] By 4! BD) 6) ZI IDENT OPTION 01 OPTION 02 0.068 0.130 #0.005 wee 0.060 4 TYP 0.300 = 0.320 (1.651) \ (3.302 0.127) =| [- Crsaa) TYP [> oprionaL 7 (7.620 = 8.128) { 0.145 = 0.200 ! | (3.683 5.080) r| CI t 95 5 0.008 - 0.016 1 o 0.020 jy | 4 9005 4 TYP (0.203- 0.406) 70.508) 72280, 0.125 = 0.150 0.030 40.015 (7.112) (175 =3.810) ! (0.762 0.381) MIN 0.014= 0.023 -0.10040.010 (0.325 *9.940 (0.356 = 0.584) 0.050 0.010 (2.540 0.254) 20.015 N16E (REV F) TYP (1.2700.254) TP (8.255 ot) TYP 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems 2. Accritical component in any component of a life support doj4-dijg edAL-g pend SZLLOVPZ SZLOWPZ which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com Faircrild does not assume any responsibility for use of any circuitry described, no drcuit patent licanses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.