Product Folder Order Now Support & Community Tools & Software Technical Documents Reference Design REF2025, REF2030, REF2033, REF2041 SBOS600D - MAY 2014 - REVISED JULY 2018 REF20xx Low-Drift, Low-Power, Dual-Output, VREF and VREF / 2 Voltage References 1 Features 3 Description * Applications with only a positive supply voltage often require additional stable voltage in the middle of the analog-to-digital converter (ADC) input range to bias input bipolar signals. The REF20xx provides a reference voltage (VREF) for the ADC and a second highly-accurate voltage (VBIAS) that can be used to bias the input bipolar signals. 1 * * * * * * * * * * Two Outputs, VREF and VREF / 2, for Convenient Use in Single-Supply Systems Excellent Temperature Drift Performance: - 8 ppm/C (max) from -40C to 125C High Initial Accuracy: 0.05% (max) VREF and VBIAS Tracking over Temperature: - 6 ppm/C (max) from -40C to 85C - 7 ppm/C (max) from -40C to 125C Microsize Package: SOT23-5 Low Dropout Voltage: 10 mV High Output Current: 20 mA Low Quiescent Current: 360 A Line Regulation: 3 ppm/V Load Regulation: 8 ppm/mA Matte-Sn version (REF2025AISDDCR) for improved corrosion resistance in the Battelle Class III and similar harsh environments 2 Applications * * * * * * Digital Signal Processing: - Power Inverters - Motor Controls Current Sensing Industrial Process Controls Medical Equipment Data Acquisition Systems Single-Supply Systems The REF20xx offers excellent temperature drift (8 ppm/C, max) and initial accuracy (0.05%) on both the VREF and VBIAS outputs while operating at a quiescent current less than 430 A. In addition, the VREF and VBIAS outputs track each other with a precision of 6 ppm/C (max) across the temperature range of -40C to 85C. All these features increase the precision of the signal chain and decrease board space, while reducing the cost of the system as compared to a discrete solution. Extremely low dropout voltage of only 10 mV allows operation from very low input voltages, which can be very useful in battery-operated systems. Both the VREF and VBIAS voltages have the same excellent specifications and can sink and source current equally well. Very good long-term stability and low noise levels make these devices ideally-suited for high-precision industrial applications. Device Information(1) PART NAME REF20xx PACKAGE BODY SIZE (NOM) SOT (5) 2.90 mm x 1.60 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. space space Application Example VREF and VBIAS vs Temperature Power Supply 0.05 VIN+ RSHUNT INA213 ISENSE VOUT ADC REF VIN- VBIAS 1.5 V VREF 3.0 V Output Voltage Accuracy (%) LOAD 0.04 0.03 VBIAS 0.02 0.01 0 -0.01 -0.02 VREF -0.03 -0.04 -0.05 75 REF2030 GND EN 50 25 0 25 50 75 Temperature (C) 100 125 150 C001 VIN 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. REF2025, REF2030, REF2033, REF2041 SBOS600D - MAY 2014 - REVISED JULY 2018 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 4 7.1 7.2 7.3 7.4 7.5 7.6 4 4 4 4 5 6 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics.......................................... Typical Characteristics .............................................. Parameter Measurement Information ................ 13 8.1 Solder Heat Shift..................................................... 13 8.2 Thermal Hysteresis ................................................. 14 8.3 Noise Performance ................................................. 15 9 Detailed Description ............................................ 16 9.1 Overview ................................................................. 16 9.2 Functional Block Diagram ....................................... 16 9.3 Feature Description................................................. 16 9.4 Device Functional Modes........................................ 17 10 Applications and Implementation...................... 18 10.1 Application Information.......................................... 18 10.2 Typical Application ................................................ 19 11 Power-Supply Recommendations ..................... 24 12 Layout................................................................... 25 12.1 Layout Guidelines ................................................. 25 12.2 Layout Example .................................................... 25 13 Device and Documentation Support ................. 26 13.1 13.2 13.3 13.4 13.5 13.6 13.7 Documentation Support ........................................ Related Links ........................................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 26 26 26 26 26 26 26 14 Mechanical, Packaging, and Orderable Information ........................................................... 27 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (January 2017) to Revision D * Page Changed application information to include corrosion resistance advantages. .................................................................. 18 Changes from Revision B (July 2014) to Revision C Page * Added I/O column to Pin Functions table .............................................................................................................................. 3 * Added Storage temperature parameter to Absolute Maximum Ratings table (moved from ESD Ratings table)................... 4 * Changed ESD Rating table: changed title, updated table format .......................................................................................... 4 Changes from Revision A (June 2014) to Revision B Page * Changed device status to Production Data from Mixed Status ............................................................................................. 1 * Deleted footnote 2 from Device Information table ................................................................................................................. 1 * Deleted footnote from Device Comparison Table ................................................................................................................. 3 * Added Thermal Information table ........................................................................................................................................... 4 Changes from Original (May 2014) to Revision A * 2 Page Made changes to product preview data sheet........................................................................................................................ 1 Submit Documentation Feedback Copyright (c) 2014-2018, Texas Instruments Incorporated Product Folder Links: REF2025 REF2030 REF2033 REF2041 REF2025, REF2030, REF2033, REF2041 www.ti.com SBOS600D - MAY 2014 - REVISED JULY 2018 5 Device Comparison Table PRODUCT VREF VBIAS REF2025 2.5 V 1.25 V REF2030 3.0 V 1.5 V REF2033 3.3 V 1.65 V REF2041 4.096 V 2.048 V 6 Pin Configuration and Functions DDC Package SOT23-5 (Top View) VBIAS 1 GND 2 EN 3 5 VREF 4 VIN Pin Functions PIN I/O DESCRIPTION NO. NAME 1 VBIAS 2 GND -- 3 EN Input Enable (EN VIN - 0.7 V, device enabled) 4 VIN Input Input supply voltage 5 VREF Output Output Copyright (c) 2014-2018, Texas Instruments Incorporated Bias voltage output (VREF / 2) Ground Reference voltage output (VREF) Submit Documentation Feedback Product Folder Links: REF2025 REF2030 REF2033 REF2041 3 REF2025, REF2030, REF2033, REF2041 SBOS600D - MAY 2014 - REVISED JULY 2018 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) Input voltage Temperature MIN MAX VIN -0.3 6 EN -0.3 VIN + 0.3 Operating -55 150 Junction, Tj V 150 Storage, Tstg (1) UNIT -65 C 170 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 Electrostatic discharge (1) UNIT 4000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) V 1500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VIN (1) Supply input voltage range (IL = 0 mA, TA = 25C) NOM MAX VREF + 0.02 (1) 5.5 UNIT V See Figure 28 in Typical Characteristics for minimum input voltage at different load currents and temperature 7.4 Thermal Information REF20xx THERMAL METRIC (1) DDC (SOT23) UNIT 5 PINS RJA Junction-to-ambient thermal resistance 193.6 C/W RJC(top) Junction-to-case (top) thermal resistance 40.2 C/W RJB Junction-to-board thermal resistance 34.5 C/W JT Junction-to-top characterization parameter 0.9 C/W JB Junction-to-board characterization parameter 34.3 C/W RJC(bot) Junction-to-case (bottom) thermal resistance N/A C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright (c) 2014-2018, Texas Instruments Incorporated Product Folder Links: REF2025 REF2030 REF2033 REF2041 REF2025, REF2030, REF2033, REF2041 www.ti.com 7.5 SBOS600D - MAY 2014 - REVISED JULY 2018 Electrical Characteristics At TA = 25C, IL = 0 mA, and VIN = 5 V, unless otherwise noted. Both VREF and VBIAS have the same specifications. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ACCURACY AND DRIFT Output voltage accuracy -0.05% Output voltage temperature coefficient (1) -40C TA 125C 0.05% 3 8 1.5 6 2 7 VREF + 0.02 V VIN 5.5 V 3 35 Sourcing 0 mA IL 20 mA , VREF + 0.6 V VIN 5.5 V 8 20 Sinking 0 mA IL -20 mA, VREF + 0.02 V VIN 5.5 V 8 20 360 430 VREF and VBIAS tracking over temperature (2) -40C TA 85C -40C TA 125C ppm/C ppm/C LINE AND LOAD REGULATION VO(VI) VO(IL) Line regulation Load regulation ppm/V ppm/mA POWER SUPPLY Active mode ICC Supply current Shutdown mode -40C TA 125C 460 3.3 -40C TA 125C 9 Device in shutdown mode (EN = 0) Enable voltage Device in active mode (EN = 1) 0 0.7 VIN - 0.7 VIN 10 Dropout voltage IL = 20 mA ISC Short-circuit current ton Turn-on time 0.1% settling, CL = 1 F Low-frequency noise (3) 0.1 Hz f 10 Hz Output voltage noise density f = 100 Hz A 5 V 20 mV 600 50 mA 500 s NOISE 12 ppmPP 0.25 ppm/Hz CAPACITIVE LOAD Stable output capacitor range 0 10 F HYSTERESIS AND LONG TERM STABILITY Long-term stability 0 to 1000 hours Output voltage hysteresis (4) (1) (2) (3) (4) 25C, -40C, 125C, 25C 60 Cycle 1 60 Cycle 2 35 ppm ppm Temperature drift is specified according to the box method. See the Feature Description section for more details. The VREF and VBIAS tracking over temperature specification is explained in more detail in the Feature Description section. The peak-to-peak noise measurement procedure is explained in more detail in the Noise Performance section. The thermal hysteresis measurement procedure is explained in more detail in the Thermal Hysteresis section. Copyright (c) 2014-2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: REF2025 REF2030 REF2033 REF2041 5 REF2025, REF2030, REF2033, REF2041 SBOS600D - MAY 2014 - REVISED JULY 2018 www.ti.com 7.6 Typical Characteristics At TA = 25C, IL = 0 mA, VIN = 5-V power supply, CL = 0 F, and 2.5-V output, unless otherwise noted. 50 70 60 40 Population (%) Population (%) 50 40 30 30 20 20 10 0 0.05 0.04 0.03 0.02 0.01 0 -0.01 -0.02 -0.03 -0.04 0 -0.05 10 VREF Initial Accuracy (%) 0 1 2 3 4 5 6 7 8 VREF Drift Distribution (ppm/C) C015 C010 -40C TA 125C Figure 1. Initial Accuracy Distribution (VREF) Figure 2. Drift Distribution (VREF) 80 50 70 40 Population (%) Population (%) 60 50 40 30 30 20 20 10 0 0.05 0.04 0.03 0.02 0.01 0 -0.01 -0.02 -0.03 -0.04 0 -0.05 10 VBIAS Initial Accuracy (%) 0 1 2 3 4 5 6 7 8 VBIAS Drift Distribution (ppm/C) C015 C008 -40C TA 125C Figure 3. Initial Accuracy Distribution (VBIAS) Figure 4. Drift Distribution (VBIAS) 60 40 50 Population (%) Population (%) 30 20 40 30 20 10 0 80 60 40 20 0 20 40 60 80 0 100 10 0 1 2 3 4 5 6 VREF and VBIAS Tracking Over Temperature (ppm/C) VREF and VBIAS Matching (ppm) C016 C004 -40C TA 85C Figure 5. VREF - 2 x VBIAS Distribution 6 Submit Documentation Feedback Figure 6. Distribution of VREF - 2 x VBIAS Drift Tracking Over Temperature Copyright (c) 2014-2018, Texas Instruments Incorporated Product Folder Links: REF2025 REF2030 REF2033 REF2041 REF2025, REF2030, REF2033, REF2041 www.ti.com SBOS600D - MAY 2014 - REVISED JULY 2018 Typical Characteristics (continued) At TA = 25C, IL = 0 mA, VIN = 5-V power supply, CL = 0 F, and 2.5-V output, unless otherwise noted. 50 60 40 40 Population (%) Population (%) 50 30 20 30 20 10 10 0 0 1 2 3 4 5 6 0 7 -0.0125 -0.01 -0.0075 -0.005 -0.0025 VREF and VBIAS Tracking Over Temperature (ppm/C) 0 0.0025 Solder Heat Shift Histogram - VREF (%) C041 C017 -40C TA 125C Refer to the Solder Heat Shift section for more information. Figure 7. Distribution of VREF - 2 x VBIAS Drift Tracking Over Temperature Figure 8. Solder Heat Shift Distribution (VREF) 60 0.05 0.04 Output Voltage Accuracy (%) Population (%) 50 40 30 20 10 0.03 VBIAS 0.02 0.01 0 -0.01 -0.02 VREF -0.03 -0.04 0 -0.0125 -0.01 -0.0075 -0.005 -0.0025 0 -0.05 0.0025 75 50 25 0 Solder Heat Shift Histogram - VBIAS (%) 25 50 75 100 125 Temperature (C) 150 C001 C040 Refer to the Solder Heat Shift section for more information. Figure 9. Solder Heat Shift Distribution (VBIAS) Figure 10. Output Voltage Accuracy (VREF) vs Temperature 1000 2.5005 -40C 2.5000 500 250 VREF (V) VREF - 2 x VBIAS (ppm) 750 0 250 2.4995 25C 2.4990 125C 500 2.4985 750 1000 2.4980 75 50 25 0 25 50 75 Temperature (C) 100 125 150 20 15 10 5 C003 0 5 10 Load Current (mA) 15 20 C038 VREF output Figure 11. VREF - 2 x VBIAS Tracking vs Temperature Copyright (c) 2014-2018, Texas Instruments Incorporated Figure 12. Output Voltage Change vs Load Current (VREF) Submit Documentation Feedback Product Folder Links: REF2025 REF2030 REF2033 REF2041 7 REF2025, REF2030, REF2033, REF2041 SBOS600D - MAY 2014 - REVISED JULY 2018 www.ti.com Typical Characteristics (continued) 1.2503 -40C VBIAS (V) 1.2501 1.2499 1.2497 25C 125C 1.2495 1.2493 20 15 10 0 5 5 10 15 Load Current (mA) 20 VREF - Load Regulation Sourcing (ppm/mA) At TA = 25C, IL = 0 mA, VIN = 5-V power supply, CL = 0 F, and 2.5-V output, unless otherwise noted. 11 10 9 8 7 6 5 4 0 25 50 75 100 125 Temperature (C) VBIAS output 150 7 6 5 4 75 50 25 0 25 50 75 100 125 150 C025 IL = 20 mA Figure 14. Load Regulation Sourcing vs Temperature (VREF) 12 11 10 9 8 7 6 5 4 75 50 25 0 25 50 75 100 125 Temperature (C) IL = 20 mA VREF output 150 C021 IL = -20 mA Figure 16. Load Regulation Sinking vs Temperature (VREF) 5 12 11 VREF Line Regulation (ppm/V) VBIAS - Load Regulation Sinking (ppm/mA) 8 C020 Figure 15. Load Regulation Sourcing vs Temperature (VBIAS) 10 9 8 7 6 5 4.5 4 3.5 3 2.5 2 4 75 50 25 0 25 50 75 Temperature (C) VBIAS output 100 125 150 IL = -20 mA Submit Documentation Feedback 75 50 25 0 25 50 75 Temperature (C) C022 Figure 17. Load Regulation Sinking vs Temperature (VBIAS) 8 9 Temperature (C) VREF - Load Regulation Sinking (ppm/mA) VBIAS - Load Regulation Sourcing (ppm/mA) 12 25 10 VREF output Figure 13. Output Voltage Change vs Load Current (VBIAS) 50 11 C039 VBIAS output 75 12 100 125 150 C019 VREF output Figure 18. Line Regulation vs Temperature (VREF) Copyright (c) 2014-2018, Texas Instruments Incorporated Product Folder Links: REF2025 REF2030 REF2033 REF2041 REF2025, REF2030, REF2033, REF2041 www.ti.com SBOS600D - MAY 2014 - REVISED JULY 2018 Typical Characteristics (continued) At TA = 25C, IL = 0 mA, VIN = 5-V power supply, CL = 0 F, and 2.5-V output, unless otherwise noted. 100 4.5 VBIAS 80 4 PSRR (dB) VBIAS Line Regulation (ppm/V) 5 3.5 VREF 60 3 40 2.5 2 20 75 50 25 0 25 50 75 100 Temperature (C) 125 150 1 10 100 1k 10k 100k Frequency (Hz) C018 VBIAS output C026 CL = 0 F Figure 19. Line Regulation vs Temperature (VBIAS) Figure 20. Power-Supply Rejection Ratio vs Frequency 100 VIN + 0.25 V VBIAS 500 mV/div PSRR (dB) 80 VIN + 0.25 V VIN - 0.25 V VREF VREF 40 mV/div 60 40 20 1 10 100 1k 10k Frequency (Hz) Time (500 s/div) 100k C027 C006 CL = 10 F CL = 1 F Figure 21. Power-Supply Rejection Ratio vs Frequency VIN + 0.25 V 500 mV/div Figure 22. Line Transient Response VIN + 0.25V +1 mA VIN - 0.25V +1 mA 2 mA/div - 1 mA VREF 40 mV/div VREF 20 mV/div Time (500 s/div) Time (500 s/div) C006 CL = 10 F Figure 23. Line Transient Response Copyright (c) 2014-2018, Texas Instruments Incorporated C032 CL = 1 F IL = 1-mA step Figure 24. Load Transient Response Submit Documentation Feedback Product Folder Links: REF2025 REF2030 REF2033 REF2041 9 REF2025, REF2030, REF2033, REF2041 SBOS600D - MAY 2014 - REVISED JULY 2018 www.ti.com Typical Characteristics (continued) At TA = 25C, IL = 0 mA, VIN = 5-V power supply, CL = 0 F, and 2.5-V output, unless otherwise noted. +20 mA +20 mA +1 mA +1 mA 40 mA/div 2 mA/div -20 mA - 1 mA VREF VREF 20 mV/div 40 mV/div Time (500 s/div) Time (500 s/div) C037 CL = 10 F C031 IL = 1-mA step CL = 1 F Figure 25. Load Transient Response IL = 20-mA step Figure 26. Load Transient Response 400 125C Dropout Voltage (mV) +20 mA +20 mA 40 mA/div -20 mA VREF 40 mV/div 300 25C 40C 200 100 0 Time (500 s/div) 30 20 10 CL = 10 F 0 10 20 Load Current (mA) C036 C005 IL = 20-mA step Figure 27. Load Transient Response Figure 28. Minimum Dropout Voltage vs Load Current VIN VIN 2 V/div 2 V/div VREF VREF Time (100 s/div) Time (100 s/div) C033 CL = 1 F Figure 29. Turn-On Settling Time 10 30 Submit Documentation Feedback C034 CL = 10 F Figure 30. Turn-On Settling Time Copyright (c) 2014-2018, Texas Instruments Incorporated Product Folder Links: REF2025 REF2030 REF2033 REF2041 REF2025, REF2030, REF2033, REF2041 www.ti.com SBOS600D - MAY 2014 - REVISED JULY 2018 Typical Characteristics (continued) 500 500 450 450 Quiescent Current ( A) Quiescent Current ( A) At TA = 25C, IL = 0 mA, VIN = 5-V power supply, CL = 0 F, and 2.5-V output, unless otherwise noted. 400 350 300 400 350 300 250 250 200 200 75 50 25 0 25 50 75 100 125 2 150 Temperature (C) 3 4 5 6 Input Voltage (V) C006 Voltage (5 V/div) Figure 32. Quiescent Current vs Input Voltage Voltage (5 V/div) Figure 31. Quiescent Current vs Temperature C007 Time (1 s/div) Time (1 s/div) C028 C029 VREF output VBIAS output Figure 33. 0.1-Hz to 10-Hz Noise (VREF) Figure 34. 0.1-Hz to 10-Hz Noise (VBIAS) 100 CL = 0 F Output Impedance ( ) 2XWSXW 1RLVH 6SHFWUDO 'HQVLW\ SSP +] 1 CL = 0 F 0.1 CL = 4.7 F 10 CL = 1F 1 CL = 10 F 0.1 CL = 10 F 0.01 1 10 100 1k Frequency (Hz) 10k 0.01 0.01 0.1 1 10 100 1k 10k Frequency (Hz) C030 100k C024 VREF output Figure 35. Output Voltage Noise Spectrum Copyright (c) 2014-2018, Texas Instruments Incorporated Figure 36. Output Impedance vs Frequency (VREF) Submit Documentation Feedback Product Folder Links: REF2025 REF2030 REF2033 REF2041 11 REF2025, REF2030, REF2033, REF2041 SBOS600D - MAY 2014 - REVISED JULY 2018 www.ti.com Typical Characteristics (continued) At TA = 25C, IL = 0 mA, VIN = 5-V power supply, CL = 0 F, and 2.5-V output, unless otherwise noted. 100 40 35 30 10 Population (%) Output Impedance ( ) CL = 0 F CL = 1F 1 CL = 10 F 25 20 15 10 0.1 100 1k 10k 80 60 100k Frequency (Hz) 120 10 100 1 40 0 0.1 20 0.01 0.01 0 5 Thermal Hysterisis - VREF (ppm) C023 C013 VBIAS output Figure 37. Output Impedance vs Frequency (VBIAS) Figure 38. Thermal Hysteresis Distribution (VREF) 40 35 Population (%) 30 25 20 15 10 120 100 80 60 40 20 0 0 5 Thermal Hysteresis - VBIAS (ppm) C014 Figure 39. Thermal Hysteresis Distribution (VBIAS) 12 Submit Documentation Feedback Copyright (c) 2014-2018, Texas Instruments Incorporated Product Folder Links: REF2025 REF2030 REF2033 REF2041 REF2025, REF2030, REF2033, REF2041 www.ti.com SBOS600D - MAY 2014 - REVISED JULY 2018 8 Parameter Measurement Information 8.1 Solder Heat Shift The materials used in the manufacture of the REF20xx have differing coefficients of thermal expansion, resulting in stress on the device die when the part is heated. Mechanical and thermal stress on the device die can cause the output voltages to shift, degrading the initial accuracy specifications of the product. Reflow soldering is a common cause of this error. In order to illustrate this effect, a total of 92 devices were soldered on four printed circuit boards [23 devices on each printed circuit board (PCB)] using lead-free solder paste and the paste manufacturer suggested reflow profile. The reflow profile is as shown in Figure 40. The printed circuit board is comprised of FR4 material. The board thickness is 1.57 mm and the area is 171.54 mm x 165.1 mm. The reference and bias output voltages are measured before and after the reflow process; the typical shift is displayed in Figure 41 and Figure 42. Although all tested units exhibit very low shifts (< 0.01%), higher shifts are also possible depending on the size, thickness, and material of the printed circuit board. An important note is that the histograms display the typical shift for exposure to a single reflow profile. Exposure to multiple reflows, as is common on PCBs with surface-mount components on both sides, causes additional shifts in the output bias voltage. If the PCB is exposed to multiple reflows, the device should be soldered in the second pass to minimize its exposure to thermal stress. 300 Temperature (C) 250 200 150 100 50 0 0 50 100 150 200 250 300 Time (seconds) 350 400 C01 Figure 40. Reflow Profile 60 50 50 Population (%) Population (%) 40 30 20 10 0 40 30 20 10 -0.0125 -0.01 -0.0075 -0.005 -0.0025 0 0.0025 Solder Heat Shift Histogram - VREF (%) 0 -0.0125 -0.01 -0.0075 -0.005 -0.0025 0 0.0025 Solder Heat Shift Histogram - VBIAS (%) C040 C041 Figure 41. Solder Heat Shift Distribution, VREF (%) Copyright (c) 2014-2018, Texas Instruments Incorporated Figure 42. Solder Heat Shift Distribution, VBIAS (%) Submit Documentation Feedback Product Folder Links: REF2025 REF2030 REF2033 REF2041 13 REF2025, REF2030, REF2033, REF2041 SBOS600D - MAY 2014 - REVISED JULY 2018 www.ti.com 8.2 Thermal Hysteresis Thermal hysteresis is measured with the REF20xx soldered to a PCB, similar to a real-world application. Thermal hysteresis for the device is defined as the change in output voltage after operating the device at 25C, cycling the device through the specified temperature range, and returning to 25C. Hysteresis can be expressed by Equation 1: VPRE VPOST * 6 VHYST x 10 (ppm) V NOM (c) where * * * * VHYST = thermal hysteresis (in units of ppm), VNOM = the specified output voltage, VPRE = output voltage measured at 25C pre-temperature cycling, and VPOST = output voltage measured after the device has cycled from 25C through the specified temperature range of -40C to 125C and returns to 25C. (1) 40 35 35 30 30 C013 Figure 43. Thermal Hysteresis Distribution (VREF) Submit Documentation Feedback 120 Thermal Hysteresis - VBIAS (ppm) Thermal Hysterisis - VREF (ppm) 14 100 120 0 100 0 80 5 60 5 40 10 20 10 80 15 60 15 20 40 20 25 20 25 0 Population (%) 40 0 Population (%) Typical thermal hysteresis distribution is as shown in Figure 43 and Figure 44. C014 Figure 44. Thermal Hysteresis Distribution (VBIAS) Copyright (c) 2014-2018, Texas Instruments Incorporated Product Folder Links: REF2025 REF2030 REF2033 REF2041 REF2025, REF2030, REF2033, REF2041 www.ti.com SBOS600D - MAY 2014 - REVISED JULY 2018 8.3 Noise Performance Voltage (5 V/div) Voltage (5 V/div) Typical 0.1-Hz to 10-Hz voltage noise can be seen in Figure 45 and Figure 46. Device noise increases with output voltage and operating temperature. Additional filtering can be used to improve output noise levels, although care should be taken to ensure the output impedance does not degrade ac performance. Peak-to-peak noise measurement setup is shown in Figure 47. Time (1 s/div) Time (1 s/div) C028 C029 Figure 45. 0.1-Hz to 10-Hz Noise (VREF) Figure 46. 0.1-Hz to 10-Hz Noise (VBIAS) 10 k 100 40 mF VIN To scope VREF REF20xx 0.1 F GND + 10 F EN 1k 2-Pole High-pass 4-Pole Low-pass 0.1 Hz to 10 Hz Filter VBIAS Figure 47. 0.1-Hz to 10-Hz Noise Measurement Setup Copyright (c) 2014-2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: REF2025 REF2030 REF2033 REF2041 15 REF2025, REF2030, REF2033, REF2041 SBOS600D - MAY 2014 - REVISED JULY 2018 www.ti.com 9 Detailed Description 9.1 Overview The REF20xx are a family of dual-output, VREF and VBIAS (VREF / 2) band-gap voltage references. The Functional Block Diagram section provides a block diagram of the basic band-gap topology and the two buffers used to derive the VREF and VBIAS outputs. Transistors Q1 and Q2 are biased such that the current density of Q1 is greater than that of Q2. The difference of the two base emitter voltages (VBE1 - VBE2) has a positive temperature coefficient and is forced across resistor R5. The voltage is amplified and added to the base emitter voltage of Q2, which has a negative temperature coefficient. The resulting band-gap output voltage is almost independent of temperature. Two independent buffers are used to generate VREF and VBIAS from the band-gap voltage. The resistors R1, R2 and R3, R4 are sized such that VBIAS = VREF / 2. e-TrimTM is a method of package-level trim for the initial accuracy and temperature coefficient of VREF and VBIAS, implemented during the final steps of manufacturing after the plastic molding process. This method minimizes the influence of inherent transistor mismatch, as well as errors induced during package molding. e-Trim is implemented in the REF20xx to minimize the temperature drift and maximize the initial accuracy of both the VREF and VBIAS outputs. 9.2 Functional Block Diagram R2 R6 R1 R7 + VREF + e-Trim R5 + VBE1 - + R4 VBE2 - R3 Q2 Q1 VBIAS + e-Trim 9.3 Feature Description 9.3.1 VREF and VBIAS Tracking Most single-supply systems require an additional stable voltage in the middle of the analog-to-digital converter (ADC) input range to bias input bipolar signals. The VREF and VBIAS outputs of the REF20xx are generated from the same band-gap voltage as shown in the Functional Block Diagram section. Hence, both outputs track each other over the full temperature range of -40C to 125C with an accuracy of 7 ppm/C (max). The tracking accuracy increases to 6 ppm/C (max) when the temperature range is limited to -40C to 85C. The tracking error is calculated using the box method, as described by Equation 2: VDIFF(MAX) VDIFF (MIN) * 6 Tracking Error x 10 (ppm) (c) VREF x Temperature Range where * 16 VDIFF VREF 2 VBIAS (2) Submit Documentation Feedback Copyright (c) 2014-2018, Texas Instruments Incorporated Product Folder Links: REF2025 REF2030 REF2033 REF2041 REF2025, REF2030, REF2033, REF2041 www.ti.com SBOS600D - MAY 2014 - REVISED JULY 2018 Feature Description (continued) The tracking accuracy is as shown in Figure 48. 0.05 Output Voltage Accuracy (%) 0.04 0.03 VBIAS 0.02 0.01 0 -0.01 -0.02 VREF -0.03 -0.04 -0.05 75 50 25 0 25 50 75 Temperature (C) 100 125 150 C001 Figure 48. VREF and VBIAS Tracking vs Temperature 9.3.2 Low Temperature Drift The REF20xx is designed for minimal drift error, which is defined as the change in output voltage over temperature. The drift is calculated using the box method, as described by Equation 3: V REF(MAX) V REF(MIN) * 6 Drift x 10 (ppm) x V Temperature Range (c) REF (3) 9.3.3 Load Current The REF20xx family is specified to deliver a current load of 20 mA per output. Both the VREF and VBIAS outputs of the device are protected from short circuits by limiting the output short-circuit current to 50 mA. The device temperature increases according to Equation 4: TJ TA PD R -$ where * * * * TJ = junction temperature (C), TA = ambient temperature (C), PD = power dissipated (W), and RJA = junction-to-ambient thermal resistance (C/W) (4) The REF20xx maximum junction temperature must not exceed the absolute maximum rating of 150C. 9.4 Device Functional Modes When the EN pin of the REF20xx is pulled high, the device is in active mode. The device should be in active mode for normal operation. The REF20xx can be placed in a low-power mode by pulling the ENABLE pin low. When in shutdown mode, the output of the device becomes high impedance and the quiescent current of the device reduces to 5 A in shutdown mode. See the Electrical Characteristics for logic high and logic low voltage levels. Copyright (c) 2014-2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: REF2025 REF2030 REF2033 REF2041 17 REF2025, REF2030, REF2033, REF2041 SBOS600D - MAY 2014 - REVISED JULY 2018 www.ti.com 10 Applications and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information The low-drift, bidirectional, single-supply, low-side, current-sensing solution, described in this section, can accurately detect load currents from -2.5 A to 2.5 A. The linear range of the output is from 250 mV to 2.75 V. Positive current is represented by output voltages from 1.5 V to 2.75 V, whereas negative current is represented by output voltages from 250 mV to 1.5 V. The difference amplifier is the INA213 current-shunt monitor, whose supply and reference voltages are supplied by the low-drift REF2030. Industrial applications with electronics in corrosive environments are susceptible to corrosive damage due to the exposure to heat, moisture, and corrosive gases. The combination of the following conditions in a given system lead to higher risk of corrosive damage: 1. 2. 3. 4. Ventilated enclosures exposing underlying PCB. PCBs not conformally coated. Exposed-lead components with plating susceptible to corrosion. Changes in plating techniques for RoHS compliance (e.g. removal of Pb (lead) and certain types of plating). To improve resistance to corrosion in harsh environments, the REF2025AISDDCR uses Matte-Sn plating with improved assembly process to reduce exposed Cu, leading to improved corrosion resistance in the Battelle Class III and similar harsh environments. The "S" in the part number identifies this special plating option. REF2025 versions that do not have the "S" will continue to be available in industry standard NiPdAu processing technique. 18 Submit Documentation Feedback Copyright (c) 2014-2018, Texas Instruments Incorporated Product Folder Links: REF2025 REF2030 REF2033 REF2041 REF2025, REF2030, REF2033, REF2041 www.ti.com SBOS600D - MAY 2014 - REVISED JULY 2018 10.2 Typical Application 10.2.1 Low-Side, Current-Sensing Application REF20xx VREF + VIN Bandgap EN + VCC VBIAS + GND REF ILOAD VBUS + IN+ V+ VREF + RSHUNT OUT ADC VOUT INGND INA213B Figure 49. Low-Side, Current-Sensing Application Copyright (c) 2014-2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: REF2025 REF2030 REF2033 REF2041 19 REF2025, REF2030, REF2033, REF2041 SBOS600D - MAY 2014 - REVISED JULY 2018 www.ti.com Typical Application (continued) 10.2.1.1 Design Requirements The design requirements are as follows: 1. Supply voltage: 5.0 V 2. Load current: 2.5 A 3. Output: 250 mV to 2.75 V 4. Maximum shunt voltage: 25 mV 10.2.1.2 Detailed Design Procedure Low-side current sensing is desirable because the common-mode voltage is near ground. Therefore, the currentsensing solution is independent of the bus voltage, VBUS. When sensing bidirectional currents, use a differential amplifier with a reference pin. This procedure allows for the differentiation between positive and negative currents by biasing the output stage such that it can respond to negative input voltages. There are a variety of methods for supplying power (V+) and the reference voltage (VREF, or VBIAS) to the differential amplifier. For a low-drift solution, use a monolithic reference that supplies both power and the reference voltage. Figure 50 shows the general circuit topology for a low-drift, low-side, bidirectional, current-sensing solution. This topology is particularly useful when interfacing with an ADC; see Figure 49. Not only do VREF and VBIAS track over temperature, but their matching is much better than alternate topologies. For a more detailed version of the design procedure, refer to TIDU357. REF20xx VREF + VIN Bandgap EN + VCC VBIAS + GND REF ILOAD VBUS + IN+ VSHUNT V+ + RSHUNT OUT VOUT INGND INA213B Figure 50. Low-Drift, Low-side, Bidirectional, Current-Sensing Circuit Topology The transfer function for the circuit given in Figure 50 is as shown in Equation 5: VOUT G r VSHUNT VBIAS G rILOAD RSHUNT 20 VBIAS Submit Documentation Feedback (5) Copyright (c) 2014-2018, Texas Instruments Incorporated Product Folder Links: REF2025 REF2030 REF2033 REF2041 REF2025, REF2030, REF2033, REF2041 www.ti.com SBOS600D - MAY 2014 - REVISED JULY 2018 Typical Application (continued) 10.2.1.2.1 Shunt Resistor As illustrated in Figure 50, the value of VSHUNT is the ground potential for the system load. If the value of VSHUNT is too large, issues may arise when interfacing with systems whose ground potential is actually 0 V. Also, a value of VSHUNT that is too negative may violate the input common-mode voltage of the differential amplifier in addition to potential interfacing issues. Therefore, limiting the voltage across the shunt resistor is important. Equation 6 can be used to calculate the maximum value of RSHUNT. VSHUNT(max) R SHUNT(max) I LOAD(max) (6) Given that the maximum shunt voltage is 25 mV and the load current range is 2.5 A, the maximum shunt resistance is calculated as shown in Equation 7. VSHUNT (max) 25mV R SHUNT (max) 10m: I LOAD (max) 2.5A (7) To minimize errors over temperature, select a low-drift shunt resistor. To minimize offset error, select a shunt resistor with the lowest tolerance. For this design, the Y14870R01000B9W resistor is used. 10.2.1.2.2 Differential Amplifier The differential amplifier used for this design should have the following features: 1. Single-supply (3 V), 2. Reference voltage input, 3. Low initial input offset voltage (VOS), 4. Low-drift, 5. Fixed gain, and 6. Low-side sensing (input common-mode range below ground). For this design, a current-shunt monitor (INA213) is used. The INA21x family topology is shown in Figure 51. The INA213B specifications can be found in the INA213 product data sheet. V+ - IN- OUT + IN+ REF GND Copyright (c) 2017, Texas Instruments Incorporated Figure 51. INA21x Current-Shunt Monitor Topology Copyright (c) 2014-2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: REF2025 REF2030 REF2033 REF2041 21 REF2025, REF2030, REF2033, REF2041 SBOS600D - MAY 2014 - REVISED JULY 2018 www.ti.com Typical Application (continued) The INA213B is an excellent choice for this application because all the required features are included. In general, instrumentation amplifiers (INAs) do not have the input common-mode swing to ground that is essential for this application. In addition, INAs require external resistors to set their gain, which is not desirable for low-drift applications. Difference amplifiers typically have larger input bias currents, which reduce solution accuracy at small load currents. Difference amplifiers typically have a gain of 1 V/V. When the gain is adjustable, these amplifiers use external resistors that are not conducive to low-drift applications. 10.2.1.2.3 Voltage Reference The voltage reference for this application should have the following features: 1. Dual output (3.0 V and 1.5 V), 2. Low drift, and 3. Low tracking errors between the two outputs. For this design, the REF2030 is used. The REF20xx topology is as shown in the Functional Block Diagram section. The REF2030 is an excellent choice for this application because of its dual output. The temperature drift of 8 ppm/C and initial accuracy of 0.05% make the errors resulting from the voltage reference minimal in this application. In addition, there is minimal mismatch between the two outputs and both outputs track very well across temperature, as shown in Figure 52 and Figure 53. 60 40 50 Population (%) Population (%) 30 20 40 30 20 10 0 80 60 40 20 0 20 40 60 80 0 100 10 0 1 2 3 4 5 6 VREF and VBIAS Tracking Over Temperature (ppm/C) VREF and VBIAS Matching (ppm) C016 C004 Figure 52. VREF - 2 x VBIAS Distribution (At TA = 25C) Figure 53. Distribution of VREF - 2 x VBIAS Drift Tracking Over Temperature 10.2.1.2.4 Results Table 1 summarizes the measured results. Table 1. Measured Results UNCALIBRATED (%) CALIBRATED (%) Error across the full load current range (25C) ERROR 0.0355 0.004 Error across the full load current range (-40C to 125C) 0.0522 0.0606 22 Submit Documentation Feedback Copyright (c) 2014-2018, Texas Instruments Incorporated Product Folder Links: REF2025 REF2030 REF2033 REF2041 REF2025, REF2030, REF2033, REF2041 www.ti.com SBOS600D - MAY 2014 - REVISED JULY 2018 10.2.1.3 Application Curves Performing a two-point calibration at 25C removes the errors associated with offset voltage, gain error, and so forth. Figure 54 to Figure 56 show the measured error at different conditions. For a more detailed description on measurement procedure, calibration, and calculations, please refer to TIDU357. 3 800 Uncalibrated error (ppm) Output Voltage (Vout) -40C 600 2.5 2 1.5 1 0.5 400 0C 200 0 25C 85C 200 400 600 0 125C 800 -3 -2 -1 0 1 2 Load current (mA) 3 3 2 1 0 1 2 Load current (mA) C00 Figure 54. Measured Transfer Function 3 C00 Figure 55. Uncalibrated Error vs Load Current 800 -40C Calibrated error (ppm) 600 400 0C 200 0 25C 85C 200 400 600 125C 800 3 2 1 0 1 2 Load current (mA) 3 C00 Figure 56. Calibrated Error vs Load Current Copyright (c) 2014-2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: REF2025 REF2030 REF2033 REF2041 23 REF2025, REF2030, REF2033, REF2041 SBOS600D - MAY 2014 - REVISED JULY 2018 www.ti.com 11 Power-Supply Recommendations The REF20xx family of references feature an extremely low-dropout voltage. These references can be operated with a supply of only 20 mV above the output voltage. For loaded reference conditions, a typical dropout voltage versus load is shown in Figure 57. A supply bypass capacitor ranging between 0.1 F to 10 F is recommended. 400 Dropout Voltage (mV) 125C 300 25C 40C 200 100 0 30 20 10 0 10 20 Load Current (mA) 30 C005 Figure 57. Dropout Voltage vs Load Current 24 Submit Documentation Feedback Copyright (c) 2014-2018, Texas Instruments Incorporated Product Folder Links: REF2025 REF2030 REF2033 REF2041 REF2025, REF2030, REF2033, REF2041 www.ti.com SBOS600D - MAY 2014 - REVISED JULY 2018 12 Layout 12.1 Layout Guidelines Figure 58 shows an example of a PCB layout for a data acquisition system using the REF2030. Some key considerations are: * Connect low-ESR, 0.1-F ceramic bypass capacitors at VIN, VREF, and VBIAS of the REF2030. * Decouple other active devices in the system per the device specifications. * Using a solid ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. * Place the external components as close to the device as possible. This configuration prevents parasitic errors (such as the Seebeck effect) from occurring. * Minimize trace length between the reference and bias connections to the INA and ADC to reduce noise pickup. * Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if possible, and only make perpendicular crossings when absolutely necessary. INOUT Analog Input Via to GND Plane V+ Via to Input Power C GND C REF VBIAS C GND EN REF20xx IN+ INA213 12.2 Layout Example REF VREF C Microcontroller A/D Input C VIN DIG1 AIN Figure 58. Layout Example Copyright (c) 2014-2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: REF2025 REF2030 REF2033 REF2041 25 REF2025, REF2030, REF2033, REF2041 SBOS600D - MAY 2014 - REVISED JULY 2018 www.ti.com 13 Device and Documentation Support 13.1 Documentation Support 13.1.1 Related Documentation For related documentation see the following: * INA21x Voltage Output, Low- or High-Side Measurement, Bidirectional, Zero-Drift Series, Current-Shunt Monitors (SBOS437) * Low-Drift Bidirectional Single-Supply Low-Side Current Sensing Reference Design (TIDU357) 13.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 2. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY REF2025 Click here Click here Click here Click here Click here REF2030 Click here Click here Click here Click here Click here REF2033 Click here Click here Click here Click here Click here REF2041 Click here Click here Click here Click here Click here 13.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 13.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 13.5 Trademarks E2E is a trademark of Texas Instruments. e-Trim is a trademark of Texas Instruments, Inc. All other trademarks are the property of their respective owners. 13.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 13.7 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 26 Submit Documentation Feedback Copyright (c) 2014-2018, Texas Instruments Incorporated Product Folder Links: REF2025 REF2030 REF2033 REF2041 REF2025, REF2030, REF2033, REF2041 www.ti.com SBOS600D - MAY 2014 - REVISED JULY 2018 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright (c) 2014-2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: REF2025 REF2030 REF2033 REF2041 27 PACKAGE OPTION ADDENDUM www.ti.com 23-Jun-2018 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) REF2025AIDDCR ACTIVE SOT-23-THIN DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 GACM REF2025AIDDCT ACTIVE SOT-23-THIN DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 GACM REF2025AISDDCR ACTIVE SOT-23-THIN DDC 5 3000 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 1M98 REF2030AIDDCR ACTIVE SOT-23-THIN DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 GADM REF2030AIDDCT ACTIVE SOT-23-THIN DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 GADM REF2033AIDDCR ACTIVE SOT-23-THIN DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 GAEM REF2033AIDDCT ACTIVE SOT-23-THIN DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 GAEM REF2041AIDDCR ACTIVE SOT-23-THIN DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 GAFM REF2041AIDDCT ACTIVE SOT-23-THIN DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 GAFM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com (4) 23-Jun-2018 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 2-Jun-2018 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) REF2025AIDDCR SOT23-THIN DDC 5 3000 179.0 8.4 REF2025AIDDCT SOT23-THIN DDC 5 250 179.0 REF2025AISDDCR SOT23-THIN DDC 5 3000 REF2030AIDDCR SOT23-THIN DDC 5 REF2030AIDDCT SOT23-THIN DDC REF2033AIDDCR SOT23-THIN REF2033AIDDCT 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 SOT23-THIN DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 REF2041AIDDCR SOT23-THIN DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 REF2041AIDDCT SOT23-THIN DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 2-Jun-2018 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) REF2025AIDDCR SOT-23-THIN DDC 5 3000 195.0 200.0 45.0 REF2025AIDDCT SOT-23-THIN DDC 5 250 195.0 200.0 45.0 REF2025AISDDCR SOT-23-THIN DDC 5 3000 195.0 200.0 45.0 REF2030AIDDCR SOT-23-THIN DDC 5 3000 195.0 200.0 45.0 REF2030AIDDCT SOT-23-THIN DDC 5 250 195.0 200.0 45.0 REF2033AIDDCR SOT-23-THIN DDC 5 3000 195.0 200.0 45.0 REF2033AIDDCT SOT-23-THIN DDC 5 250 195.0 200.0 45.0 REF2041AIDDCR SOT-23-THIN DDC 5 3000 195.0 200.0 45.0 REF2041AIDDCT SOT-23-THIN DDC 5 250 195.0 200.0 45.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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