Preliminary Specifications
©2003 Silicon Storage Technology, Inc.
S71223-03-000 11/03
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
16 Mbit / 32 Mbit / 64 Mbit (x16) Multi-Purpose Flash Plus
SST39VF1601 / SST39V F32 01 / SST39V F64 01
SST39VF1602 / SST39V F32 02 / SST39V F64 02
FEATURES:
Organized as 1M x16: SST39VF1601/1602
2M x16: SST39VF3201/3202
4M x16: SST39VF6401/6402
Single Voltage Read and Write Operations
2.7-3.6V
Superior Reliability
Endurance: 100,000 Cycles (Typical)
Greater than 100 years Data Retention
Low P o wer Consumption (typical values at 5 MHz)
Active Current: 9 mA (typical)
Standby Current: 3 µA (typical)
Auto Low Power Mode: 3 µA (typical)
Hardware Block-Protection/WP# Input Pin
Top Block-Protection (top 32 KWord)
for SST39V F160 2/32 02/6402
Bottom Block-Protection (bottom 32 KWord)
for SST39V F160 1/32 01/6401
Sector-Erase Capability
Uniform 2 KWord sectors
Block-Erase Capability
Uniform 32 KW ord blocks
Chip-Erase Capability
Erase-Suspend/Erase-Resume Capabilities
Hardware Reset Pin (RST#)
Security-ID Feature
SST: 128 bits; User: 128 bits
Fast Read Access Time:
70 ns
90 ns
Latched Address and Data
Fast Erase and Word-Program:
Sector-Erase Time: 18 ms (typical)
Block-Erase Time: 18 ms (typical)
Chip-Erase Time: 40 ms (typical)
Word-Program Time: 7 µs (typical)
Automatic Write Timing
Internal VPP Generation
End-of-Write Detection
Toggle Bits
Data# Polling
CMOS I/O Compatibility
JEDEC Standard
Flash EEPROM Pinouts and command sets
Packages Available
48-lead TSOP (12mm x 20mm)
48-ball TFBGA (6mm x 8mm) for 16M and 32M
48-ball TFBGA (8mm x 10mm) for 64M
PRODUCT DESCRIPTION
The SST39VF160x/320x/640x devices are 1M x16, 2M
x16, and 4M x16 respectively, CMOS Multi-Purpose
Flash Plus (MPF+) manufactured with SST’s proprietar y,
high performance CMOS SuperFlash technology. The
split-gate cell design and thick-oxide tunneling injector
attain better reliability and manufacturability compared
with alternate approaches. The SST39VF160x/320x/640x
write (Program or Erase) with a 2.7-3.6V power supply.
These devices conform to JEDEC standard pinouts for
x16 memories.
Featuring high performance Word-Program, the
SST39 VF160 x/320x/ 640x d evices provide a typi cal Word-
Program time of 7 µsec. These device s use Toggle Bit or
Data# P olling to indicate the completion of Program opera-
tion. To protect against inadvertent write, they have on-chip
hardware and Software Data Protection schemes.
Designed, manufactured, and tested for a wide spectrum of
applications, these devices are offered with a guaranteed
typical endurance of 100,000 cycles. Data retention is rated
at greater than 100 years.
The SST39VF160x/320x/640x devices are suited for appli-
cations that require convenient and economical updating of
program, configuration, or data memory. For all system
applications, they significantly improve performance and
reliability, while lowering power consumption. They inher-
ently use less energy during Erase and Program than alter-
native flash te chnologies. Th e total energy consumed is a
function of the applied voltage, current, and time of applica-
tion. Since for any given voltage range, the SuperFlash
technolog y uses less current to program and has a shorter
erase time, the total energy consumed during any Erase or
Program operation is less than alternative flash technolo-
gies. These devices also improve flexibility while lowering
the cost for program, data, and configuration storage appli-
cations.
The SuperFlash technology provides fixed Erase and Pro-
gr am times, independent of the number of Er ase/Prog ram
cycles that have occurred. Therefore the system software
or hardwa re does not hav e to be modified or de-r ated as is
necessary with alternative flash technologies, whose
Erase and Program times increase with accumulated
Erase/Prog ram cycles.
SST39VF160x / 320x / 640x2.7V 16Mb / 32Mb / 64Mb (x16) MPF+ memories
2
Preliminary Specifications
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
©2003 Silicon Sto rage Technology, Inc. S71223-03-000 11/03
To meet high density, surface mount requirements, the
SST39VF160x/320x/640x are offered in 48-lead TSOP
and 48-ball TFBGA packages. See Figures 1 and 2 for
pin assignme nts .
Device Operation
Commands are used to initiate the memory operation func-
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asse rtin g WE# low while keepi ng CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever oc curs l ast. T he data bus is latc hed o n
the rising edge of WE# or CE#, whiche ver occurs first.
The SST39VF160x/320x/640x also have the Auto Low
Power mode which puts the device in a near standby
mode after data has been accessed with a valid Read
operation. This reduces the IDD active read current from
typically 9 mA to typically 3 µA. The A uto Low P ow er mode
reduces the typical IDD activ e re ad cur rent to the ra nge of 2
mA/MHz o f Read cycle t ime. The de vice e xits the A uto Lo w
Power mode with any address transition or control signal
transition used to initiate another Read cycle, with no
access time penalty. Note that the device does not enter
Auto-Low Power mode after power-up with CE# held
steadily low, until the first address transition or CE# is
driv en hi gh.
Read
The Read operation of the SST39VF160x/320x/640x is
cont rolled by C E# and O E#, bot h have to b e low for t he
system to obtain data from the outputs. CE# is used for
device selection. When CE# is high, the chip is dese-
lected and only standby power is consumed. OE# is the
output control and is used to gate data from the output
pins. The data bus is in high impedance state when
either C E# or OE# is high. R ef er to the Rea d cycle t iming
diagram fo r f urther deta ils (Figur e 3).
Word-Program Operation
The SST39VF160x/320x/640x are programmed on a
word-by-word basis. Before programming, the sector
where th e word exists mus t be fully erased . The Program
operation is accomplished in three steps. The first step is
the three-byte load sequence f or Software Data Protection.
The second step is to load word address and word data.
During the Word-Program operation, the addresses are
latched on the falling edge of either CE# or WE#, which-
eve r occur s last. T he data i s latched on the r ising edge o f
either CE# or WE#, whiche ver occurs first. The third step is
the internal Program operation which is initiated after the
rising edge of the fourth WE# or CE#, whichever occurs
first. The Program operation, once initiated, will be com-
pleted within 10 µs. See Figures 4 and 5 f or WE# and CE#
controlled Program operation timing diagrams and Figure
19 for flowcharts. During the Program operation, the only
valid reads are Data# Polling and Toggle Bit. During the
internal Program operation, the host is free to perform addi-
tional tasks. Any commands issued during the internal Pro-
gram operation are ignored. During the command
sequence, WP# should be statically held high or low.
Sector/Block-Erase Operation
The Sector- (or Block-) Erase operation allows the system
to erase the device on a sector-by-sector (or block-by-
block) basis. The SST39VF160x/320x/640x offer both Sec-
tor-Erase and Block-Erase mode. The sector architecture
is based on uniform sector size of 2 KWord. The Block-
Erase m ode is based on uniform block size of 32 K Wor d.
The Sec tor-Erase op eration is in itiated by executi ng a six-
byte command sequence with Sector-Erase command
(30H) and sector address (SA) in the last bus cycle. The
Block-Erase operation is initiated by executing a six-byte
command sequence with Block-Erase command (50H)
and block address (BA) in the last bus cycle. The sector or
block address is latched on the falling edge of the sixth
WE# pulse, while the command (30H or 50H) is latched on
the ri sing edge of th e sixth WE # puls e. The int er na l Erase
operation begins after the sixth WE# pulse. The End-of-
Erase operation can be determined using either Data#
P olling or Toggle Bit methods. See Figures 9 and 10 for tim-
ing waveforms and Figure 23 for the flowchart. Any com-
mands i s su ed during the S ec tor- or Bl ock-Era se op erat io n
are ignored. When WP# is low, any attempt to Sector-
(Block-) Erase the protected block will be ignored. During
the command sequence, WP# should be statically held
high or low.
Erase-Suspend/Erase-Resume Commands
The Erase-Suspend operation temporarily suspends a
Sector- or Block-Erase operation thus allowing data to be
read from any memor y loca tion, or program dat a into any
sector /block that i s not sus pended for an Eras e operation .
The operation is executed by issuing one byte command
sequence with Erase-Suspend command (B0H). The
device automatically enters read mode typically within 20
µs after the Erase-Suspend command had been issued.
Valid data can be read from any sector or block that is not
suspended from an Erase operation. Reading at address
locati on within erase-suspended sectors/blocks will output
DQ2 toggling and DQ6 at “1”. While in Erase-Suspend
mode, a W ord-Program operation is allowed except for the
sector or block selected for Erase-Suspend.
Preliminary Specifications
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
3
©2003 Silicon Sto rage Technology, Inc. S71223-03-000 11/03
To resume Sector-Erase or Block-Erase operation which has
been suspended the system must issue Erase Resume
command. The operation is executed by issuing one byte
command sequence with Erase Resume command (30H)
at an y address in the last Byte sequence .
Chip-Erase Operation
The SST39VF160x/320 x/640x pro vide a Chip-Erase oper-
ation, which allows the user to erase the entire memory
array to the “1” state. This is useful when the entir e device
must be quic kly erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command
(10H) at address 5555H in the last byte sequence. The
Erase operation begins with the rising edge of the sixth
WE# or CE#, whichever occurs first. During the Erase
operation, the only valid read is Toggle Bit or Data# P olling.
See Table 6 for the command sequence, Figure 9 for tim-
ing diagram, and Figure 23 for the flowchart. Any com-
mands issued during the Chip-Erase operation are
ignored. When WP# is low, any attempt to Chip-Erase will
be ignored. During the command sequence, WP# should
be statically held high or lo w.
Write Operation Status Detection
The SST39VF160x/320x/640x provide two software
means to detect the completion of a Write (Program or
Erase) cycle, in order to optimize the system write cycle
time. The software detection includes two status bits: Data#
Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write
detection mode is enabled after the rising edge of WE#,
which initiates the internal Program or Erase operation.
The actual completion of the nonvolatile write is asyn-
chronous with the system; therefore, either a Data# Poll-
ing or Toggle Bit read may be simultaneous with the
completion of the write cycle. If this occurs, the system
may possibly get an erroneous result, i.e., valid data may
appear t o conf lict w it h e ith er D Q 7 or DQ6. In order to pre-
vent spurious rejectio n, if an erroneous result occurs , the
software routine should include a loop to read the
accessed location an additional two (2) times. If both
reads are va lid, then the device has completed the Write
cycle, ot herwise the reje ction is valid.
Data# Polling (DQ7)
When the SST39VF160x/320x/640x are in the internal
Program operation, any attempt to read DQ7 will produce
the complement of the true data. Once the Program oper-
ation is completed, DQ7 will produce true data. Note that
even t hough DQ7 may have valid data imm ediat ely follow-
ing the completion of an internal Write operation, the
remaining data outputs may still be invalid: valid data on the
entire data bus will appear in subsequent successiv e Read
cycle s a f ter an in te rv a l o f 1 µ s . Du ring internal Erase oper-
ation, an y at tempt t o read D Q7 will produce a ‘0’. Once the
internal Erase operation is completed, DQ7 will produce a
‘1’. The Dat a# Polling is valid after the rising edge o f f ourth
WE# (or CE#) pulse for Program operation. For Sector-,
Block- or Chip-Erase, the Data# Polling is valid after the
rising edge of sixth WE# (or CE#) pulse. See Figure 6 for
Data# P olling t iming diagram and Fig ure 20 for a flowchart.
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 w ill pr od uc e a lt ernat in g “1 ”s
and “0”s, i.e., togg li ng between 1 and 0. Wh en t he inte rnal
Program or Erase op eration is compl eted, the DQ6 bit will
stop toggling. The device is then ready for the next opera-
tion. For Sector-, Block -, or Chip-Erase, the toggle bit (DQ6)
is valid after the rising edge of sixth WE# (or CE#) pulse.
DQ6 will be set to “1” if a Read operation is attempted on an
Erase-Suspended Sector/Block. If Program operation is ini-
tiated in a sector/block not selected in Erase-Suspend
mode, DQ6 will to ggle .
An addi tio na l Toggl e B i t i s available on DQ2, which can be
used in conjunction with DQ6 to ch eck whethe r a particula r
sector is being actively erased or erase-suspended. Table 1
shows detailed status bits information. The Toggle Bit
(DQ2) is valid after the rising edge of the last WE# (or CE#)
pulse of Write operation. See Figure 7 for Toggle Bit timing
diagram and Figure 20 for a flowchart.
Note: DQ7 and DQ2 require a valid address when reading
status inf ormation.
TABLE 1: WRITE OPERATION STATUS
Status DQ7DQ6DQ2
Normal
Operation Standard
Program DQ7# Toggle No Toggle
Standard
Erase 0 Toggle Toggle
Erase-
Suspend
Mode
Read from
Erase-Suspended
Sector/Block
1 1 Toggle
Read from
Non- Erase-Suspended
Sector/Block
Data Data Data
Program DQ7# Toggle N/A
T1.0 1223
4
Preliminary Specifications
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
©2003 Silicon Sto rage Technology, Inc. S71223-03-000 11/03
Data Protection
The SST39VF160x/320x/640x provide both hardware and
software f eatures to protect nonvolatile data from inadvertent
writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# o r CE# pulse of le ss than 5
ns will not ini tiate a w rite cycle .
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will in hi bit t he Write ope rati on . Thi s pr events i nad vert-
ent w rites durin g pow er-u p or po wer- dow n.
Hardware Block Protection
The SST39VF1602/3202/6402 support top hardware bloc k
protection, which protects the top 32 KWord block of the
device. The SST39VF1601/3201/6401 support bottom
hardware block protection, which protects the bottom 32
KWord block of the device. The Boot Block address ranges
are described in Table 2. Program and Erase operations
are prevented on the 32 KWord when WP# is low . If WP# is
left floating, it is internally held high via a pull-up resistor,
and the B oot Block is unp rotected, enabling P rogram and
Erase operations on that block.
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the
device to read array data. When the RST# pin is held low
f or at least TRP, any in-progress operation will terminate and
return to Read mode. When no internal Program/Erase
operation is in progress, a minimum period of TRHR is
required after RST# is driven high bef ore a valid Read can
take place (see Figure 15).
The Erase or Program operation that has been interrupted
needs to be reinitiated after the device resumes normal
operation mode to ensure data integrity.
Software Data Protection (SDP)
The SST39VF160x/320x/640x provide the JEDEC
approved Software Data Protection scheme for all data
alteration operations, i.e., Program and Erase. Any Pro-
gram operation requires the inclusion of the three-byte
sequence. The three-byte load sequence is used to initiate
the Program operation, providing optimal protection from
inadvertent Write operations, e.g., during the system
power-up or power-down. Any Erase operation requires the
inclusion of six-byte sequence. These devices are shipped
with the Software Data Protection permanently enabled.
See Table 6 f or the specific software command codes. Dur-
ing SDP command sequence, inv alid commands will abort
the device t o re a d mo de wi th in T RC. The contents of DQ15-
DQ8 can be VIL or VIH, but no other value , during any SDP
command sequence.
Common Flash Memory Interface (CFI)
The SST39VF160x/320x/640x also contain the CFI infor-
mation to describe the characteristics of the device. In
order to enter the C FI Query mode, the system must write
three-b yte sequence, same as prod uct ID entry command
with 98H (CFI Query command) to address 5555H in the
last by te sequence. Once the de vice enters the CFI Query
mode, the system can read CFI data at the addresses
given in Tables 7 through 10. The system must write the
CFI Exit command to return to Read mode from the CFI
Query mode .
TABLE 2: BOOT BLOCK ADDRESS RANGES
Product Address Range
Bottom Boot Block
SST39VF1601/3201/6401 000000H-007FFFH
Top Boot Block
SST39VF1602 0F8000H-0FFFFFH
SST39VF3202 1F8000H-1FFFFFH
SST39VF6402 3F8000H-3FFFFFH
T2.0 1223
Preliminary Specifications
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
5
©2003 Silicon Sto rage Technology, Inc. S71223-03-000 11/03
Product Identifica tion
The Produc t Identific ation mode identifies the devices as
the SST39VF1601, SST39VF1602, SST39VF3201,
SST39VF3202, SST39VF6401, SST39VF6402, and
manufacturer as SST. This mod e may be acces sed soft-
ware operations. Users may use the Software Product
Identification operation to identify the part (i.e., using the
device ID) when using multiple manuf acturers in the same
socket. For details, see Table 6 for software operation,
Figure 11 for the Software ID Ent r y and Rea d tim ing dia-
gram and Figure 21 for the Software ID Entr y command
sequence flowchart.
Product Identification Mode Exit/
CFI Mode Exit
In order to return to the standard Read mode, the Software
Produc t Ident ificati on mode must be exited. Exit is acco m-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read mode.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. Please note that the Software ID Exit/
CFI Exit command is ignored during an internal Program or
Erase operation. See Table 6 for software command
codes, Figur e 13 for timing wave form, an d Figu res 21 an d
22 for flowcharts.
Security ID
The SST39VF160x/320x/640x devices offer a 256-bit
Security ID space. The Secure ID space is divided into two
128-bi t segm ents - one factor y pr ogramme d seg ment an d
one user programmed segme nt. The first se gment is pro-
grammed an d locked at SST w ith a rando m 128-bit num-
ber. The user segment is left un-programmed for the
customer to program as desired.
To program the user segment of the Security ID, the user
must use the Security ID Word-Program command. To
detect end-of-write for the SEC ID, read the toggle bits. Do
not use Data# Polling. Once this is complete, the Sec ID
should be locked using the User Sec ID Program Lock-Out.
This dis ables any futur e c orrupti on of this sp ac e. Note tha t
regardless of whether or not the Sec ID is locked, neither
Sec ID segment can be erased.
The Secure ID space can be queried by executing a three-
byte command sequence with Enter Sec ID command
(88H) at ad dress 5555H in th e last byte sequenc e. To exit
this mode, the Exit Sec ID command should be executed.
Refer to Table 6 f or more details.
TABLE 3: PRODUCT IDENTIFICATION
Address Data
Manufacturer’s ID 0000H BFH
Device ID
SST39VF1601 0001H 234BH
SST39VF1602 0001H 234AH
SST39VF3201 0001H 235BH
SST39VF3202 0001H 235AH
SST39VF6401 0001H 236BH
SST39VF6402 0001H 236AH
T3.2 1223
6
Preliminary Specifications
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
©2003 Silicon Sto rage Technology, Inc. S71223-03-000 11/03
FIGURE 1: PIN ASSIGNMENTS FOR 48-LEAD TSOP
Y-Decoder
I/O Buffers and Data Latches
1223 B1.0
Address Buffer & Latches
X-Decoder
DQ15 - DQ0
Memory Address
OE#
CE#
WE#
SuperFlash
Memory
Control Logic
WP#
RESET#
FUNCTIONAL BLOCK DIAGRAM
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RST#
A21
WP#
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RST#
NC
WP#
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1223 48-tsop P01.3
Standard Pinout
Top View
Die Up
SST39VF160x/320x/640x
SST39VF6401/6402
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE#
RST#
NC
WP#
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
SST39VF1601/1602
SST39VF3201/3202
Preliminary Specifications
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
7
©2003 Silicon Sto rage Technology, Inc. S71223-03-000 11/03
FIGURE 2: PIN ASSIGNMENTS FOR 48-BALL TFBGA
1223 4-tfbga B1K P02b.2
A B C D E F G H
SST39VF6401/6402
6
5
4
3
2
1
TOP VIEW (balls facing down)
A13
A9
WE#
NC
A7
A3
A12
A8
RST#
WP#
A17
A4
A14
A10
A21
A18
A6
A2
A15
A11
A19
A20
A5
A1
A16
DQ7
DQ5
DQ2
DQ0
A0
NC
DQ14
DQ12
DQ10
DQ8
CE#
DQ15
DQ13
VDD
DQ11
DQ9
OE#
VSS
DQ6
DQ4
DQ3
DQ1
VSS
A13
A9
WE#
NC
A7
A3
A12
A8
RST#
WP#
A17
A4
A14
A10
NC
A18
A6
A2
A15
A11
A19
A20
A5
A1
A16
DQ7
DQ5
DQ2
DQ0
A0
NC
DQ14
DQ12
DQ10
DQ8
CE#
DQ15
DQ13
VDD
DQ11
DQ9
OE#
VSS
DQ6
DQ4
DQ3
DQ1
VSS
1223 48-tfbga B3K P02a.2
SST39VF3201/3202
TOP VIEW (balls facing down)
6
5
4
3
2
1
A B C D E F G H
A13
A9
WE#
NC
A7
A3
A12
A8
RST#
WP#
A17
A4
A14
A10
NC
A18
A6
A2
A15
A11
A19
NC
A5
A1
A16
DQ7
DQ5
DQ2
DQ0
A0
NC
DQ14
DQ12
DQ10
DQ8
CE#
DQ15
DQ13
VDD
DQ11
DQ9
OE#
VSS
DQ6
DQ4
DQ3
DQ1
VSS
1223 48-tfbga B3K P02.0
SST39VF1601/1602
TOP VIEW (balls facing down)
6
5
4
3
2
1
A B C D E F G H
8
Preliminary Specifications
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
©2003 Silicon Sto rage Technology, Inc. S71223-03-000 11/03
TABLE 4: PIN DESCRIPTION
Symbol Pin Name Functions
AMS1-A0Address Inputs To provide memory addresses.
During Sector-Eras e AMS-A11 address lines will select the sector.
During Bloc k- Er as e AMS-A15 address lines will select the block.
DQ15-DQ0Data Input/output To output data during Read cycles and receiv e input data du ring Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
WP# Write Protect To protect the top/bottom boot block from Erase/Program operation when grounded.
RST# Reset To reset and return the device to Read mod e .
CE# Chip Enable To activate the device when CE# is low.
OE# Output Enable To gate the data output buffers.
WE# Write Enable To control the Write operations.
VDD Power Supply To provide power supply voltage: 2.7-3.6V
VSS Ground
NC No Connection Unconnected pins.
T4.2 1223
1. AMS = Most significant address
AMS = A19 for SST39VF1601/1602, A20 for SST39VF3201/3202, and A21 for SST39VF6401/6402
TABLE 5: OPERATION MODES SELECTION
Mode CE# OE# WE# DQ Address
Read VIL VIL VIH DOUT AIN
Program VIL VIH VIL DIN AIN
Erase VIL VIH VIL X1
1. X can be VIL or VIH, but no other value.
Sector or block address,
XXH for Chip-Erase
Standby VIH X X High Z X
Write Inhibit X VIL X High Z/ DOUT X
XXV
IH High Z/ DOUT X
Product Identification
Softw are Mode VIL VIL VIH See Table 6
T5.0 1223
Preliminary Specifications
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
9
©2003 Silicon Sto rage Technology, Inc. S71223-03-000 11/03
TABLE 6: SOFTWARE COMMAND SEQUENCE
Command
Sequence 1st Bus
Write Cycle 2nd Bus
Write Cycle 3rd Bus
Write Cycle 4th Bus
Write Cycle 5th Bus
Write Cycle 6th B us
Write Cycle
Addr1Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data2
Word-Program 5555H AAH 2AAAH 55H 5555H A0H WA3Data
Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SAX430H
Block-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H BAX450H
Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
Erase-Suspend XXXXH B0H
Erase-Resume XXXXH 30H
Query Sec ID55555H AAH 2AAAH 55H 5555H 88H
User Security ID
Word-Program 5555H AAH 2AAAH 55H 5555H A5H WA6Data
User Security ID
Program Lock-Out 5555H AAH 2AAAH 55H 5555H 85H XXH60000H
Software ID En tr y 7,8 5555H AAH 2AAAH 55H 5555H 90H
CFI Quer y Entry 5555H AAH 2AAAH 55H 5555H 98H
Software ID Exit9,10
/CFI Exit/ Sec ID Ex it 5555H AAH 2AAAH 55H 5555H F0H
Software ID Ex i t 9,10
/CFI Exit/ Sec ID Ex it XXH F0H
T6.6 1223
1. Address format A14-A0 (Hex).
Addresses A15-A19 can be VIL or VIH, b ut no other value, for Command sequence for SST39VF1601/1602,
Addresses A15-A20 can be VIL or VIH, b ut no other value, for Command sequence for SST39VF3201/3202,
Addresses A15- A21 can be VIL or VIH, but no other value, for Command sequence for SST39VF6401/6402.
2. DQ15-DQ8 can be VIL or VIH, but no other value, for Command sequence
3. WA = Program Word address
4. SAX for Sector-Erase; uses AMS-A11 address lines
BAX, for Block-Erase; uses AMS-A15 address lines
AMS = Most significant address
AMS = A19 for SST39VF1601/1602, A20 for SST39VF3201/3202, and A21 for SST39VF6401/6402
5. With AMS-A4 = 0; Sec ID is read with A3-A0,
SST ID is read with A3 = 0 (Address range = 000000H to 000007H),
User ID is read with A3 = 1 (Address range = 000010H to 000017H).
Lock Status is read with A7-A0 = 0000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0.
6. Valid Word-Addresses for Sec ID are from 000000H-000007H and 000010H-000017H.
7. The device does not remain in Software Product ID Mode if powered down.
8. With AMS-A1 =0; SST Manuf acturer ID = 00BFH, is read with A0 = 0,
SST39VF1601 Device ID = 234BH, is read with A0 = 1,
SST39VF1602 Device ID = 234AH, is read with A0 = 1,
SST39VF3201 Device ID = 235BH, is read with A0 = 1,
SST39VF3202 Device ID = 235AH, is read with A0 = 1,
SST39VF6401 Device ID = 236BH, is read with A0 = 1,
SST39VF6402 Device ID = 236AH, is read with A0 = 1.
AMS = Most significant address
AMS = A19 for SST39VF1601/1602, A20 for SST39VF3201/3202, and A21 for SST39VF6401/6402
9. Both Software ID Exit operations are equivalent
10. If users nev er loc k after programming, Sec ID can be programmed over the prev iously unprogrammed bits (data=1) using the Sec ID
mode again (the programmed “0” bits cannot be reversed to “1”). Valid Word-Addresses for Sec ID are from 000000H-000007H and
000010H-000017H.
10
Preliminary Specifications
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
©2003 Silicon Sto rage Technology, Inc. S71223-03-000 11/03
TABLE 7: CFI QUERY IDENTIFICATION STRING1 FOR S ST39V F16 0X/320X/640X
Address Data Data
10H 0051H Query Unique ASCII string “QRY”
11H 0052H
12H 0059H
13H 0001H Primary OEM command set
14H 0007H
15H 0000H Address for Primary Extended Table
16H 0000H
17H 0000H Alternate OEM command set (00H = none exists)
18H 0000H
19H 0000H Address for Alternate OEM extended Table (00H = none exits)
1AH 0000H T7.1 1223
1. Refer to CFI publication 100 for more details.
TABLE 8: SYSTEM INTERFACE INFORMATION FOR SST39VF 160X/320X/640X
Address Data Data
1BH 0027H VDD Min (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1CH 0036H VDD Max (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1DH 0000H VPP min. (00H = no VPP pin)
1EH 0000H VPP max. (00H = no VPP pin)
1FH 0003H Typical time out for Word-Program 2N µs (23 = 8 µs)
20H 0000H Typical time out for min. size buffer program 2N µs (00H = not supported)
21H 0004H Typical time out for indiv idual Sec tor/Bl ock-Erase 2N ms (24 = 16 ms)
22H 0005H Typical time out for Chip-Erase 2N ms (25 = 32 ms)
23H 0001H Maximum time out for Word-Program 2N times typical (21 x 23 = 16 µs)
24H 0000H Maximum time out for buffer program 2N times typical
25H 0001H Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms)
26H 0001H Maximum time out for Chip-Erase 2N times typ ic al (21 x 25 = 64 ms)
T8.3 1223
TABLE 9: DEVICE GEOMETRY INFORMATION FOR SST39VF1601 /1602
Address Data Data
27H 0015H Device size = 2N Bytes (15H = 21; 221 = 2 MByte)
28H 0001H Flash Device Interface description; 0001H = x16-only asynchronous interface
29H 0000H
2AH 0000H Maximum number of byte in multi-byte write = 2N ( 00H = not su pport ed)
2BH 0000H
2CH 0002H Number of Erase Sector/Block sizes supported by device
2DH 00FFH Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
2EH 0001H y = 511 + 1 = 512 sectors (01FF = 511
2FH 0010H
30H 0000H z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)
31H 001FH Block Information (y + 1 = Number of blocks; z x 256B = block size)
32H 0000H y = 31 + 1 = 32 bl ocks (001F = 31)
33H 0000H
34H 0001H z = 256 x 256 Bytes = 64 KByte/block (0100H = 256) T9.0 1223
Preliminary Specifications
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
11
©2003 Silicon Sto rage Technology, Inc. S71223-03-000 11/03
TABLE 10: DEVICE GEOMETRY INFORMATION FOR SST39VF3201 /3202
Address Data Data
27H 0016H Device size = 2N Bytes (16H = 22; 222 = 4 MByte)
28H 0001H Flash Device Interface description; 0001H = x16-only asynchronous interface
29H 0000H
2AH 0000H Maximum number of byte in multi-byte write = 2N ( 00H = not su pport ed)
2BH 0000H
2CH 0002H Number of Erase Sector/Block sizes supported by device
2DH 00FFH Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
2EH 0003H y = 1023 + 1 = 1024 (03FFH = 1023)
2FH 0010H
30H 0000H z = 16 x 256 Bytes = 4 KBytes/sector (0010H = 16)
31H 003FH Block Information (y + 1 = Number of blocks; z x 256B = block size)
32H 0000H y = 63 + 1 = 64 blocks (003FH = 63)
33H 0000H
34H 0001H z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256) T10.2 1223
TABLE 11: DEVICE GEOMETRY INFORMATION FOR SST39VF6401 /6402
Address Data Data
27H 0017H Device size = 2N Bytes (17H = 23; 223 = 8 MByte)
28H 0001H Flash Device Interface description; 0001H = x16-only asynchronous interface
29H 0000H
2AH 0000H Maximum number of bytes in multi-byte write = 2N (00H = not supported)
2BH 0000H
2CH 0002H Number of Erase Sector/Block sizes supported by device
2DH 00FFH Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
2EH 0007H y = 2047 + 1 = 2048 sectors (07FFH = 2047)
2FH 0010H
30H 0000H z = 16 x 256 Bytes = 4 KBytes/sector (0010H = 16)
31H 007FH Block Information (y + 1 = Number of blocks; z x 256B = block size)
32H 0000H y =127 + 1 = 128 bloc k s (007 FH = 127)
33H 0000H
34H 0001H z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256) T11.2 1223
12
Preliminary Specifications
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
©2003 Silicon Sto rage Technology, Inc. S71223-03-000 11/03
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may caus e per manent d amage to the device. This is a stres s rating only and funct ional operatio n
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.0V to VDD+2.0V
Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V
Pac kage Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shor ted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE
Range Ambient Temp VDD
Commercial
Industrial 0°C to +70°C
-40°C to +85°C 2.7-3.6V
2.7-3.6V
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figures 17 and 18
Preliminary Specifications
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
13
©2003 Silicon Sto rage Technology, Inc. S71223-03-000 11/03
TABLE 12: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V1
Symbol Parameter
Limits
Test ConditionsMin Max Units
IDD Power Supply Current Address input=VILT/VIHT2, at f=5 MHz,
VDD=VDD Max
Read318 mA CE#=VIL, OE#=WE#=VIH, all I/Os open
Program and Erase 35 mA CE#=WE#=VIL, OE# =VIH
ISB Standby VDD Current 20 µA CE#=VIHC, VDD=VDD Max
IALP Auto Low Power 20 µA CE#=VILC, VDD=VDD Max
All inputs=VSS or VDD, WE#=VIHC
ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max
ILIW Input Leakage Current
on WP# pin and RST# 10 µA WP#=GND to VDD or RST#=GND to VDD
ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max
VIL Input Low Voltage 0.8 V VDD=VDD Min
VILC Input Low Voltage (CMOS) 0.3 V VDD=VDD Max
VIH Input High Voltage 0.7VDD VV
DD=VDD Max
VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max
VOL Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min
VOH Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min
T12.8 1223
1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C
(room temperature), and VDD = 3V. Not 100% tested.
2. See Figure 17
3. The IDD current listed is typically less than 2mA/MHz, with OE# at VIH. Typical VDD is 3V.
TABLE 13: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol Parameter Minimum Units
TPU-READ1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Power-up to Read Operation 100 µs
TPU-WRITE1Power-up to Program/Erase Operation 100 µs
T13.0 1223
TABLE 14: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)
Parameter Description Test Condition Maximum
CI/O1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
I/O Pin Capacitance VI/O = 0V 12 pF
CIN1Input Capacitance VIN = 0V 6 pF
T14.0 1223
TABLE 15: RELIABILITY CHARACTERISTICS
Symbol Parameter Minimum Specification Units Test Method
NEND1,2
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a
higher minimum specification.
Endurance 10,000 Cycles JEDEC Standard A117
TDR1Data Retention 100 Years JEDEC Standard A103
ILTH1Latch Up 100 + IDD m A JEDEC Standard 78
T15.2 1223
14
Preliminary Specifications
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
©2003 Silicon Sto rage Technology, Inc. S71223-03-000 11/03
AC CHARACTERISTICS
TABLE 16: READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V
Symbol Parameter
SST39VFxx01/xx02-70 SST39VFxx01/xx02-90
UnitsMin Max Min Max
TRC Read Cycle Time 70 90 ns
TCE Chip Enable Access Time 70 90 ns
TAA Address Access Time 70 90 ns
TOE Output Enable Access Time 35 45 ns
TCLZ1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
CE# Low to Active Output 0 0 ns
TOLZ1OE# Low to Active Output 0 0 ns
TCHZ1CE# High to High-Z Output 20 30 ns
TOHZ1OE# High to High-Z Output 20 30 ns
TOH1Output Hold from Address Change 0 0 ns
TRP1RST# Pulse Width 500 500 ns
TRHR1RST# High before Read 50 50 ns
TRY1,2
2. This parameter applies to Sector-Erase, Block-Erase and Program operations.
This parameter does not apply to Chip-Erase operations.
RST# Pin Low to Re ad Mod e 20 20 µs
T16.3 1223
TABLE 17: PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol Parameter Min Max Units
TBP Word-Program Time 10 µs
TAS Address Setup Time 0 ns
TAH Address Hol d Time 30 ns
TCS WE# and CE# Setup Time 0 ns
TCH WE# and CE# Hold Time 0 ns
TOES OE# High Setup Time 0 ns
TOEH OE# High Hold Time 10 ns
TCP CE# Pulse W idth 40 ns
TWP WE# Pulse Width 40 ns
TWPH1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
WE# Pulse Width High 30 ns
TCPH1CE# Pu lse Width H igh 30 ns
TDS Data Setup Time 30 ns
TDH1Data Hold Time 0 ns
TIDA1Software ID Access and Exit Time 150 ns
TSE Sector-Erase 25 ms
TBE Block-Erase 25 ms
TSCE Chip-Erase 50 ms
T17.1 1223
Preliminary Specifications
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
15
©2003 Silicon Sto rage Technology, Inc. S71223-03-000 11/03
FIGURE 3: READ CYCLE TIMING DIAGRAM
FIGURE 4: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
1223 F03.2
ADDRESS AMS-0
DQ15-0
WE#
OE#
CE# TCE
TRC TAA
TOE
TOLZVIH
HIGH-Z TCLZ TOH TCHZ HIGH-Z
D ATA VALIDD ATA VALID
TOHZ
Note: AMS = Most significant address
AMS = A19 for SST39VF1601/1602, A20 for SST39VF3201/3202, and A21 for SST39VF6401/6402
1223 F04.3
ADDRESS AMS-0
DQ15-0
TDH
TWPH
TDS
TWP
TAH
TAS
TCH
TCS
CE#
SW0 SW1 SW2
5555 2AAA 5555 ADDR
XXAA XX55 XXA0 DATA
INTERNAL PROGRAM OPERATION STARTS
WORD
(ADDR/DATA)
OE#
WE#
TBP
Note: AMS = Most significant address
AMS = A19 for SST39VF1601/1602, A20 for SST39VF3201/3202, and A21 for SST39VF6401/6402
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence
X can be VIL or VIH, but no other value
16
Preliminary Specifications
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
©2003 Silicon Sto rage Technology, Inc. S71223-03-000 11/03
FIGURE 5: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
FIGURE 6: DATA# POLLING TIMING DIAGRAM
1223 F05.3
ADDRESS AMS-0
DQ15-0
TDH
TCPH
TDS
TCP
TAH
TAS
TCH
TCS
WE#
SW0 SW1 SW2
5555 2AAA 5555 ADDR
XXAA XX55 XXA0 DATA
INTERNAL PROGRAM OPERATION STARTS
WORD
(ADDR/DATA)
OE#
CE#
TBP
Note: AMS = Most significant address
AMS = A19 for SST39VF1601/1602, A20 for SST39VF3201/3202, and A21 for SST39VF6401/6402
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence
X can be VIL or VIH, but no other value
1223 F06.2
ADDRESS AMS-0
DQ7DATA DATA# DATA# DATA
WE#
OE#
CE#
TOEH
TOE
TCE
TOES
Note: A
MS
= Most significant address
A
MS
= A
19
for SST39VF1601/1602, A
20
for SST39VF3201/3202, and A
21
for SST39VF6401/6402
Preliminary Specifications
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
17
©2003 Silicon Sto rage Technology, Inc. S71223-03-000 11/03
FIGURE 7: TOGGLE BITS T IMING DIAGRAM
FIGURE 8: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM
1223 F07.3
ADDRESS AMS-0
DQ6 and DQ2
WE#
OE#
CE#
TOETOEH
TCE
TOES
TWO READ CYCLES
WITH SAME OUTPUTS
Note: AMS = Most significant address
AMS = A19 for SST39VF1601/1602, A20 for SST39VF3201/3202, and A21 for SST39VF6401/6402
1223 F08.4
ADDRESS AMS-0
DQ15-0
WE#
SW0 SW1 SW2 SW3 SW4 SW5
5555 2AAA 2AAA5555 5555
XX55 XX10XX55XXAA XX80 XXAA
5555
OE#
CE#
SIX-BYTE CODE FOR CHIP-ERASE
TSCE
TWP
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are
interchageable as long as minimum timings are met. (See Table 17)
AMS = Most significant address
AMS = A19 for SST39VF1601/1602, A20 for SST39VF3201/3202, and A21 for SST39VF6401/6402
WP# must be held in proper logic state (VIH) 1 µs prior to and 1 µs after the command sequence
X can be VIL or VIH, but no other value
18
Preliminary Specifications
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
©2003 Silicon Sto rage Technology, Inc. S71223-03-000 11/03
FIGURE 9: WE# CONTROLLED BLOCK-ERASE TIMING D IAGRAM
FIGURE 10: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM
1223 F09.4
ADDRESS AMS-0
DQ15-0
WE#
SW0 SW1 SW2 SW3 SW4 SW5
5555 2AAA 2AAA5555 5555
XX55 XX50XX55XXAA XX80 XXAA
BAX
OE#
CE#
SIX-BYTE CODE FOR BLOCK-ERASE
TBE
TWP
Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are
interchageable as long as minimum timings are met. (See Table 17)
BAX = Block Address
AMS = Most significant address
AMS = A19 for SST39VF1601/1602, A20 for SST39VF3201/3202, and A21 for SST39VF6401/6402
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence
X can be VIL or VIH, but no other value
1223 F10.4
ADDRESS AMS-0
DQ15-0
WE#
SW0 SW1 SW2 SW3 SW4 SW5
5555 2AAA 2AAA5555 5555
XX55 XX30XX55XXAA XX80 XXAA
SAX
OE#
CE#
SIX-BYTE CODE FOR SECTOR-ERASE
TSE
TWP
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are
interchageable as long as minimum timings are met. (See Table 17)
SAX = Sector Address
AMS = Most significant address
AMS = A19 for SST39VF1601/1602, A20 for SST39VF3201/3202, and A21 for SST39VF6401/6402
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence
X can be VIL or VIH, but no other value
Preliminary Specifications
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
19
©2003 Silicon Sto rage Technology, Inc. S71223-03-000 11/03
FIGURE 11: SOFTWARE ID ENTRY AND READ
FIGU R E 12: CFI Q UERY ENTRY AND READ
1223 F11.2
ADDRESS A14-0
TIDA
DQ15-0
WE#
SW0 SW1 SW2
5555 2AAA 5555 0000 0001
OE#
CE#
Three-Byte Sequence for Software ID Entry
TWP
TWPH TAA
00BF
Device ID
XX55XXAA XX90
Note: Device ID = 234BH for 39VF1601, 234AH for 39VF1602, 235BH for 39VF3201, 235AH for 39VF3202,
236BH for 39VF6401, and 236AH for 39VF6402,
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence
X can be VIL or VIH, but no other value
1223 F12.1
ADDRESS A14-0
TIDA
DQ15-0
WE#
SW0 SW1 SW2
5555 2AAA 5555
OE#
CE#
Three-Byte Sequence for CFI Query Entry
TWP
TWPH TAA
XX55XXAA XX98
Note: WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence
X can be VIL or VIH, but no other value