REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2001
AD9226
Complete 12-Bit, 65 MSPS
ADC Converter
FUNCTIONAL BLOCK DIAGRAM
VINA
CAPT
CAPB
SENSE
OTR
BIT 1
(MSB)
BIT 12
(LSB)
VREF
DRVSS
AVSS
AD9226
SHA
CORRECTION LOGIC
OUTPUT BUFFERS
VINB
1V
REFCOM
4
16 3
12
DRVDD
AVDD
CLK
MODE
SELECT
MDAC1 A/D
A/D
8-STAGE
1-1/2-BIT PIPELINE
MODE
REF
SELECT
CALIBRATION
ROM
DUTY CYCLE STABILIZER
FEATURES
Signal-to-Noise Ratio: 69 dB @ fIN = 31 MHz
Spurious-Free Dynamic Range: 85 dB @ fIN = 31 MHz
Intermodulation Distortion of –75 dBFS @ fIN = 140 MHz
ENOB = 11.1 @ fIN = 10 MHz
Low-Power Dissipation: 475 mW
No Missing Codes Guaranteed
Differential Nonlinearity Error: ⴞ0.6 LSB
Integral Nonlinearity Error: ⴞ0.6 LSB
Clock Duty Cycle Stabilizer
Patented On-Chip Sample-and-Hold with
Full Power Bandwidth of 750 MHz
Straight Binary or Two’s Complement Output Data
28-Lead SSOP, 48-Lead LQFP
Single 5 V Analog Supply, 3 V/5 V Driver Supply
Pin-Compatible to AD9220, AD9221, AD9223,
AD9224, AD9225
PRODUCT DESCRIPTION
The AD9226 is a monolithic, single-supply, 12-bit, 65 MSPS
analog-to-digital converter with an on-chip, high-performance
sample-and-hold amplifier and voltage reference. The AD9226
uses a multistage differential pipelined architecture with a pat-
ented input stage and output error correction logic to provide
12-bit accuracy at 65 MSPS data rates. There are no missing
codes over the full operating temperature range (guaranteed).
The input of the AD9226 allows for easy interfacing to both
imaging and communications systems. With a truly differential
input structure, the user can select a variety of input ranges and
offsets including single-ended applications.
The sample-and-hold amplifier (SHA) is well suited for IF
undersampling schemes such as in single-channel communi-
cation applications with input frequencies up to and well
beyond Nyquist frequencies.
The AD9226 has an on-board programmable reference. For sys-
tem design flexibility, an external reference can also be chosen.
A single clock input is used to control all internal conversion
cycles. An out-of-range signal indicates an overflow condition
that can be used with the most significant bit to determine low
or high overflow.
The AD9226 has two important mode functions. One will set
the data format to binary or two’s complement. The second will
make the ADC immune to clock duty cycle variations.
PRODUCT HIGHLIGHTS
IF Sampling—The patented SHA input can be configured for
either single-ended or differential inputs. It will maintain out-
standing AC performance up to input frequencies of 300 MHz.
Low Power—The AD9226 at 475 mW consumes a fraction of
the power presently available in existing, high-speed monolithic
solutions.
Out of Range (OTR)—The OTR output bit indicates when
the input signal is beyond the AD9226’s input range.
Single Supply—The AD9226 uses a single 5 V power supply
simplifying system power supply design. It also features a sepa-
rate digital output driver supply line to accommodate 3 V and
5 V logic families.
Pin Compatibility—The AD9226 is similar to the AD9220,
AD9221, AD9223, AD9224, and AD9225 ADCs.
Clock Duty Cycle Stabilizer—Makes conversion immune to
varying clock pulsewidths.
REV. B
–2–
AD9226–SPECIFICATIONS
(AVDD = 5 V, DRVDD = 3 V, fSAMPLE = 65 MSPS, VREF = 2.0 V, Differential inputs, TMIN to TMAX unless otherwise
noted.)
DC SPECIFICATIONS
P
arameter Temp Test Level Min Typ Max Unit
RESOLUTION 12 Bits
ACCURACY
Integral Nonlinearity (INL) Full V ±0.6 LSB
25°CI ±1.6 LSB
Differential Nonlinearity (DNL) Full V ±0.6 LSB
25°CI ±1.0 LSB
No Missing Codes Guaranteed Full I 12 Bits
Zero Error Full V ±0.3 % FSR
25°CI ±1.4 % FSR
Gain Error 25°CI ±2.0 % FSR
Full V ±0.6 % FSR
TEMPERATURE DRIFT
Zero Error Full V ±2 ppm/°C
Gain Error
1
Full V ±26 ppm/°C
Gain Error
2
Full V ±0.4 ppm/°C
POWER SUPPLY REJECTION
AVDD
(5 V ± 0.25 V) Full V ±0.05 % FSR
25°CI ±0.4 % FSR
INPUT REFERRED NOISE
VREF = 1.0 V Full V 0.5 LSB rms
VREF = 2.0 V Full V 0.25 LSB rms
ANALOG INPUT
Input Span (VREF = 1 V) Full V 1 V p-p
(VREF = 2 V) Full V 2 V p-p
Input (VINA or VINB) Range Full IV 0 AVDD V
Input Capacitance Full V 7 pF
INTERNAL VOLTAGE REFERENCE
Output Voltage (1 V Mode) Full V 1.0 V
Output Voltage Tolerance (1 V Mode) 25°CI ±15 mV
Output Voltage (2.0 V Mode) Full V 2.0 V
Output Voltage Tolerance (2.0 V Mode) 25°CI ±29 mV
Output Current (Available for External Loads) Full V 1.0 mA
Load Regulation
3
Full V 0.7 mV
25°C I 1.5 mV
REFERENCE INPUT RESISTANCE Full V 5 kΩ
POWER SUPPLIES
Supply Voltages
AVDD Full V 4.75 5 5.25 V (±5% AVDD
Operating)
DRVDD Full V 2.85 5.25 V (±5% DRVDD
Operating)
Supply Current
IAVDD
4
Full V 86 mA (2 V External VREF)
25°C I 90.5 mA (2 V External VREF)
IDRVDD
5
Full V 14.6 mA (2 V External VREF)
25°C I 16.5 mA (2 V External VREF)
POWER CONSUMPTION
4, 5
Full V 475
25°C I 500 mW (2 V External VREF)
NOTES
1
Includes internal voltage reference error.
2
Excludes internal voltage reference error.
3
Load regulation with 1 mA load current (in addition to that required by the AD9226).
4
AVDD = 5 V
5
DRVDD = 3 V
Specifications subject to change without notice.
REV. B –3–
AD9226
DIGITAL SPECIFICATIONS
Parameters Temp Test Level Min Typ Max Unit
LOGIC INPUTS (Clock, DFS
1
, Duty Cycle
1
,
and
Output Enable
1
)
High-Level Input Voltage Full IV 2.4 V
Low-Level Input Voltage Full IV 0.8 V
High-Level Input Current (V
IN
= AVDD) Full IV –10 +10 µA
Low-Level Input Current (V
IN
= 0 V) Full IV –10 +10 µA
Input Capacitance Full V 5 pF
Output Enable
1
Full IV V
LOGIC OUTPUTS (With DRVDD = 5 V)
High-Level Output Voltage (I
OH
= 50 µA) Full IV 4.5 V
High-Level Output Voltage (I
OH
= 0.5 mA) Full IV 2.4 V
Low-Level Output Voltage (I
OL
= 1.6 mA) Full IV 0.4 V
Low-Level Output Voltage (I
OL
= 50 µA) Full IV 0.1 V
Output Capacitance 5pF
LOGIC OUTPUTS (With DRVDD = 3 V)
High-Level Output Voltage (I
OH
= 50 µA) Full IV 2.95 V
High-Level Output Voltage (I
OH
= 0.5 mA) Full IV 2.80 V
Low-Level Output Voltage (I
OL
= 1.6 mA) Full IV 0.4 V
Low-Level Output Voltage (I
OL
= 50 µA) Full IV 0.05 V
NOTES
1
LQFP package.
Specifications subject to change without notice.
SWITCHING SPECIFICATIONS
Parameters Temp Test Level Min Typ Max Unit
Max Conversion Rate Full VI 65 MHz
Clock Period
1
Full V 15.38 ns
CLOCK Pulsewidth High
2
Full V 3 ns
CLOCK Pulsewidth Low
2
Full V 3 ns
Output Delay Full V 3.5 7 ns
Pipeline Delay (Latency) Full V 7 Clock Cycles
Output Enable Delay
3
Full V 15 ns
NOTES
1
The clock period may be extended to 10 µs without degradation in specified performance @ 25°C.
2
When MODE pin is tied to AVDD or grounded, the AD9226 SSOP is not affected by clock duty cycle.
3
LQFP package.
Specifications subject to change without notice.
(AVDD = 5 V, DRVDD = 3 V, fSAMPLE = 65 MSPS, VREF = 2.0 V, TMIN to TMAX, unless otherwise noted.)
(TMIN to TMAX with AVDD = 5 V, DRVDD = 3 V, CL = 20 pF)
n+1 n+2
n+3
n+4
n+5 n+6
n+7
n+8
n
ANALOG
INPUT
CLOCK
DATA
OUT n–8 n–7 n–6 n–5 n–4 n–3 n–2 n+1
n
n–1
TOD = 7.0 MAX
3.5 MIN
Figure 1. Timing Diagram
DRVDD
205–.
DRVDD
205+.
REV. B
–4–
AD9226–SPECIFICATIONS
AC SPECIFICATIONS
(AVDD = 5 V, DRVDD = 3 V, fSAMPLE = 65 MSPS, VREF = 2.0 V, TMIN to TMAX, Differential Input unless otherwise noted.)
Parameter Temp Test Level Min Typ Max Unit
SIGNAL-TO-NOISE RATIO
f
IN
= 2.5 MHz Full V 68.9 dBc
25°C
I 68 dBc
f
IN
= 15 MHz Full V 68.4 dBc
25°C
I 67.4 dBc
f
IN
= 31 MHz Full V 68 dBc
f
IN
= 60 MHz Full V 68 dBc
f
IN
= 200 MHz
1
Full V 65 dBc
SIGNAL-TO-NOISE RATIO AND DISTORTION
f
IN
= 2.5 MHz Full V 68.8 dBc
25°C
I 67.9 dBc
f
IN
= 15 MHz Full V 68.3 dBc
25°C
I 67.3 dBc
f
IN
= 31 MHz Full V 67 dBc
f
IN
= 60 MHz Full V 67 dBc
f
IN
= 200 MHz
1
Full V 60 dBc
TOTAL HARMONIC DISTORTION
f
IN
= 2.5 MHz Full V –84 dBc
25°C
I–77.0 dBc
f
IN
= 15 MHz Full V –82.3 dBc
25°C
I–76.0 dBc
f
IN
= 31 MHz Full V –68 dBc
f
IN
= 60 MHz Full V –68 dBc
f
IN
= 200 MHz
1
Full V –61 dBc
SECOND AND THIRD HARMONIC DISTORTION
f
IN
= 2.5 MHz Full V –86.5 dBc
25°C
I–78 dBc
f
IN
= 15 MHz Full V –86.7 dBc
25°C
I–76 dBc
f
IN
= 31 MHz Full V –83 dBc
f
IN
= 60 MHz Full V –82 dBc
f
IN
= 200 MHz
1
Full V –75 dBc
SPURIOUS FREE DYNAMIC RANGE
f
IN
= 2.5 MHz Full V 86.4 dBc
25°C
I 78 dBc
f
IN
= 15 MHz Full V 85.5 dBc
25°C
I 76 dBc
f
IN
= 31 MHz Full V 82 dBc
f
IN
= 60 MHz Full V 81 dBc
f
IN
= 200 MHz
1
Full V 60 dBc
ANALOG INPUT BANDWIDTH 25°C V 750 MHz
NOTES
1
1.0 V Reference and Input Span
Specifications subject to change without notice.
REV. B
AD9226
–5–
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9226 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
1
With
Pin Name Respect to Min Max Unit
AVDD AVSS –0.3 +6.5 V
DRVDD DRVSS –0.3 +6.5 V
AVSS DRVSS –0.3 +0.3 V
AVDD DRVDD –6.5 +6.5 V
REFCOM AVSS –0.3 +0.3 V
CLK, MODE AVSS –0.3 AVDD + 0.3 V
Digital Outputs DRVSS –0.3 DRVDD + 0.3 V
VINA, VINB AVSS –0.3 AVDD + 0.3 V
VREF AVSS –0.3 AVDD
+ 0.3 V
SENSE AVSS –0.3 AVDD
+ 0.3 V
CAPB, CAPT AVSS –0.3 AVDD
+ 0.3 V
OEB
2
DRVSS –0.3 DRVDD + 0.3 V
CM LEVEL
2
AVSS –0.3 AVDD
+ 0.3 V
VR
2
AVSS –0.3 AVDD
+ 0.3 V
Junction Temperature 150 °C
Storage Temperature –65 +150 °C
Lead Temperature (10 sec) 300 °C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
2
LQFP package.
EXPLANATION OF TEST LEVELS
Test Level
I. 100% production tested.
II. 100% production tested at 25°C and sample tested at
specified temperatures. AC testing done on sample basis.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization
testing.
V. Parameter is a typical value only.
VI. All devices are 100% production tested at 25°C; sample tested
at temperature extremes.
THERMAL RESISTANCE
θ
JC
SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23°C/W
θ
JA
SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63.3°C/W
θ
JC
LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17°C/W
θ
JA
LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76.2°C/W
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD9226ARS –40°C to +85°C 28-Lead Shrink Small Outline (SSOP) RS-28
AD9226AST –40°C to +85°C 48-Lead Thin Plastic Quad Flatpack (LQFP) ST-48
AD9226-EB Evaluation Board (SSOP)
AD9226-LQFP-EB Evaluation Board (LQFP)
REV. B
AD9226
–6–
48-PIN FUNCTION DESCRIPTIONS
Pin
Number Name Description
1, 2, 32, 33 AVSS Analog Ground
3, 4, 31, 34 AVDD 5 V Analog Supply
5, 6, 8, 10, NC No Connect
11, 44
7 CLK Clock Input Pin
9OEB Output Enable (Active Low)
12 BIT 12 Least Significant Data Bit (LSB)
13 BIT 11 Data Output Bit
14, 22, 30 DRVSS Digital Output Driver Ground
15, 23, 29 DRVDD 3 V to 5 V Digital Output
Driver Supply
16–21, BITS 10–5, Data Output Bits
24–26 BITS 4–2
27 BIT 1 Most Significant Data Bit (MSB)
28 OTR Out of Range
35 MODE2 Data Format Select
36 SENSE Reference Select
37 VREF Reference In/Out
38 REFCOM Reference Common
(AVSS)
39, 40 CAPB Noise Reduction Pin
41, 42 CAPT Noise Reduction Pin
43 MODE1 Clock Stabilizer
45 CM LEVEL Midsupply Reference
46 VINA Analog Input Pin (+)
47 VINB Analog Input Pin (–)
48 VR Noise Reduction Pin
PIN CONNECTION
28-Lead SSOP
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD9226
OTR
(MSB) BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
CLK
(LSB) BIT 12
BIT 11
BIT 10
BIT 7
BIT 8
BIT 9
AVDD
AVSS
SENSE
VREF
REFCOM (AVSS)
CAPB
CAPT
DRVDD
DRVSS
AVDD
AVSS
MODE
VINA
VINB
PIN CONNECTION
48-Lead LQFP
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44 39 38 3743 42 41 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
SENSE
MODE2
AVDD
AVSS
AVSS
AVDD
DRVSS
AVSS
AVSS
AVDD
AVDD
NC
NC
CLK
NC = NO CONNECT
NC
OEB
NC
NC
DRVDD
OTR
BIT 1 (MSB)
BIT 2
AD9226
(LSB) BIT 12 BIT 3
VR
VINB
VINA
CM LEVEL
NC
MODE1
CAPT
CAPT
CAPB
CAPB
REF COM (AVSS)
VREF
BIT 11
DRVSS
DRVDD
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
DRVSS
DRVDD
BIT 4
28-PIN FUNCTION DESCRIPTIONS
Pin
Number Name Description
1 CLK Clock Input Pin
2 BIT 12 Least Significant Data Bit (LSB)
3–12 BITS 11–2 Data Output Bits
13 BIT 1 Most Significant Data Bit (MSB)
14 OTR Out of Range
15, 26 AVDD 5 V Analog Supply
16, 25 AVSS Analog Ground
17 SENSE Reference Select
18 VREF Input Span Select (Reference I/O)
19 REFCOM Reference Common
(AVSS)
20 CAPB Noise Reduction Pin
21 CAPT Noise Reduction Pin
22 MODE Data Format Select/Clock Stabilizer
23 VINA Analog Input Pin (+)
24 VINB Analog Input Pin (–)
27 DRVSS Digital Output Driver Ground
28 DRVDD 3 V to 5 V Digital Output
Driver Supply
REV. B
AD9226
–7–
DEFINITIONS OF SPECIFICATIONS
INTEGRAL NONLINEARITY (INL)
INL refers to the deviation of each individual code from a line
drawn from “negative full scale” through “positive full scale.”
The point used as “negative full scale” occurs 1/2 LSB before
the first code transition. “Positive full scale” is defined as a level
1 1/2 LSB beyond the last code transition. The deviation is
measured from the middle of each particular code to the true
straight line.
DIFFERENTIAL NONLINEARITY (DNL, NO MISSING
CODES)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 12-bit resolution indicates that all 4096
codes, respectively, must be present over all operating ranges.
ZERO ERROR
The major carry transition should occur for an analog value
1/2 LSB below VINA = VINB. Zero error is defined as the
deviation of the actual transition from that point.
GAIN ERROR
The first code transition should occur at an analog value
1/2 LSB above negative full scale. The last transition should
occur at an analog value 1 1/2 LSB below the positive full scale.
Gain error is the deviation of the actual difference between first
and last code transitions and the ideal difference between first
and last code transitions.
TEMPERATURE DRIFT
The temperature drift for zero error and gain error specifies the
maximum change from the initial (25°C) value to the value at
T
MIN
or T
MAX
.
POWER SUPPLY REJECTION
The specification shows the maximum change in full scale from
the value with the supply at the minimum limit to the value with
the supply at its maximum limit.
APERTURE JITTER
Aperture jitter is the variation in aperture delay for successive
samples and can be manifested as noise on the input to the ADC.
APERTURE DELAY
Aperture delay is a measure of the sample-and-hold amplifier
(SHA) performance and is measured from the rising edge of the
clock input to when the input signal is held for conversion.
SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD)
RATIO
S/N+D is the ratio of the rms value of the measured input
signal to the rms sum of all other spectral components below
the Nyquist frequency, including harmonics but excluding dc.
The value for S/N+D is expressed in decibels.
EFFECTIVE NUMBER OF BITS (ENOB)
For a sine wave, SINAD can be expressed in terms of the num-
ber of bits. Using the following formula,
N = (SINAD – 1.76)/6.02
it is possible to obtain a measure of performance expressed as
N, the effective number of bits.
Thus, effective number of bits for a device for sine wave inputs
at a given input frequency can be calculated directly from its
measured SINAD.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured input signal and is
expressed as a percentage or in decibels.
SIGNAL-TO-NOISE RATIO (SNR)
SNR is the ratio of the rms value of the measured input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc. The value
for SNR is expressed in decibels.
SPURIOUS FREE DYNAMIC RANGE (SFDR)
SFDR is the difference in dB between the rms amplitude of the
input signal and the peak spurious signal.
ENCODE PULSEWIDTH DUTY CYCLE
Pulsewidth high is the minimum amount of time that the clock
pulse should be left in the logic “1” state to achieve rated per-
formance; pulsewidth low is the minimum time the clock pulse
should be left in the low state. At a given clock rate, these specs
define an acceptable clock duty cycle.
MINIMUM CONVERSION RATE
The clock rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
MAXIMUM CONVERSION RATE
The encode rate at which parametric testing is performed.
OUTPUT PROPAGATION DELAY
The delay between the clock logic threshold and the time when
all bits are within valid logic levels.
TWO TONE SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. May be reported in dBc
(i.e., degrades as signal levels are lowered) or in dBFS (always
related back to converter full scale).
REV. B
AD9226
–8–
DRVDD
DRVSS
DRVDD
DRVSS
DRVDD
AVSS
AVDD
AVSS
AVDD
AVDD
AVSS
Figure 2. Equivalent Circuits
a. D0–D11, OTR b. Three-State (OEB) c. CLK
d. AIN e. CAPT, CAPB, MODE, SENSE, VREF
REV. B
FREQUENCY – MHz
0
dBFS
–120
–100
–80
–60
–40
–20
032.56.5 13 19.5 26
–110
–90
–70
–50
–30
–10 SNR = 69.9dBc
SINAD = 69.8dBc
ENOB = 11.4BITS
THD = –86.4dBc
SFDR = 88.7dBc
TPC 1. Single-Tone 8K FFT with f
IN
= 5 MHz
FREQUENCY – MHz
0
dBFS
–120
–100
–80
–60
–40
–20
032.56.5 13 19.5 26
–110
–90
–70
–50
–30
–10 SNR = 70.4dBFS
SFDR = 87.5dBFS
TPC 2. Dual-Tone 8K FFT with f
IN–1
= 18 MHz and
f
IN–2
= 20 MHz (A
IN–1 =
A
IN–2
= –6.5 dBFS)
FREQUENCY – MHz
0
dBFS
–120
–100
–80
–60
–40
–20
0 32.56.5 13 19.5 26
–110
–90
–70
–50
–30
–10 SNR = 69.5dBc
SINAD = 69.4dBc
ENOB = 11.3BITS
THD = –85dBc
SFDR = 87.6dBc
TPC 3. Single-Tone 8K FFT with f
IN
= 31 MHz
(AVDD = 5.0 V, DRVDD = 3.0 V, fSAMPLE = 65 MSPS with CLK Stabilizer Enabled, TA = 25ⴗC, 2 V Differential Input Span, VCM = 2.5 V, AIN = –0.5 dBFS,
VREF = 2.0 V, unless otherwise noted.)
Typical Performance Characteristics–A
D9226
–9–
SNR – dBFS
SFDR – dBc
SFDR – dBFS
SNR – dBc
100
80
60
40
AIN – dBFS
dBFS AND dBc
–30 –25 –20 –15 –10 0
–5
50
70
90
TPC 4. Single-Tone SNR/SFDR vs. A
IN
with f
IN
= 5 MHz
SNR – dBFS
SFDR – dBc
SNR – dBc
100
80
60
40
dBFS AND dBc
50
70
90
A
IN
– dBFS
–30 –25 –20 –15 –10 0
–5
SFDR – dBFS
TPC 5. Dual-Tone SNR/SFDR vs. A
IN
with f
IN–1
= 18 MHz
and f
IN–2
= 20 MHz
100
80
60
40
AIN – dBFS
dBFS AND dBc
–30 –25 –20 –15 –10 0
–5
50
70
90
SNR – dBFS
SFDR – dBc
SFDR – dBFS
SNR – dBc
TPC 6. Single-Tone SNR/SFDR vs. A
IN
with f
IN
= 31 MHz
REV. B
AD9226
–10–
FREQUENCY – MHz
45
1 1000
SINAD – dBc
100
10
50
55
60
65
75
70
7.3
8.1
8.9
9.8
10.6
11.4
12.2
ENOB – Bits
2V SPAN, DIFFERENTIAL
1V SPAN,
DIFFERENTIAL
2V SPAN, SINGLE-ENDED
1V SPAN,
SINGLE-ENDED
TPC 7. SINAD/ENOB vs. Frequency
FREQUENCY – MHz
1 1000
THD – dBc
100
10
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
2V SPAN,
DIFFERENTIAL
1V SPAN,
DIFFERENTIAL
1V SPAN,
SINGLE-ENDED
2V SPAN, SINGLE-ENDED
TPC 8. THD vs. Frequency
FREQUENCY – MHz
1 1000
SNR – dBc
100
10
62
64
66
72
70
68
+85ⴗC
+25ⴗC
–40ⴗC
TPC 9. SNR vs. Temperature and Frequency
FREQUENCY – MHz
61
1 1000
SNR – dBc
10010
62
64
66
68
71
70
69
67
65
63
2V SPAN, DIFFERENTIAL
1V SPAN,
DIFFERENTIAL
1V SPAN,
SINGLE-ENDED
2V SPAN, SINGLE-ENDED
TPC 10. SNR vs. Frequency
FREQUENCY – MHz
45
1 1000
SFDR – dBc
100
10
50
60
70
80
95
90
85
75
65
55
2V SPAN,
DIFFERENTIAL
1V SPAN,
DIFFERENTIAL
1V SPAN,
SINGLE-ENDED
2V SPAN, SINGLE-ENDED
TPC 11. SFDR vs. Frequency
THD – dBc
–72
–74
–76
–78
–80
–82
–84
–86
–88
–90
–70
FREQUENCY – MHz
110010
+85ⴗC
+25ⴗC
–40ⴗC
TPC 12. THD vs. Temperature and Frequency
REV. B
AD9226
–11–
FREQUENCY – MHz
1 1000
HARMONICS – dBc
100
10
55
65
75
105
95
85
4th HARMONIC
3RD HARMONIC
2ND HARMONIC
TPC 13. Harmonics vs. Frequency
100
90
85
95
SAMPLE RATE – MSPS
10 20 30 40 50 7060
SFDR – dBc
80
f
IN
= 2MHz
f
IN
= 12MHz
f
IN
= 20MHz
TPC 14. SFDR vs. Sample Rate
CODE
4000
INL – LSB
1.0
0.8
0.6
0.4
0.2
0.0
–0.2
–0.4
–0.6
–0.8
–1.0 3500300025002000150010005000
TPC 15. Typical INL
70.5
70
69.5
69
69.25
69.75
70.25
SAMPLE RATE – MSPS
10 20 30 40 50 7060
SINAD – dBc
fIN = 2MHz
fIN = 12MHz
fIN = 20MHz
TPC 16. SINAD vs. Sample Rate
% POSITIVE DUTY CYCLE
30 45
SINAD/SFDR – dBc
35 50 55 70
45
50
55
60
65
70
75
80
85
90
40 60 65
SFDR – CLOCK STABILIZER ON
SINAD – CLOCK STABILIZER ON
SFDR – CLOCK STABILIZER OFF
SINAD – CLOCK STABILIZER OFF
TPC 17. SINAD/SFDR vs. Duty Cycle @ f
IN
= 20 MHz
CODE
1
0
–10
DNL – LSB
500 1k 1500 2k 2500 3k 3500 4k
–0.8
–0.6
–0.4
–0.2
0.2
0.4
0.6
0.8
TPC 18. Typical DNL
REV. B
AD9226
–12– REV. B
FREQUENCY – MHz
0
dBFS
–80
–60
–40
–20
024
412 16 20
–90
–70
–50
–30
–10
828 32
–120
–100
–110
SNR = 70.2dBFS
SFDR = 89dBFS
NOISE FLOOR = 145.33dBFS/Hz
TPC 19. Dual-Tone 8K FFT with f
IN–1
= 44.2 MHz and
f
IN–2
= 45.6 MHz
FREQUENCY – MHz
0
dBFS
–80
–60
–40
–20
02441216
20
–90
–70
–50
–30
–10
828
32
–120
–100
–110
SNR = 68.5dBFS
SFDR = 75dBFS
NOISE FLOOR = 143.6dBFS/Hz
TPC 20. Dual-Tone 8K FFT with f
IN–1
= 69.2 MHz and
f
IN–2
= 70.6 MHz
FREQUENCY – MHz
0
dBFS
–80
–60
–40
–20
024
412 16 20
–90
–70
–50
–30
–10
828 32
–120
–100
–110
SNR = 67.5dBFS
SFDR = 75dBFS
NOISE FLOOR = 142.6dBFS/Hz
TPC 21. Dual-Tone 8K FFT with f
IN–1
= 139.2 MHz and
f
IN–2
= 140.7 MHz
AD9226–Typical IF Sampling Performance Characteristics
–12–
(AVDD = 5.0 V, DRVDD = 3.0 V, fSAMPLE = 65 MSPS with CLK Stabilizer Enabled, TA = 25ⴗC, 2 V Differential Input Span, VCM = 2.5 V, AIN = –6.5 dBFS,
VREF = 2.0 V, unless otherwise noted.)
AIN – dBFS
–24
SNR/SFDR – dBFS
–21
65
70
75
95
80
85
90
–18 –15 –12 –9–6
SNR/NOISE FLOOR – 2V SPAN
SFDR – 2V SPAN
NOISE FLOOR – dBFS/Hz
140.1
145.1
150.1
170.1
155.1
160.1
165.1
TPC 22. Dual-Tone SNR and SFDR with f
IN–1
= 44.2 MHz
and f
IN–2
= 45.6 MHz
AIN – dBFS
–24
SNR/SFDR – dBFS
–21
60
65
70
90
75
80
85
–18 –15 –12 –9–6
NOISE FLOOR – dBFS/Hz
135.1
140.1
145.1
165.1
150.1
155.1
160.1
SNR/NOISE FLOOR – 1V SPAN
SFDR – 2V SPAN
SNR/NOISE FLOOR – 2V SPAN
SFDR – 1V SPAN
TPC 23. Dual-Tone SNR and SFDR with f
IN–1
= 69.2 MHz
and f
IN–2
= 70.6 MHz
AIN – dBFS
–24
SNR/SFDR – dBFS
–21
60
65
70
90
75
80
85
–18 –15 –12 –9–6
NOISE FLOOR – dBFS/Hz
135.1
140.1
145.1
165.1
150.1
155.1
160.1
SNR/NOISE FLOOR – 1V SPAN
SFDR – 2V SPAN
SNR/NOISE FLOOR – 2V SPAN
SFDR – 1V SPAN
TPC 24. Dual-Tone SNR and SFDR with f
IN–1
= 139.2 MHz
and f
IN–2
= 140.7 MHz
REV. B
AD9226
–13–
FREQUENCY – MHz
0
dBFS
–80
–60
–40
–20
025
51520
–90
–70
–50
–30
–10
10 30
–120
–100
–110
f
IN
= 190.82MHz
f
SAMPLE
= 61.44MSPS
TPC 25. Single-Tone 8K FFT at IF
= 190 MHz–WCDMA
(f
IN
= 190.82 MHz, f
SAMPLE
= 61.44 MSPS)
FREQUENCY – MHz
0
dBFS
–80
–60
–40
–20
024
412 16 20
–90
–70
–50
–30
–10
828 32
–120
–100
–110
SNR = 65.1dBFS
SFDR = 59dBFS
NOISE FLOOR = 140.2dBFS/Hz
TPC 26. Dual-Tone 8K FFT with f
IN–1
= 239.1 MHz and
f
IN–2
= 240.7 MHz
FREQUENCY – MHz
11000
CMRR – dBc
100
10
–95
–85
–75
–65
–55
–45
–35
INPUT SPAN = 2V p–p
INPUT SPAN = 1V p–p
TPC 27. CMRR vs. Frequency (A
IN
= –0 dBFS and
CML = 2.5 V)
AIN – dBFS
–24
SNR/SFDR – dBFS
–21
60
65
70
90
75
80
85
–18 –15 –12 –9–6
NOISE FLOOR – dBFS/Hz
135.1
140.1
145.1
165.1
150.1
155.1
160.1
SNR/NOISE FLOOR – 1V SPAN
SFDR – 2V SPAN
SNR/NOISE FLOOR – 2V SPAN
SFDR – 1V SPAN
TPC 28. Single-Tone SNR and SFDR vs. A
IN
at IF
= 190 MHz
–WCDMA (f
IN–1
= 190.8 MHz, f
SAMPLE
= 61.44 MSPS)
AIN – dBFS
–24
SNR/SFDR – dBFS
–21
55
60
65
85
70
75
80
–18 –15 –12 –9–6
NOISE FLOOR – dBFS/Hz
130.1
135.1
140.1
160.1
145.1
150.1
155.1
SNR/NOISE FLOOR – 1V SPAN
SFDR – 2V SPAN
SNR/NOISE FLOOR – 2V SPAN
SFDR – 1V SPAN
TPC 29. Dual-Tone SNR and SFDR with f
IN–1
= 239.1 MHz
and f
IN–2
= 240.7 MHz
REV. B
AD9226
–14–
THEORY OF OPERATION
The AD9226 is a high-performance, single-supply 12-bit ADC.
The analog input of the AD9226 is very flexible allowing for both
single-ended or differential inputs of varying amplitudes that can
be ac- or dc-coupled.
It utilizes a nine-stage pipeline architecture with a wideband,
sample-and-hold amplifier (SHA) implemented on a cost-
effective CMOS process. A patented structure is used in the
SHA to greatly improve high frequency SFDR/distortion. This
also improves performance in IF undersampling applications.
Each stage of the pipeline, excluding the last stage, consists of a
low resolution flash ADC connected to a switched capacitor
DAC and interstage residue amplifier (MDAC). The residue
amplifier amplifies the difference between the reconstructed DAC
output and the flash input for the next stage in the pipeline. One
bit of redundancy is used in each of the stages to facilitate digital
correction of flash errors. The last stage simply consists of a
flash ADC.
Factory calibration ensures high linearity and low distortion.
ANALOG INPUT OPERATION
Figure 3 shows the equivalent analog input of the AD9226 which
consists of a 750 MHz differential SHA. The differential input
structure of the SHA is highly flexible, allowing the device to be
easily configured for either a differential or single-ended input.
The analog inputs, VINA and VINB, are interchangeable with
the exception that reversing the inputs to the VINA and VINB
pins results in a data inversion (complementing the output word).
The optimum noise and dc linearity performance for either
differential or single-ended inputs is achieved with the largest input
signal voltage span (i.e., 2 V input span) and matched input
impedance for VINA and VINB. Only a slight degradation in
dc linearity performance exists between the 2 V and 1 V input
spans.
High frequency inputs may find the 1 V span better suited to
achieve superior SFDR performance. (See Typical Perfor-
mance Characteristics.)
The ADC samples the analog input on the rising edge of the clock
input. During the clock low time (between the falling edge and
rising edge of the clock), the input SHA is in the sample mode;
during the clock high time it is in hold. System disturbances just
prior to the rising edge of the clock and/or excessive clock jitter
on the rising edge may cause the input SHA to acquire the wrong
value and should be minimized.
When the ADC is driven by an op amp and a capacitive load is
switched onto the output of the op amp, the output will momen-
tarily drop due to its effective output impedance. As the output
recovers, ringing may occur. To remedy the situation, a series
resistor can be inserted between the op amp and the SHA
input as shown in Figure 4. A shunt capacitance also acts like
a charge reservoir, sinking or sourcing the additional charge
required by the hold capacitor, C
H
, further reducing current
transients seen at the op amp’s output.
The optimum size of this resistor is dependent on several factors,
including the ADC sampling rate, the selected op amp, and the
particular application. In most applications, a 30 Ω to 100 Ω
resistor is sufficient.
For noise-sensitive applications, the very high bandwidth of the
AD9226 may be detrimental and the addition of a series resistor
and/or shunt capacitor can help limit the wideband noise at the
ADC’s input by forming a low-pass filter. The source imped-
ance driving VINA and VINB should be matched. Failure to
provide matching will result in degradation of the AD9226’s
SNR, THD, and SFDR.
CS
QS1
QH1
VINA
VINB
CS
QS1
CPIN
CPAR
CPIN
CPAR
QS2
CH
QS2
CH
Figure 3. Equivalent Input Circuit
10F
VINA
VINB
SENSE
AD9226
0.1F
VCC
VEE
RS
33⍀
VREF
REFCOM
15pF
RS
33⍀
Figure 4. Series Resistor Isolates Switched-Capacitor
SHA Input from Op Amp; Matching Resistors Improve
SNR Performance
OVERVIEW OF INPUT AND REFERENCE
CONNECTIONS
The overall input span of the AD9226 is equal to the potential
at the VREF pin. The VREF potential may be obtained from
the internal AD9226 reference or an external source (see
Reference Operation section).
In differential applications, the center point of the span is
obtained by the common-mode level of the signals. In single-
ended applications, the center point is the dc potential applied
to one input pin while the signal is applied to the opposite input
pin. Figures 5a–5f show various system configurations.
DRIVING THE ANALOG INPUTS
The AD9226 has a very flexible input structure allowing it to
interface with single-ended or differential input interface circuitry.
The optimum mode of operation, analog input range, and asso-
ciated interface circuitry will be determined by the particular
applications performance requirements as well as power sup-
ply options.
DIFFERENTIAL DRIVER CIRCUITS
Differential operation requires that VINA and VINB be simulta-
neously driven with two equal signals that are 180ⴗ out of phase
with each other.
Differential modes of operation (ac- or dc-coupled input) provide
the best THD and SFDR performance over a wide frequency
range. They should be considered for the most demanding
spectral-based applications (e.g., direct IF conversion to digital).
REV. B
AD9226
–15–
10F
VINA
VREF
AD9226
VINB
0.5V
SENSE
REFCOM 0.1F
10F0.1F
0.1F
15pF
1.5V
33⍀
33⍀
1V
0.1F
CAPT
CAPB
Figure 5a. 1 V Single-Ended Input, Common-Mode
Voltage = 1 V
10F
VINA
VREF
AD9226
VINB
0.75V
SENSE
0.1F
10F0.1F
0.1F
15pF
1.25V
33⍀
33⍀
1V
0.1F
49.9⍀
1.25V
0.75V
CAPB
CAPT
Figure 5b. 1 V Differential Input, Common-Mode
Voltage = 1 V
10F
VINA
VREF
AD9226
VINB
1.5V
SENSE
0.1F
10F0.1F
0.1F
15pF
2.5V
33⍀
33⍀
2V
0.1F
49.9⍀
2.5V
1.5V
CAPT
CAPB
Figure 5c. 2 V Differential Input, Common-Mode
Voltage = 2 V
10F
VINA
VREF
AD9226
VINB
1.0V
SENSE
REFCOM 0.1F
10F0.1F
0.1F
15pF
3.0V
33⍀
33⍀
2V
0.1F
CAPT
CAPB
Figure 5d. 2 V Single-Ended Input, Common-Mode
Voltage = 2 V
10F
VINA
VREF
AD9226
(LQFP)
VINB
2.0V
SENSE
0.1F
10F0.1F
0.1F
15pF
3.0V
33⍀
33⍀
2V
0.1F
49.9⍀
3.0V
2.0V
2.5V
2.5V
CMLEVEL
0.1F
2.5V
CAPB
CAPT
Figure 5e. 2 V Differential Input, Common-Mode
Voltage = 2.5 V
10F
VINA
VREF
AD9226
VINB
2.0V
SENSE
0.1F
10F0.1F
0.1F
15pF
2.75V
33⍀
33⍀
1V
0.1F
49.9⍀
2.75V
2.25V
2.5V
2.5V
CAPT
CAPB
0.1F
2.5V
AVDD
10k⍀10k⍀
Figure 5f. 1 V Differential Input, Common-Mode
Voltage = 2.5 V (Recommended for IF Undersampling)
The differential input characterization for this data sheet was
performed using the configuration shown in Figure 7.
Since not all applications have a signal preconditioned for
differential operation, there is often a need to perform a single-
ended-to-differential conversion. In systems that do not need to
be dc-coupled, an RF transformer with a center tap is the best
method to generate differential inputs for the AD9226. It pro-
vides all the benefits of operating the ADC in the differential
mode without contributing additional noise or distortion. An RF
transformer also has the added benefit of providing electrical
isolation between the signal source and the ADC. An improvement
in THD and SFDR performance can be realized by operating
the AD9226 in the differential mode. The performance enhance-
ment between the differential and single-ended mode is most
noteworthy as the input frequency approaches and goes beyond
the Nyquist frequency (i.e., f
IN
> F
S
/2).
The circuit shown in Figure 6a is an ideal method of applying
a differential dc drive to the AD9226. It uses an AD8138 to
derive a differential signal from a single-ended one. Figure 6b
illustrates its performance.
Figure 7 presents the schematic of the suggested transformer
circuit. The circuit uses a Minicircuits RF transformer, model
T1-1T, which has an impedance ratio of four (turns ratio of 2).
The schematic assumes that the signal source has a 50 Ω source
impedance. The center tap of the transformer provides a con-
venient means of level-shifting the input signal to a desired
common-mode voltage. In Figure 7 the transformer centertap
is connected to a resistor divider at the midsupply voltage.
REV. B
AD9226
–16–
1V p-p
VINA
CAPB
AD9226
0.1F
1k⍀
49.9⍀
499⍀
499⍀
499⍀
0.1F
10F
0.1F
CAPT
0.1F
450⍀
VINB
AD8138
10F
AVDD
0.1F
10F
5V
0.1F
1k⍀
0V
Figure 6a. Direct-Coupled Drive Circuit with AD8138
Differential Op Amp
0
–20
–40
–60
–80
–100
–120
048121620242832
MHz
SNR = 66.9dBc
SFDR = 70.0dBc
dBc
Figure 6b. FS = 65 MSPS, f
IN
= 30 MHz, Input Span = 1 V p-p
The same midsupply potential may be obtained from the
CMLEVEL pin of the AD9226 in the LQFP package.
Referring to Figure 7, a series resistor, R
S
, is inserted between the
AD9226 and the secondary of the transformer. The value of
33 ohm was selected to specifically optimize both the THD and
SNR performance of the ADC. R
S
and the internal capacitance
help provide a low-pass filter to block high-frequency noise.
Transformers with other turns ratios may also be selected to
optimize the performance of a given application. For example, a
given input signal source or amplifier may realize an improve-
ment in distortion performance at reduced output power levels
and signal swings. By selecting a transformer with a higher
impedance ratio (e.g., Minicircuits T16-6T with a 1:16 imped-
ance ratio), the signal level is effectively “stepped up” thus
further reducing the driving requirements of signal source.
VINA
VINB
AD9226
49.9⍀
RS
33⍀
MINICIRCUITS
T1-1T
0.1F
RS
33⍀
0.1F
10F0.1F
0.1F
CAPB
CAPT
15pF
1k⍀
1k⍀
AVDD
Figure 7. Transformer-Coupled Input
SINGLE-ENDED DRIVER CIRCUITS
The AD9226 can be configured for single-ended operation using
dc- or ac-coupling. In either case, the input of the ADC must be
driven from an operational amplifier that will not degrade the
ADC’s performance. Because the ADC operates from a single
supply, it will be necessary to level-shift ground-based bipolar
signals to comply with its input requirements. Both dc- and
ac-coupling provide this necessary function, but each method
results in different interface issues which may influence the
system design and performance.
Single-ended operation requires that VINA be ac- or dc-coupled
to the input signal source, while VINB of the AD9226 be biased
to the appropriate voltage corresponding to the middle of the input
span. The single-ended specifications for the AD9226 are char-
acterized using Figure 9a circuitry with input spans of 1 V and
2 V. The common-mode level is 2.5 V.
If the analog inputs exceed the supply limits, internal parasitic
diodes will turn on. This will result in transient currents within
the device. Figure 8 shows a simple means of clamping an input.
It uses a series resistor and two diodes. An optional capacitor is
shown for ac-coupled applications. A larger series resistor can
be used to limit the fault current through D1 and D2. This
can cause a degradation in overall performance. A similar
clamping circuit can also be used for each input if a differen-
tial input signal is being applied. A better method to ensure
the input is not overdriven is to use amplifiers powered by a single
5 V supply such as the AD8138.
AVDD
AD9226
R
S1
30⍀
V
CC
V
EE
OPTIONAL
AC-COUPLING
CAPACITOR
D2
D1
R
S2
20⍀
Figure 8. Simple Clamping Circuit
AC-COUPLING AND INTERFACE ISSUES
For applications where ac-coupling is appropriate, the op amp
output can be easily level-shifted by means of a coupling
capacitor. This has the advantage of allowing the op amp’s com-
mon-mode level to be symmetrically biased to its midsupply
level (i.e., (AVDD/2). Op amps that operate symmetrically with
respect to their power supplies typically provide the best ac
performance as well as greatest input/output span. Various high-
speed performance amplifiers that are restricted to +5 V/–5 V
operation and/or specified for 5 V single-supply operation can be
easily configured for the 2 V or 1 V input span of the AD9226.
Simple AC Interface
Figure 9a shows a typical example of an ac-coupled, single-
ended configuration of the SSOP package. The bias voltage
shifts the bipolar, ground-referenced input signal to approxi-
mately AVDD/2. The capacitors, C1 and C2, are 0.1 µF ceramic
and 10 µF tantalum capacitors in parallel to achieve a low
cutoff frequency while maintaining a low impedance over a
wide frequency range. The combination of the capacitor and the
resistor form a high-pass network with a high-pass –3 dB fre-
quency determined by the equation,
f
–3 dB
= 1/(2 × π × R × (C1 + C2))
REV. B
AD9226
–17–
The low-impedance VREF output can be used to provide dc
bias levels to the fixed VINB pin and the signal on VINA. Fig-
ure 9b shows the VREF configured for 2.0 V, thus the input
range of the ADC is 1.0 V to 3.0 V. Other input ranges could
be selected by changing VREF.
When the inputs are biased from the reference (Figure 9b),
there may be a slight degeneration of dynamic performance. A
midsupply output level is available at the CM LEVEL pin of the
LQFP package.
10F
VINA
VINB
AD9226
VIN
VREF
15pF
0.1F
10F0.1F
0.1F
R
0.1F
10F
RS
RS
C1
10F
CAPB
CAPT
RR
+5V
–5V
C2
0.1F
R
0.1F
VV
+1V
–1V
0V
3.5
1.5
2.5
Figure 9a. AC-Coupled Input Configuration
10F
VINA
VINB
AD9226
V
IN
VREF
15pF
0.1F
10F0.1F
0.1F
1k⍀
1k⍀
0.1F10F
0.1F
R
S
R
S
10F
0.1F
CAPB
CAPT
Figure 9b. Alternate AC-Coupled Input Configuration
–84
–83
–82
–81
–80
–79
–78
–77
–76
5.0
dBc
Volts
4.54.03.53.02.52.01.51.00.50
Figure 10. THD vs. Common-Mode Voltage
(2 V Differential Input Span, f
IN
= 10 MHz)
Figure 10 illustrates the relation between common-mode voltage
and THD. Note that optimal performance occurs when the
reference voltage is set to 2.0 V (input span = 2.0 V).
DC-COUPLING AND INTERFACE ISSUES
Many applications require the analog input signal to be dc-coupled
to the AD9226. An operational amplifier can be configured to
rescale and level-shift the input signal to make it compatible
with the selected input range of the ADC.
The selected input range of the AD9226 should be considered
with the headroom requirements of the particular op amp to
prevent clipping of the signal. Many of the new high-performance
op amps are specified for only ±5 V operation and have limited
input/output swing capabilities. Also, since the output of a dual
supply amplifier can swing below absolute minimum (–0.3 V),
clamping its output should be considered in some applications
(see Figure 8). When single-ended, dc-coupling is needed, the
use of the AD8138 in a differential configuration (Figure 9a) is
highly recommended.
Simple Op Amp Buffer
In the simplest case, the input signal to the AD9226 will already
be biased at levels in accordance with the selected input range. It
is necessary to provide an adequately low source impedance for
the VINA and VINB analog pins of the ADC.
REFERENCE OPERATION
The AD9226 contains an on-board bandgap reference that
provides a pin-strappable option to generate either a 1 V or
2 V output. With the addition of two external resistors, the user
can generate reference voltages between 1 V and 2 V. See
Figures 5a-5f for a summary of the pin-strapping options for the
AD9226 reference configurations. Another alternative is to use
an external reference for designs requiring enhanced accuracy
and/or drift performance described later in this section.
Figure 11a shows a simplified model of the internal voltage refer-
ence of the AD9226. A reference amplifier buffers a 1 V fixed
reference. The output from the reference amplifier, A1, appears
on the VREF pin. The voltage on the VREF pin determines
the full-scale input span of the ADC. This input span equals,
Full-Scale Input Span = VREF
The voltage appearing at the VREF pin, and the state of the
internal reference amplifier, A1, are determined by the voltage
appearing at the SENSE pin. The logic circuitry contains com-
parators that monitor the voltage at the SENSE pin. If the
SENSE pin is tied to AVSS, the switch is connected to the
internal resistor network thus providing a VREF of 2.0 V. If the
SENSE pin is tied to the VREF pin via a short or resistor, the
switch will connect to the SENSE pin. This connection will pro-
vide a VREF of 1.0 V. An external resistor network will provide
an alternative VREF between 1.0 V and 2.0 V (see Figure 12).
Another comparator controls internal circuitry that will disable
the reference amplifier if the SENSE pin is tied to AVDD.
Disabling the reference amplifier allows the VREF pin to be
driven by an external voltage reference.
REV. B
AD9226
–18–
A2
LOGIC
A1
DISABLE
A1
1V
TO
A/D
AD9226
CAPT
CAPB
VREF
SENSE
REFCOM
2.5V
Figure 11a. Equivalent Reference Circuit
0.1F10F
0.1F
0.1F
CAPT
CAPB
AD9226
VREF
0.1F10F
Figure 11b. CAPT and CAPB DC-Coupling
The actual reference voltages used by the internal circuitry of the
AD9226 appear on the CAPT and CAPB pins. The voltages
on these pins are symmetrical about the analog supply. For
proper operation when using an internal or external reference, it
is necessary to add a capacitor network to decouple these pins.
Figure 11b shows the recommended decoupling network. The
turn-on time of the reference voltage appearing between CAPT
and CAPB is approximately 10 ms and should be evaluated in
any power-down mode of operation.
USING THE INTERNAL REFERENCE
The AD9226 can be easily configured for either a 1 V p-p input
span or 2 V p-p input span by setting the internal reference.
Other input spans can be realized with two external gain-
setting resistors as shown in Figure 12 of this data sheet, or
using an external reference.
Pin Programmable Reference
By shorting the VREF pin directly to the SENSE pin, the inter-
nal reference amplifier is placed in a unity-gain mode and the
resultant VREF output is 1 V. By shorting the SENSE pin
directly to the REFCOM pin, the internal reference amplifier is
configured for a gain of 2.0 and the resultant VREF output is
2.0 V. The VREF pin should be bypassed to the REFCOM pin
with a 10 µF tantalum capacitor in parallel with a low-inductance
0.1 µF ceramic capacitor as shown in Figure 11b.
Resistor Programmable Reference
Figure 12 shows an example of how to generate a reference
voltage other than 1.0 V or 2.0 V with the addition of two exter-
nal resistors. Use the equation,
VREF = 1 V × (1 + R1/R2)
to determine appropriate values for R1 and R2. These resistors
should be in the 2 kΩ to 10 kΩ range. For the example shown,
R1 equals 2.5 kΩ and R2 equals 5 kΩ. From the equation above,
the resultant reference voltage on the VREF pin is 1.5 V. This
sets the input span to be 1.5 V p-p. The midscale voltage can
also be set to VREF by connecting VINB to VREF. Alterna-
tively, the midscale voltage can be set to 2.5 V by connecting
VINB to a low-impedance 2.5 V source as shown in Figure 12.
VINA
VREF
AD9226
VINB
1.75V
SENSE
REFCOM 0.1F
10F0.1F
0.1F
15pF
3.25V 33⍀
33⍀1.5V
0.1F
CAPT
2.5V
10F
R1
2.5k⍀
R2
5k⍀
CAPB
Figure 12. Resistor Programmable Reference (1.5 V p-p
Input Span, Differential Input V
CM
= 2.5 V)
USING AN EXTERNAL REFERENCE
The AD9226 contains an internal reference buffer, A2 (see
Figure 11b), that simplifies the drive requirements of an external
reference. The external reference must be able to drive about
5kΩ (±20%) load. Note that the bandwidth of the reference
buffer is deliberately left small to minimize the reference noise
contribution. As a result, it is not possible to rapidly change the
reference voltage in this mode.
Figure 13 shows an example of an external reference driving
both VINB and VREF. In this case, both the common-mode
voltage and input span are directly dependent on the value of
VREF. Both the input span and the center of the input span are
equal to the external VREF. Thus the valid input range extends
from (VREF + VREF/2) to (VREF – VREF/2). For example,
if the REF191, a 2.048 V external reference, is selected, the
input span extends to 2.048 V. In this case, 1 LSB of the AD9226
corresponds to 0.5 mV. It is essential that a minimum of a 10 µF
capacitor, in parallel with a 0.1 µF low-inductance ceramic
capacitor, decouple the reference output to ground.
To use an external reference, the SENSE pin must be connected
to AVDD. This connection will disable the internal reference.
VINA
VREF
AD9226
VINB
SENSE 0.1F
10F0.1F
0.1F
15pF
VINA+VREF/2 33⍀
33⍀
0.1F
CAPT
CAPB
VINB–VREF/2
10F
VREF
0.1F
5V
5V
Figure 13. Using an External Reference
REV. B
AD9226
–19–
MODE CONTROLS
Clock Stabilizer
The clock stabilizer is a circuit that desensitizes the ADC from
clock duty cycle variations. The AD9226 eases system clock
constraints by incorporating a circuit that restores the internal duty
cycle to 50%, independent of the input duty cycle. Low jitter on
the rising edge (sampling edge) of the clock is preserved while
the noncritical falling edge is generated on-chip.
It may be desirable to disable the clock stabilizer, and may be
necessary when the clock frequency speed is varied or completely
stopped. Once the clock frequency is changed, over 100 clock
cycles may be required for the clock stabilizer to settle to a dif-
ferent speed. When the stabilizer is disabled, the internal switching
will be directly affected by the clock state. If the external clock is
high, the SHA will be in hold. If the clock pulse is low, the SHA
will be in track. TPC 16 shows the benefits of using the clock
stabilizer. See Tables I and III.
Data Format Select (DFS)
The AD9226 may be set for binary or two’s complement data
output formats. See Tables I and II.
SSOP Package
The SSOP mode control (Pin 22) has two functions. It enables/
disables the clock stabilizer and determines the output data format.
The exact functions of the mode pin are outlined in Table I.
Table I. Mode Select (SSOP)
Mode DFS Clock Duty Cycle Shaping
DNC Binary Clock Stabilizer Disabled
AVDD Binary Clock Stabilizer Enabled
GND Two’s Complement Clock Stabilizer Enabled
10 kΩTwo’s Complement Clock Stabilizer Disabled
Resistor To GND
LQFP Package
Pin 35 of the LQFP package determines the output data format
(DFS). If it is connected to AVSS, the output word will be straight
binary. If it is connected to AVDD, the output data format will
be two’s complement. See Table II.
Pin 43 of the LQFP package controls the clock stabilizer function
of the AD9226. If the pin is connected to AVSS, both clock
edges will be used in the conversion architecture. When Pin 43
is connected to AVDD, the internal duty cycle will be determined
by the clock stabilizer function within the ADC. See Table III.
Table II. DFS Pin Controls
DFS Function Pin 35 Connection
Straight Binary AVSS
Two’s Complement AVDD
Table III. Clock Stabilizer Pin
Clock Restore Function Pin 43 Connection
Clock Stabilizer Enabled AVDD
Clock Stabilizer Disabled AVSS
DIGITAL INPUTS AND OUTPUTS
Digital Outputs
Table IV details the relationship among the ADC input, OTR, and
straight binary output.
Table IV. Output Data Format
Two’s
Binary Complement
Input (V) Condition (V) Output Mode Mode OTR
VINA–VINB < – VREF 0000 0000 0000 1000 0000 0000 1
VINA–VINB = – VREF 0000 0000 0000 1000 0000 0000 0
VINA–VINB = 0 1000 0000 0000 0000 0000 0000 0
VINA–VINB = + VREF – 1 LSB 1111 1111 1111 0111 1111 1111 0
VINA–VINB ≥ + VREF 1111 1111 1111 0111 1111 1111 1
Out of Range (OTR)
An out-of-range condition exists when the analog input voltage
is beyond the input range of the converter. OTR is a digital
output that is updated along with the data output corresponding
to the particular sampled analog input voltage. Hence, OTR has
the same pipeline delay (latency) as the digital data. It is LOW
when the analog input voltage is within the analog input range.
It is HIGH when the analog input voltage exceeds the input
range as shown in Figure 14. OTR will remain HIGH until the
analog input returns within the input range and another conversion
is completed. By logical ANDing OTR with the MSB and its
complement, overrange high or underrange low conditions can be
detected. Table V is a truth table for the over/underrange
circuit in Figure 15, which uses NAND gates. Systems requiring
programmable gain conditioning of the AD9226 input signal
can immediately detect an out-of-range condition, thus elimi-
nating gain selection iterations. Also, OTR can be used for
digital offset and gain calibration.
Table V. Out-of-Range Truth Table
OTR MSB Analog Input Is
0 0 In Range
0 1 In Range
1 0 Underrange
1 1 Overrange
1111 1111 1111
1111 1111 1111
1111 1111 1110
OTR
–FS +FS
–FS +1/2 LSB
+FS – 1/2 LSB–FS – 1/2 LSB
+FS – 1 1/2 LSB
0000 0000 0001
0000 0000 0000
0000 0000 0000
1
0
0
0
0
1
OTR DATA OUTPUTS
Figure 14. OTR Relation to Input Voltage and Output Data
OVER = 1
UNDER = 1
MSB
OTR
MSB
Figure 15. Overrange or Underrange Logic
REV. B
AD9226
–20–
Digital Output Driver Considerations
The AD9226 output drivers can be configured to interface with
5 V or 3.3 V logic families by setting DRVDD to 5 V or 3.3 V
respectively. The output drivers are sized to provide sufficient
output current to drive a wide variety of logic families. However,
large drive currents tend to cause glitches on the supplies and may
affect converter performance. Applications requiring the ADC to
drive large capacitive loads or large fan outs may require external
buffers or latches.
OEB Function (Three-State)
The LQFP-packaged AD9226 has Three-State (OEB) ability. If
the OEB pin is held low, the output data drivers are enabled. If
the OEB pin is high, the output data drivers are placed in a high
impedance state. It is not intended for rapid access to buss.
Clock Input Considerations
High-speed, high-resolution ADCs are sensitive to the quality of
the clock input. The clock input should be treated as an analog
signal in cases where aperture jitter may affect the dynamic
performance of the AD9226. Power supplies for clock drivers
should be separated from the ADC output driver supplies to
avoid modulating the clock signal with digital noise. Low-jitter
crystal controlled oscillators make the best clock sources.
The quality of the clock input, particularly the rising edge, is
critical in realizing the best possible jitter performance of the
part. Faster rising edges often have less jitter.
Clock Input and Power Dissipation
Most of the power dissipated by the AD9226 is from the analog
power supplies. However, lower clock speeds will reduce digital
current. Figure 16 shows the relationship between power and
clock rate.
SAMPLE RATE – Msps
515
POWER DISSIPATION – mW
250
200
25 35
300
350
400
450
500
550
600
45 55 65 75
DRVDD = 3V
DRVDD = 5V
Figure 16. Power Consumption vs. Sample Rate
GROUNDING AND DECOUPLING
Analog and Digital Grounding
Proper grounding is essential in any high-speed, high-resolution
system. Multilayer printed circuit boards (PCBs) are recom-
mended to provide optimal grounding and power schemes. The
use of ground and power planes offers distinct advantages:
1. The minimization of the loop area encompassed by a signal
and its return path.
2. The minimization of the impedance associated with ground
and power paths.
3. The inherent distributed capacitor formed by the power
plane, PCB insulation, and ground plane.
It is important to design a layout that prevents noise from cou-
pling onto the input signal. Digital signals should not be run in
parallel with input signal traces and should be routed away from
the input circuitry. While the AD9226 features separate analog
and driver ground pins, it should be treated as an analog com-
ponent. The AVSS and DRVSS pins must be joined together
directly under the AD9226. A solid ground plane under the
ADC is acceptable if the power and ground return currents are
carefully managed.
0.1F
AVDD
AVSS
AD9226
10F
Figure 17. Analog Supply Decoupling
Analog and Digital Driver Supply Decoupling
The AD9226 features separate analog and digital supply and
ground pins, helping to minimize digital corruption of sensitive
analog signals. In general, AVDD (analog power) should be
decoupled to AVSS (analog ground). The AVDD and AVSS
pins are adjacent to one another. Also, DRVDD (digital power)
should be decoupled to DRVDD (digital ground). The decoupling
capacitors (especially 0.1 µF) should be located as close to the
pins as possible. Figure 17 shows the recommended decoupling
for the pair of analog supplies; 0.1 µF ceramic chip and 10 µF
tantalum capacitors should provide adequately low impedance
over a wide frequency range.
0.1F
CML
AD9226
0.1F
VR
Figure 18. CML Decoupling (LQFP)
Bias Decoupling
The CML and VR are analog bias points used internally by the
AD9226. These pins must be decoupled with at least a 0.1 µF
capacitor as shown in Figure 18. The dc level of CML is approxi-
mately AVDD/2. This voltage should be buffered if it is to be
used for any external biasing. CML and VR outputs are only
available in the LQFP package.
0.1F
DRVDD
DRVSS
AD9226
10F
Figure 19. Digital Supply Decoupling
CML
The LQFP-packaged AD9226 has a midsupply reference point.
This midsupply point is used within the internal architecture of
the AD9226 and must be decoupled with a 0.1 µF capacitor. It
will source or sink a load of up to 300 µA. If more current is
required, it should be buffered with a high impedance amplifier.
REV. B
AD9226
–21–
VR
VR is an internal bias point on the LQFP package. It must be
decoupled to ground with a 0.1 µF capacitor.
The digital activity on the AD9226 chip falls into two general
categories: correction logic and output drivers. The internal
correction logic draws relatively small surges of current, mainly
during the clock transitions. The output drivers draw large
current impulses while the output bits are changing. The size
and duration of these currents are a function of the load on the
output bits: large capacitive loads are to be avoided.
For the digital decoupling shown in Figure 19, 0.1 µF ceramic
chip and 10 µF tantalum capacitors are appropriate. Reason-
able capacitive loads on the data pins are less than 20 pF per
bit. Applications involving greater digital loads should consider
increasing the digital decoupling proportionally and/or using
external buffers/latches.
A complete decoupling scheme will also include large tantalum
or electrolytic capacitors on the power supply connector to
reduce low-frequency ripple to negligible levels.
EVALUATION BOARD AND TYPICAL BENCH
CHARACTERIZATION TEST SETUP
The AD9226 evaluation board is configured to operate upon
applying both power and the analog and clock input signals. It
provides three possible analog input interfaces to characterize
the AD9226’s ac and dc performance. For ac characterization, it
provides a transformer coupled input with the common-mode
input voltage (CMV) set to AVDD/2. Note, the evaluation
board is shipped with a transformer coupled interface and a 2 V
input span. For differential dc coupled applications, the evalua-
tion board has provisions to be driven by the AD8138 amplifier.
If a single-ended input is desired, it may be driven through the
S3 connector. The various input signal options are accessible by
the jumper connections. Refer to the Evaluation Board schematic.
The clock input signal to the AD9226 evaluation board can be
applied to one of two inputs, CLOCK and AUXCLK. The
CLOCK input should be selected if the frequency of the input
clock signal is at the target sample rate of the AD9226. The
input clock signal is ac-coupled and level-shifted to the switch-
ing threshold of a 74VHC02 clock driver. The AUXCLK input
should be selected in applications requiring the lowest jitter and
SNR performance (i.e., IF Undersampling characterization). It
allows the user to apply a clock input signal that is 4× the target
sample rate of the AD9226. A low-jitter, differential divide-by-4
counter, the MC100EL33D, provides a 1× clock output that is
subsequently returned back to the CLOCK input via JP7. For
example, a 260 MHz signal (sinusoid) will be divided down to
a 65 MHz signal for clocking the ADC. Note, R1 must be
removed with the AUXCLK interface. Lower jitter is often
achieved with this interface since many RF signal generators
display improved phase noise at higher output frequencies and
the slew rate of the sinusoidal output signal is 4× that of a 1×
signal of equal amplitude.
Figure 20 shows the bench characterization setup used to evalu-
ate the AD9226’s ac performance for many of the data sheet
characterization curves. Signal and Clock RF generators A and
B are high-frequency, “very” low-phase noise frequency sources.
These generators should be phase locked by sharing the same
10 MHz REF signal (located on the instruments back panel) to
allow for nonwindowed, coherent FFTs. Also, the AUXCLK
option on the AD9226 evaluation board should be used to
achieve the best SNR performance. Since the distortion and
broadband noise of an RF generator can often be a limiting
factor in measuring the true performance of an ADC, a high Q
passive bandpass filter should be inserted between the generator
and AD9226 evaluation board.
5V5V 3V 3V
AVDD GND GND DUT
DVDD
DVDDDUT
AVDD
DSP
EQUIPMENT
S4
INPUT
xFMR
S1
INPUT
CLOCK
AD9226
EVALUATION BOARD
1MHz
BANDPASS FILTER
SIGNAL SYNTHESIZER
65(OR 260MHz), 4V p-p
HP8644 OUTPUT
WORD
(P1)
S4
AUX CLOCK
(ⴜ4)
REFIN
CLK SYNTHESIZER
65(OR 260MHz), 4V p-p
HP8644
10MHz
REFOUT
Figure 20. Evaluation Board Connections
REV. B
AD9226
–22–
U1
11
12
13
16
17
18
19
27
26
25
20
21
24
28
D20
D30
D40
D50
D60
D70
D80
D90
D100
D110
D120
D130
OTR0
47
46
45
42
41
40
39
4
1
2
38
37
36
3
D10
48
9
8
10 D00
44
7
43
35
15
14
JP2
JP1
JP6
AVDD
C2
0.1F
R42
1k⍀
R6
1k⍀
R10
1k⍀
DUTCLK
WHT
TP6
C40
0.001F
C37
0.1F
29
23
22
31
34
30
C3
10F
10V
33
5
6
32
C41
0.001F
C38
0.1F
C23
10F
10V
DUTAVDD
VINA
VINB
SHEET 3
C50
0.1F
C33
0.1F
C20
10F
10V
C32
0.1F
C34
0.1F
C39
0.001F
C36
0.1F
C1
10F
10V
DUTAVDD
JP22JP23
JP25
JP24
C35
0.1F
C21
10F
10V
R4
10k⍀
R3
10k⍀
TP5
WHT
OTR
MSB-B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
LSB-B14
NC3
OEB
VR
DUTY
CLK
NC4
DRVDD2
DRVSS2
DFS
AVDD1
AVDD2
AVSS1
AVSS2
SENSE
VREF
REFCOM
CAPB1
CAPB2
CAPT1
CAPT2
CML
VINA
VINB
NC1
NC2
AVSS3
AVSS4
AVDD3
AVDD4
DRVSS3
DRVDD3
DRVDD1
DRVSS1
DUTDRVDD
AD9226LQFP
NC = NO CONNECT
C59
0.1F
C58
22F
25V
2TB1
3TB1AGND
FBEAD
2
L1
1
TP2
RED
DUTAVDDDUTAVDDIN
C53
0.1F
C48
22F
25V
5TB1
4TB1AGND
FBEAD
2
L3
1
TP3
RED
DUTDRVDDDRVDDIN
C52
0.1F
C47
22F
25V
1TB1
FBEAD
2
L2
1
TP1
RED
AVDD
AVDDIN
C14
0.1F
C6
22F
25V
6TB1
FBEAD
2
L4
1
TP4
RED
DVDD
DVDDIN
TP11
BLK
TP12
BLK
TP13
BLK TP14
BLK
Figure 21. AD9226 Evaluation Board
REV. B
AD9226
–23–
U7
20
VCC
17
Y2
10
GND
18
Y1
G1
16
Y3
15
Y4
14
Y5
13
Y6
12
Y7
11
Y8
19
G2
2
D5
A1
3
D4
A2
4
D3
A3
5
D2
A4
6
D1
A5
7
D0
A6
8
OTR
A7
9
A8
1
10F
1
10V
2C5
C11
0.1F
74VHC541
U6
20
VCC
17
Y2
10
GND
18
Y1
G1
16
Y3
15
Y4
14
Y5
13
Y6
12
Y7
11
Y8
19
G2
2
D13
A1
3
D12
A2
4
D11
A3
5
D10
A4
6
D9
A5
7
D8
A6
8
D7
A7
9
A8
1
10F
1
10V
2C4
C12
0.1F
74VHC541
D6
DVDD
RP1
22⍀
116
RP1
22⍀
413
RP1
22⍀
314
RP1
22⍀
215
RP1
22⍀
512
RP1
22⍀
611
RP1
22⍀
710
RP1
22⍀
89
1P1
3P1
5P1
7P1
9P1
11 P1
13 P1
15 P1
2P1
4P1
6P1
8P1
10P1
12P1
14P1
16P1
RP2
22⍀
116 17 P1 18P1
RP2
22⍀
215 19 P1 20P1
RP2
22⍀
314 21 P1 22P1
RP2
22⍀
413 23 P1 24P1
RP2
22⍀
512 25 P1 26P1
RP2
22⍀
611 27 P1 28P1
29 P1 30P1
31 P1 32P1
RP2
22⍀
89 33 P1 34P1
35 P1 36P1
37 P1 38P1
RP2
22⍀
710 39 P1 40P1
R9
22⍀
JP4
JP3
21 8c
74VHC04
1011 8b
74VHC04
R7
22⍀DUTCLK
1213 8a
74VHC04
TP7
JP17 1
2
AB
3
C13
0.10F
R1
49.9⍀
R19
4k⍀
R2
5k⍀
R18
4k⍀AVDD
JP7
R15
90⍀
R13
113⍀C19
0.1F
AVDD
R14
90⍀
R12
113⍀
C17
0.1F
AVDD
U3
1
NC
2
INA
3
INB
4
INCOM
8
AVDD
VCC
7
OUT
6
REF
5
VEE
T2
1
2
3
6
5
4
T1–1T
2
2
D2
D1
1N5712
1N5712
R11
49.9⍀
CLOCK
S1
2
1
2
1
AUXCLK
S5
MC100EL33D
WHT
NC = NO CONNECT
C18
0.1F
C26
10F
10V
U3
DECOUPLING
AVDD
C10
0.1F
C3
10F
10V
U8
DECOUPLING
AVDD
8
98d
74VHC04
65 8e
74VHC04
4
38f
74VHC04
Figure 22. AD9226 Evaluation Board
REV. B
AD9226
–24–
1
2
JP5
C9
0.33F
R5
49.9⍀
SINGLE
INPUT
S3
R41
1k⍀
R40
1k⍀
C7
0.1F
AVDD
2
1
8
U2
6
AD8138
5
VDC
VO–
VOⴙ
VCC
VEE
ⴙW
–W
3
4
R37
499⍀
R36
499⍀
R34
523⍀
R35
499⍀
AMP INPUT
S2 1
2R31
49.9⍀
C69
0.1F
C15
10F
10V
21
AVDD
R33
10k⍀
R32
10k⍀
AVDD
C8
0.1F
JP42
JP40
JP45 R21
22⍀
C44
TBD
VINA
JP46
JP41
JP43
R22
22⍀
C43
TBD
VINB
C24
50pF SHEET 1
T2
1
2
3
6
5
4
T1–1T
R24
49.9⍀
1
2
XFMR INPUT
S4
DUTAVDD
R38
1k⍀
C25
0.33F
C16
0.1F
R8
1k⍀RP6
22⍀8
1D3D30 RP6
22⍀7
2D2D20
RP6
22⍀6
3D1
D10
RP6
22⍀5
4D0D00
RP5
22⍀8
1D6D60 RP5
22⍀7
2D5D50
RP5
22⍀6
3D4
D40
RP5
22⍀5
4
RP4
22⍀8
1D10D100 RP4
22⍀7
2D9D90
RP4
22⍀6
3D8
D80
RP4
22⍀5
4D7D70
RP3
22⍀8
1OTROTRO RP3
22⍀7
2D13D130
RP3
22⍀6
3D12
D120
RP3
22⍀5
4D11D110
Figure 23. AD9226 Evaluation Board
Figure 24. Evaluation Board Component Side Layout (Not to Scale)
REV. B
AD9226
–25–
Figure 25. Evaluation Board Solder Side Layout (Not to Scale)
Figure 26. Evaluation Board Power Plane
REV. B
AD9226
–26–
Figure 27. Evaluation Board Ground Plane
Figure 28. Evaluation Board Component Side (Not to Scale)
REV. B
AD9226
–27–
Figure 29. Evaluation Board Solder Side (Not to Scale)
REV. B
–28–
AD9226
C01027–0–3/01(B)
PRINTED IN U.S.A.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Shrink Small Outline
(RS-28)
0.009 (0.229)
0.005 (0.127)
0.03 (0.762)
0.022 (0.558)
8°
0°
0.008 (0.203)
0.002 (0.050)
0.07 (1.79)
0.066 (1.67)
0.078 (1.98)
0.068 (1.73)
0.015 (0.38)
0.010 (0.25) SEATING
PLANE
0.0256
(0.65)
BSC
0.311 (7.9)
0.301 (7.64)
0.212 (5.38)
0.205 (5.21)
28 15
141
0.407 (10.34)
0.397 (10.08)
PIN 1
48-Lead Thin Plastic Quad Flatpack
(ST-48)
TOP VIEW
(PINS DOWN)
1
12
13
25
24
36
37
48
0.019 (0.5)
BSC
0.276
(7.00)
BSC
SQ
0.011 (0.27)
0.006 (0.17)
0.354 (9.00) BSC SQ
0.063 (1.60)
MAX
0.030 (0.75)
0.018 (0.45)
0.008 (0.2)
0.004 (0.09)
0ⴗ
MIN
COPLANARITY
0.003 (0.08)
SEATING
PLANE
0.006 (0.15)
0.002
(
0.05
)
7ⴗ
0ⴗ
0.057 (1.45)
0.053 (1.35)
