68HC912DG128CPV8 - Freescale Semiconductor, Inc.

M68HC12

Microcontrollers

MC68HC912DG128/D

Rev. 3, 10/2002

MC68HC912DG128

Technical Data

Freescale Semiconductor, I

Freescale Semiconductor, Inc.

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Freescale Semiconductor, I

Freescale Semiconductor, Inc.

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MC68HC912DG128 — Rev 3.0 Technical Data

MC68HC912DG128

Technical Data — Rev 3.0

Freescale Semiconductor, I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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Technical Data MC68HC912DG128 — Rev 3.0

Freescale Semiconductor, I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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MC68HC912DG128 — Rev 3.0 Technic al Data
List of Paragraphs
 
Technical Data — MC68HC912DG128
List of Paragraphs
List of Par a graphs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
List of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Section  1. General Descrip t ion . . . . . . . . . . . . . . . . . . . .23
Section 2. Centra l Processing Unit . . . . . . . . . . . . . . . . .29
Section 3. Pinout and Signal Descriptions. . . . . . . . . . .37
Section 4. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Section 5. Operating Modes. . . . . . . . . . . . . . . . . . . . . . .75
Section 6. Bus Control and Input/Output . . . . . . . . . . . .95
Section 7. Flash Memory . . . . . . . . . . . . . . . . . . . . . . . .107
Section 8. EEPROM Memory . . . . . . . . . . . . . . . . . . . . .125
Section 9. Resets  and Interrupts. . . . . . . . . . . . . . . . . .133
Section 10. I/O  Ports with Key Wake-up . . . . . . . . . . . .147
Section  11. Clock Functions . . . . . . . . . . . .  . . . . . . . . .155
Section 12. Pulse Width Modulator . . . . . . . . . . . . . . . .191
Section  13. Enhanced Capture Timer . . . . . . . . . . . . . .207
Section 14. Multiple Serial Interface . . . . . . . . . . . . . . .249
Section 15. Int er-IC Bus . . . . . . . . . . . . . . . . . . . . . . . . .273
Section 16. Analog-to-Digital Converter . . . . . . . . . . . .297
    
  
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List of Paragraphs

Technical Data MC68HC912DG128 — Rev 3.0

List of Paragraphs

Section 17. MSCAN Controller. . . . . . . . . . . . . . . . . . . .311

Section 18. Development Support. . . . . . . . . . . . . . . . .355

Section 19. Electr ical Specifications. . . . . . . . . . . . . . .385

Section 20. Appendix: CGM Practical Aspects . . . . . .407

Section 21. Appendix: MC68HC912DG128A Flash . . .419

Section 22. Appendix: MC68HC912DG128A EEPROM 427

Section 23. Revision History . . . . . . . . . . . . . . . . . . . . .439

Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .441

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MC68HC912DG128 — Rev 3.0 Technic al Data
Table of Contents
 
Technical Data — MC68HC912DG128
Table of Contents
List of Paragraphs
Table of Contents
List of Figures
List of Tables
Section 1. General Description
1.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.4 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1.5 MC68HC912DG128 Block Diagram. . . . . . . . . . . . . . . . . . . . .28
Section 2. Central Processing Unit
2.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.3 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.4 Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.5 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.6 Indexed Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . .34
2.7 Opcodes and Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
    
  
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Table of Contents
Technical Data MC68HC912DG128 — Rev 3.0
Table of Conten ts
Section 3. Pinout and Signal Descriptions
3.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.2 Pin Assignments in 112-pin QFP . . . . . . . . . . . . . . . . . . . . . . .37
3.3 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
3.4 Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
3.5 Port Signals  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Section 4. Regist ers
4.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
4.2 Register Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Section 5. Operating Modes
5.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
5.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
5.3 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
5.4 Background Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
5.5 Internal Resource Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . .81
5.6 Memory Maps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Section 6. Bus Control and Input/Output
6.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
6.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
6.3 Detecting Access Type from External Signals . . . . . . . . . . . . .95
6.4 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Section 7. Flash Memory
7.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
7.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
    
  
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Table of Contents
 
7.3 Future Flash EEPROM Support . . . . . . . . . . . . . . . . . . . . . . .108
7.4 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
7.5 Flash EEPROM Control Block . . . . . . . . . . . . . . . . . . . . . . . .109
7.6 Flash EEPROM Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
7.7 Flash EEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .1 10
7.8 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 15
7.9 Programming the Flash EEPROM . . . . . . . . . . . . . . . . . . . . .118
7.10 Erasing the Flash EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . .120
7.11 Program/Erase Protection Interlocks . . . . . . . . . . . . . . . . . . .1 22
7.12 Stop or Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
7.13 Test Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
Section 8. EEPROM Memory
8.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
8.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
8.3 Future EEPROM Support. . . . . . . . . . . . . . . . . . . . . . . . . . . .126
8.4 EEP ROM Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . .127
8.5 EEPROM Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . .128
Section 9. Resets and Interrupts
9.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
9.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
9.3 Maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
9.4 Latching of Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
9.5 Interrupt Control and Priority Registers  . . . . . . . . . . . . . . . . .137
9.6 Interrupt test registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 38
9.7 Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
    
  
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Table of Contents
Technical Data MC68HC912DG128 — Rev 3.0
Table of Contents
9.8 Effects of Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
9.9 Register Stacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
9.10 Important User Information. . . . . . . . . . . . . . . . . . . . . . . . . . .145
Section 10. I/O Ports with Key Wake-up
10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
10.3 Key Wake-up and Port Registers . . . . . . . . . . . . . . . . . . . . . .148
10.4 Key Wake-Up Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
Section 11. Clock Functions
11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
11.3 Clock Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
11.4 Phase-Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . .157
11.5 Acquisition and Tracking Modes. . . . . . . . . . . . . . . . . . . . . . .159
11.6 Limp-Home and Fast STOP Recovery modes. . . . . . . . . . . .161
11.7 System Clock Frequency formulas. . . . . . . . . . . . . . . . . . . . .179
11.8 Clock Divider Chains  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
11.9 Computer Operating Properly (COP) . . . . . . . . . . . . . . . . . . .184
11.10 Real-Time Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
11.11 Clock Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
11.12 Clock Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
Section 12. Pulse Width Modulator
12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
    
  
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12.3 PWM Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . .195
12.4 PWM Boundary Cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
Section 13. Enhanced Capture Timer
13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
13.3 Enhanced Capture Timer Modes of Operation. . . . . . . . . . . .214
13.4 Timer Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217
13.5 Timer and Modulus Counter Operation in Different Modes . .247
Section 14. Multiple Serial Interface
14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
14.3 Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250
14.4 Serial Communication Interface (SCI) . . . . . . . . . . . . . . . . . .2 50
14.5 Serial Peripheral Interface (SPI). . . . . . . . . . . . . . . . . . . . . . .262
14.6 Port S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271
Section 15. Inter-IC Bus
15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273
15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273
15.3 IIC Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274
15.4 IIC System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . .276
15.5 IIC Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .276
15.6 IIC Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . .281
15.7 IIC Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . .290
    
  
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Table of Contents
Technical Data MC68HC912DG128 — Rev 3.0
Table of Contents
Section 16. Analog-to-Digital  Converter
16.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297
16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297
16.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298
16.4 ATD Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299
16.5 ATD Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .310
Section 17. MSCAN Controller
17.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311
17.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311
17.3 External Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312
17.4 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313
17.5 Identifier Acceptance Filter. . . . . . . . . . . . . . . . . . . . . . . . . . .318
17.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322
17.7 Protocol Violation Protection. . . . . . . . . . . . . . . . . . . . . . . . . .324
17.8 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325
17.9 Timer Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
17.10 Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
17.11 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332
17.12 Programmer’s Model of Message Storage. . . . . . . . . . . . . . .332
17.13 Programmer’s Model of Control Registers . . . . . . . . . . . . . . .338
Section 18. Development Support
18.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355
18.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355
18.3 Instruction Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355
18.4 Background Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .357
    
  
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18.5 Breakpoints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375
18.6 Instruction Tagging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382
Section 19. Electr ical Specifications
19.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .385
19.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .385
19.3 Tables of Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 86
Section 20. Appendix: CGM Practical Aspects
20.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .407
20.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .407
20.3 A Few Hints For The CGM Crystal Oscillator Application. . . .407
20.4 Practical Aspects For The PLL Usage . . . . . . . . . . . . . . . . . .4 10
20.5 Printed Circuit Board Guidelines. . . . . . . . . . . . . . . . . . . . . . .415
Section 21. Appendix: MC68HC912DG128A Flash
21.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .419
21.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .419
21.3 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .420
21.4 Flash EEPROM Control Block . . . . . . . . . . . . . . . . . . . . . . . .420
21.5 Flash EEPROM Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .420
21.6 Flash EEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .421
21.7 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 23
21.8 Programming the Flash EEPROM . . . . . . . . . . . . . . . . . . . . .424
21.9 Erasing the Flash EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . .425
21.10 Stop or Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .425
    
  
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Table of Contents
Technical Data MC68HC912DG128 — Rev 3.0
Table of Contents
Section 22. Appendix: MC68HC912DG128A EEPROM
22.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .427
22.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .427
22.3 EEPROM Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . .428
22.4 EEPROM Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . .430
22.5 Program/Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .436
22.6 Shadow Word Mapping  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .436
22.7 Programming EEDIVH and EEDIVL Registers. . . . . . . . . . . .437
Section 23. Revision Histor y
Glossary
    
  
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List of Figures
 
Technical Data — MC68HC912DG128
List of Figures
Figure Title Page
2-1 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
3-1 MC68HC912D G128 Pi n Assignments in 112-pin QFP. . . . . . .38
3-2 112-pin QFP Mechanical Dimensions (case no987)  . . . . . . . .39
3-3 PLL Loop FIlter Connections . . . . . . . . . . . . . . . . . . . . . . . . . .41
3-4 Common Crystal Connections . . . . . . . . . . . . . . . . . . . . . . . . .43
3-5 External Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . .43
5-1 Memory Map after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
5-2 Memory Paging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
6-1 Access Type vsBus Control Pins . . . . . . . . . . . . . . . . . . . . . . .96
7-1 Program Sequence Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
7-2 Erase Sequence Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
10-1 STOP Key Wake-up Filter  . . . . . . . . . . . . . . . . . . . . . . . . . . .153
11-1 Internal Clock Relationships. . . . . . . . . . . . . . . . . . . . . . . . . .157
11-2 PLL Functional Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
11-3 Clock Loss during Normal Operation . . . . . . . . . . . . . . . . . . .162
11-4 No Clock at Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . .164
11-5 STOP Exit and Fast STOP Recovery. . . . . . . . . . . . . . . . . . .167
11-6 Clock Generation Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
11-7 Clock Chain for SCI0, SCI1, RTI, COP. . . . . . . . . . . . . . . . . .181
11-8 Clock Chain for ECT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
11-9 Clock Chain for MSCAN, SPI, ATD0, ATD1 and BDM. . . . . .1 83
12-1 Block Diagram of PWM Left-Aligned Output Channel . . . . . .192
12-2 Block Diagram of PWM Center-Al i gned Output Channe l . . . .193
12-3 PWM Clock Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
13-1 Timer Block Diagram in Latch Mode. . . . . . . . . . . . . . . . . . . .209
13-2 Timer Block Diagram in Queue Mode. . . . . . . . . . . . . . . . . . .210
13-3 8-Bit Pulse Accumulators Block Diagram. . . . . . . . . . . . . . . .211
13-4 16-Bit Pulse Accumulators Block Diagram. . . . . . . . . . . . . . .212
    
  
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List of Figures
Technical Data MC68HC912DG128 — Rev 3.0
List of Figures
13-5 Block Diagram for Port7 with Output compare / Pulse 
Accumulator A  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
13-6 C3F-C0F Interrupt Flag Setting  . . . . . . . . . . . . . . . . . . . . . . .213
14-1 Multiple Serial Interface Block Diagram . . . . . . . . . . . . . . . . .250
14-2 Serial Communications Interface Block Diagram . . . . . . . . . .251
14-3 Serial Peripheral Interface Block Diagram . . . . . . . . . . . . . . .263
14-4 SPI Clock Format 0 (CPHA = 0). . . . . . . . . . . . . . . . . . . . . . .264
14-5 SPI Clock Format 1 (CPHA = 1). . . . . . . . . . . . . . . . . . . . . . .265
14-6 Normal Mode and Bidirectional Mode. . . . . . . . . . . . . . . . . . .266
15-1 IIC Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275
15-2 IIC Transmission Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . .276
15-3 IIC Clock Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . .2 80
15-4 Flow-Chart of Typical IIC Interrupt Routine  . . . . . . . . . . . . . .295
16-1 Analog-to-Digital Converter Block Diagram . . . . . . . . . . . . . .298
17-1 The CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313
17-2 User Model for Message Buffer Organization. . . . . . . . . . . . .3 16
17-3 32-bit Maskable Identifier Acceptance Filters. . . . . . . . . . . . .3 20
17-4 16-bit Maskable Acceptance Filters . . . . . . . . . . . . . . . . . . . .320
17-5 8-bit Maskable Acceptance Filters . . . . . . . . . . . . . . . . . . . . .321
17-6 SLEEP Request / Acknowledge Cycle . . . . . . . . . . . . . . . . . .327
17-7 Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
17-8 Segments within the Bit Time. . . . . . . . . . . . . . . . . . . . . . . . .331
17-9 CAN Standard Compliant Bit Time Segment Settings . . . . . .331
17-10 msCAN12 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332
17-11 Message Buffer Organization. . . . . . . . . . . . . . . . . . . . . . . . .333
17-12 Receive/Transmit Message Buffer Extended Identifier. . . . . .334
17-13 Standard Identifier Mapping . . . . . . . . . . . . . . . . . . . . . . . . . .335
17-14 Identifier Acceptance Registers (1st bank). . . . . . . . . . . . . . .351
17-15 Identifier Acceptance Registers (2nd bank) . . . . . . . . . . . . . .351
17-16 Identifier Mask Registers (1st bank). . . . . . . . . . . . . . . . . . . .352
17-17 Identifier Mask Registers (2nd bank) . . . . . . . . . . . . . . . . . . .352
18-1 BDM Host to Target Serial Bit Timing. . . . . . . . . . . . . . . . . . .359
18-2 BDM Target to Host Serial Bit Timing (Logic 1) . . . . . . . . . . .3 59
18-3 BDM Target to Host Serial Bit Timing (Logic 0) . . . . . . . . . . .3 60
19-1 VFP Conditioning Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393
19-2 VFP Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .394
19-3 Timer Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395
19-4 POR and External Reset Timing Diagram . . . . . . . . . . . . . . .396
    
  
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List of Figures
 
19-5 STOP Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . .397
19-6 WAIT Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . .398
19-7 Interrupt Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .399
19-8 Port Read Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .400
19-9 Port Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .400
19-10 Multiplexed Expansion Bus Timing Diagram . . . . . . . . . . . . .402
A) SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . .404
B) SPI Master Timing (CPHA = 1) . . . . . . . . . . . . . . . . . . . . .404
19-11 SPI Timing Diagram (1 of 2). . . . . . . . . . . . . . . . . . . . . . . . . .404
19-11 A) SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . .405
19-11 B) SPI Slave Timing (CPHA = 1) . . . . . . . . . . . . . . . . . . . . . .405
19-12 SPI Timing Diagram (2 of 2). . . . . . . . . . . . . . . . . . . . . . . . . .405
    
  
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List of Figures

Technical Data MC68HC912DG128 — Rev 3.0

List of Figures

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MC68HC912DG128 — Rev 3.0 Technic al Data
List of Tables
 
Technical Data — MC68HC912DG128
List of Tab les
Table Title Page
1-1 Device Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . .27
1-2 Development Tools Ordering Information. . . . . . . . . . . . . . . . .27
2-1 M68HC12 Addressing Mode Summary . . . . . . . . . . . . . . . . . .32
2-2 M68HC12 Addressing Mode Summary . . . . . . . . . . . . . . . . . .33
2-3 Summary of Indexed Operations . . . . . . . . . . . . . . . . . . . . . . .34
3-1 Power and Ground Connection Summary . . . . . . . . . . . . . . . .42
3-2 Signal Description Summary  . . . . . . . . . . . . . . . . . . . . . . . . . .49
3-3 Port Description Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
3-4 Port Pull-Up, Pull-Down and Reduced Drive Summary . . . . . .60
4-1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
5-1 Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
5-2 Mapping Precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
5-3 Program space Page Index . . . . . . . . . . . . . . . . . . . . . . . . . . .86
5-4 Flash Register space Page Index. . . . . . . . . . . . . . . . . . . . . . .86
5-5 Test mode program space Page Index. . . . . . . . . . . . . . . . . . .87
5-6 RFSTR Stretch Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . .90
5-7 EXSTR Stretch Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . .91
7-1 Effects of ENPE, LAT and ERAS on Array Reads . . . . . . . . .114
8-1 2K byte EEPROM Block Protection . . . . . . . . . . . . . . . . . . . .129
8-2 Erase Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 31
9-1 Interrupt Vector Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
9-2 Stacking Order on Entry to Interrupts. . . . . . . . . . . . . . . . . . .144
11-1 Summary of STOP Mode Exit Conditions. . . . . . . . . . . . . . . .172
11-2 Summary of Pseudo STOP Mode Exit Conditions . . . . . . . . .173
11-3 Clock Monitor Time-Outs . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
11-4 Real Time Interrupt Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . .186
11-5 COP Watchdog Rates  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
12-1 Clock A and Clock B Prescaler. . . . . . . . . . . . . . . . . . . . . . . .196
12-2 PWM Left-Aligned Boundary Conditions  . . . . . . . . . . . . . . . .206
    
  
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List of Tables
Technical Data MC68HC912DG128 — Rev 3.0
List of Tables
12-3 PWM Center-Aligned Boundary Conditions . . . . . . . . . . . . . .206
13-1 Compare Result Output Action. . . . . . . . . . . . . . . . . . . . . . . .222
13-2 Edge Detector Circuit Configuration. . . . . . . . . . . . . . . . . . . .223
13-3 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
14-1 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 52
14-2 Loop Mode Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 55
14-3 SS Output Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265
14-4 SPI Clock Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . .269
15-1 IIC Tap and Prescale Values . . . . . . . . . . . . . . . . . . . . . . . . .282
15-2 IIC Divider and SDA Hold values . . . . . . . . . . . . . . . . . . . . . .283
16-1 ATD Response to Background Debug Enable . . . . . . . . . . . .301
16-2 Final Sample Time Selection . . . . . . . . . . . . . . . . . . . . . . . . .302
16-3 Clock Prescaler Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303
16-4 Multichannel Mode Result Register Assignment . . . . . . . . . .305
17-1 msCAN12 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . .324
17-2 msCAN12 vsCPU operating modes . . . . . . . . . . . . . . . . . . . .325
17-3 Data length codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336
17-4 Synchronization jump width . . . . . . . . . . . . . . . . . . . . . . . . . .341
17-5 Baud rate prescaler  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 41
17-6 Time segment syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .342
17-7 Time segment values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .342
17-8 Identifier Acceptance Mode Settings . . . . . . . . . . . . . . . . . . .349
17-9 Identifier Acceptance Hit Indication  . . . . . . . . . . . . . . . . . . . .349
18-1 IPIPE Decoding  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .356
18-2 Hardware Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362
18-3 BDM Firmware Commands  . . . . . . . . . . . . . . . . . . . . . . . . . .363
18-4 BDM registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .366
18-5 TTAGO Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .371
18-6 TTAGO Value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .371
18-7 Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .371
18-8 REGN Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .371
18-9 Breakpoint Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . .378
18-10 Breakpoint Address Range Control . . . . . . . . . . . . . . . . . . . .379
18-11 Breakpoint Read/Write Control. . . . . . . . . . . . . . . . . . . . . . . .380
18-12 Tag Pin Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .383
19-1 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .386
19-2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .386
19-3 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .387
    
  
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List of Tables
 
19-4 Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .389
19-5 ATD DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . .389
19-6 Analog Converter Characteristics (Operating) . . . . . . . . . . . .390
19-7 ATD AC Characteristics (Operating). . . . . . . . . . . . . . . . . . . .391
19-8 ATD Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .391
19-9 EEPROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .392
19-10 Flash EEPROM Characteristics . . . . . . . . . . . . . . . . . . . . . . .392
19-11 Pulse Width Modulator Characteristics. . . . . . . . . . . . . . . . . .394
19-12 Control Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395
19-13 Peripheral Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400
19-14 Multiplexed Expansion Bus Timing. . . . . . . . . . . . . . . . . . . . .401
19-15 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .403
19-16 CGM Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .406
19-17 Key Wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .406
19-18 msCAN12 Wake-up Time from Sleep Mode. . . . . . . . . . . . . .406
20-1 Suggested 8MHz Synthesis PLL Filter Elements 
(Tracking Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .413
20-2 Suggested 8MHz Synthesis PLL Filter Elements 
(Acquisition Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .414
22-1 EEDIV Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .431
22-2 2K byte EEPROM Block Protection . . . . . . . . . . . . . . . . . . . .433
22-3 Erase Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .434
22-4 Shadow word mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .436
    
  
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List of Tables

Technical Data MC68HC912DG128 — Rev 3.0

List of Tables

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MC68HC912DG128 — Rev 3.0 Technic al Data

General Description

Technical Data — MC68HC912DG128

Section 1. General Descriptio n

1.1 Contents

1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

1.4 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

1.5 MC68HC912DG128 Block Diagram. . . . . . . . . . . . . . . . . . . . .28

1.2 Introduction

The MC68HC912DG128 mic rocontroller unit (MCU) is a 16-bit device

composed of standard on-chip peripherals including a 16-bit central

processing unit (CPU12), 128K b ytes of flash EEPROM , 8K bytes of

RAM, 2K byte s of EEPROM , two asyn chron ous ser i al comm un i cati o n

interfaces (SCI), a serial peripheral interface (SPI), an inter-IC interface

(I2C), an enhanced capture timer (ECT), two 8-channel,10-bit analog-to-

digital converte rs (ATD), a four-channel pulse-width modulator (PWM),

and two CAN 2.0 A, B software com pa ti ble mo dules (MSCAN 12 ) .

System resource mapping, clock generation, interrupt control and bus

interfacing are managed by the lite integration module (LIM). The

MC68 HC912 DG128 has fu ll 16-bit da ta paths th rougho ut, howeve r, the

external bus can operate in an 8-bit narrow mode so single 8-bit wide

memory can be interfaced for lower cost systems. The inclusion of a PLL

circuit allows power consumption and performance to be adjusted to suit

operationa l requirements. In a ddition to the I/O ports available in each

module, 16 I/O port pins are available with Key-Wake-Up capability from

STOP or WAIT mode.

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General Description

Technical Data MC68HC912DG128 — Rev 3.0

General Description

1.3 Features

•16-bit CPU12

–Upward compa tible with M68HC11 instruction set

–Interrupt stacking and programmer’s model iden tical to

M68HC11

–20-bit ALU

–Instruction queue

–Enhanced indexed addressing

•Multiplexe d bus

–Single chi p or expan ded

–16 address/16 data wide or 16 address/8 data narrow mode

•Memory

–128K byte flash EEPROM, made of four 32K byte modules

with 8K bytes protecte d BOOT secti on in each modul e

–2K byte EEPROM

–8K byte RAM, made of two 4K byte modules with Vstby in each

module.

•Analog-t o-digital converters

–2 times x 8-channels, 10-bit resolution

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General Description

Features

MC68HC912DG128 — Rev 3.0 Technic al Data

General Description

•1M bit per second, CAN 2.0 A, B software compatible modules,

two on the MC68HC912DG128, each with:

–Two receiv e an d three tr ansm i t buff ers

–Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or

8x8bit

–Four separate interrupt channels for Rx, Tx, error and wake-up

–Low-pass fi l ter wake - up fun cti on

–Loop-back for self test operation

–Programmable link to a timer input capture channel, fo r time-

stamping and network synchronization.

•Enhanced capture timer (ECT)

–16-bit main counter with 7-bit presca ler

–8 prog ra m mabl e i npu t ca ptu re or output com pa re channel s; 4

of the 8 input captures with buffer

–Input cap ture filt ers and b uffers, th ree successive ca ptures o n

four chann els, or two cap tur es on fou r channe l s wit h a

capture/compare selectable on the remaining four

–Four 8-bit or two 16-bit pulse accumulators

–16-bit modulus down-counter with 4-bit prescaler

–Four user-selectable delay co unters for signal filtering

•4 PWM channels with programmable period and duty cycle

–8-bit 4-channel or 16-bit 2-channel

–Separate control for each pulse width and duty cycle

–Center- or left-aligned outputs

–Prog rammable clock select logic with a wide range of

frequencies

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General Description

Technical Data MC68HC912DG128 — Rev 3.0

General Description

•Serial interfaces

–Two asynchronous serial communications interfaces (SCI)

–Inter IC bus interface (I2C)

–Synchronous serial peripheral interface (SPI)

•LIM (lite integration module)

–WCR (windowed COP watchdog, real time interrupt, clock

monitor)

–ROC (reset and clocks)

–MEBI (multip lexed external bus interface)

–MBI (internal bus interface and memory map)

–INT (interrupt control)

•Two 8-bit ports with key wake-up interrupt

•Clock gen er at io n

–Phase-locked loop clock frequency multiplier

–Limp home mode in absence of external clock

–Slow mode divider

–Low power 0.5 to 16 MHz crystal oscillator reference clock

•112-Pin TQFP package

–Up to 66 general-purpose I/O lines, plus up to 18 input-only

lines

•8MHz operat ion at 5V

•Developme nt supp ort

–Sing le-wire backg round debug™ mode (BDM)

–On-chip hardware breakpoints

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General Description

Ordering Information

MC68HC912DG128 — Rev 3.0 Technic al Data

General Description

1.4 Ordering Information

* Important: M temperatu re oper ation is avai l ab l e only for single chip modes

NOTE: SDBUG12 is a P & E Micro Product. It can be obtained from P & E from

their web site (http://www.pemicro.com) for ap proximately $100.

Third party tools: http://www.mcu.motsps.com/dev_tools/3rd/index.htm

Table 1-1. Device Ordering Information

Package Temperature Voltage Frequency Order Number

Range Designator

112-Pin TQFP

Single Tray

60 Pcs

0 to +70°C

4.5V–5.5V 8 MHz

68HC912DG128PV8

–40 to +85°C C 68HC912DG128CPV8

–40 to +105°C V 68HC912DG128VPV8

–40 to +125°C M* 68HC912DG128MPV8

Table 1-2. Development Tools Ordering Information

Description Name Order Number

MCUez Free from World Wide Web

Serial Debug Interface SDI M68SDIL (3 –5V), M68DIL12 (SDIL + MCUez +

SDBUG12)

Evaluation board EVB M68EVB912DG128 (EVB only)

M68KIT912DG128 (EVB + SDIL12)

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General Description

Technical Data MC68HC912DG128 — Rev 3.0

General Description

1.5 MC68HC912DG128 Block Diagram

TxCAN1

DDRH

PORTH

KWH4

KWH3

KWH2

KWH1

KWH0

KWH7

KWH6

KWH5 PH4

PH3

PH2

PH1

PH0

PH7

PH6

PH5

DDRJ

PORTJ

PJ4

PJ3

PJ2

PJ1

PJ0

PJ7

PJ6

PJ5

KWJ4

KWJ3

KWJ2

KWJ1

KWJ0

KWJ7

KWJ6

KWJ5

IOC0

IOC1

IOC2

IOC3

IOC4

IOC5

IOC6

IOC7

DDRT

PORT T

128K byte flash EEPROM

8K byte RAM

PORT E

Enhanced

PT0

PT1

PT2

PT3

PT4

PT5

PT6

PT7

SPI

DDRS

PORT S

PORT AD 1

PE1

PE2

PE4

PE5

PE6

PE3

PAD13

PAD14

PAD15

PAD16

PAD17

VDDA

VSSA

VRH1

VRL1

PAD10

PAD11

PAD12

RESET

EXTAL

XTAL

PW0

PW1

PW2

PW3

PWM

DDRP

PORT P

PP0

PP1

PP2

PP3

VDD ×2

VSS ×2

SCI0 RxD0

TxD0

RxD1

TxD1

SDI/MISO

SDO/MOSI

SCK

PS0

PS1

PS2

PS3

PS4

PS5

PS6

PS7

2K byte EEPROM

PE0

PE7

AN13

AN14

AN15

AN16

AN17

VDDA

VSSA

VRH1

VRL1

AN10

AN11

AN12

BKGD

ECLK

R/W

LSTRB

MODA

MODB

XIRQ

DBE/CAL

capture

timer

Lite

IRQ

PIB5

PIB4

SCI1

integration

module

(LIM)

VFP

CPU12

Periodic interrupt

COP watchdog

Clock monitor

Single-wire

background

debug module Breakpoints

PLL

VSSPLL

XFC

VDDPLL

CAN1 RxCAN1

DDRA

PORT A

DDRB

PORT B

PA4

PA3

PA2

PA1

PA0

PA7

PA6

PA5

PB4

PB3

PB2

PB1

PB0

PB7

PB6

PB5

DATA15

Multiplexed Address/Data Bus

ADDR15

ADDR14

ADDR13

ADDR12

ADDR11

ADDR10

ADDR9

ADDR8

DATA14

DATA13

DATA12

DATA11

DATA10

DATA9

DATA8

ADDR7

ADDR6

ADDR5

ADDR4

ADDR3

ADDR2

ADDR1

ADDR0

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

ATD1

PORT AD 0

PAD03

PAD04

PAD05

PAD06

PAD07

VRH0

VRL0

PAD00

PAD01

PAD02

AN03

AN04

AN05

AN06

AN07

VDDA

VSSA

VRH0

VRL0

AN00

AN01

AN02

ATD0

PPAGE

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

Wide

bus

Narrow bus

VDDX ×2

VSSX ×2

Power for internal circuitry

Power for I/ O driv e r s

PK0

PK1

PK2

PK3

VSTBY

IIC SCL

SDA PIB7

PIB6

DDRK

PORT K

PIX0

PIX1

PIX2

ECS

DDRIB

PORTIB

KWU

Clock

Generation

module

I/O

PK7

I/O

TxCAN0

CAN0 RxCAN0

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MC68HC912DG128 — Rev 3.0 Technic al Data
Central Processing Unit
 
Technical Data — MC68HC912DG128
Section 2. Central Processing Unit
2.1  Contents
2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.3 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.4 Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.5 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.6 Indexed Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . .34
2.7 Opcodes and Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.2  Introduction
The CPU1 2 is a high-speed, 16-bit processing  unit. It has full 16-bit data 
paths and wider internal registers (up to 20 bits) for high-speed extended 
math instructions. The instruction set is a proper superset of the 
M68HC11instruction set. The CPU12 allows instructions with odd byte 
counts, including many single-byte instructions. This provides efficient 
use of ROM space. An instruction queue buffers program information so 
the CPU always has immediate access to at least three bytes of machine 
code at the start of every instruction. The CPU12 also offers an 
extensive set of indexed addressing capabilities.
2.3  Programming Model
CPU12 r egist ers are a n integr al par t of the C PU a nd are no t addr essed 
as if they were memory locations.
    
  
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Central Processing Unit

Technical Data MC68HC912DG128 — Rev 3.0

Central Processing Unit

Figure 2-1. Programming Model

Accumulators A and B are general-purpose 8-bit accumulators used to

hold operands and results of arithmetic calculations or data

manipulations. Some instructions treat the combination of these tw o 8-

bit accumulators as a 16-bit double accumulator (accumulator D).

Index regist er s X and Y are used for indexed addressing mode. In the

indexed addressing mode, the contents of a 16-bit index register are

added to 5-bit, 9-bit, or 16-bit constants or the content of an accumulator

to form the effective address of the operand to be used in the instruction.

Stack pointer (SP) points to the last stack location used. The CPU12

supports an automatic program stack that is used to save system

contex t dur ing su br ou ti ne ca l ls an d inte rru pts, and can also be u sed for

temporary storage of data. The stack pointer can also be used in all

indexed addressing modes.

Program counter is a 16-bit register that holds the address of the next

instruction to be executed. The program counter can be used in all

indexed ad dress ing modes except autoincrement/decrement.

NSXHI ZVC

CONDITION CODE REGISTER

8-BIT ACCUMULATORS A & B

16-BIT DOUBLE ACCUMULATOR D

INDEX REGISTER X

INDEX REGISTER Y

STACK POINTER

PROGRAM COUNTER

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Central Processing Unit

Data Types

MC68HC912DG128 — Rev 3.0 Technic al Data

Central Processing Unit

Condition Code Register (CCR) contains five status indicators, two

interrupt masking bits, and a STOP disable bit. The five flags are half

carry (H), negative (N), zero (Z), overflow (V), and carry/borrow (C). The

half-carry fla g is used on l y for BCD arithmetic oper ations. The N, Z, V,

and C status bits al low for branchin g based on the results of a pr evious

operation.

After a reset, the CPU fetches a vector from the appropriate address and

begins executing instructions. The X and I interrupt mask bits are set to

mask any interrupt requests. The S bit is also set to inhibit the STOP

instruction.

2.4 Data Types

The CPU12 supports the following data types:

•Bit data

•8-bit and 16-bit signed and unsigned integers

•16-bit unsigned fr actions

•16-bit addr esses

A byte is eight bits wide and can be accessed at any byte location. A

word is composed of two consecutive bytes with the most significant

byte at the lower value address. There are no special requirements for

alignment of instructions or operands.

2.5 Addressing Modes

Addressing modes determine how the CPU accesses memory locations

to be operated upon. The CPU12 includes all of the addressing modes

of the M68HC11 CPU as well as several new forms of indexed

addressing. Table 2-1 is a summary of the available addressing modes.

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Central Processing Unit

Technical Data MC68HC912DG128 — Rev 3.0

Central Processing Unit

Table 2-1. M68HC12 Addressi ng Mode Summary

Addressing Mode Source Format Abbreviation Description

Inherent INST

(no externally supplied

operands) INH Operands (if any) are in CPU registers

Immediate INST #opr8i

INST #opr16i IMM Operand is included in instruction stream

8- or 16-bit size implied by context

Direct INST opr8a DIR Operand is the lower 8-bits of an address in the

range $0000 – $00FF

Extended INST opr16a EXT Operand is a 16-bit address

Relative INST rel8

INST rel16 REL An 8-bit or 16-bit relative offset from the current

pc is supplied in the instruction

Indexed

(5-bit offset) INST oprx5,xysp IDX 5-bit signed constant offset from x, y, sp, or pc

Indexed

(auto pre-decrement ) INST oprx3,–xys IDX Auto pre-decrement x, y, or sp by 1 ~ 8

Indexed

(aut o pre-increment) INST oprx3,+xys IDX Auto pre-increment x, y, or sp by 1 ~ 8

Indexed

(aut o post-

decrement) INST oprx3,xys–IDX Auto post-decrement x, y, or sp by 1 ~ 8

Indexed

(auto post-increment) INST oprx3,xys+IDX Auto post-increment x, y, or sp by 1 ~ 8

Indexed

(accumul ator offset) INST abd,xysp IDX Indexed with 8-bit (A or B) or 16-bit (D)

accumulator offset from x, y, sp, or pc

Indexed

(9-bit offset) INST oprx9,xysp IDX1 9-bit signed constant offset from x, y, sp, or pc

(lower 8-bits of offset in one extension byte)

Indexed

(16-bit offset) INST oprx16,xysp IDX2 16-bit constant offset from x, y, sp, or pc

(16-bit offset in two extension bytes)

Indexed-Indirect

(16-bit offset) INS T [oprx16,xysp][IDX2] Pointer to operand is found at...

16-bit constant offset from x, y, sp, or pc

(16-bit offset in two extension bytes)

Indexed-Indirect

(D accumulator

offset) INST [D,xysp][D,IDX] Pointer to operand is found at...

x, y, sp, or pc plus the value in D

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Central Processing Unit

Addressing Modes

MC68HC912DG128 — Rev 3.0 Technic al Data

Central Processing Unit

Table 2-2. M68HC12 Addressi ng Mode Summary

Addressing Mode Source Format Abbreviation Description

Inherent INST

(no externally

suppli ed operands) INH Operands (if any) are in CPU registers

Immediate INST #opr8i

INST #opr16i IMM Operand is included in instruction stream

8- or 16-bit size implied by context

Direct INST opr8a DIR Operand is the lower 8-bits of an address in

the range $0000 – $00FF

Extended INST opr16a EXT Operand is a 16-bit address

Relative INST rel8

INST rel16 REL An 8-bit or 16-bit relative offset from the

current pc is supplied in the instruction

Indexed

(5- bit offse t ) INST oprx5,xysp IDX 5-bit signed constant offset from x, y, sp, or

Indexed

(auto pre-decrement) INST oprx3,–xys IDX Auto pre-decrement x, y, or sp by 1 ~ 8

Indexed

(auto pre-increment) INST oprx3,+xys IDX Auto pre-increment x, y, or sp by 1 ~ 8

Indexed

(auto post-decrement) INST oprx3,xys–IDX Auto post-decrement x, y, or sp by 1 ~ 8

Indexed

(auto post-increm ent) INST oprx3,xys+IDX Auto post-increment x, y, or sp by 1 ~ 8

Indexed

(accumulat or offset) INST abd,xysp IDX Indexed with 8-bit (A or B) or 16-bit (D)

accumulator offset from x, y, sp, or pc

Indexed

(9- bit offse t ) INST oprx9,xysp IDX1 9-bit signed constant offset from x, y, sp, or

(lower 8-bits of offset in one extension byte)

Indexed

(16-bit offset) INST oprx16,xysp IDX2 16-bit constant offset from x, y, sp, or pc

(16-bit offset in two extension bytes)

Indexed-Indirect

(16-bit offset) INST [oprx16,xysp][IDX2] Pointer to operand is found at...

16-bit constant offset from x, y, sp, or pc

(16-bit offset in two extension bytes)

Indexed-Indirect

(D accumulator offset) INST [D,xysp][D,IDX] Pointer to operand is found at...

x, y, sp, or pc plus the value in D

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Central Processing Unit

Technical Data MC68HC912DG128 — Rev 3.0

Central Processing Unit

2.6 Indexed Addressing Modes

The CPU12 indexed modes reduce execution time and eliminate code

size penalties for using the Y index register. CPU1 2 indexed addressing

uses a postbyte plus zero, one, or two extension bytes after the

instruction opco de. The postb yte and exte nsion s do th e fo llow ing ta sks:

•Specify which index register is used.

•Determine whether a value in an accumulator is used as an offset.

•Enable automatic pre- or post-increment or dec rem ent

•Specify use of 5-bit, 9- bi t, or 16- bit signed offsets.

Table 2-3. Summary of Indexed Operations

Postbyte

Code (xb)

Source

Code

Syntax Comments

rr0nnnnn ,r

n,r

–n,r

5-bit constant offset n = –16 to +15

rr can specify X, Y, SP, or PC

111rr0zs n,r

–n,r

Constant offset (9- or 16-bit signed)

z-0 = 9-bit with sign in LSB of postbyte(s)

1 = 16-bit

if z = s = 1, 16-bit offset indexed-indirect (see below)

rr can specify X, Y, SP, or PC

111rr011 [n,r] 16-bit offset indexed-indirect

rr can specify X, Y, SP, or PC

rr1pnnnn n,–r n,+r

n,r– n,r+

Auto pre-decrement/increment or Auto post-

decrement/increment;

p = pre-(0) or post-(1), n = –8 to –1, +1 to +8

rr can specify X, Y, or SP (PC not a valid choice)

111rr1aa A,r

B,r

D,r

Accumulator offset (unsigned 8-bit or 16-bit)

aa-00 = A

01 = B

10 = D (16-bit)

11 = see accumulator D offset indexed-indirect

rr can specify X, Y, SP, or PC

111rr111 [D,r] Accumulator D offset indexed-indirect

rr can specify X, Y, SP, or PC

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Central Processing Unit

Opcodes and Operands

MC68HC912DG128 — Rev 3.0 Technic al Data

Central Processing Unit

2.7 Opcodes and Operands

The CPU12 uses 8-bit opcodes. Each opcode identifies a particular

instruction and associated addressing mode to the CPU. Several

opcodes are required to provide each instruction with a range of

addressing capabilities.

Only 256 opcodes would be available if the range of values were

restricted to the number that can be represented by 8-bit binary

numbers. To expand the number of opcodes, a second page is added to

the opcode map. Opcodes on the second page are preceded by an

additional byte with the value $18.

To provide additional addressing flexibility, opcodes can also be

follow ed by a po stbyte or exten sio n bytes. P ostbytes i mplem ent ce rtai n

forms of indexed addr essing, transfers, e xchanges, and loo p primitiv es.

Extension bytes contain additional program information such as

addre sses, offse ts, and immediat e data .

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Central Processing Unit

Technical Data MC68HC912DG128 — Rev 3.0

Central Processing Unit

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MC68HC912DG128 — Rev 3.0 Technic al Data
Pinout and Signal Descriptions
 
Technical Data — MC68HC912DG128
Section 3. Pinout and Signal Descriptions
3.1  Contents
3.2 Pin Assignments in 112-pin QFP . . . . . . . . . . . . . . . . . . . . . . .37
3.3 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
3.4 Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
3.5 Port Signals  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
3.2  Pin Assignments in 112-pin QFP
The MC68HC912DG128 is ava ilable in a 112 - pin thin quad flat pack 
(TQFP). Most pins perform two or more functions, as described in the 
Signal Descriptions. Figure 3-2 sh ows pin assign ments. In exp anded  
narrow modes the lower byte data is multiplexed with higher byte data 
through pins 57-64.
    
  
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Pinout and Signal Descriptions

Technical Data MC68HC912DG128 — Rev 3.0

Pinout and Signal Descriptions

Figure 3-1. MC68HC912DG128 Pin Assignments in 112-pin QFP

112

111

110

109

108

107

106

105

104

103

102

101

100

MC68HC912DG128

112TQFP

PAD17/AN17

PAD07/AN07

PAD16/AN16

PAD06/AN06

PAD15/AN15

PAD05/AN05

PAD14/AN14

PAD04/AN04

PAD13/AN13

PAD03/AN03

PAD12/AN12

PAD02/AN02

PAD11/AN11

PAD01/AN01

PAD10/AN10

PAD00/AN00

VRL0

VRH0

VSS

VDD

PA7/ADDR15/DATA15/DATA7

PA6/ADDR14/DATA14/DATA6

PA5/ADDR13/DATA13/DATA5

PA4/ADDR12/DATA12/DATA4

PA3/ADDR11/DATA11/DATA3

PA2/ADDR10/DATA10/DATA2

PA1/ADDR9/DATA9/DATA1

PA0/ADDR8/DATA8/DATA0

PP3/PW3

PK0/PIX0

PK1/PIX1

PK2/PIX2

PK7/ECS

DDX

SSX

RxCAN0

TxCAN0

RxCAN1

TxCAN1

PIB4

PIB5

PIB6/SDA

PIB7/SCL

PS7/SS

PS6/SCK

PS5/SDO/MOSI

PS4/SDI/MISO

PS3/TxD1

PS2/RxD1

PS1/TxD0

PS0/RxD0

SSA

RL1

RH1

DDA

PW2/PP2

PW1/PP1

PW0/PP0

IOC0/PT0

IOC1/PT1

IOC2/PT2

IOC3/PT3

KWJ7/PJ7

KWJ6/PJ6

KWJ5/PJ5

KWJ4/PJ4

VDD

PK3

VSS

IOC4/PT4

IOC5/PT5

IOC6/PT6

IOC7/PT7

KWJ3/PJ3

KWJ2/PJ2

KWJ1/PJ1

KWJ0/PJ0

SMODN/TAGHI/BKGD

ADDR0/DATA0/PB0

ADDR1/DATA1/PB1

ADDR2/DATA2/PB2

ADDR3/DATA3/PB3

ADDR4/DATA4/PB4

ADDR5/DATA5/PB5

ADDR6/DATA6/PB6

ADDR7/DATA7/PB7

KWH7/PH7

KWH6/PH6

KWH5/PH5

KWH4/PH4

DBE/CAL/PE7

MODB/IPIPE1/PE6

MODA/IPIPE0/PE5

ECLK/PE4

SSX

VSTBY

DDX

DDPLL

XFC

SSPLL

RESET

EXTAL

XTAL

KWH3/PH3

KWH2/PH2

KWH1/PH1

KWH0/PH0

LSTRB/TAGLO/PE3

R/W/PE2

IRQ/PE1

XIRQ/PE0

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Pinout and Signal Descriptions

Pin Assignments in 112-pin QFP

MC68HC912DG128 — Rev 3.0 Technic al Data

Pinout and Signal Descriptions

Figure 3-2. 112-pin QFP Mechanical Dimensions (case no. 987)

DIM

AMIN MAX

20.000 BSC

MILLIMETERS

A1 10.000 BSC

B20.000 BSC

B1 10.000 BSC

C--- 1.600

C1 0.050 0.150

C2 1.350 1.450

D0.270 0.370

E0.450 0.750

F0.270 0.330

G0.650 BSC

J0.090 0.170

K0.500 REF

P0.325 BSC

R1 0.100 0.200

R2 0.100 0.200

S22.000 BSC

S1 11.000 BSC

V22.000 BSC

V1 11.000 BSC

Y0.250 REF

Z1.000 REF

AA 0.090 0.160

θ11 °

11 °13 °

7 °

13 °

VIEW Y

L-M0.20 NT

4X 4X 28 TIPS

PIN 1

IDENT

112 85

28 57

29 56

VIEW AB

0.10

CC2

2θ

0.050

SEATING

PLANE

GAGE PLANE

1θ

VIEW AB

(Z)

(Y) E

(K)

R1 0.25

VIEW Y

108X

SECTION J1-J1

BASE

ROTATED 90 COUNTERCLOCKWISE

METAL

JAA

DL-M

0.13 NT

L-M0.20 NT

112X

X=L, M OR N

8 °

3 °

0 °

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. DIMENSIONS IN MILLIMETERS.

3. DATUMS L, M AND N TO BE DETERMINED AT

SEATING PLANE, DATUM T.

4. DIMENSIONS S AND V TO BE DETERMINED A T

SEATING PLANE, DATUM T.

5. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION. ALLOWABLE

PROTRUSION IS 0.25 PER SIDE. DIMENSIONS

A AND B INCLUDE MOLD MISMATCH.

6. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL NOT CAUSE THE D

DIMENSION TO EXCEED 0.46.

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Pinout and Signal Descriptions

Technical Data MC68HC912DG128 — Rev 3.0

Pinout and Signal Descriptions

3.3 Power Supply Pins

Power and ground pins are described below and summarized in Table

3-1.

3.3.1 Internal Power (VDD) and Ground (VSS)

Power is supplied to the MCU through VDD and VSS. Because fast signal

transitio ns place high , s hort-duration curren t demands on the powe r

supply, use bypass capacitors with high-frequency characteristics and

place them as close to the MCU as possible. Bypass requirements

depend on how heavily the MCU pins are loaded.

3.3.2 External Power (VDDX) and Ground (VSSX)

External power and ground for I/O drivers. Because fast signal

transitio ns place high , s hort-duration curren t demands on the powe r

supply, use bypass capacitors with high-frequency characteristics and

place them as close to the MCU as possible. Bypass requirements

depend on how heavily the MCU pins are loaded.

3.3.3 VDDA, VSSA

Prov ides operati ng volt age and grou nd for the ana l og- to - digi tal

converter. This allows the supply voltage to the ATD to be bypassed

independentl y. Connecting VDDA to VDD if the ATD modules are not

used will not result in an increase of po wer consumption.

3.3.4 Analog to Digital Reference Voltages (VRH, VRL)

VRH0, VRL0: reference voltage high and low for ATD converter 0.

VRH1, VRL1: reference voltage high and low for ATD converter 1.

If the ATD module s are no t used, l eaving VRH co nnected t o VDD will not

result in an increase of power consumption.

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Power Supply Pins

MC68HC912DG128 — Rev 3.0 Technic al Data

Pinout and Signal Descriptions

3.3.5 VDDPLL, VSSPLL

Provides operating voltage and ground for the Phase-Locked Loop. This

allows the supply voltage to the PLL to be bypassed independently.

NOTE: The VSSPLL pin should always be grounded even if the PLL is not used.

The VDDPLL pin should not be left floating. It is recommended to

connect the VDDPLL pin to ground if the PLL is not used.

3.3.6 XFC

PLL loop filt er. Pl ea se see Appendix: CGM Practical Aspects for

informatio n on how to calculate PLL loop filter elements. Any current

leakage on this pin must be avoided.

Figure 3-3. PLL Loop FIlter Connections

If VDDP LL is conn ecte d to VS S (t hi s is no rm a l case) , then the XFC pin

should either be left floating or connected to VSS (never to VDD). If

VDDPLL i s tied to VDD but the PLL is switch ed off (P LLON bi t cleared) ,

then th e XFC pin should be co nnected prefe rably to V DDPLL (i.e. ready

for VCO minimu m frequency).

3.3.7 VFP

Flash EEPROM program/erase voltage and supply voltage during

normal operation.

MCU

XFC

VDDPLL

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Technical Data MC68HC912DG128 — Rev 3.0

Pinout and Signal Descriptions

3.3.8 VSTBY

Stand-by voltage supply to static RAM. Used to maintain the contents of

RAM with minimal p owe r when the rest of the chip is powered down.

3.4 Signal Descriptions

3.4.1 Crystal Driver and External Clock Input (XTAL, EXTAL)

These pins provide the interface for either a crystal or a CMOS

compatible clock to control the internal clock generator circuitry. Out of

reset th e freque ncy app lied to EXTAL i s twic e the desired E–clock rate.

All the device clocks are derived from the EXTAL input frequency.

NOTE: CRYSTAL CIRCUIT IS CHANGED FROM STANDARD.

Table 3-1. Power and Ground Connection Summary

Mnemonic Pin N um b er Description

112-pin QFP

VDD 12, 65 Intern al powe r and ground.

VSS 14, 66

VDDX 42, 107 External power and ground, supply to pin drivers.

VSSX 40, 106

VDDA 85 Operating voltage and ground for the analog-to-digital converter, allows the

supply voltage to the A/D to be bypassed independently.

VSSA 88

VRH1 86 Reference voltages for the analog-to-digital converter 1

VRL1 87

VRH0 67 Reference voltages for the analog-to-digital converter 0.

VRL0 68

VDDPLL 43 Provides operating voltage and ground for the Phase-Locked Loop. This allows

the supply voltage to the PLL to be bypassed independently.

VSSPLL 45

VFP 97 Program/erase voltage for the Flash EEPROM and required supply for normal

operation.

VSTBY 41 Stand-by voltage supply to maintain the contents of RAM with minimal power

when the rest of the chip is powered down.

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MC68HC912DG128 — Rev 3.0 Technic al Data

Pinout and Signal Descriptions

NOTE: The internal return path for the oscilla tor is the VS SPLL pin. Ther efore it

is reco mmende d t o connect th e comm on n ode of the re sonato r and the

capacitor directly to the VSSP LL pi n.

Figure 3-4. Common Crystal Connections

NOTE: When sele cting a crystal, i t is recom mended to use one with t he lowe st

possible frequency in order to minimise EMC emissions.

Figure 3-5. External Oscillator Connections

XTAL is the crystal output.The XTAL pin must be left unterminated when

an external CMOS compatible clock input is connected to the EXTAL

pin. The XTAL output is normally int ended to drive onl y a crystal. The

XTAL output can be buffered with a high-impedance buffer to drive the

EXTAL input of another device.

In all cases take extra care in the circuit board layout around the

oscillator pins. Load capacitances in the o scillator circuits include all

stray layout capacitances. Refer to Figure 3-4 and Figure 3-5 for

diag rams of os cill ator ci rcuit s.

MCU

EXTAL

XTAL

2 x E crystal or ceramic resonator

MCU

EXTAL

XTAL

2 x E

CMOS-COMPATIBLE

EXTERNAL OSCILLATOR

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Technical Data MC68HC912DG128 — Rev 3.0

Pinout and Signal Descriptions

3.4.2 E-Clock Output (ECLK)

ECLK is the output connection for the internal bus clock. It is used to

demultiplex the address and data in expanded modes and is used as a

timing reference. ECLK frequency is equal to 1/2 the crystal frequency

out of reset . Th e E-clo ck outp ut is turn ed o ff in si ngl e chip user mode to

reduce the effects of RFI. It can be turned on if necessary. In special

single-chip mode, the E-clock is turned ON at reset and can be turned

OFF. In special peripheral mode the E-clock is an input to the MCU. All

clocks, including th e E clock, are halted when the MCU is in STOP

mode. It is possible to configure the MCU to interface to slow external

memory. ECLK can be stretched for such accesses.

3.4.3 Reset (RESET)

An active low bidirectional control signal, RESET, acts as an input to

initialize the MCU to a known start-up state. It also acts as an open-drain

output to indicate that an internal failure has been detected in either the

clock monitor or COP watchdog circuit. The MCU goes into reset

asynchro no usl y and com es out of re set synch ro no usl y. This al low s the

part to reach a proper reset state even if the clocks have failed, while

allowing sy nchronized operat ion when st arting out of reset.

It is important to use an external low-voltage reset circuit (such as

MC34064 or MC34164) to prevent corruption of RAM or EEPROM due

to power transitions.

The reset sequence is initiated by any of the following events:

•Power-o n-reset (POR)

•COP watchdog enabled and watchdog timer times out

•Clock monitor enabled and Clock monitor detects slow or stopped

clock

•User appl ies a low level to the reset pin

Exte rnal circuitry connected to the reset p in should not include a large

capacitance that would interfere with the ability of this signal to rise to a

valid logic one within nine bus cycles after the low drive is released.

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MC68HC912DG128 — Rev 3.0 Technic al Data

Pinout and Signal Descriptions

Upon de tection of any re set, an internal c i rcuit drives the reset pin low

and a clocked reset sequence controls when the MCU can begin normal

processing. In the case of POR or a clock monitor error, a 4096 cycle

oscillator startup delay is imposed before the reset recovery sequence

starts (reset is driven low throughout this 4096 cycle delay). The internal

reset recovery sequence then drives reset low for 16 to 17 cycles and

releases the drive to allow reset to rise. Nine cycles later this circuit

sampl es the rese t pin to see if it has rise n to a l ogic on e leve l. If rese t is

low at this point, the reset is assumed to be coming from an external

request and the internally latched states of the COP time-out and clock

monitor failure are cleared so the normal reset vector ($FFFE:FFFF) is

taken when reset is finally released. If reset is high after this nine cycle

delay, the reset source is tentatively assumed to be either a COP failure

or a clock monitor fail. If the internally latched state of the clock monitor

fail circuit is true, processing begins by fetching the clock monitor vector

($FFFC:FFFD). If no clock monitor failure is indicated, and the latched

state of the COP time-out is true, processing begins by fetching the COP

vector ($FFFA:FFFB). If neither clock monitor fail nor COP time-out are

pending, processing begins by fetching the normal reset vector

($FFFE:FFFF).

3.4.4 Maskable Interrupt Request (IRQ)

The IRQ input provides a means of applying asynchronous interrupt

requests to the MCU. Either falling edge-sensitive triggering or level-

sensitive trigger ing is progra m selectable (INTCR register). IRQ is

always enabled and configured to level-sensitive triggering at reset. It

can be disabl ed by clearing the IRQEN bit (INTCR r egister). When the

MCU is reset, the IRQ function is m asked in the conditio n code register.

This pin is always an input and can always be read. There is an active

pull-up on this pin while in reset and immediatel y out of reset. The pull-

up can be turned off by clearing PUPE in the PUCR re gister.

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Technical Data MC68HC912DG128 — Rev 3.0

Pinout and Signal Descriptions

3.4.5 Nonmaskable Interrupt (XIRQ)

The XIRQ input provides a means of requesting a nonmaskable interrupt

after reset ini tialization. Dur ing reset, the X bit in the condition code

enables it. Because the XIRQ input is level sensitive, it can be connected

to a multiple-source wired-OR netw ork. Th is pin is always an inp ut and

can always be read. There is an active pull-up on this pin while in reset

and immediately out of reset. The pull-up can be turned off by clearing

PUPE in the PUCR register. XIRQ is often used as a power loss detect

interrupt.

Whenever XIRQ or IRQ are used with multiple interrupt sources (IRQ

must be configured for level-sensitive operation if there is more than one

source of IRQ interrupt), each source must drive the interrupt input with

an ope n-drain type o f driver t o avoid conten tion betwee n outputs. The re

must also be an interlock mechanism at each interrupt source so that the

source holds the in terrupt line low unti l the MCU recognizes and

acknowledges the interrupt request. If the interrupt line is held low, the

MCU will recognize another interrupt as soon as the interrupt mask bit in

the MCU is cleared (normally upon return from an interrupt).

3.4.6 Mode Select (SMODN, MODA, and MODB)

The state of these pins during reset determine the MCU operating mode.

After reset, MODA and MODB can be configured as instruction queue

tracking signals IPIPE0 and IPIPE1 in expanded modes. MODA and

MODB have active pull-downs during reset.

The SMODN pin has an active pull-up when configured as an input. This

pin can be us ed as BKGD or TAGHI after reset.

3.4.7 Single-Wire Background Mode Pin (BKGD)

The BKGD pin receives and transmits serial background debugging

commands. A special self-t iming proto col is used. Th e BKGD pin has an

active pull-up when configured as an input; BKGD has no pull-up control.

Refer to Development Support.

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MC68HC912DG128 — Rev 3.0 Technic al Data

Pinout and Signal Descriptions

3.4.8 External Address and Data Buses (ADDR[15:0] and DATA[15:0])

Externa l bu s pi n s sha re fu ncti o ns wi th ge ner a l-pu r po se I/O por ts A and

B. In single-chip operating modes, the pins can be used for I/O; in

expanded modes, the pins are used for the external buses.

In expanded wide mode, ports A and B are u sed for multip lexed 16-bit

data and address buses. PA[7:0] correspond to

ADDR[15:8]/DATA[15:8]; PB[7:0] correspond to ADDR[7:0]/DATA[7:0].

In expanded narrow mode, ports A and B are u sed for the16-bit address

bus, and an 8-bit data bus is multiplexed with the most significant half of

the address bus on port A. In this mode, 16-bit data is handled as two

back-to-back bus cycles, one for the high byte followed by one for the

low byte. PA[7:0] correspond to ADDR[15:8] and to DATA[15:8] or

DATA[7:0], depending on the bus cycle. The state of the address pins

should be latched at the rising edge of E. To allow for maximum address

setup time at external devices, a trans parent latch should be used.

3.4.9 Read/Write (R/W)

In all modes this pin can be used as a general-purpose I/O and is an

input with an active pull-up out of reset. If the read/write function is

required it should be enabled by setting the RDWE bit in the PEAR

3.4.10 Low-Byte Strobe (LSTRB)

In all modes this pin can be used as a general-purpose I/O and is an

input with an active pull-up out of reset. If the strobe function is required ,

it shou ld be enabl ed by setting th e LSTRE bit in t he PEAR re gister. This

signal is used in write operations and so external low byte writes will not

be possible until this function is enabled. This pin is also used as T AGLO

in Special Expanded modes and is multiplexed with the LSTRB function.

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Pinout and Signal Descriptions

Technical Data MC68HC912DG128 — Rev 3.0

Pinout and Signal Descriptions

3.4.11 Instruction Queue Tracking Signals (IPIPE1 and IPIPE0)

These signals are used to track the state of the internal instruction

execution queue. Execution state is time-multiplexed on the two signals.

Refer to Development Support.

3.4.12 Data Bus Enable (DBE)

The DBE pin (PE7) is an active low signal that will be asserted low during

E-clock high time. DBE provides separation between out put of a

multip lexed add ress and the inpu t of data. When an exte rnal addr ess is

stretched, DBE is asserted during what would be the last quarter cycle

of the last E-clock cycle of stretch. In expanded modes this pin is used

to enable th e dr i v e cont rol o f e x te rn al buses d uri ng external reads. U s e

of the DBE is controlled by the NDBE bit in the PEAR register. DBE is

enabl ed out of r e set i n exp and ed mo de s. Thi s pin h as an act ive pull-u p

during and after reset in single chip modes.

3.4.13 Inverted E clock (ECLK)

The ECLK pin (PE7) can be used to latch the address for de-

multip le xi ng . It has th e sam e be ha vi or as the ECLK, except is inver te d.

In expanded modes this pin is used to enable the drive control of external

buses during external reads. Use of the ECLK is controlled by the NDBE

and DBENE bits in the PEAR register.

3.4.14 Calibration reference (CAL)

The CAL pin (P E7) is th e output of the Slow Mo de pro gramm able clock

divider , SLW CLK, an d is u sed as a cali brati on re ference. The SLWCL K

frequency is equal to the crystal frequency out of reset and always has

a 50% duty. If the DBE function is enabled it will override the enabled

CAL output. The CAL pin output is disabled by clearing CALE bit in the

PEAR register.

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MC68HC912DG128 — Rev 3.0 Technic al Data

Pinout and Signal Descriptions

3.4.15 Clock generation module test (CGMTST)

The CGMTST pin (PE6) is the ou tput of the clocks test ed when CGMTE

bit is set in P EAR register. The PIP OE bit must be cleared for the clocks

to be tested.

Table 3-2. Signal Description Summary

Pin Name Shared

port

Number Description

112-pin

EXTAL - 47 Crystal driver and external clock input pins. On reset all the device clocks

are derived from the EXTAL input frequency. XTAL is the crystal output.

XTAL - 48

RESET - 46 An active low bidirectional control signal, RESET acts as an input to

initialize the MCU to a known start-up state, and an output when COP or

clock monitor causes a reset.

ADDR[7:0]

DATA[7:0] PB[7:0] 31–24 External bus pins share function with general-purpose I/O ports A and B.

In single chip modes, the pins can be used for I/O. In expanded modes,

the pins are used for the external buses.

ADDR[15:8]

DATA[15:8] PA[7:0] 64–57

DBE PE7 36 Data bus control and, in expanded mode, enables the drive control of

external buses during external reads.

ECLK PE7 36 Inverted E clock used to latch the address.

CAL PE7 36

CAL is the output of the Slow Mode programmable clock divider,

SLWCLK, and is used as a calibration reference for functions such as

time of day. It is overridden when DBE function is enabled. It always has

a 50% duty.

CGMT ST PE6 37 Clock gener ation module test output .

MODB/

IPIPE1,

MODA/

IPIPE0

PE6, PE5 37, 38

State of mode select pins during reset determine the initial operating

mode of the MCU. After reset, MODB and MODA can be configured as

instruction queue tracking signals IPIPE1 and IPIPE0 or as general-

purpose I/O pins.

ECLK PE4 39 E Clock is the output connection for the external bus clock. ECLK is used

as a timing reference and for address demultiplexing.

LSTRB/

TAGLO PE3 53

Low byte strobe (0 = low byte valid), in all modes this pin can be used as

I/O. The low strobe function is the exclusive-NOR of A0 and the internal

SZ8 signal. (The SZ8 internal signal indicates the size 16/8 access.) Pin

function TAGLO used in instruction tagging. See Development Support.

R/W PE2 54 Indicates direction of data on expansion bus. Shares function with

general-purpose I/O. Read/write in expanded modes.

IRQ PE1 55

Maskable interrupt request input provides a means of applying

asynchronous interrupt requests to the MCU. Either falling edge-

sensitive triggering or level-sensitive triggering is program selectable

(INTCR register).

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XIRQ PE0 56 Provides a means of requesting asynchronous nonmaskable interrupt

requests after reset initialization

SMODN/

BKGD/

TAGHI -23

During reset, this pin determines special or normal operating mode. After

reset, single-wire background interface pin is dedicated to the

background debug function. Pin function TAGHI used in instruction

tagging. See Development Support.

IX[2:0] PK[2:0] 109-111 Page Index register emulation outputs.

ECS PK7 108 Emulation Chip select.

PW[3:0] PP[3:0] 112, 1–3 Pulse Width Modulator channel outputs.

SS PS7 96 Slave sele ct output for SPI master mode, input for slave mode or master

mode.

SCK PS6 95 Seri al clock for SPI system.

SDO/MOSI PS5 94 Master out/slave in pin for serial peripheral interface

SDI/MISO PS4 93 Master in/slave out pin for serial peripheral interface

TxD1 PS3 92 SCI1 transmit pin

RxD1 PS2 9 1 SCI1 receive pin

TxD0 PS1 90 SCI0 transmit pin

RxD0 PS0 8 9 SCI0 receive pin

IOC[7:0] PT[7:0] 18–15, 7–4 Pins used for input capture and output compare in the timer and pulse

accumulator subsystem.

AN1[7:0] PAD1[7:0] 84/82/80/7

8/76/74/72/

70 Analog inputs for the analog-to-digital conversion module 1

AN0[7:0] PAD0[7:0] 83/81/79/7

7/75/73/71/

69 Analog inputs for the analog-to-digital conversion module 0

TxCAN1 - 102 MSCAN1 transmit pin

RxCAN1 - 103 MSCAN1 receive pin

TxCAN0 - 104 MSCAN0 transmit pin

RxCAN0 - 105 MSCAN0 receive pin

SCL PIB7 98 I2C bus serial clock line pin

SDA PIB6 99 I2C bus serial data line pin

KWJ[7:0] PJ[7:0] 8–11,

19–22 Key wake-up and general purpose I/O; can cause an interrupt when an

input transitions from high to low or from low to high (KWPJ).

KWH[7:0] PH[7:0] 32–35,

49–52 Key wake-up and general purpose I/O; can cause an interrupt when an

input transitions from high to low or from low to high (KWPH).

Table 3-2. Signal Description Summary

Pin Name Shared

port

Number Description

112-pin

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Pinout and Signal Descriptions

Port Signals

MC68HC912DG128 — Rev 3.0 Technic al Data

Pinout and Signal Descriptions

3.5 Port Signals

The MC68HC912DG128 incorporates eleven ports whi ch are u sed to

control and access the various device subsystems. When not used for

these purposes, port pins may be used for general-purpose I/O. In

addition to the pins described below, each port consists of a data register

which can be read and written at any time, and, with the exception of port

AD0, port AD1, PE[1:0], RxCAN and TxCAN, a data direction register

which controls the direction of each pin. After reset all general purpose

I/O pins are config ured as input.

3.5.1 Port A

Port A pins are used for address an d data in ex panded mo des. In single

chip modes, the pin s can be used as gene ral purpose I/O. The port data

operation. When it is in the map, port A can be read or written at anytime.

DDRA is not in the address map during expanded and peripheral mode

operation. Setting a bit in DDRA makes the corresponding bit in port A

an output; clearing a bit in DDRA makes the corresponding bit in port A

an input. The d efault reset state of DDRA is all zeros.

When the PUPA bit in the PUCR re gister i s set, all port A i nput pi ns are

pulled-up internally by an active pull-up device. PUCR is not in the

address map in peripheral mode.

Setting the RDPA bit in register RDRIV causes all port A outputs to have

reduced drive level. RDRIV can be written once after reset. RDRIV is not

in the address map in peripheral mode. Refer to Bus Control and

Input/Output.

3.5.2 Port B

Port B pins are used for address an d data in ex panded mo des. In single

chip modes, the pin s can be used as gene ral purpose I/O. The port data

operation. When it is in the map, port B can be read or written at anytime.

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DDRB is not in the address map during expanded and peripheral mode

operation. Setting a bit in DDRB makes the corresponding bit in port B

an output; clearing a bit in DDRB makes the corresponding bit in port B

an input. The d efault reset state of DDRB is all zeros.

When the PUPB bit in the PUCR re gister i s set, all port B i nput pi ns are

pulled-up internally by an active pull-up device. PUCR is not in the

address map in peripheral mode.

Setting the RDPB bit in register RDRIV causes all port B outputs to have

reduced drive level. RDRIV can be written once after reset. RDRIV is not

in the address map in peripheral mode. Refer to Bus Control and

Input/Output.

3.5.3 Port E

Port E pins operate differently from port A and B pins. Port E pins are

used for bus contro l signals an d interrup t service requ est signals. When

a pin is not used for one of these specific functions, it can be used as

general-purpose I/O. However, two of the pins (PE[1:0]) can only be

used f or i npu t, a nd the state s of th ese pi ns ca n be r ead in th e port da ta

The PEAR register de termines pi n funct ion, and register DDRE

determines whether each pin is an input or output when it is used for

general-purpose I/O. PEAR settings override DDRE settings. Because

PE[1:0] are input-only pins, on ly DDRE[7:2] have effect. Setting a bit in

the DDRE register makes the corresponding bit in port E an outpu t;

clearing a bit in the DDRE register makes the corresponding bit in port E

an input. The d efault reset state of DDRE is all zeros.

When the PU PE bit in the PUCR register is set, PE[7,3,2,1, 0] are pulled

up. PE[7,3,2 ,0] are ac tive pull-up devices. PUPCR is no t in the address

map in peripheral mode.

Neither port E nor DDRE is in the map in peripheral mode; neither is in

the internal map in expanded modes with EME set.

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Port Signals

MC68HC912DG128 — Rev 3.0 Technic al Data

Pinout and Signal Descriptions

Setting the RDPE bit in register RDRIV causes all port E outputs to have

reduced drive level. RDRIV can be written once after reset. RDRIV is not

in the address map in peripheral mode. Refer to Bus Control and

Input/Output.

3.5.4 Port H

Port H pins are us ed for key wake-ups that can be used with the pins

configured as inputs or outputs. The key wake-ups are triggered with

either a rising or fal ling edge sign al (KWPH). An in terrupt is gene rated if

the corr esp on ding bit is en abl e d (K WI EH ). If any of the i nte rrupts is not

enabled, the corresponding pin can be used as a general purpose I/O

pin. Refer to I/O Ports with Key Wake-up.

Setting a bit in DDRH makes the corresponding bit in port H an output;

clearing a bit in DDRH makes the corresponding bit in port H a n in put.

The default reset state of DDRH is all zeros.

are triggered, but it also determines what type of resistive load is used

for por t H in put pins w hen P UPH bi t is se t in the P UCR reg ister . Settin g

a bit in KWPH makes the correspondin g key wake up input pin trigger at

rising edges and loads a pull down in the corresponding port H input pin.

Clearin g a bit in KWPH make s the corr espondin g key wake up input p in

trigger at falling edges and loads a pull up in the corresponding port H

input pin. The default state of KWPH is all zeros.

Setting the RDPH bit in register RDRIV causes all port H outputs to have

reduced drive level. RDRIV can be written once after reset. RDRIV is not

in the address map in peripheral mode. Refer to Bus Control and

Input/Output.

3.5.5 Port J

Port J pins are used for key wake-ups that can be used with the pins

configured as inputs or outputs. The key wake-ups are triggered with

either a rising or falling e dge si gnal ( KWPJ). An i nter rupt is g ener ated if

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Pinout and Signal Descriptions

the corresponding bit is enabled (KWIEJ). If any of the interrupts is not

enabled, the corresponding pin can be used as a general purpose I/O

pin. Refer to I/O Ports with Key Wake-up.

Setting a bit in DDRJ makes the corresponding bit in port J an output;

clearing a bit in DDRJ makes the corresponding bit in port J an input. The

default reset state of DDRJ is all zeros.

are triggered, but it also determines what type of resistive load is used

for port J input pins whe n PUPJ bit is set in the PUCR registe r. Setting a

bit in KWPJ makes the corresponding key wake up input pin trigger at

rising edges and loa ds a pull dow n in the corre sponding p ort J inpu t pin.

Clearin g a bit in KWPJ m akes the corre spond ing key wa ke up inp ut pin

trigger at falling edges and loads a pull up in the corresponding port J

input pin. The default state of KWPJ is all zeros.

Setting the RDPJ bit in register RDRIV causes all port J outputs to have

reduced drive level. RDRIV can be written once after reset. RDRIV is not

in the address map in peripheral mode. Refer to Bus Control and

Input/Output.

3.5.6 Port K

Port K pins are use d for page index emulat ion in expanded or peripheral

modes. When page index emulation is not enabled, EMK is not set in

MODE register, or the part is in single chip mode, these pins can be used

for general purpose I/O. Port K bit 3 is used as a general purpose I/O pin

only. The port data register is not in the address map during expanded

and peripheral mod e operation with EMK set. When it is in the map, p ort

K can be read or written at anytime.

DDRK is not in the address map during expanded and peripheral mode

operation with EMK set. Setting a bit in DDRK makes the corresponding

bit in port K an output; clearing a bit in DDRK makes the corresponding

bit in port K a n in put. The default reset state of DDRK is all zeros.

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Port Signals

MC68HC912DG128 — Rev 3.0 Technic al Data

Pinout and Signal Descriptions

When the PUPK bit in the PUCR re gister i s set, all port K i nput pi ns are

pulled-up internally by an active pull-up device. PUCR is not in the

address map in peripheral mode.

Setting the RDPK bit in register RDRIV causes all port K outputs to have

reduced drive level. RDRIV can be written once after reset. RDRIV is not

in the address map in peripheral mode. Refer to Bus Control and

Input/Output.

3.5.7 Port CAN1

The MSCAN1 uses two external pins, one input (RxCAN1) and one

output (TxCAN 1). The TxCAN1 output pin r epresen ts the logic leve l on

the CAN: ‘0’ is for a dominant state, and ‘1’ is for a recessive state.

RxCAN1 is on bit 0 of Port CAN1, TxCAN1 is on bit 1.

3.5.8 Port CAN0

The MSCAN0 uses two external pins, one input (RxCAN0) and one

output (TxCAN 0). The TxCAN0 output pin r epresen ts the logic leve l on

the CAN: ‘0’ is for a dominant state, and ‘1’ is for a recessive state.

RxCAN0 is on bit 0 of Port CAN0, TxCAN0 is on bit 1.

3.5.9 Port IB

Bidirectional pins to IIC bus interface subsystem. The IIC bus interface

uses a Serial Data line (SDA) and Serial Clock line (SCL) for data

transfer. The pins are connected to a positive voltage supply via a pull

up resistor. The pull ups can be enabled internally or connected

externally. The output stages have open drain outputs in order to

perform the wired-AND function. When the IIC is disabled the pins can

be used as general pu rpose I/O pi ns. SCL is on bit 7 of Por t IB and SD A

is on bit 6. The remaining pins of Port IB (PIB[5:4]) are controlled by

regist ers in the IIC address space.

general-purpose I/O. Wh en DDRIB bits are set, the corresponding pin is

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Pinout and Signal Descriptions

configure d fo r output. On reset the DDRIB bits a re cleared and th e

corresponding pin is configured for input.

When the PUPIB bit in the IBPURD register is set, all input pin s are

pulled up internally by an active pull-up device. Pull-ups are disabled

after reset, except for input ports 0 through 3, which are always on

regard less of PUPIB b i t.

Setting the RDPIB bit in the IBPURD register configures all port IB

outputs to have reduced drive levels. Levels are at normal drive

capability after reset. The IBPURD register can be read or written

anytime after reset. Refer to section Inter-IC Bus.

3.5.10 Port AD1

This port is an an alog inpu t in terfa ce to th e a na log-to -di gita l subsystem

and used for general-purpose input. When analog-to-digital functions

are n ot enabled, the port has eight general-purpose input pins,

PAD1[7:0]. The ADPU bit in the ATD1CTL2 register enables the A/D

function.

Port AD1 pins are inputs; no data direction register is associated with this

port. The port has no resistive input loads and no reduced drive controls.

Refer to MSCAN Controlle r .

3.5.11 Port AD0

This port is an analog input interface to the analog-to-digital subs ystem

and used for general-purpose input. When analog-to-digital functions are

not enabled, the port has eight general-purpose input pins, PA D0[7:0].

The ADPU bit in the ATD0CTL2 register enables the A/D f unction.

Port AD0 pins are inputs; no data direction register is associated with this

port. The port has no resistive input loads and no reduced drive controls.

Refer to MSCAN Controlle r .

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Port Signals

MC68HC912DG128 — Rev 3.0 Technic al Data

Pinout and Signal Descriptions

3.5.12 Port P

The four pulse-width modulation channel outputs share general-purpose

port P pins. The PWM function is enabled with the PWEN register.

Enabling PWM pins takes precedence over the general-purpose port.

When pulse-width modulation is not in use, the port pins may be used for

general-purp ose I/O.

general-purpose I/O. When DDRP bits are set, the corresponding pin is

configure d fo r output. On reset the DDRP bits are cleare d and the

corresponding pin is configured for input.

When the PUPP bit in the PWCTL register is set, all input pins are pulled

up internally by an active pull-up device. Pull-ups are disabled after reset.

Setting the RDPP bit in the PWCTL register configures all port P outputs

to have reduced drive levels. Levels are at normal drive capa bility after

reset. The PWCTL register can be read or written anytime after reset.

Refer to Pulse Width Modulator.

3.5.13 Port S

Port S i s th e 8 -b it i nte r face to t he standar d ser ial i nte rface consisting of

the two serial communications interfaces (SCI1 and SCI0) and the serial

peripheral interface (SPI) subsystems. Port S pins are available for

general-purp ose I/O when standa rd serial fun ction s are not enable d.

Port S pins serve several functions depending on the various internal

control registers. If WOMS bit in the SC0CR1register is set, the P-

channel drivers of the output buffers are disabled (wire-or mode) for pins

0 through 3. If SWOM bit in the SP0CR1 register is set, the P-channel

drive rs of the ou tput buffers are disable d (wi r e- or mod e) for pi ns 4

through 7. The open drain control affects both the serial and the general-

purpose outputs. If the RDPS bit in the SP0CR2 register is set, Port S

pin drive capabilities are reduced. If PUPS bit in the SP0CR2 register is

set, a pull-up device is activated for each port S pin programmed as a

general purpose input. If the pin is programmed as a general-purpose

output, the pull-up is disconnected from the pin regardless of the state of

PUPS bit. See Multiple Serial Interface.

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Technical Data MC68HC912DG128 — Rev 3.0

Pinout and Signal Descriptions

3.5.14 Port T

This port provides eigh t gen eral-pu r pose I/O pin s when n ot en ab led fo r

input capture and output compare in the timer and pulse accumulator

subsystem. The TEN bit in the TSCR register enables the timer function.

The pulse accumulator subsystem is enabled with the PAEN bit in the

PACTL registe r.

purpose I/O. When DDRT bits are set, the corresponding pin is

configure d fo r output. On reset the DDRT b its are cleared and the

corresponding pin is configured for input.

When the PUPT bit in the TMSK2 register is set, all input pins are pulled

up internally by an active pull-u p device. Pull-ups ar e disabled after

reset.

Setting the RDPT bit in the TMSK2 registe r configures all port T outp uts

to have reduced drive levels. Levels are at normal drive capa bility after

reset. The TMSK2 register can be read or written anytime after reset

Refer to Enhanced Capture Timer.

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Pinout and Signal Descriptions

Port Signals

MC68HC912DG128 — Rev 3.0 Technic al Data

Pinout and Signal Descriptions

Table 3-3. Port Description Summary

Port Name Pin Numbers Data Direction

(Address) Description

112-pin

Port A

PA[7:0] 64-57 In/Out

DDRA ($0002) Port A and port B pins are used for address and data in

expanded modes. The port data registers are not in the

address map during expanded and peripheral mode

operation. When in the map, port A and port B can be

read or written any time.

DDRA and DDRB are not in the address map in expanded

or peripheral modes.

Port B

PB[7:0] 31–24 In/Out

DDRB ($0003)

Port AD1

PAD1[7:0] 84/82/80/78/7

6/74/72/70 In Analog-to-digital converter 1 and general-purpose I/O.

Port AD0

PAD0[7:0] 83/81/79/77/7

5/73/71/69 In Analog-to-digital converter 0 and general-purpose I/O.

Port CAN1

PCAN1[1:0] 102–103 PCAN1[1] Out

PCAN 1[0] In PCAN1[1:0] are used with the MSCAN1 module and

cannot be used as general purpose I/O.

Port CAN0

PCAN0[1:0] 104–105 PCAN0[1] Out

PCAN 0[0] In PCAN0[1:0] are used with the MSCAN0 module and

cannot be used as general purpose I/O.

Port IB

PIB[7:4] 98–101 In/Out

DDRIB ($00E 7) General purpose I/O. PIB[7:6] are used with the I-Bus

module when enabled.

Port IB

PIB[3:2] 102–103 In/Out

DDRIB ($00E 7) General purpo se I/O

Port E

PE[7:0] 36–39, 53–56 PE[1:0] In

PE[7:2] In/Out

DDRE ($0009)

Mode selection, bus control signals and interrupt service

request signals; or general-purpose I/O.

Port K

PK[7,3:0] 13,

108-111 In/Out

DDRK ($00FD) Page index emulation signals in expanded or peripheral

mode or general-purpose I/O.

Port P

PP[3:0] 112,

1–3 In/Out

DDRP ($0057) General-purpose I/O. PP[3:0] are used with the pulse-width

modulator when enabled.

Port S

PS[7:0] 96–89 In/Out

DDRS ($00D7) Serial communications interfaces 1 and 0 and serial

peripheral interface subsystems; or general-purpose I/O.

Port T

PT[7:0] 18–15, 7–4 In/Out

DDRT ($00AF)

General-purpose I/O when not enabled for input capture

and output compare in the timer and pulse accumulator

subsystem.

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Technical Data MC68HC912DG128 — Rev 3.0

Pinout and Signal Descriptions

3.5.15 Port Pull-Up Pull-Down and Reduced Drive

MCU ports c an be co nfigur ed for internal pull-up. To reduce po wer

consumptio n and RFI , the pi n output drivers can be configur ed to

operate at a reduced drive level. Reduced drive causes a slight increase

in transition time depending on loading and should be used only for ports

which have a light loading. Table 3-4 summarizes the port pull-up/pu ll-

down default status and controls.

Table 3-4. Port Pull-Up, Pull-Down and Reduced Drive Summary

Enable Bit Reduced Drive Control Bit

Port

Name Resistive

Input Loads Register

(Address) Bit Name Reset

State Register

(Address) Bit Name Reset

State

Port A Pull-up PUCR ($000C) PUPA Disabled RDRIV ($000D) RDPA Full drive

Port B Pull-up PUCR ($000C) PUPB Disabled RDRIV ($000D) RDPB Full drive

Port E:

PE7, PE[3:2] Pull-up PUCR ($000C) PUPE Enabled RDRIV ($000D) RDPE Full drive

PE[1:0] Pull-up PUCR ($000C) PUPE Enabled —

PE[6:4] None —RDRIV ($000D) RDPE Full drive

Port H Pull-up or

Pull-down PUCR ($000C) PUPH Disabled RDRIV ($000D) RDPH Full drive

Port J Pull-up or

Pull-down PUCR ($000C) PUPJ Disabled RDRIV ($000D) RDPJ Full drive

Port K Pull-up PUCR ($000C) PUPK Disabled RDRIV ($000D) RDPK Full drive

Port P Pull-up PWCTL ($0054) PUPP Disabled PWCTL ($0054) RDPP Full drive

Port S Pull-up SP0CR2 ($00D1) PUPS Enabled SP0CR2 ($00D1) RDPS Full drive

Port T Pull-up TMSK2 ($008D) TPU Disabled TMSK2 ($008D) TDRB Full drive

Port IB[7:4] Pull-up IBPURD ($00E5) PUPIB Disabled IBPURD ($00E5) RDPIB Full drive

Port IB[3:2] Pull-up Always enabled when pins are input IBPURD ($00E5) RDPIB Full drive

Port AD0 None ——

Port AD1 None ——

Port CAN1[1] None ——

Port CAN1[0] Pull-up Always enabled —

Port CAN0[1] None ——

Port CAN0[0] Pull-up Always enabled —

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Pinout and Signal Descriptions

Technical Data MC68HC912DG128 — Rev 3.0

Pinout and Signal Descriptions

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Pinout and Signal Descriptions

Technical Data MC68HC912DG128 — Rev 3.0

Pinout and Signal Descriptions

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MC68HC912DG128 — Rev 3.0 Technic al Data

Registers

Technical Data — MC68HC912DG128

Section 4. Registers

4.1 Contents

4.2 Register Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

4.2 Register Block

The register block c an be mapped to any 2K byte boundary within the

stan dard 64 K byte address spac e by manipulating bi ts REG[ 15:11 ] in

the INITRG register. INITRG establishes the upper five bits of the

regist er block’s 16-bit address. The register bloc k occupies the first 1K

byte o f the 2K byte block . Default a ddressing (after re set) is in dicated in

the table below. For additional information refer to General Description.

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Registers
Technical Data MC68HC912DG128 — Rev 3.0
Registers
Address Bit 7 6 5 4 3 2 1 B it 0 Name
$0000PA7PA6PA5PA4PA3PA2PA1PA0
PORTA(1)
$0001 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PORTB(1)
$0002 DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 DDRA(1)
$0003 DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 DDRB(1)
$0004-
$0007 00000000
Reserved(3)
$0008 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PORTE(2)
$0009 DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 0 0 DDRE(2)
$000A NDBE CGMTE PIPOE NECLK LSTRE RDWE CALE DBENE PEAR(3)
$000B SMODN MODB MODA ESTR IVIS EBSWAI EMK EME MODE(3)
$000C PUPK PUPJ PUPH PUPE 0 0 PUPB PUPA PUCR(3)
$000D RDPK RDPJ RDPH RDPE 0 0 RDPB RDPA RDRIV(3)
$000E00000000
Reserved(3)
$000F00000000
Reserved(3)
$0010RAM15RAM14RAM1300000INITRM
$0011 REG15 REG14 REG13 REG12 REG11 0 0 MMSWAI INITRG
$0012 EE15 EE14 EE13 EE12 0 0 0 EEON INITEE
$0013 ROMTST NDRF RFSTR1 RFSTR0 EXSTR1 EXSTR0 ROMHM ROMON MISC
$0014 RTIE RSWAI RSBCK Reserved RTBYP RTR2 RTR1 RTR0 RTICTL
$0015RTIF0000000RTIFLG
$0016 CME FCME FCMCOP WCOP DISR CR2 CR1 CR0 COPCTL
$0017Bit 7654321Bit 0COPRST
$0018 ITE6 ITE8 ITEA ITEC ITEE ITF0 ITF2 ITF4 ITST0
$0019 ITD6 ITD8 ITDA ITDC ITDE ITE0 ITE2 ITE4 ITST1
$001A ITC6 ITC8 ITCA ITCC ITCE ITD0 ITD2 ITD4 ITST2
$001B ITB6 ITB8 ITBA ITBC ITBE ITC0 ITC2 ITC4 ITST3
$001C00000000Reserved
$001D00000000Reserved
$001EIRQEIRQENDLY00000INTCR
$001F 1 PSEL6 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1 0 HPRIO
$0020 BKEN1 BKEN0 BKPM 0 BK1ALE BK0ALE 0 0 BRKCT0
$0021 0 BKDBE BKMBH BKMBL BK1RWE BK1RW BK0RWE BK0RW BRKCT1
$0022 Bit 15 14 13 12 11 10 9 Bit 8 BRKAH
$0023Bit 7654321Bit 0BRKAL
$0024 Bit 15 14 13 12 11 10 9 Bit 8 BRKDH
Table 4-1. Register Map  (Sheet 1 of 10)
    
  
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Registers

Registe r Block

MC68HC912DG128 — Rev 3.0 Technic al Data

Registers

$0025Bit 7654321Bit 0BRKDL

$002600000000Reserved

$002700000000Reserved

$0028PJ7PJ6PJ5PJ4PJ3PJ2PJ1PJ0PORTJ

$0029PH7PH6PH5PH4PH3PH2PH1PH0PORTH

$002A DDJ7 DDJ6 DDJ5 DDJ4 DDJ3 DDJ2 DDJ1 DDJ0 DDRJ

$002B DDH7 DDH6 DDH5 DDH4 DDH3 DDH2 DDH1 DDH0 DDRH

$002C KWIEJ7 KWIEJ6 KWIEJ5 KWIEJ4 KWIEJ3 KWIEJ2 KWIEJ1 KWIEJ0 KWIEJ

$002D KWIEH7 KWIEH6 KWIEH5 KWIEH4 KWIEH3 KWIEH2 KWIEH1 KWIEH0 KWIEH

$002E KWIFJ7 KWIFJ6 KWIFJ5 KWIFJ4 KWIFJ3 KWIFJ2 KWIFJ1 KWIFJ0 KWIFJ

$002F KWIFH7 KWIFH6 KWIFH5 KWIFH4 KWIFH3 KWIFH2 KWIFH1 KWIFH0 KWIFH

$0030 KWPJ7 KWPJ6 KWPJ5 KWPJ4 KWPJ3 KWPJ2 KWPJ1 KWPJ0 KWPJ

$0031 KWPH7 KWPH6 KWPH5 KWPH4 KWPH3 KWPH2 KWPH1 KWPH0 KWPH

$003200000000Reserved

$003300000000Reserved

$0034–

$0037 Unimplemented(4) Reserved

$0038 0 0 SYN5 SYN4 SYN3 SYN2 SYN1 SYN0 SYNR

$003900000REFDV2REFDV1REFDV0REFDV

$003A TSTOUT7 TSTOUT6 TSTOUT5 TSTOUT4 TSTOUT3 TSTOUT2 TSTOUT1 TSTOUT0 CGTFLG

$003B LOCKIF LOCK 0 0 0 0 LHIF LHOME PLLFLG

$003C LOCKIE PLLON AUTO ACQ 0 PSTP LHIE NOLHM PLLCR

$003D 0 BCSP BCSS 0 0 MCS 0 0 CLKSEL

$003E 0 0 SLDV5 SLDV4 SLDV3 SLDV2 SLDV1 SLDV0 SLOW

$003FOPNLETRKTSTCLKETST4TST3TST2TST1TST0CGTCTL

$0040 CON23 CON01 PCKA2 PCKA1 PCKA0 PCKB2 PCKB1 PCKB0 PWCLK

$0041 PCLK3 PCLK2 PCLK1 PCLK0 PPOL3 PPOL2 PPOL1 PPOL0 PWPOL

$00420000PWEN3PWEN2PWEN1PWEN0PWEN

$0043 0 Bit 6 5 4 3 2 1 Bit 0 PWPRES

$0044Bit 7654321Bit 0PWSCAL0

$0045Bit 7654321Bit 0PWSCNT0

$0046Bit 7654321Bit 0PWSCAL1

$0047Bit 7654321Bit 0PWSCNT1

$0048Bit 7654321Bit 0PWCNT0

$0049Bit 7654321Bit 0PWCNT1

$004ABit 7654321Bit 0PWCNT2

$004BBit 7654321Bit 0PWCNT3

$004CBit 7654 321Bit 0PWPER0

Address Bit 7 6 5 4 3 2 1 B it 0 Name

Table 4-1. Register Map (Sheet 2 of 10)

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Registers

Technical Data MC68HC912DG128 — Rev 3.0

Registers

$004DBit 7654 321Bit 0PWPER1

$004EBit 7654321Bit 0PWPER2

$004FBit 7654321Bit 0PWPER3

$0050Bit 7654321Bit 0PWDTY0

$0051Bit 7654321Bit 0PWDTY1

$0052Bit 7654321Bit 0PWDTY2

$0053Bit 7654321Bit 0PWDTY3

$0054 0 0 0 PSWAI CENTR RDPP PUPP PSBCK PWCTL

$0055DISCRDISCPDISCAL00000PWTST

$0056 PP7 PP6 PP5 PP4 PP3 PP2 PP1 PP0 PORTP

$0057 DDP7 DDP6 DDP5 DDP4 DDP3 DDP2 DDP1 DDP0 DDRP

$0058-

$005F 00000000Reserved

$0060 Reserved ATD0CTL0

$0061 Reserved ATD0CTL1

$0062 ADPU AFFC ASWAI 0 0 0 ASCIE ASCIF ATD0CTL2

$0063000000FRZ1FRZ0ATD0CTL3

$0064 RES10 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0 ATD0CTL4

$0065 0 S8CM SCAN MULT CD CC CB CA ATD0CTL5

$0066 SCF 0 0 0 0 CC2 CC1 CC0 ATD0STAT0

$0067 CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 ATD0STAT1

$0068 SAR9 SAR8 SAR7 SAR6 SAR5 SAR4 SAR3 SAR2 ATD0TESTH

$0069 SAR1 SAR0 RST TSTOUT TST3 TST2 TST1 TST0 ATD0TESTL

$006A–$

006E 00000000Reserved

$006F PAD07 PAD06 PAD05 PAD04 PAD03 PAD02 PAD01 PAD00 PORTAD0

$0070 Bit 15 14 13 12 11 10 9 Bit 8 ADR00H

$0071Bit 7Bit 6000000ADR00L

$0072 Bit 15 14 13 12 11 10 9 Bit 8 ADR01H

$0073Bit 7Bit 6000000ADR01L

$0074 Bit 15 14 13 12 11 10 9 Bit 8 ADR02H

$0075Bit 7Bit 6000000ADR02L

$0076 Bit 15 14 13 12 11 10 9 Bit 8 ADR03H

$0077Bit 7Bit 6000000ADR03L

$0078 Bit 15 14 13 12 11 10 9 Bit 8 ADR04H

$0079Bit 7Bit 6000000ADR04L

$007A Bit 15 14 13 12 11 10 9 Bit 8 ADR05H

$007BBit 7Bit 6000000ADR05L

$007C Bit 15 14 13 12 11 10 9 Bit 8 ADR06H

Address Bit 7 6 5 4 3 2 1 B it 0 Name

Table 4-1. Register Map (Sheet 3 of 10)

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Registers

Registe r Block

MC68HC912DG128 — Rev 3.0 Technic al Data

Registers

$007DBit 7Bit 6000000ADR06L

$007E Bit 15 14 13 12 11 10 9 Bit 8 ADR07H

$007FBit 7Bit 600 0000ADR07L

$0080 IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0 TIOS

$0081 FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0 CFORC

$0082 OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0 OC7M

$0083 OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0 OC7D

$0084 Bit 15 14 13 12 11 10 9 Bit 8 TCNT

$0085Bit 7654321Bit 0TCNT

$0086 TEN TSWAI TSBCK TFFCA Reserved TSCR

$0087 Reserved TQCR

$0088 OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4 TCTL1

$0089 OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0 TCTL2

$008A EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A TCTL3

$008B EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A TCTL4

$008C C7I C6I C5I C4I C3I C2I C1I C0I TMSK1

$008D TOI 0 PUPT RDPT TCRE PR2 PR1 PR0 TMSK2

$008E C7F C6F C5F C4F C3F C2F C1F C0F TFLG1

$008FTOF0000000TFLG2

$0090 Bit 15 14 13 12 11 10 9 Bit 8 TC0

$0091Bit 7654321Bit 0TC0

$0092 Bit 15 14 13 12 11 10 9 Bit 8 TC1

$0093Bit 7654321Bit 0TC1

$0094 Bit 15 14 13 12 11 10 9 Bit 8 TC2

$0095Bit 7654321Bit 0TC2

$0096 Bit 15 14 13 12 11 10 9 Bit 8 TC3

$0097Bit 7654321Bit 0TC3

$0098 Bit 15 14 13 12 11 10 9 Bit 8 TC4

$0099Bit 7654321Bit 0TC4

$009A Bit 15 14 13 12 11 10 9 Bit 8 TC5

$009BBit 7654321Bit 0TC5

$009C Bit 15 14 13 12 11 10 9 Bit 8 TC6

$009DBit 7654 321Bit 0TC6

$009E Bit 15 14 13 12 11 10 9 Bit 8 TC7

$009FBit 7654321Bit 0TC7

$00A0 0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI PACTL

$00A1000000PAOVFPAIFPAFLG

$00A2Bit 7654321Bit 0PACN3

Address Bit 7 6 5 4 3 2 1 B it 0 Name

Table 4-1. Register Map (Sheet 4 of 10)

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Registers

Technical Data MC68HC912DG128 — Rev 3.0

Registers

$00A3Bit 7654321Bit 0PACN2

$00A4Bit 7654321Bit 0PACN1

$00A5Bit 7654321Bit 0PACN0

$00A6 MCZI MODMC RDMCL ICLAT FLMC MCEN MCPR1 MCPR0 MCCTL

$00A7 MCZF 0 0 0 POLF3 POLF2 POLF1 POLF0 MCFLG

$00A80000PA3ENPA2ENPA1ENPA0ENICPAR

$00A9000000DLY1DLY0DLYCT

$00AA NOVW7 NOVW6 NOVW5 NOVW4 NOVW3 NOVW2 NOVW1 NOVW0 ICOVW

$00AB SH37 SH26 SH15 SH04 TFMOD PACMX BUFEN LATQ ICSYS

$00AC 00000000Reserved

$00AD 000000TCBYP0TIMTST

$00AEPT7PT6PT5PT4PT3PT2PT1PT0PORTT

$00AF DDT7 DDT6 DDT5 DDT4 DDT3 DDT2 DDT1 DDT0 DDRT

$00B0 0 PBEN 0 0 0 0 PBOVI 0 PBCTL

$00B1000000PBOVF0PBFLG

$00B2Bit 7654321Bit 0PA3H

$00B3Bit 7654321Bit 0PA2H

$00B4Bit 7654321Bit 0PA1H

$00B5Bit 7654321Bit 0PA0H

$00B6 Bit 15 14 13 12 11 10 9 Bit 8 MCCNTH

$00B7 Bit 7 6 5 4 3 2 1 Bit 0 MCCNTL

$00B8 Bit 15 14 13 12 11 10 9 Bit 8 TC0H

$00B9Bit 7654321Bit 0TC0H

$00BA Bit 15 14 13 12 11 10 9 Bit 8 TC1H

$00BBBit 7654 321Bit 0TC1H

$00BC Bit 15 14 13 12 11 10 9 Bit 8 TC2H

$00BD Bit 7 6 5 4 3 2 1 B it 0 TC2H

$00BE Bit 15 14 13 12 11 10 9 Bit 8 TC3H

$00BFBit 7654 321Bit 0TC3H

$00C0 BTST BSPL BRLD SBR12 SBR11 SBR10 SBR9 SBR8 SC0BDH

$00C1SBR7SBR6SBR5SBR4SBR3SBR2SBR1SBR0SC0BDL

$00C2 LOOPS WOMS RSRC M WAKE ILT PE PT SC0CR1

$00C3 TIE TCIE RIE ILIE TE RE RWU SBK SC0CR2

$00C4 TDRE TC RDRF IDLE OR NF FE PF SC0SR1

$00C50000000RAFSC0SR2

$00C6R8T8000000SC0DRH

$00C7 R7/T7 R6/T6 R5/T5 R4/T4 R3/T3 R2/T2 R1/T1 R0/T0 SC0DRL

$00C8 BTST BSPL BRLD SBR12 SBR11 SBR10 SBR9 SBR8 SC1BDH

Address Bit 7 6 5 4 3 2 1 B it 0 Name

Table 4-1. Register Map (Sheet 5 of 10)

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Registers

Registe r Block

MC68HC912DG128 — Rev 3.0 Technic al Data

Registers

$00C9SBR7SBR6SBR5SBR4SBR3SBR2SBR1SBR0SC1BDL

$00CA LOOPS WOMS RSRC M WAKE ILT PE PT SC1CR1

$00CB TIE TCIE RIE ILIE TE RE RWU SBK SC1CR2

$00CC TDRE TC RDRF IDLE OR NF FE PF SC1SR1

$00CD0000000RAFSC1SR2

$00CE R8 T8 0 0 0000SC1DRH

$00CF R7/T7 R6/T6 R5/T5 R4/T4 R3/T3 R2/T2 R1/T1 R0/T0 SC1DRL

$00D0 SPIE SPE SWOM MSTR CPOL CPHA SSOE LSBF SP0CR1

$00D10000PUPSRDPSSSWAISPC0SP0CR2

$00D200000SPR2SPR1SPR0SP0BR

$00D3SPIFWCOL0MODF0000SP0SR

$00D4 0 0 0 0 0 0 0 0 Reserved

$00D5Bit 7654 321Bit 0SP0DR

$00D6 PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0 PORTS

$00D7 DDS7 DDS6 DDS5 DDS4 DDS3 DDS2 DDS1 DDS0 DDRS

$00D8–$

00DF 0 0 0 0 0 0 0 0 Reserved

$00E0 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 0 IBAD

$00E1 0 0 IBC5 IBC4 IBC3 IBC2 IBC1 IBC0 IBFD

$00E2 IBEN IBIE MS/SL Tx/Rx TXAK RSTA 0 IBSWAI IBCR

$00E3 TCF IAAS IBB IBAL 0 SRW IBIF RXAK IBSR

$00E4D7D6D5D4D3D2D1D0IBDR

$00E5000RDPIB000PUPIBIBPURD

$00E6PIB7PIB6PIB5PIB4PIB3PIB2PIB1PIB0PORTIB

$00E7 DDRIB7 DDRIB6 DDRIB5 DDRIB4 DDRIB3 DDRIB2 DDRIB1 DDRIB0 DDRIB

$00E8–

$00EF Unimplemented(4) Reserved

$00F0 NOBDML NOSHB 1 Reserved EESWAI

PROTLCK

EERC EEMCR

$00F1 SHPROT 1 BPROT5 BPROT4 BPROT3 BPROT2 BPROT1 BPROT0 EEPROT

$00F2 EEODD EEVEN MARG EECPD EECPRD 0 EECPM 0 EETST

$00F3 BULKP 0 0 BYTE ROW ERASE EELAT EEPGM EEPROG

$00F40000000LOCKFEELCK

$00F50000000BOOTPFEEMCR

$00F6 FSTE GADR HVT FENLV FDISVFP VTCK STRE MWPR FEETST

$00F7 0 0 0 FESWAI SVFP ERAS LAT ENPE FEECTL

$00F8 MT07 MT06 MT05 MT04 MT03 MT02 MT01 MT00 MTST0

$00F9 MT0F MT0E MT0D MT0C MT0B MT0A MT09 MT08 MTST1

$00FA MT17 MT16 MT15 MT14 MT13 MT12 MT11 MT10 MTST2

$00FB MT1F MT1E MT1D MT1C MT1B MT1A MT19 MT18 MTST3

Address Bit 7 6 5 4 3 2 1 B it 0 Name

Table 4-1. Register Map (Sheet 6 of 10)

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Registers

Technical Data MC68HC912DG128 — Rev 3.0

Registers

$00FC PK7 0 0 0 PK3 PK2 PK1 PK0 PORTK(5)

$00FD DDK7 0 0 0 DDK3 DDK2 DDK1 DDK0 DDRK(5)

$00FE00000000Reserved

$00FF00000PIX2PIX1PIX0PPAGE

$0100 0 0 CSWAI SYNCH TLNKEN SLPAK SLPRQ SFTRES C0MCR0

$010100000LOOPBWUPMCLKSRCC0MCR1

$0102 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 C0BTR0

$0103 SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 C0BTR1

$0104 WUPIF RWRNIF TWRNIF RERRIF TERRIF BOFFIF OVRIF RXF C0RFLG

$0105 WUPIE RWRNIE TWRNIE RERRIE TERRIE BOFFIE OVRIE RXFIE C0RIER

$0106 0 ABTAK2 ABTAK1 ABTAK0 0 TXE2 TXE1 TXE0 C0TFLG

$0107 0 ABTRQ2 ABTRQ1 ABTRQ0 0 TXEIE2 TXEIE1 TXEIE0 C0TCR

$0108 0 0 IDAM1 IDAM0 0 IDHIT2 IDHIT1 IDHIT0 C0IDAC

$0109–

$010D Unimplemented(4) Reserved

$010E RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 C0RXERR

$010F TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 C0TXERR

$0110 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 C0IDAR0

$0111 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 C0IDAR1

$0112 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 C0IDAR2

$0113 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 C0IDAR3

$0114 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 C0IDMR0

$0115 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 C0IDMR1

$0116 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 C0IDMR2

$0117 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 C0IDMR3

$0118 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 C0IDAR4

$0119 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 C0IDAR5

$011A AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 C0IDAR6

$011B AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 C0IDAR7

$011C AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 C0IDMR4

$011D AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 C0IDMR5

$011EAM7AM6AM5AM4AM3AM2AM1AM0C0IDMR6

$011FAM7AM6AM5AM4AM3AM2AM1AM0C0IDMR7

$0120–

$013C Unimplemented(4) Reserved

$013D000000PUPCANRDPCANPCTLCAN0

$013E PCAN7 PCAN6 PCAN5 PCAN4 PCAN3 PCAN2 TxCAN RxCAN PORTCAN0

$013F DDCAN7 DDCAN6 DDCAN5 DDCAN4 DDCAN3 DDCAN2 0 0 DDRCAN0

Address Bit 7 6 5 4 3 2 1 B it 0 Name

Table 4-1. Register Map (Sheet 7 of 10)

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Registers

Registe r Block

MC68HC912DG128 — Rev 3.0 Technic al Data

Registers

$0140–

$014F FOREGROUND RECEIVE BUFFER 0 RxFG0

$0150–

$015F TRANSMIT BUFFER 00 Tx00

$0160–

$016F TRANSMIT BUFFER 01 Tx01

$0170–

$017F TRANSMIT BUFFER 02 Tx02

$0180–

$01DF Unimplemented(4) Reserved

$01E0 Reserved ATD1CTL0

$01E1 Reserved ATD1CTL1

$01E2 ADPU AFFC ASWAI 0 0 0 ASCIE ASCIF ATD1CTL2

$01E3000000FRZ1FRZ0ATD1CTL3

$01E4 RES10 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0 ATD1CTL4

$01E5 0 S8CM SCAN MULT CD CC CB CA ATD1CTL5

$01E6 SCF 0 0 0 0 CC2 CC1 CC0 ATD1STAT0

$01E7 CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 ATD1STAT1

$01E8SAR9SAR8SAR7SAR6SAR5SAR4SAR3SAR2ATD1TESTH

$01E9 SAR1 SAR0 RST TSTOUT TST3 TST2 TST1 TST0 ATD1TESTL

$01EA–$

01EE 0 0 0 0 0 0 0 0 Reserved

$01EF PAD17 PAD16 PAD15 PAD14 PAD13 PAD12 PAD11 PAD10 PORTAD1

$01F0 Bit 15 14 13 12 11 10 9 Bit 8 ADR10H

$01F1Bit 7Bit 600 0000ADR10L

$01F2 Bit 15 14 13 12 11 10 9 Bit 8 ADR11H

$01F3Bit 7Bit 600 0000ADR11L

$01F4 Bit 15 14 13 12 11 10 9 Bit 8 ADR12H

$01F5Bit 7Bit 600 0000ADR12L

$01F6 Bit 15 14 13 12 11 10 9 Bit 8 ADR13H

$01F7Bit 7Bit 600 0000ADR13L

$01F8 Bit 15 14 13 12 11 10 9 Bit 8 ADR14H

$01F9Bit 7Bit 600 0000ADR14L

$01FA Bit 15 14 13 12 11 10 9 Bit 8 ADR15H

$01FBBit 7Bit 6000000ADR15L

$01FC Bit 15 14 13 12 11 10 9 Bit 8 ADR16H

$01FDBit 7Bit 6000000ADR16L

$01FE Bit 15 14 13 12 11 10 9 Bit 8 ADR17H

$01FFBit 7Bit 600 0000ADR17L

Address Bit 7 6 5 4 3 2 1 B it 0 Name

Table 4-1. Register Map (Sheet 8 of 10)

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Registers

Technical Data MC68HC912DG128 — Rev 3.0

Registers

$0200-

$02FF Unimplemented(4) Reserved

$0300 0 0 CSWAI SYNCH TLNKEN SLPAK SLPRQ SFTRES C1MCR0

$030100000LOOPBWUPMCLKSRCC1MCR1

$0302 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 C1BTR0

$0303 SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 C1BTR1

$0304 WUPIF RWRNIF TWRNIF RERRIF TERRIF BOFFIF OVRIF RXF C1RFLG

$0305 WUPIE RWRNIE TWRNIE RERRIE TERRIE BOFFIE OVRIE RXFIE C1RIER

$0306 0 ABTAK2 ABTAK1 ABTAK0 0 TXE2 TXE1 TXE0 C1TFLG

$0307 0 ABTRQ2 ABTRQ1 ABTRQ0 0 TXEIE2 TXEIE1 TXEIE0 C1TCR

$0308 0 0 IDAM1 IDAM0 0 IDHIT2 IDHIT1 IDHIT0 C1IDAC

$0309–

$030D Unimplemented(4) Reserved

$030E RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 C1RXERR

$030F TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 C1TXERR

$0310 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 C1IDAR0

$0311 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 C1IDAR1

$0312 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 C1IDAR2

$0313 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 C1IDAR3

$0314AM7AM6AM5AM4AM3AM2AM1AM0C1IDMR0

$0315AM7AM6AM5AM4AM3AM2AM1AM0C1IDMR1

$0316AM7AM6AM5AM4AM3AM2AM1AM0C1IDMR2

$0317AM7AM6AM5AM4AM3AM2AM1AM0C1IDMR3

$0318 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 C1IDAR4

$0319 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 C1IDAR5

$031A AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 C1IDAR6

Address Bit 7 6 5 4 3 2 1 B it 0 Name

Table 4-1. Register Map (Sheet 9 of 10)

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Registers

Technical Data MC68HC912DG128 — Rev 3.0

Registers

$031B AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 C1IDAR7

$031CAM7AM6AM5AM4AM3AM2AM1AM0C1IDMR4

$031DAM7AM6AM5AM4AM3AM2AM1AM0C1IDMR5

$031E AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 C1IDMR6

$031FAM7AM6AM5AM4AM3AM2AM1AM0C1IDMR7

$0320–

$033C Unimplemented(4) Reserved

$033D000000PUPCANRDPCANPCTLCAN1

$033E PCAN7 PCAN6 PCAN5 PCAN4 PCAN3 PCAN2 TxCAN RxCAN PORTCAN1

$033F DDCAN7 DDCAN6 DDCAN5 DDCAN4 DDCAN3 DDCAN2 0 0 DDRCAN1

$0340–

$034F FOREGROUND RECEIVE BUFFER 1 RxFG1

$0350–

$035F TRANSMIT BUFFER 10 Tx10

$0360–

$036F TRANSMIT BUFFER 11 Tx11

$0370–

$037F TRANSMIT BUFFER 12 Tx12

$0380-

$03FF Unimplemented(4) Reserved

= Reserved or unimplem ented bits.

1. Port A, port B and data direction registers DDRA, DDRB are not in map in expanded and peripheral modes.

2. Port E and DDRE not in the map in peripheral and expanded modes with EME set.

3. Registers also not in map in peripheral mode.

4. Data read at these locati ons is undefined.

5. Port K and DDRK not in the map in peripheral and expanded modes with EMK set.

Address Bit 7 6 5 4 3 2 1 B it 0 Name

Table 4-1. Register Map (Sheet 10 of 10)

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Registers

Technical Data MC68HC912DG128 — Rev 3.0

Registers

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MC68HC912DG128 — Rev 3.0 Technic al Data
Operating Modes
 
Technical Data — MC68HC912DG128
Section 5. Operating Modes
5.1  Contents
5.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
5.3 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
5.4 Background Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
5.5 Internal Resource Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . .81
5.6 Memory Maps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
5.2  Introduction
Eight possible operating modes determine the operating configuration of 
the MC68HC912DG128. Each mode has an associated default memory 
map and e xternal bus configuration.  After reset, most system resour ces 
can be mapped to other addresses by writing to the appropriate control 
registers.
5.3  Operating Modes
The operating mode out of reset is determined by the states of the 
BKGD, MODB, and MODA pins during reset.
The SMODN, MODB, and MODA bits in the MODE register show current 
operating mode and pro vide limited mode switching duri ng operation.  
The states of th e BKGD, M ODB, and MOD A pins are la tched into the se 
bits on the rising edge of the reset signal.
In expanded modes, all address space not used by internal resource s is 
by default external m emory.
    
  
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Operating Modes

Technical Data MC68HC912DG128 — Rev 3.0

Operating Modes

There are two basic types of operating modes:

Normal modes — some registers and bits are protected

against accidental changes.

Special modes — allow greater access to pr otected cont rol

registers and bits for s pecial purpose s such as testing and

emulation.

For op eration abov e 105°C, the MC68HC912DG128 (M temperature

range product only) is limited to single chip modes of operation.

A system development and debug feature, background debug mode

(BDM), is available in all modes. In special single-chip mode, BDM is

active immediately after reset.

5.3.1 Normal Operating Modes

These modes provide three operating configurations. Background

debugging is available in all three modes, but must first be enabled for

some operations by means of a BDM background command, then

activated.

Table 5-1. Mode Selection

BKGD MODB MODA Mode Port A Port B

1 0 0 Normal Single Chip G.P. I/O G.P. I/O

1 0 1 Normal Expanded Narrow ADDR/DATA ADDR

110 Reserved (Forced to

Peripheral) ——

1 1 1 Normal Expanded Wide ADDR/DATA ADDR/DATA

0 0 0 Special Single Chip G.P. I/O G.P. I/O

0 0 1 Special Expanded Narrow ADDR/DATA ADDR

0 1 0 Special Peripheral ADDR/DATA ADDR/DATA

0 1 1 Spec ial Expan ded Wide ADDR/DATA ADDR/DATA

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Operating Modes

MC68HC912DG128 — Rev 3.0 Technic al Data

Operating Modes

Normal Single-Chip Mode — There are no external address

and data buses in this mode. The MCU operates as a stand-

alone device a nd al l pro gram an d dat a reso urces are on- chip .

External port pins normally associated with address and data

buses can be us ed for general-purpose I/O .

Normal Expanded Wide Mode — This is a normal mode of

operation in which the expanded bus is present with a 16-bit

data bus. Ports A and B are used for the 16-bit multiplexed

addre ss/da ta bus.

Normal Expanded Narrow Mode — This is a normal mode of

operation in which the expanded bus is present with an 8-bit

data bus. Ports A and B are used for the16-bit address bus.

Port A is use d as t he da ta bu s, multi ple xed w ith add resse s. In

this mode, 16-bit data is presented one byte at a time, the high

byte followed by the low byte. Th e address is autom atically

incremented on the second cycle.

5.3.2 Special Operating Modes

There are three special operating modes that correspond to normal

operating modes. These operating modes are commonly used in factory

testing and system development. In addition, there is a special

peripheral mode, in which an external master, such as an I.C. tester, can

control the on-chip peripherals.

Special Single-Chip Mode — This mode can be used to force

the MCU to active BDM mode to allow system debug through

the BKGD pin. There are no external address and data buses

in this m ode. The M CU oper at es as a stand- alon e device and

all program and data sp ace are on-chip. Ext ernal port pins can

be used for general-purpose I/O.

Special Expanded Wide Mode — Th is mode can be used fo r

emulation of normal expanded wide mode and emulation of

normal single-chip mode. Ports A and B are used for the 16-bit

multiplexed address/data bus.

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Operating Modes

Technical Data MC68HC912DG128 — Rev 3.0

Operating Modes

Special Expanded Narrow Mode — Th i s m ode can be use d

for emulation of normal expanded narrow mode. Ports A and B

are used for the 16-bi t address bu s. Port A i s used as th e data

bus, multiplexed with addresses. In this mode, 16-bit data is

presented one byte at a time, the high byte followed by the low

byte. The address is automa tically incremented on the second

cycle.

Special Peripheral Mode — The CPU is not active in this

mode. An external master can control on-chip peripherals for

testing purposes. It is not possible to change to or from this

mode without going through reset. Background debugging

should not be used while the MCU is in sp ecial peripheral

mode as inte rnal bu s conflic ts betwee n BDM and the exter nal

master can cause improper operation of both modes.

5.4 Background Debug Mode

Background debug mode (BDM) is an auxiliary operating mode that is

used for system development. BDM is implemented in on-chip hardware

and pr ovides a fu ll set of deb ug operati ons. Some BD M comman ds can

be executed while the CPU is operating normally. Other BDM

commands are firmware based, and require the BDM firmware to be

enabled and active for execution.

Bit 7654321Bit 0

SMODN MODB MODA ESTR IVIS EBSWAI EMK EME

RESET:00011011Special Single Chip

RESET:00111011Special Exp Nar

RESET:01011011Peripheral

RESET:01111011Special Exp Wide

RESET:10010000Normal Single Chip

RESET:10110000Normal Exp Nar

RESET:11110000Normal Exp Wide

MODE — Mode Register $000B

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Operating Modes

Background Debug Mode

MC68HC912DG128 — Rev 3.0 Technic al Data

Operating Modes

In special single-chip mode, BDM is enabled and active immediately out

of res et. BD M is available in all other operating modes, but must be

enabled before it can be activated. BDM should not be used in special

peripheral mode because of potential bus conflicts.

Once enabled, background mode can be made active by a serial

command sent via the BKGD pin or execution of a CPU12 BGND

instruction. While background mode is active, the CPU can interpret

specia l debugging commands, and read and write CPU registers,

periph eral registers, and loca tions in memory.

While BD M is act ive, t he CPU e xecut es code l ocated i n a sma ll on-ch ip

ROM mapped to addresses $FF20 to $FFFF, and BDM control registers

are accessible at addresses $FF00 to $FF06. The BDM ROM replaces

the regular system vectors while BDM is active. While BDM is active, the

user memory from $FF00 to $FFFF is not in the map except through

serial BDM commands.

The MODE register controls the MCU operating mode and various

configuration options. This register is not in the map in peripheral mode

SMODN, MODB, MODA — Mode Select Special, B and A

These bits sho w the current op eratin g mode an d refl ect the statu s of

the BKGD, MODB and MODA input pins at the rising edge of reset.

SMODN is Read a nytime. May only be written in special modes

(SMODN = 0). The first write is ignored;

Bit 7654321Bit 0

SMODN MODB MODA ESTR IVIS EBSWAI 0 EME

RESET: 00011001Special Single Chip

RESET: 00111001Special Exp Nar

RESET: 01011001Peripheral

RESET: 01111001Special Exp Wide

RESET: 10010000Normal Single Chip

RESET: 10110000Normal Exp Nar

RESET: 11110000Normal Exp Wide

MODE — Mode Register $000B

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Operating Modes

Technical Data MC68HC912DG128 — Rev 3.0

Operating Modes

MODB, MODA may be written once in Normal modes (SMODN = 1).

Write anytime in sp ecial modes (first write is ign ored) – special

peripheral and reserved modes cannot be selected.

ESTR — E Clock Stretch Enable

Determines if the E Clock behaves as a simple free-running clock or

as a bus control signal that is active only for external bus cycles.

ESTR is always one in expanded modes since it is required for

addres s and da ta bus de-multiplexing and must follow stretched

cycles.

0 = E never stretches (always free running).

1 = E stretches high during external access cycles and low during

non-visible internal accesses (IVIS = 0).

Normal modes: write once; Specia l modes: write anytime. Read

anytime.

IVIS — Internal Visi bility

This bit determine s wheth er int ernal AD DR, DATA, R/W an d L STR B

signals can be seen on the external bus during accesses to internal

locations. In Special Narrow Mode if this bit is set and an internal

access occurs the data will appear wide on Ports A and B. This serves

the same function as the EMD bit of the non-multiplexed versions of

the HC12 and allows for emulation. Visibility is not available when the

part is operating in a single-chip mode.

0 = No visibility of interna l bus operations on external bus.

1 = Interna l bus oper ati o ns are visibl e on exte rn al bus.

Normal modes: write once; Specia l modes: write anytime EXCEPT

the first time. Read anytime.

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MC68HC912DG128 — Rev 3.0 Technic al Data

Operating Modes

EBSWAI — External Bus Module Stop in Wait Control

This bit contro ls access to the externa l bus interface wh en in wait

mode. The modul e will delay before shutting down in wait mode to

allow for final bus activity to complete.

0 = Ext ernal bus and registers continue func tioning durin g wait

mode.

1 = External bus is shut down during wait mode.

Normal modes: write anytime; spec ial modes: write never. Read

anytime.

EMK — Emulate Port K

In single-chip mod e PORTK a nd DDRK are always in the map

regardless of the state of this bit.

0 = Port K and DDR K re gi ste rs are in the mem o ry ma p. Me mory

expansion emulation is disabled and all pins are general

purpose I/O.

1 = In expanded or peripheral mode, PORTK and DDRK are

removed from the internal memory map. Removing these

of these registers externally.

Normal modes: write once; special modes: write anytime EXCEPT

the first time. Read anytime.

5.5 Internal Resource Mapping

The internal register block, RAM, and EEPROM have default locations

within the 64K byte stand ard address space but may be reass i gned to

other locations during program execution by setting bits in mapping

registers INITRG, INITRM, and INITEE. During normal operating modes

these r egister s can be written once . It is advisa ble to ex plicit ly establi sh

these resource locations during the initialization phase of program

execution, even if default values are c hosen, in ord er to protect the

registers from inadvertent modification later.

Writes to the mapping registers go into effect between the cycle that

follows the write and the cycle after that. To assure that there are no

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Technical Data MC68HC912DG128 — Rev 3.0

Operating Modes

unintended operations, a write to one of these registers should be

followed with a NOP instruction.

If conflicts occur when mapping resources, the register block will take

precedence over the other resources; RAM or EEPROM addresses

occupied by the register block will not be available for storage. When

active, BDM ROM takes precedence over other resources, although a

conflict between BDM ROM and register space is not possible. The

following table shows resource mapping precedence.

The MC68HC912DG128 contains 128K bytes of Flash EEPROM

nonvolatile memory which can be used to store program code or static

data. This physical memory comprises four 32k byte array modules,

00FEE32K, 01FEE32K, 10FEE32K and 11FEE32K. The 32K byte array

11FEE32K has a fixed location from $4000 to $7FFF and $C000 to

$FFFF. The three 32K by te arra ys 00FEE32K, 01FEE32K an d

10FEE32K ar e accessible through a 16K byt e program page window

mapped from $8000 to $BFFF. The fixed 32K byte array 11FEE32K can

also be accessed through the program page window..

5.5.1 Register Block Mapping

After reset the 1K byte register block resides at location $0000 but can

be reassigned to any 2K byte boundary within the standard 64K byte

addre ss spa ce. Ma ppi n g o f inte r nal r egi ster s is co ntr oll ed by five bit s i n

the INITRG register. The registe r block occu pies the first 1K byte bytes

of the 2K byte block.

Table 5-2. Mapping Precedence

Precedence Resource

1 BDM ROM (if active)

2 Register Space

3RAM

4EEPROM

5 On-Chip Flash EEPROM

6 External Memory

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Internal Resource Mapping

MC68HC912DG128 — Rev 3.0 Technic al Data

Operating Modes

REG[15:11] — Internal register map position

These bits specify the upper five bits of the 16-bit registers address.

Normal modes: write once; special modes: write anytime. Re ad

anytime.

MMSWAI — Memory Mapping Interface Stop in Wait Control

This bit controls access to the me mory mapping interface when in

Wait mode.

Normal modes: write anytime; spec ial modes: write never. Read

anytime.

0 = Memory mapping interface cont inues to functi on during Wait

mode.

1 = Memory mapping interface acces s is shut down dur i ng Wait

mode.

5.5.2 RAM Mapping

The MC68HC912DG128 has 8K bytes of fully static RAM that is used for

storing instructions, variables, and temporary data during program

execution. Since the RAM is actually implemented with two 4K RAM

arrays, any misaligned word access between last address of first 4K

RAM and first address of second 4K RAM will take two cycles instead of

one. After reset, RAM addressing begins at location $2000 but can be

assigned to any 8K byte boundary within the standard 64K byte address

space. Mapping of internal RAM is controlled by three bits in the INITRM

INITRG — Initialization of Internal Register Position Register $0011

Bit 7654321Bit 0

REG15 REG14 REG13 REG12 REG11 0 0 MMSWAI

RESET: 0 0000000

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Technical Data MC68HC912DG128 — Rev 3.0

Operating Modes

RAM[15:13] — Internal RAM map position

These bits specify the upper three bits of the 16-bit RAM address.

Normal modes: write once; special modes: write anytime. Re ad

anytime.

5.5.3 EEPROM Mapping

The MC68HC912DG128 has 2K bytes of EEPROM which is activated by

the EEON bit in the INITEE register. Mapping of internal EEPROM is

controlled by four bits in the INITEE register. After reset EEPROM

address space begins at location $0800 but can be mapped to any 4K

byte bounda ry withi n the standard 64K b yte address space. The

EEPROM block occupies the last 2K bytes of the 4K byte block.

EE[15:12] — Internal EEPROM map position

These bi ts specify th e upper f our bits of t he 16-bit EEPRO M address.

Normal modes: write once; special modes: write anytime. Re ad

anytime.

EEON — internal EEPROM On (Enabled)

This bit is forc ed to one in single-chip mo des.

Read or wr ite anytime.

0 = Removes the EEPROM from the map.

1 = Places the on-chip EEPROM in the memory map at the address

selected by EE[15:12].

INITRM — Initialization of Internal RAM Position Register $0010

Bit 7654321Bit 0

RAM15 RAM14 RAM13 0 0 0 0 0

RESET: 0 0100000

INITEE— Initialization of Internal EEPROM Position Register $0012

Bit 7654321Bit 0

EE15 EE14 EE13 EE12 0 0 0 EEON

RESET: 0 0000001

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Internal Resource Mapping

MC68HC912DG128 — Rev 3.0 Technic al Data

Operating Modes

5.5.4 Flash EEPROM mapping through internal Memory Expansion

The Page Index register or PPAGE provides memory management for

the MC68HC912DG128. PPAGE consists of three bits to indicate which

physical location is active within the windows of the MC68HC912DG128.

The MC68HC912DG128 has a user’s program space window, a register

space window for Flash mo dule regi sters , and a t es t prog ram space

window.

The user’s program page window consists of 16K Flash EEPROM bytes.

One of eight pages is viewed through this window for a total of 128K

accessible Flash EEPR OM byte s.

On the MC68HC912DG128, the regi ster space window consists of a 4-

byte register block. One of four pages is viewed through this window for

each of the 32K flash module register blocks of MC68HC912DG128.

The test mode prog ra m pag e wi n dow consis t s of 32K Flash EEPR OM

bytes. One of the fou r 32K byte arra ys is viewed through this window for

a total 128K accessible Flash EEPROM bytes. This window is only

available in special mode for test purposes and replaces the user’s

program page window.

MC68H C 912DG128 h as a fi ve pin port, Port K, for emulation and for

general purpose I/O. Three pins are used to emulate the three page

indices (PPAGE bits) and one pin is used as an emulation chip select.

When these four pins are not used for emulation they serve as general

purpose I/O pins. The fifth Port K pin is used as a general purpose I/O

pin.

5.5.5 Program space expansion

There are 128K bytes of Flash EEPROM. With a 64K byte address

space, the PPAGE register is needed to perform on-chip memory

expansion. A program space window of 16K byte pages is located from

$8000 to $BFFF. Three page indices are used to point to one of eight

different 16K byte pages. They can be viewed as expanded addresses

x16, x15 and x14.

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Technical Data MC68HC912DG128 — Rev 3.0

Operating Modes

* The 16K byte program space page 6 can also be accessed at a fixed

location from $4000 to $7FFF. The 16K byte program space page 7 can

also be accessed at a fixed location from $C000 to $FFFF.

5.5.6 Flash register space expansion

There are four 32K Flash arrays for MC68HC912DG128 and each

requires a 4-byte register bloc k. A register space wi ndow i s used t o

access one of the four 4-byte blocks and the PPAGE register to map

each one into the w indow . The register space window is located from

$00F4 to $00F7 after reset. Only two page indices are used to point to

one of the four pages of the register space.

Table 5-3. Program space Page Index

Page Index 2

(PPAGE bit 2 ) Page Index 1

(PPAGE bit 1) Page Index 0

(PPAGE bit 0 ) 16K Program space Page Flash array

0 0 0 16K byte Page 0 00FEE32K

0 0 1 16K byte Page 1 00FEE32K

0 1 0 16K byte Page 2 01FEE32K

0 1 1 16K byte Page 3 01FEE32K

1 0 0 16K byte Page 4 10FEE32K

1 0 1 16K byte Page 5 10FEE32K

1 1 0 16K byte Page 6* 11FEE32K

1 1 1 16K byte Page 7* 11FEE32K

Table 5-4. Flash Register space Page Index

Page Index 2

(PPAGE bit 2) Page Index 1

(PPAGE bit 1) Page Index 0

(PPAGE bit 0 ) Flash register space Page Flash array

0 0 X $00F4-$00F7 Page 0 00FEE32K

0 1 X $00F4-$00F7 Page 1 01FEE32K

1 0 X $00F4-$00F7 Page 2 10FEE32K

1 1 X $00F4-$00F7 Page 3 11FEE32K

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Internal Resource Mapping

MC68HC912DG128 — Rev 3.0 Technic al Data

Operating Modes

5.5.7 Test mode Program space expansion

In special mode and f or test purpo ses only, the 128K b ytes of Flash

EEPROM can be accessed through a test program space window of 32K

bytes . This window replaces the us er ’s program space window to be

able to access an entire array. In special mode and with ROMTST bit set

in MISC register, a program space is located from $8000 to $FFFF. Only

two page indices are used to point to one of the four 32K byte arrays.

They can be viewed as expanded addresses X16 and X15.

5.5.8 Page Index register descriptions

Read and write anytime

Writing to the port does not change the pin states when it is configured

for page index emulation output.

This port is associated with the page index emulation pins. When the

port is not enabled to emulate page index, the port pins are used as

general-purpose I/O. Port K bit 3 is always a general purpose I/O pin.

This re gister is not in the memory map in pe ripheral or expanded modes

when the EMK control bit in MODE register is set.

Table 5-5. Test mode program space Page Index

Page Index 2

(PPAGE bit 2) Page Index 1

(PPAGE bit 1 ) Page Index 0

(PPAGE bit 0 ) Flash register space Page Flash array

0 0 X 32K byte array Page 0 00FEE32K

0 1 X 32K byte array Page 1 01FEE32K

1 0 X 32K byte array Page 2 10FEE32K

1 1 X 32K byte array Page 3 11FEE32K

PORTK — Port K Data Register $00FC

Bit 7 6 5 4 3 2 1 Bit 0

PORT PK7 0 0 0 PK3 PK2 PK1 PK0

Emulation ECS 0 0 0 - PIX2 PIX1 PIX0

RESET: - 0 0 0 - - - -

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Technical Data MC68HC912DG128 — Rev 3.0

Operating Modes

When selected as inputs, these pins can be configured to be high

impedance or pulled up.

ECS — Emulation Chip Select of selected p rogram space

When this signal is active low it indicates that the program space is

accessed. Th is also a pplies t o te st mode pro gram spac e. A n access

is mad e if an ad dr ess is in the pro gram sp ace w ind ow an d ei the r the

Flash or external memory is accessed. The ECS timing is E clock high

and can be stretched when accessing external memory depending on

the EXTR0 and EXTR1 bits in the MISC register. The ECS signal is

only active when the EMK bit is set.

PIX[2:0] — The content of the PPAGE register emulated externally.

This content indicates which Flash module register space is in the

memory map and which 16K byte Flash memory is in the program

space. In special mode and with ROMTST bit set, the content of the

Page Index register indicates which 32K byte Flash array is in the test

prog ram spac e.

Read and write: anytime.

This register determines the primary direction for each port K pin

configured as general-purpose I/O.

0 = Associated pin is a high-impedance input.

1 = Associated pin is an output.

This register is not in the map in peripheral or expanded modes when the

EMK control bit is set.

DDRK — Port K Data Direction Register $00FD

Bit 7 6 5 4 3 2 1 Bit 0

DDK7 0 0 0 DDK3 DDK2 DDK1 DDK0

RESET: 0 0 0 0 0 0 0 0

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Internal Resource Mapping

MC68HC912DG128 — Rev 3.0 Technic al Data

Operating Modes

Read and write: anytime.

This register determines the active page viewed through

MC68H C 912DG128 win dows.

CALL and RTC instructions have a special single wire mechanism to

read and write this register without us ing an add r ess bus.

5.5.9 Miscellaneous Sy stem Control Re gister

Additional mapping and external resource controls are available. To use

exte rnal resources the part must be operated in one of the ex panded

modes.

Normal modes: write once; Specia l modes: write anytime. Read

anytime.

ROMTST — FLASH EEPROM Test mode

In normal modes, this bit is forced to zero.

0 = 16K window for Flash memory is located from $8000–$BFFF

1 = 32K window for Flash memory is located from $8000–$FFFF

PPAGE — (Program) Page Index Register $00FF

Bit 7 6 5 4 3 2 1 Bit 0

0 0 0 0 0 PIX2 PIX1 PIX0

RESET: 0 0 0 0 0 0 0 0

MISC — Miscellaneous Mapping Control Register $0013

Bit 7654321Bit 0Mode

ROMTST NDRF RFSTR1 RFSTR0 EXSTR1 EXSTR0 ROMHM ROMON

RESET: 0 0 0 0 1 1 0 0 Exp mode

RESET: 0 0 0 0 1 1 0 1 peripheral or

SC mode

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Operating Modes

Technical Data MC68HC912DG128 — Rev 3.0

Operating Modes

NDRF — Narrow Data Bus for Register-Following Map Space

This bit enab les a narrow bus feature for the 1K 512 byte Regis ter-

Following Map. This is useful for accessing 8-bit peripherals and

allows 8-bit and 16-bit external memory devices to be mixed in a

system. In Expanded Narrow (eight bit) modes, Single Chip Modes,

and Peripheral mode, this bit has no effect.

0 = Makes Register-Following MAP space act as a full 16 bit data bus.

1 = Makes the Re giste r -Following MAP space act the same as an 8

bit only external data bus (data only goes through port A externally).

The Register-Following space is mapped from $0400 to $07FF after

reset, which is next to the register map. If the registers are moved this

space follows.

RFSTR1, RFSTR0 — Register Following Stretch

This two bit field de termines the amount of clock stretch on accesses

to the 1K byte Register Following Map. It is valid regardless of the

state of the NDRF bit. In Single Chip and Periphe r al Modes this bit

has no mean ing or effect.

Table 5 -6 . RFSTR Stret ch Bit Definition

RFSTR1 RFSTR0 Number of E Clocks

Stretched

00 0

01 1

10 2

11 3

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Operating Modes

Internal Resource Mapping

MC68HC912DG128 — Rev 3.0 Technic al Data

Operating Modes

EXSTR1, EXSTR0 — External Access Stretch

This two bit field de termines the amount of clock stretch on accesses

to the Ext ernal Add ress Space. In Single Chip and P eripher al Modes

this bit has no me an ing or effect.

ROMHM — FLASH EEPROM only in second Half of Map

This bit has no mean i ng if ROMON bit is clear.

0 = The 16K byte of fixed Flash EEPROM in location $4000–$7FFF

can be accessed.

1 = Disables direct access to 16K byte Flash EEPROM from

$4000–$7FFF in the memo ry ma p. The physical locati on of

this16K byte Flash can still be accessed through the Program

Page window.

In special mode, with ROMTST bit set, this bit will allow overlap of the

four 32K Flash EEPROM arrays and overlap the four 4-byte Flash

at the same time.

0 = The four 32K Flash arrays are accessed with four pages for

each.

1 = The four 32 K Flash arrays coincide i n the sa me space and are

selected at the same time for programming.

CAUTION: Bit must be cleared before reading any of the arrays or registers.

ROMON — Enable FLASH EEPROM

These bits are used to enable the Flash EEPR OM

0 = Disables Fla s h EEP ROM in the mem o ry ma p.

1 = Enables Flash EEPROM in the memory map.

Table 5 -7 . EXSTR Stre tch Bit Definition

EXSTR1 EXSTR0 Number of E Clocks

Stretched

00 0

01 1

10 2

11 3

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Operating Modes

Technical Data MC68HC912DG128 — Rev 3.0

Operating Modes

5.5.10 Mapping test registers

These registers are used for testing the mapping logic. They can only be

read and after each read they get cleared. A write to each register will

have no effect.

MTST0 — Mapping Test Register 0 $00F8

Bit 7654321Bit 0

MT07 MT06 MT05 MT04 MT03 MT02 MT01 MT00

RESET: 00000000

MTST1 — Mapping Test Register 1 $00F9

Bit 7654321Bit 0

MT0F MT0E MT0D MT0C MT0B MT0A MT09 MT08

RESET: 00000000

MTST2 — Mapping Test Register 2 $00FA

Bit 7654321Bit 0

MT17 MT16 MT15 MT14 MT13 MT12 MT11 MT10

RESET: 0 0 0 00000

MTST3 — Mapping Test Register 3 $00FB

Bit 7654321Bit 0

MT1F MT1E MT1D MT1C MT1B MT1A MT19 MT18

RESET: 0 0 0 00000

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Operating Modes

Memory Maps

MC68HC912DG128 — Rev 3.0 Technic al Data

Operating Modes

5.6 Memory Maps

The following diagrams illustrate the memory map for each mode of

operation immediately after reset.

Figure 5-1. Memory Map after reset

The following diagram illustrates the memory paging scheme.

$03FF REGISTERS

(MAPPABLE TO ANY 2K SPACE)

8K bytes RAM

(MAPPABLE TO ANY 8K SPACE)

EXPANDEDNORMAL

SINGLE CHIP SPECIAL

SINGLE CHIP

$0000

$3FFF

$2000

2K bytes EEPROM

(MAPPABLE TO ANY 4K SPACE)

$0FFF

$0800

VECTORSVECTORSVECTORS

BDM

(if active)

$FFFF

$FF00

16K Page Window

Eight 16K Flash EEPROM pages

$BFFF

$8000

EXT

$A000 - $BFFF Pro tec ted BOOT

at odd programing pages

$0000

$2000

$0800

$1000

$8000

$FF00

$FFFF

$0400

16K Fixed Flash EEPROM

$4000

16K Fixed Flash EEPROM

$FFFF

$C000

$E000 - $FFFF Protected BOOT

$4000

$C000

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Operating Modes

Technical Data MC68HC912DG128 — Rev 3.0

Operating Modes

Figure 5-2. Memory Paging

* This 32K Flash

accessible as

pages 6 & 7 and

as unpaged

$4000 - $7FFF &

$C000 - $FFFF

NORMAL

SINGLE CHIP

00 Flash 32K

VECTORS

One 16K Page accessible at a time (selected by PPAGE value = 0 to 7)

$0000

$2000

$0800

$1000

$8000

$FF00

$FFFF

$0400

16K Flash

(Unpaged)

$4000

$C000

1234567

01 Flash 32K 10 Flash 32K 11 Flash 32K *

16K Flash

(Unpaged)

16K Flash

(Paged)

(8K Boot)

(8K Boot) (8K Boot) (8K Boot) (8K Boot)

$E000

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MC68HC912DG128 — Rev 3.0 Technic al Data
Bus Control and Input/Output
 
Technical Data — MC68HC912DG128
Section 6. Bus Control and Input/Output
6.1  Contents
6.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
6.3 Detecting Access Type from External Signals . . . . . . . . . . . . .95
6.4 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
6.2  Introduction
Internally the MC68HC912DG128 has full 16-bit data paths, but 
depending upon the operating mode and control registers, the external 
multip le xed  bus may be 8 or 16 bits. Ther e ar e cases wh er e 8-bi t and  
16-bit accesses ca n appe ar on adjacent  cycles using  the LS TRB si gnal  
to indicate 8- or 16-bit data.
It is possible to have a mix of 8 and 16 bit peripherals attached to the 
external multiplexed bus, using the NDRF bit in the MISC register while 
in expand ed  wi de mo de s.
6.3  Detecting Access Type from External Signals
The external signals LSTRB, R/W, and A0 can be used to determine the 
type of bus access that is taking place. Accesses to the internal RAM 
module are the only type of access that produce LSTRB =A0=1, 
because the internal RAM is specifically designed to allow misaligned 
16-bit accesses in a single cycle. In these cases the data for the address 
    
  
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Bus Control and Input/Output

Technical Data MC68HC912DG128 — Rev 3.0

Bus Control and Input/Output

that was accessed is on the low half of the data bus and the data for

address + 1 is on the high half of the data bus.

6.4 Registers

Not all registers are visible in the MC68HC912DG128 memory map

under certain conditions. In special peripheral mode the first 16 registers

associated with bus expansion are removed from the memory map.

In expanded modes, some or all of po rt A, port B, and port E are used

for expansion buses and control signals. In order to allow emulation of

the single-chip functions of these ports, some of these registers must be

rebuilt in an external port replacement unit. In any expanded mode, port

A, and p ort B, ar e used fo r address a nd data lines so r egisters for these

ports, as well as the data direction registers for these ports, are removed

from the on-chip memory map and become external accesses.

In any expanded mode, port E pins may be needed for bus control (e.g.,

ECLK , R/W). To regain the single-chip functions of port E, the emulate

port E (EME) control bit in the MODE register may be set. In this special

case of exp anded mo de and EM E set, PORTE and DDRE register s are

removed from the on-chip memory map and become external accesses

so port E may be rebuilt externally.

Figure 6-1. Access Type vs. Bus Control Pins

LSTRB A0 R/W Type of Access

1 0 1 8-bit read of an even address

0 1 1 8-bit read of an odd address

1 0 0 8-bit write of an even address

0 1 0 8-bit write of an odd address

0 0 1 16-bit read of an even address

111

16-bit read of an odd address

(low/high data swapped)

0 0 0 16-bit write to an even address

110

16-bit write to an even address

(low/high data swapped)

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Bus Control and Input/Output

Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

Bus Control and Input/Output

Bits PA[7:0] are associated respectively with addresses ADDR[15:8],

DATA[15 :8] and D ATA[7:0], in n arrow mo de. When this port i s not used

for external addresses such as in single-chip mode, these pins can be

used as general-purpose I/O. DDRA determines the primary direction of

each pin. This register is not in the on-chi p map in expanded an d

peripheral modes. Read and write anytime.

This register determines the primary direction for each port A pin when

functioning as a general-purpose I/O port. DDRA is not in the on-chip

map in expanded and peripheral modes. Read and write anytime.

0 = Associated pin is a high-impedance input

1 = Associated pin is an output

Bit 7654321Bit 0

Single Chip PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0

RESET: ————————

Expanded

& Periph: ADDR15/

DATA15 ADDR14/

DATA14 ADDR13/

DATA13 ADDR12/

DATA12 ADDR11/

DATA11 ADDR10/

DATA10 ADDR9/

DATA9 ADDR8/

DATA8

Expanded

narrow ADDR15/

DATA15/

DATA7

ADDR14/

DATA14/

DATA6

ADDR13/

DATA13/

DATA5

ADDR12/

DATA12/

DATA4

ADDR11/

DATA11/

DATA3

ADDR10/

DATA10/

DATA2

ADDR9/

DATA9/

DATA1

ADDR8/

DATA8/

DATA0

PORTA — Port A Register $0000

Bit 765432 1Bit 0

DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0

RESET: 0 0 0 0 0 0 0 0

DDRA — Port A Data Direction Register $0002

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Bus Control and Input/Output

Technical Data MC68HC912DG128 — Rev 3.0

Bus Control and Input/Output

Bits PB[7:0] are associa ted with addresses ADDR[7:0] and DATA[7:0]

(except in narrow mode) respectively. When this port is not used for

external addresses such as in single-chip mode, these pins can be used

as general-purpose I/O. DDRB determines the primary direction of each

pin. This register is not in the on-chip map in expanded and peripheral

modes. R ead and wr i te anyti me .

This register determines the primary direction for each port B pin when

functioning as a general-purpose I/O port. DDRB is not in the on-chip

map in expanded and peripheral modes. Read and write anytime.

0 = Associated pin is a high-impedance input

1 = Associated pin is an output

Bit 7654321Bit 0

Single Chip PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0

RESET: ————————

Expanded

& Periph: ADDR7/

DATA7 ADDR6/

DATA6 ADDR5/

DATA5 ADDR4/

DATA4 ADDR3/

DATA3 ADDR2/

DATA2 ADDR1/

DATA1 ADDR0/

DATA0

Expanded

narrow ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0

PORTB — Port B Register $0001

Bit 765432 1Bit 0

DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0

RESET: 0 0 0 0 0 0 0 0

DDRB — Port B Data Direction Register $0003

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Bus Control and Input/Output

Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

Bus Control and Input/Output

This register is associated with external bus control signals and interrupt

inputs, including data bus enable (DBE), mode select (MODB/IPI PE1,

MODA/IPIPE0), E clock, size (LSTRB), read/write (R/W), IRQ, and

XIRQ. When the associated pin is not used for one of these specific

functions, the pin can be used as general-purpose I/O. The port E

assignment register (PEAR) selects the function of each pin. DDRE

determines the primary direction of each port E pin when configured to

be general-purpose I/O.

Some of thes e pins h ave sof tware selectable pull-ups (DBE, LSTRB,

R/W, IRQ, and XIRQ ). A single control bit enables the pull-ups for all

these pins which are configured as inputs.

This register is not in the map in peripheral mode or expanded modes

when the EME bit is set.

Read and write anytime.

BIT 7654321BIT 0

PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0

RESET: ————————

Alt. Pin

Function DBE or

ECLK or

CAL

MODB or

IPIPE1 or

CGMTST MODA or

IPIPE0 ECLK LSTRB or

TAGLO R/W IRQ XIRQ

PORTE — Port E Register $0008

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Bus Control and Input/Output

Technical Data MC68HC912DG128 — Rev 3.0

Bus Control and Input/Output

This register determines the primary direction for each port E pin

configured as general-purpose I/O.

0 = Associated pin is a high-impedance input

1 = Associated pin is an output

PE[1:0] are associated with XIRQ and IRQ and cannot be configured as

outputs. These pi ns can be read r egardless of wheth er the alternate

interrupt functions are enabled.

This reg ister is not in the m ap in peri pheral mo de and ex panded m odes

while the EME control bit is set.

Read and write anytime.

The PEAR register is used to choo se be twee n th e ge nera l-purpo se I/O

functions and the alternate bus control functions of Port E. When an

Bit 7654321Bit 0

DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 0 0

RESET: 0 0 000000

DDRE — Port E Data Direction Register $0009

BIT 7654321BIT 0

NDBE CGMTE PIPOE NECLK LSTRE RDWE CALE DBENE

RESET: 0 0 0 0 0 0 0 0 Normal

Expanded

RESET: 0 0 1 0 1 1 0 0 Special

Expanded

RESET: 1 1 0 1 0 0 0 0 Peripheral

RESET: 1 0 0 1 0 0 0 0 Normal

single chip

RESET: 0 0 1 0 1 1 0 0 Special

single chip

PEAR — Port E Assignment Register $000A

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Bus Control and Input/Output

Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

Bus Control and Input/Output

alternate control function is selected, the associated DDRE bits are

overridden.

The reset condition of this regi ster depends on the mode of operation

because bus -control signals are needed immediately after reset in some

modes.

In norm al single -chip m ode, no extern al bus contr ol sign als are ne eded

so all of port E is configured for general-purpose I/O.

In normal expanded modes, the reset vector is located in external

memory. The DBE and E clock are req uired for de-m ultiplexing ad dress

and data, but LS TRB and R/W are only needed by the system when

there are external writable resources. Therefore in normal expanded

modes, only the DBE and E clock are conf igured for their alterna te bus

control functions and the other bits of port E are configured for general-

purpose I/O. If the normal expanded system needs any other bus-control

signals, P EAR w ould n eed to be wri tten b efore a ny ac cess that n eeded

the additional signals.

In speci al expande d mode s, DBE, IPIPE1 , IPIPE0, E, LSTRB, and R/W

are configured as bus-control signa l s.

In special single chip modes, DBE, IPIPE1, IPIPE0, E, LSTRB, R/W, and

CALE are configured as bus-co ntrol signals.

In peripheral mode, the PEAR register is not accessible for reads or

writes. However, the CGMTE control bit is reset to one to configure PE6

as a test output from the PLL module.

NDBE — No Data Bus Enable

Normal: write once; Special: write an yti me EXCEPT the first. Read

anytime.

0 = PE7 is used for DBE, external control of data enable on

memories, or inverted E clock.

1 = PE7 is the CAL function if CALE bit is set in PEAR register or

general-purp ose I/O.

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Bus Control and Input/Output

Technical Data MC68HC912DG128 — Rev 3.0

Bus Control and Input/Output

NDBE controls the use of the DBE pin of Port E. The NDBE bit has no

effect in Single Chip or Periphe ral Modes. The associa ted pin will

default to the CAL function if the CALE bit is set in PEAR register or

otherwise to an I/O.

CGMTE — Clock Generator Module Testing Enable

Normal: write never; Special: write anytime EXCEPT the first. Read

anytime.

0 = PE6 is general-purpose I/O or pipe output.

1 = PE6 is a test signal output from the CGM module (no effect in

single chi p or no rmal expan ded m odes). PIP OE = 1 o verri des

this function and forces PE6 to be a pipe status output signal.

PIPOE — Pipe Status Signal Output Enable

Normal: write once; Special: write an yti me EXCEPT the first time.

Read anyt ime .

0 = PE[6:5] are general-purpose I/O (if CGMTE = 1, PE6 is a test

output signal fro m the CGM module).

1 = PE[6:5] are outputs and indicate the state of the instruction

queue (only effective in expanded modes).

NECLK — No External E Clock

Normal single chip: write once; special single chip: write anytime; all

other modes: write never.

Read anytime. In peripheral mode, E is an input and in all other

modes, E is an output.

0 = PE4 is the external E-clock pin subject to the following

limitation: In single-chip modes, to get an E clock output signal,

it is necessary to have ESTR = 0 in addition to NECLK = 0. A

16-bit write to PEAR and MODE registers can configure all

three bits in one operation.

1 = PE4 is a general-purpose I/O pin.

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Bus Control and Input/Output

Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

Bus Control and Input/Output

LSTRE — Low Strobe (LSTRB) En able

Normal: write once; Special: write an yti me EXCEPT the first time.

Read anytime. This bit has no effect in single-chip modes or normal

expanded narrow mode.

0 = PE3 is a general-purpose I/O pin.

1 = PE3 is configured as the LSTRB bus-control output, provided

the MCU is not in single chip or normal expanded narrow

modes.

LSTRB is used during external writes. After reset in normal expanded

mode, LSTRB is disabled. If needed, it should be enabled before

external writes. External reads do not normally need LSTRB because

all 16 data bits can be driven even if the MCU only needs 8 bits of

data.

In normal exp anded narrow mode this p in is reset to an output driving

high allowing the pin to be an output while in and immediately after

reset.

TAGLO is a shared function of the PE3/LSTRB pi n. In specia l

expan ded modes with LSTRE set and th e BDM taggin g on, a zero at

the falling edge of E tags the instruction word low byte being read into

the instruction queue.

RDWE — Read/Write Enable

Normal: write once; Special: write an yti me EXCEPT the first time.

Read an ytime. This bit ha s no effec t in single-chip modes .

0 = PE2 is a general-purpose I/O pin.

1 = PE2 is configured as the R/W pin. In single chip modes, RDWE

has no effect and PE2 is a general-purpose I/O pin.

R/W is used for external writes. After reset in normal expanded mode,

it is disabled. If needed it should be enabled before any external

writes.

CALE — Calibration Reference Enable

Read and write anytime.

0 = Calibration referenc e is disabled and PE7 is general-purpose

I/O in sin gl e chip or p eri ph er al m od es or i f t he N DB E b it i s set.

1 = Calibration referenc e is enabled on P E7 in single chip a nd

peripheral modes or if the NDBE bit is set.

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Bus Control and Input/Output

Technical Data MC68HC912DG128 — Rev 3.0

Bus Control and Input/Output

DBENE — DBE or Inverted E Clock on PE7

Normal modes: write once. Specia l modes: write anytime EXCEPT

the first; read anytime.

DBENE controls which signal is output on PE7 when NDBE control bit

is cle ared. The inver ted E clock output can be used to latch the

addre ss for demultip lexing. It has the same be haviour as the E clock,

except it is inverted. Please note that in the case of idle expansion

bus, the ‘not E clock’ signal could stay high for many cycles.

The DBENE bit has no effect in single chip or peripheral modes and

PE7 is defaulted to the CAL function if the CALE bit is set in the PEAR

regist er or to an I/O otherwise.

0 = PE7 pin used for DB E external control of data enable on

memories in expanded modes when NDBE = 0

1 = PE7 pin used for inverted E clock output in expanded modes

when NDBE = 0

These bits select pull-up resistors for any pin in the corresponding port

that is cur rently conf igured as an input. Thi s registe r is not in the ma p in

peripheral mode .

Read and write anytime.

PUPK — Pull-Up Port K Enable

0 = Port K pull-ups are disabled.

1 = Enable pull-up d evices for all port K input pins.

PUPJ — Pull- Up or Pull-Dow n Port J Enable

0 = Port J resistive loads (pull-ups or pull-downs) are disabled.

1 = Enable resistive load devices (pull-ups or pull-downs) for all

port J input pins.

Bit 7654321Bit 0

PUPK PUPJ PUPH PUPE 0 0 PUPB PUPA

RESET: 0 0 010000

PUCR — Pull-Up Control Register $000C

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Bus Control and Input/Output

Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

Bus Control and Input/Output

PUPH — Pull-Up or Pull-Down Port H Enable

0 = Port H resi sti ve lo ads (p ul l - ups or pull -d ow ns) are disa bl ed .

1 = Enable resistive load devices (pull-ups or pull-downs) for all

port H inpu t p ins.

PUPE — Pull-Up Port E Enable

0 = Po rt E pull- up s o n P E7, PE3, PE2, PE1 an d PE0 a re disa bled .

1 = Enable pull-up devices for port E input pins PE7, PE3, PE2,

PE1 and PE0.

When this bit is set port E input pins 7, 3, 2, 1 and 0 have an active

pull- up devi ce.

PUPB — Pull-Up Port B Enable

0 = Port B pull-ups are disabled.

1 = Enable pull-up d evices for all port B input pins.

This bit has no effect if port B is being used as part of the address/data

bus (the pull- ups are inactive).

PUPA — Pull-Up Port A Enable

0 = Port A pull-ups are disabled.

1 = Enable pull-up d evices for all port A input pins.

This bit has no effect if port B is being used as part of the address/data

bus (the pull- ups are inactive).

These bits select reduced drive for the associated port pins. This

gives reduced powe r consumption and red uced RFI with a slight

increase in transition time (depending on loading). The reduced drive

function is independent of which function is being used on a particular

port.

This register is not in the map in peripheral mode.

Normal: write once; Special: write an yti me EXCEPT the first time.

Read anyt ime .

RDRIV — Reduced Drive of I/O Lines $000D

Bit 7654321Bit 0

RDPK RDPJ RDPH RDPE 0 0 RDPB RDPA

RESET: 0 0000000

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Bus Control and Input/Output

Technical Data MC68HC912DG128 — Rev 3.0

Bus Control and Input/Output

RDPK — Redu ced Drive of Port K

0 = All port K output pins have full drive enabled.

1 = All port K output pins have reduced drive capabilit y.

RDPJ — Reduced Drive o f Por t J

0 = All port J output pins have full drive enabled.

1 = All port J output pins have red uce d drive capability.

RDPH — Reduced Drive of Port H

0 = All port H output pins have full drive ena bled.

1 = All port H output pi ns have reduced drive capability.

RDPE — Redu ced Drive of Port E

0 = All port E output pins have full drive enabled.

1 = All port E output pins have reduced drive capabilit y.

RDPB — Redu ced Drive of Port B

0 = All port B output pins have full drive enabled.

1 = All port B output pins have reduced drive capabilit y.

RDPA — Redu ced Drive of Port A

0 = All port A output pins have full drive enabled.

1 = All port A output pins have reduced drive capabilit y.

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MC68HC912DG128 — Rev 3.0 Technic al Data
Flash Memory
 
Technical Data — MC68HC912DG128
Sectio n 7. Flas h Memory
7.1  Contents
7.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
7.3 Future Flash EEPROM Support . . . . . . . . . . . . . . . . . . . . . . .108
7.4 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
7.5 Flash EEPROM Control Block . . . . . . . . . . . . . . . . . . . . . . . .109
7.6 Flash EEPROM Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
7.7 Flash EEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .1 10
7.8 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 15
7.9 Programming the Flash EEPROM . . . . . . . . . . . . . . . . . . . . .118
7.10 Erasing the Flash EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . .120
7.11 Program/Erase Protection Interlocks . . . . . . . . . . . . . . . . . . .1 22
7.12 Stop or Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
7.13 Test Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
7.2  Introduction
The four Flash EEPROM array modules 00FEE32K, 01FEE32K, 
10FEE32K and 11FEE32K for the MC68HC912DG128 serve as 
electrically erasable and programmable, non-volatile ROM emulation 
memory. The modules can be used for program code that must either 
execute at high speed or is frequently executed, such as operating 
system kernels a nd standard sub routines, or they  can be used  for static 
data which is read frequently. The Flash EEPROM is ideal for program 
storage for single-chip applications allowing for field reprogramming.
    
  
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Flash Memory

Technical Data MC68HC912DG128 — Rev 3.0

Flash Memory

7.3 Future Flash EEPROM Support

Design is underway to introduce an improved 5V programming Flash

EEPROM module based on SuperFlash with integrated state machine

for simplified programming and erase to be introduced on the

68HC912DG128A.

Appendix: MC68HC912DG128A Flash contains detailed information to

assist in software planning for future Flash EEPROM compatibility and

easy transition to the 68HC912DG128A.

Read operation will be fully compatible with the present Flash EEPROM

design. Write and erase algo rithms will be chang ed alo ng with the

functions of the bits in the control register FEECTL

It is recommended th at the flash algorithm not be stored as part of the

code but l oaded and execute d from RAM whe n required. This simpli fies

compatibility issues and reduces the remote possibility of Flash

corruptio n in the unlikely event of runaway code.

The AUTO bit i n the 6 8HC91 2DG128A Fla sh EE PROM cont rol registe r

provides supp ort for in-circuit detection of th e NVM type — attempts to

set and clear this bit will only be successful on the 68HC912DG128A

where it will read as ‘1’ or ‘0’ as a ppropriate , on the 68H C912DG1 28A it

is tied to ‘0’.

To ensure full compat ibility it is recommended that all of Appendix:

MC68H C 912DG128A Flash be revi ewed.

7.4 Overview

The Flash E EPROM array is arran ged in a 16-bit configu ration and may

be read as either bytes, aligned words or misaligned words. Access time

is one bus cycle for byte and aligned word access and two bus cycles for

misaligned word operat ions.

The Flash EEPROM module requires an external program/erase voltage

(VFP) to program or erase the Flash EEPROM array. The external

program/erase voltage is provided to the Flash EEPROM module via an

external VFP pin. To preven t damage to t he flash array, VFP should

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Flash Memory

Flash EEPROM Control Block

MC68HC912DG128 — Rev 3.0 Technic al Data

Flash Memory

alwa ys be within the specific ation as define d in Table 19-10 in Electrical

Specifications. Programmi ng is by byt e or aligned word . The Flash

EEPROM modul e sup ports bul k er ase only.

The Flash EEPROM module has hardware interlocks which protect

stored data from accidental corruption. An erase- and program-

protected 8-Kbyte block for boot routines is located at the top of each 32-

Kbyte array. Since boot programs must be available at all times, the only

useful boot block is at $E000–$FFFF location. All paged boot blocks can

be used as protected program space if desired.

7.5 Flash EEPROM Control Block

A 4-byte register block for each module controls the Flash EEPROM

module operation. Configuration information is specified and

programmed independently from the contents of the Flash EEPROM

array. At reset, the 4-byte regist er sec tion starts at address $00F4 and

points to the 00FEE32K register block.

7.6 Flash EEPROM Arrays

After reset, a fixed 32K Flash EEPROM array, 11FEE32K, is located

from addresses $4000 to $7FFF and from $C000 to $FFFF. The other

three 32K Flash EEPROM arrays 00FEE32K, 01FEE32K and

10FEE32K, are mapped through a 16K byte program pag e window

located from addresses $8000 to $BFFF. The page window has eight

16K byte pages. The last two pages also map the physical location of the

fixed 32K Flash EEPROM array 11FEE32K. In expanded modes, the

Flash EEPROM arrays are turned off. See Operating Modes.

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Flash Memory

Technical Data MC68HC912DG128 — Rev 3.0

Flash Memory

7.7 Flash EEPROM Registers

Each 32K byte Flash EEPROM module has a set of registers. The

Each re gister page of four bytes maps t he registe r space for each Flash

module an d each pa ge is sel ect ed by the PPA GE re gi ster. See

Operatin g Mo de s.

In normal modes the LOCK bit can only be written once after reset.

LOCK — Lock Register Bit

0 = Enable write to FEEMCR register

1 = Disable write to FEEMCR register

This regi ste r cont ro l s the operation of the Flash EEPROM array.

BOOTP cannot be changed when the LOCK control bit in the

FEELCK register is set or if ENPE in the FEECTL register is set.

BOOTP — Boot Protect

The boot blo cks are located at $E0 00–$FFFF and $A000–$BFFF for

odd program pages for each Flash EEPROM module. Since boot

programs must be available at all times, the only useful boot block is

at $E000–$FFFF location. All paged boot blocks can be used as

protected program space if desired.

0 = Enable erase and program of 8K byte boot block

1 = Disable erase and program of 8K byte boot block

FEELCK — Flash EEPROM Lock Control Register $00F4

Bit 7 6 5 4 3 2 1 Bit 0

0 0 0 0 0 0 0 LOCK

RESET: 0 0 0 0 0 0 0 0

FEEMCR — Flash EEPROM Module Configuration Register $00F5

Bit 7 6 5 4 3 2 1 Bit 0

0 0 0 0 0 0 0 BOOTP

RESET: 0 0 0 0 0 0 0 1

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Flash Memory

Flash EEPROM Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

Flash Memory

In normal mode, writes to FEETST control bits have no effect and always

read zero. The Flash EEPROM module cannot be placed in test mode

inadvertently during normal operation.

FSTE — Stress Test Enable

0 = Disables the gate/drain stress circuitry

1 = Enables the gate/drain stress circuitry

GADR — Gate/Drain Stress Test Select

0 = Selects the drain stress circuitry

1 = Selects the gate stress circuitry

HVT — Stress Test High Voltage Status

0 = High voltage not present during stress test

1 = High voltage present during stress test

FENLV — Enable Low Voltage

0 = Disables low voltage transistor in current reference circuit

1 = Enables low voltage transistor in current reference circuit

FDISVFP — Disa ble Status VFP Voltage Lock

When the VFP pin is below normal programming voltage the Flash

module will not allow writing to the LAT bit; the user cannot erase or

program the Flash module. The FDISVFP control bit enables writing

to the LAT bit regardless of the voltage on the VFP pin.

0 = Enable the a utomatic lock mechanism if VFP is low

1 = Disable the automatic lock mechanism if VFP is low

FEETST — Flash EEPROM Module Test Register $00F6

Bit 7 6 5 4 3 2 1 Bit 0

FSTE GADR HVT FENLV FDISVFP VTCK STRE MWPR

RESET: 0 0 0 0 0 0 0 0

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Flash Memory

Technical Data MC68HC912DG128 — Rev 3.0

Flash Memory

VTCK — VT Check Test Enable

When VTCK is set, the Flash EEPROM module uses the VFP pin to

control the control gate voltage; the sense amp time-out path is

disabled. This allows for indirect measurements of the bit cells

program and erase threshold. If VFP < VZBRK (breakdown voltage) the

control ga te will equal the VFP vo ltage.

If VFP > VZBRK the control gate will be regulated by the following

equation: Vcontrol gate = VZBRK + 0.44 × (VFP − VZBRK)

0 = VT test disable

1 = VT test enable

STRE — Spare Test Row Enable

The spare test row consists of one Flash EEPROM array row. The

reserved word at location 31 contains production test information

which must be maintained through several erase cycles. When STRE

is set, the decoding for th e spare test ro w overrides the a ddress lines

which normally select the other rows in the array.

0 = LIB accesses are to the Flash EEPROM array

1 = Spare test ro w i n array en abled if SMOD is a ctive

MWPR — Multiple Word Pro grammin g

Used primarily for testing, if MWPR = 1, the tw o least-significant

address lines ADDR[1:0] will be ignored when programming a Flash

EEPROM location. The word location addressed if ADDR[1:0] = 00,

along with the word location addressed if ADDR[1:0] = 10, will both be

programmed with the same word data from the programming latches.

This bit should not be changed during programming.

0 = Multiple word programming disabled

1 = Program 32 bits of data

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Flash Memory

Flash EEPROM Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

Flash Memory

This regi ste r control s the pro gr am m i ng an d era sur e of the Fla s h

EEPROM.

FEESWAI — Flash EEPROM Stop in Wait Control

0 = Do not halt Flash EEPROM clock when the part is in wait mode.

1 = Halt Flash EEPROM clock when the part is in wait mode.

NOTE: The FEESWAI bit cannot be asserted if the interrupt vector resides in the

Flash EEPROM array.

SVFP — Status VFP Voltage

SVFP is a read on ly bit.

0 = Volt age of VFP pin is below normal programming voltage levels

1 = Volt age of VFP pin is above normal programming voltage levels

ERAS — Erase Cont ro l

This bit can be read anytime or written when ENPE = 0. When set, all

locations in the array will be erased at the same time. The boot block

will be erased only if BOOTP = 0. This bit also affects the result of

attempted array reads. See Table 7- 1 for more information. Status of

ERAS cannot change if ENPE is set.

0 = Flash EEPROM config ur ed for pr ogram mi n g

1 = Flash EEP ROM configured for er asu re

LAT — La tch Control

This bit can be read anytime or written when ENPE = 0. When set, the

Flash EEPROM is config ured for progr amming o r erasu re and, up on

the next valid write to the array, the address and data will be latched

for th e programming seque nce. See Table 7-1 for the effects of LAT

on array reads. A high voltage detect circuit on the VFP pin will prevent

assertion of the LAT bit when the programming voltage is at normal

levels.

FEECTL — Flash EEPROM Control Register $00F7

Bit 7 6 5 4 3 2 1 Bit 0

0 0 0 FEESWAI SVFP ERAS LAT ENPE

RESET: 0 0 0 0 0 0 0 0

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Flash Memory

Technical Data MC68HC912DG128 — Rev 3.0

Flash Memory

0 = Programming latches disabled

1 = Programming latches enabled

ENPE — Enable Programming /Er ase

0 = Disables program/erase voltage to Flash EEPROM

1 = Applies program/erase volt age to Flash EEPROM

ENPE can b e asserte d only af ter L AT has b een asser ted an d a write

to the data and address latches has occurred. If an attempt is made

to as sert ENPE w hen LAT is negated, or if t he latches h ave not b een

written to after LAT was asserted, ENPE will remain negated after the

write cycle is complete.

The LAT, ER AS and BOOTP bits ca nn ot b e cha ng ed w h en EN PE i s

asserted. A write to FEECTL may only affect the state of ENPE.

Attempts to read a Flash EEPROM array location in the Flash

EEPROM module while ENPE is asserted will not return the da ta

addressed. See Table 7-1 for more information.

Flash EEPROM module control registers may be read or written while

ENPE is asserted. If ENPE is asserted and LAT is negated on the

same write access, no programming or erasure will be performed.

Table 7-1. Effects of ENPE, LAT and ERAS on Array Reads

ENPE LAT ERAS Result of Read

00–Normal read of location addressed

0 1 0 Read of location being programmed

0 1 1 Normal read of location addressed

1––Read cycle is ignored

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Flash Memory

Operation

MC68HC912DG128 — Rev 3.0 Technic al Data

Flash Memory

7.8 Operation

The Flash EEPROM can contain program and data. On reset, it can

operate as a bootstrap memory to provide the CPU with internal

initializatio n in formation dur ing the reset sequence .

7.8.1 Bootstrap Operation Single-Chip Mode

After reset, the CPU controlling the system will begin booting up by

fetching the first program address from address $FFFE.

7.8.2 Normal Operation

The Fla sh EEPROM al lows a by te or aligne d word re ad/write i n one bu s

cycle. Misaligned word read/write require an additional bus cycle. The

Flash EEPROM array responds to read operations only. Write

operations are ignored.

7.8.3 Program/Erase Operation

An unprogrammed Fl ash EEPROM bit has a lo gic st ate of one. A bit

must be programmed to change its state from one to zero. Erasing a bit

returns it to a logic one. The Flash EEPROM has a minimum

program/erase life of 100 cycles. Programming or erasing the Flash

EEPROM is accomplished by a series of control register writes and a

write to a set of programming latches.

Programming is restricted to a single byte or aligned word at a time as

determined by internal signal SZ8 and ADDR[0]. The Flash EEPROM

must first be completely erased prior to programming final data values.

It is possible to program a location in the Flash EEPROM without erasing

the entire array if the new value does not require the changing of bit

values from zero to one.

Read/Write Accesses During Program/Erase — During program or

erase operations , read and write accesses may be different fr om those

duri ng norm al oper at ion an d are affe cted by the state of the cont ro l bits

in the Fla s h EE PR OM cont ro l r egister (FEECTL) . The next w rite to any

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Technical Data MC68HC912DG128 — Rev 3.0

Flash Memory

valid address to the array after LAT is set will ca use the address and

data to be latched into the programming latches. Once the address and

data are latched, write accesses to the array will be ignored while LAT is

set. Writes to the control registers will occur normally.

Program/Erase Verification — When prog ra m mi n g or erasi ng the

Flash EEPROM array, a special verification method is required to ensure

that the prog ram/erase process is reliable, and also to provide the

longest possible life expectancy. This method requires stopping the

program/erase sequence at periods of tPPULSE (tEPULSE for erasing) to

determine if the Flash EEPROM is programmed/erased. After the

location reaches the proper value, it must continue to be

programmed/erased with additional margin pulses to ensure that it will

remain progra mmed/eras ed. Failure to pr ovide the ma rgin pulse s could

lead to corrupted or unreliable data.

Program/Erase Sequence — To begin a program or erase sequence

the external VFP voltage must be applied and stabilized. The ERAS bit

must be set or cleared, depending on whether a program sequence or

an er ase seq uence is to occur. The LAT bit will be set to cause any

subseque nt data writt en to a valid add ress within t he Flash EEPROM to

be latched into the programming address and data latches. The next

Flash array write cycle must be either to the location that is to be

programmed if a programming sequence is being performed, or, if

erasing, to any valid Flash EEPROM array location. Writing the new

address and data information to the Flash EEPROM is followed by

assertion of ENPE to turn on the program/erase voltage to

prog ram/erase the new location(s). The LAT bi t must be asserted and

the address and data latched to allow the setting of the ENPE control bit.

If the data and address have not been latched, an attempt to assert

ENPE will be ignored and ENPE will remain negated after the write cycle

to FEECTL is completed. The LAT bit must remain asserted and the

ERAS bit must remain in its current state as long as ENPE is asserted.

A write to the LAT b it to clea r it while ENPE is set will be ignored. That

is, after the write cycle, LAT will remain asserted. Likewise, an attempt

to change the state of ERAS will be ignored and the state of the ERAS

bit will remain unchanged.

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Flash Memory

Operation

MC68HC912DG128 — Rev 3.0 Technic al Data

Flash Memory

The programming software is responsible for all timing during a program

sequence. This includes the total number of program pulses (nPP), the

length of the program pulse (tPPULSE), the program margin pulses (pm)

and the delay between turning off the high voltage and verifying the

operation (tVPROG).

The erase software is responsible for all timing during an erase

sequence. This includes the total number of erase pulses (em), the

length of the erase pulse (tEPULSE), the erase margin pulse or pulses,

and the delay between turning off the high voltage and verifying the

operation (tVERASE).

Software also controls the supply of the proper program/erase voltage to

the VFP pin, and should be at the proper level before ENPE is set during

a program/erase sequence.

A program/erase cycle should not be in progress when starting another

program/erase, or while attempting to read from the array.

NOTE: Although clear ing ENPE disabl es the progra m/erase voltage (VFP) from

the VFP pin to the array, ca re must be taken to ensure that V FP is at VDD

whenever pr ogramming/erasing is not in progress. Not doing so could

damage the part. Ensuring that VFP is always greater or equal to VDD

can be acco mplished by controlling the VFP power supply with the

programming software via an output pin. Alternatively, all programming

and eras ing can be done prior to installing th e device on an application

circu it board which can always connect VFP to VDD. Programmin g can

also be accomplished by plugging the board into a special programming

fixt ure which provides program/era se volt age to the VFP pin.

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Flash Memory

Technical Data MC68HC912DG128 — Rev 3.0

Flash Memory

7.9 Programming the Flash EEPROM

Programming the Flash EEPROM is accomplished by the following

sequence. The VFP pin voltage must be at the proper level prior to

executing step 4 the first time.

1. Ap ply pro gram/erase voltage to the VFP pin.

2. Set the PPAGE to point to the 16K Flash window to be

programmed and corresponding register block. Clear ERAS and

set the L AT bit in the FEECTL r egister to es tablish program mode

and enable programming address and data latches.

3. Write data to a valid address. The address and data is latched. If

BOOTP is asserted, an attempt to program an address in the boot

block will be ignored.

4. Apply programming voltage by setting ENPE.

5. Delay for on e progra mming pulse (tPPULSE).

6. Remove programming v oltage by clea ring ENPE.

7. Delay while high voltage is tu rning off (tVPROG).

8. Re ad the addres s locat ion to verify that it has been programmed

9. If the locati on is not progra mmed, repeat steps 4 through 7 until

the location is programmed or until the specified maximum

number of program pulses has been reached (nPP)

10. If the location is programmed, repeat the same number of pulses

as r equired to prog ram the locati on. This provides 100% pr ogram

margin.

11. Read the address location to verify that it remains programmed.

12. Clear LAT.

13. If there ar e more l ocations to program , repe at steps 2 throu gh 10.

14. Turn off VFP (reduce vol ta ge on VFP pin to VDD).

The flowchart in Figure 7-1 demonstrates the recomme nded

program m ing seq uence.

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Flash Memory

Programming the Flash EEPROM

MC68HC912DG128 — Rev 3.0 Technic al Data

Flash Memory

Figure 7-1. Program Sequence Flow

START PROG

WRITE DATA

TO ADDRESS

SET ENPE

READ

GET NEXT

ADDRESS/DATA

LOCATION FAILED

LOCATION

CLEAR MARGIN FLAG

INCREMENT

nPP COUNTER

DECREMENT

nPP COUNTER

YES

TO PROGRAM

TURN ON VFP

DELAY FOR DURATION

OF PROGRAM PULSE

(tPPULSE)

CLEAR ENPE

DELAY BEFORE VERIFY

MARGIN FLAG

SET? NO

YES

DATA

CORRECT?

SET

MARGIN FLAG

DATA

CORRECT?

nPP = 0?

DONE?

TURN OFF VFP

(tVPROG)

nPP = 50?

YES

DONE PROG

CLEAR PROGRAM PULSE COUNTER (nPP)

CLEAR LAT

WRITE PPAGE

CLEAR ERAS

SET LAT

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Flash Memory

Technical Data MC68HC912DG128 — Rev 3.0

Flash Memory

7.10 Erasing the Flash EEPROM

The fol lowing sequen ce demonstr ates t he re commen ded p roced ure f or

erasing any of the Flash EEPROM. The VFP pin voltag e mu st be at the

prop er level prior to exe cuting s tep 4 the first time.

1. Turn on VFP (apply program/erase voltage to the VFP pin).

2. Set the PPAGE register to point to the 32K Flash array to be

erased. Set the LAT bit and ERAS bit to configure the Flash

EEPROM for erasing.

3. Writ e to any val id addr ess in the 32 K Flas h array. This allows the

erase voltage to be turned on; the data writt en and the ad dress

written are not important. The boot block will be erased only if the

control bit BOOTP is negated.

4. Apply erase voltage by setting ENPE.

5. Delay for a single erase pulse (tEPULSE).

6. Remove erase voltage by clearing ENPE.

7. Delay while high voltage is tu rning off (tVERASE).

8. Read the entire array to ensure that the Flash EEPROM is erased.

9. If a ll of the Flash EEPRO M loca tions ar e not e rased, repeat ste ps

4 through 7 until either the remaining locations are erased, or until

the maximum erase pulses have been applied (nEP)

10. If all of the Flash EE PROM locati ons are erased , repeat the sa me

number of pulses as required to erase the array. This provides

100% erase margin.

11. Read the entire array to ensure that the Flash EEPROM is erased.

12. Clear LAT.

13. Turn off VFP (reduce vol ta ge on VFP pin to VDD).

The flowchart in Figure 7-2 demonstrates the recomme nded erase

sequence.

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Flash Memory

Erasing the Flash EEPROM

MC68HC912DG128 — Rev 3.0 Technic al Data

Flash Memory

Figure 7-2. Erase Sequence Flow

START ERASE

WRITE PPAGE

WRITE TO ARRAY

SET ENPE

READ

ARRAY FAILED TO ERASE

ARRAY

CLEAR MARGIN FLAG

INCREMENT

nEP COUNTER

DECREMENT

nEP COUNTER

YES

TURN ON VFP

DELAY FOR DURATION

OF ERASE PULSE

(tEPULSE)

CLEAR ENPE

DELAY BEFORE VERIFY

MARGIN FLAG

SET? NO

YES

ARRAY

ERASED?

SET

MARGIN FLAG

nEP = 0?

TURN OFF VFP

(tVERASE)

nEP = 5?

YES

ARRAY ERASED

CLEAR ERASE PULSE COUNTER (nEP)

CLEAR LAT

ARRAY

ERASED?

SET ERAS

SET LAT

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Flash Memory

Technical Data MC68HC912DG128 — Rev 3.0

Flash Memory

7.11 Program/Era se Protection Interlocks

The Flash EEPROM program and erase mechanisms provide maximum

protection from accidental programming or erasure.

The voltage required to program/erase the Flash EEPROM (VFP) is

supplied via an external pin. If VFP is not prese nt , no

programming/erasing will occur. Furthermore, the program/erase

voltage will not be app lied to the Flash EEPROM u nle ss turned on by

setting a control bit (ENPE). The ENPE bit may not be set unless the

program m ing ad dr ess and data la tch es have be en wr itte n pr evi ou sl y

with a valid address. The latches may not be written unless enabled by

setting a control bit (LAT). The LAT and ENPE control bits must be

written on separate writes to the control register (FEECTL) and must be

separated by a write to the programming latches. The ERAS and LAT

bits are also protected when ENPE is set. This prevents inadvertent

switching be tween erase/prog ram mode and al so prevents the lat ched

data and address from being changed after a program cycle has been

initiated.

7.12 Stop or Wait Mode

When stop or wait commands are exec uted , the MC U puts the Flash

EEPROM in stop or wait mode. In these modes the Flash module will

cease erasure or programming immediately. It is advised not to enter

stop or wait modes when programming the Flash array.

CAUTION: The Flash EEPROM module requires a 250nsec delay for wake-up from

STOP mode. If the operating bus frequency is greater than 4MHz, the

Flash cannot be used when recovering from STOP mode when the DLY

bit in the INTCR regis ter is cleared.

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Flash Memory

Test Mode

MC68HC912DG128 — Rev 3.0 Technic al Data

Flash Memory

7.13 Test Mode

The Flash EEPROM has some special test functions which are only

accessible when the device is in test mode. Test mode is indicated to the

Flash EEPROM module when the SMOD line on the LIB is asserted.

When SMOD is asserted, the special test con trol bits may be accessed

via the LIB to invoke the special test functions in the Flash EEPROM

module. When SMOD is not asserted, writes to the te st control bits h ave

no effect and all bits in the test register FEETST will be cleared. This

ensures that Flash EEPROM test mode cannot be invoked inadvertently

during normal operation.

Note that the Flash EEPROM module will ope rate normally, ev en if

SMOD is asserted, until a special test function is invoked. The test mode

adds additional features over normal mode which allow the tests to be

performed even after the device is installed in the final product.

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Flash Memory

Technical Data MC68HC912DG128 — Rev 3.0

Flash Memory

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MC68HC912DG128 — Rev 3.0 Technic al Data
EEPROM Mem ory
 
Technical Data — MC68HC912DG128
Section 8. EEPROM Memory
8.1  Contents
8.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
8.3 Future EEPROM Support. . . . . . . . . . . . . . . . . . . . . . . . . . . .126
8.4 EEP ROM Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . .127
8.5 EEPROM Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . .128
8.2  Introduction
The MC68HC912DG128 EE PROM nonvolatile memory is arranged in a 
16-bi t configur at ion. The EEPROM arr ay may be re ad  as eithe r  bytes, 
aligned words or misaligned words. Acce ss times a re on e bus cycle  for 
byte and aligned word access and two bus cycles for misaligned word 
operations. 
Programming is by byte or aligned word. Attempts to program or erase 
misaligned words will fail. Only the lower byte will be latched and 
programmed or erased. Programming and erasing of the user EEPROM 
can be done in all modes.
Each EEPROM byte or aligned word must be erased before 
programming. The EEPROM module  supports byte, aligned word, row 
(32 bytes) or bulk erase, all using the internal charge pump. The 
EEPROM module has hardware interlocks which protect stored data 
from  corruption by  accidentally enabling the program/erase v oltage. 
Programming voltage is derived from the internal VDD supply with an 
internal charge pump.
    
  
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EEPROM Memory

Technical Data MC68HC912DG128 — Rev 3.0

EEPROM Mem ory

8.3 Future EEPROM Support

Design is underway to introduce an improved EEPROM m odule with

integrated state machine to simplify programming and erase. This will be

introduced on the 68HC912DG128A together with 5V programming

Flash EEPROM.

Appendix: MC68HC912DG128A EEPROM contains detailed

information to assist in software planning for future EEPROM

compatibility and transition to the 68HC912DG128A. Read, write and

erase algorithms are fully compatible with the present EEPROM design.

The key change comes in the form of a self timed state machine for

erasing & writing data. This is implemented using a pre-scaler loaded

from a new word register EEDIV ($00EE) - located in a presently unused

location this register can be written without effect, reading the location

will return unpredictable data.

Adding 5 bytes of initialisation code to current software to load EEDIV

(with value appropriate for the application’s crystal frequency, EXTA Li)

will help ensure compatibility.

Other new features for performance improvement are disabled at reset

providing a compatible algorithm for modifying the EEPR OM.

CAUTION: Other areas for consideration include:

Program/Erase is not guaranteed in Limp home mode. Clock monitor

CME bit must be enabled during program/erase.

Program/erase should not be performed with input clock frequency <250

KHz.

Resonator/crystal frequency tolerance should be better than 2% total for

< 2MHz, 3% total for >= 2MHz.

Successive writes to an EEPROM location must be preceded by an

erase cycle.

To ensure full compat ibility it is recommended that all of Appendix:

MC68HC912DG128A EEPROM be reviewed .

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EEPROM Memory

EEPROM Programmer’s Model

MC68HC912DG128 — Rev 3.0 Technic al Data

EEPROM Mem ory

8.4 EEPROM Programmer’s Model

The EEPR OM module con sists of two se parately addr essable sectio ns.

The first is a four-byte memory mapped control register block used for

control, testing and configuration of the E EPROM array. The second

section is the EEPROM array itself.

At res et, the four -byte register section starts at address $00F0 and the

EEPROM array is located from addresses $0800 to $0FFF. For

information on re-mapping the register block and EEPROM address

space, refer to Operating Modes.

Read/write access to the memory array section can be enabled or

disabled by the EEON control bit in the INITEE register. This feature

allows the access to memory map ped resources with lower priority than

the EEPROM memory array. EEPROM control registers can be accessed

regardless of the state of EEON. Any EEPROM erase or program

operations already in progress will not be affected by modifying EEON.

Using the normal EEPROG control, it is possible to continue

program/erase operations during WAIT. For lowest power consumption

during WAIT, stop program/erase by turning off EEPGM.

If the STOP mode is entered during programmin g or erasing ,

program/erase voltage will be automatically turned off and the RC clock

(if enabled) is stopped. However, the EEPGM control bit will remain set.

When STOP mode is terminated, the pr ogram/erase voltage will be

automatically turned back on if EEPGM is set.

At low bus frequen cies, t he RC clock must be turned on fo r

program/erase.

The EEPROM module contains an extra byte called SHADOW byte

which is loaded at reset into the EEMCR register.

To program the SHADOW byte, when in special modes (SMODN=0), the

NOSHB bit in EEMCR register must be cleared. Normal programming

routines are used to program the SHADOW byte which becomes

accessible at address $0FC0 when NOSHB is cleared.

At the next reset the SHADOW byte data is loaded into the EEMCR.

The SHADOW byte can be protected from being programmed or erased

by setting the SHPROT bit of EEPROT register.

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EEPROM Memory

Technical Data MC68HC912DG128 — Rev 3.0

EEPROM Mem ory

8.5 EEPROM Control Registers

Bits[7:4] are loaded at reset from the EEPROM SHADOW byte.

NOTE: Bits 5 and 4 are reserved for test purposes. These locations in the

SHADOW byte shou ld n ot be progr ammed other wise so me lo catio ns in

the regular EEPROM array will no lon ge r be visible.

NOBDML — Background Debug Mod e Lockout Disable

0 = The BDM lockout is enabled.

1 = The BDM lockout is disabled.

Loaded from SHADOW byte at reset.

Read anytime. Write anytime in special modes (SMODN=0).

NOSHB — SHADOW Byte Disable

0 = SHADOW byte enabled and acce ssible at address $0FC0.

1 = Regula r EEPROM array at address $0FC0.

Loaded from SHADOW byte at reset.

Read anytime. Write anytime in special modes (SMODN=0).

When NOSHB cleared, the regular EEPROM array byte at address

$0FC0 is no longer visible. The SHADOW byte is accessed instead

for both read and program/erase operations. BULK, ODD and EVEN

program/erase only apply if the SHADOW byte is enabled.

NOTE: Bit 6 of the SHADOW byte should not be cleared (set to ‘0’) in order to

have the full EEPROM array visible.

EESWAI — EEPROM Stops in Wait Mode

0 = The module is not affected during WAIT mode

1 = The module ceases to be clocked during WAIT mode

Read and write anytime.

NOTE: The EESWAI bit should be cleared if the WAIT mode vectors are

mapped in the EEPROM array.

EEMCR — EEPROM Module Configuration $00F0

Bit 7654 321Bit 0

NOBDML NOSHB 1(1)

1. Bits 4 and 5 have test functions and should not be programmed.

1(1) 1 EESWAI PROTLCK EERC

RESET: —(2)

2. Loaded from SHADOW byte.

—(2) —(2) —(2) 1100

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EEPROM Memory

EEPROM Contro l Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

EEPROM Mem ory

PROTLCK — Block Protect Write Lock

0 = Block protect bits and bulk erase protection bit can be written

1 = Block protect bits are locked

Read anytime. Write once in normal modes (SMODN = 1), set and

clear any time in special modes (SMODN = 0 ).

EERC — EEPROM Charge Pump Clock

0 = System clock is used as clock source for the internal charge

pump. Internal RC oscillator is stopped.

1 = Internal RC oscillator drives the charge pump. The RC oscillator

is required when the system bus clock is lower than fPROG.

Read and write anytime.

Preven ts accident al write s to EEPROM. R ead anytim e. Write a nytime if

EEPGM = 0 and PROTLCK = 0.

SHPROT — SHADOW Byte Protection

0 = The SHADOW byte can be programmed and erased.

1 = The SHADOW byte is protected from being programmed and

erased.

BPROT[5:0] — EEPROM Block Protection

0 = Associated EEPROM block ca n be programmed and erased.

1 = Associated EEPROM block is protected from being

prog rammed a nd erased.

EEPROT — EEPROM Block Protect $00F1

Bit 7654321Bit 0

SHPROT 1 BPROT5 BPROT4 BPROT3 BPROT2 BPROT1 BPROT0

RESET: 1 1 1 1 1 1 1 1

Table 8-1. 2K byte EEPROM Block Protection

Bit Name Block Protected Block Size

BPROT5 $ 0800 to $0BFF 10 24 Bytes

BPROT4 $0C00 to $0DFF 512 Bytes

BPROT3 $0E00 to $0EFF 256 Bytes

BPROT2 $0F00 to $0F7F 128 Bytes

BPROT1 $0F80 to $0FBF 64 Bytes

BPROT0 $0FC0 to $0FFF 64 Bytes

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EEPROM Memory

Technical Data MC68HC912DG128 — Rev 3.0

EEPROM Mem ory

Read anytime. Write in special modes only (SMODN = 0). These bits are

used for test purposes only. In normal modes the bits are forced to zero.

EEODD — Odd Row Programming

0 = Odd ro w bulk programming/eras ing is di sabled.

1 = Bulk program/erase all odd rows .

EEVEN — Even Row Programming

0 = Even row bulk programming/erasing is disabled.

1 = Bulk program/erase all even rows.

MARG — Program and Erase Voltage Margin Test Enable

0 = Normal operation.

1 = Program and Erase Margin test.

This bit is used to evaluate the program/erase voltage margin.

EECPD — Charge Pump Disable

0 = Char ge pump is turned on during program/erase .

1 = Disable charge pump.

EECPRD — Charge Pump Ra mp Disable

Known to enhance write/erase endurance of EEPROM cells.

0 = Charge pump is turned on progressively during program/erase.

1 = Disable charge pump controlled ramp up.

EECPM — Charge Pump Monitor Enable

0 = Normal operation.

1 = Output the charge pump voltage on the IRQ/VPP pin.

EETST — EEPROM Test $00F2

Bit 7654321Bit 0

EEODD EEVEN MARG EECPD EECPRD 0 EECPM 0

RESET:00000000

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EEPROM Memory

EEPROM Contro l Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

EEPROM Mem ory

BULKP — Bulk Erase Protection

0 = EEPROM can be bulk erased.

1 = EEPROM is protected from being bulk or row erased.

Read anytime. Write anytime if EEPGM = 0 and PROTLCK = 0.

BYTE — Byte and Aligned Word Erase

0 = Bulk or row erase is enab led.

1 = One byte or one aligned word erase only.

Read anytime. Write anytime if EEPGM = 0.

ROW — Row or Bulk Erase (when BYTE = 0)

0 = Erase entire EEPROM array.

1 = Erase only one 32-byte row.

Read anytime. Write anytime if EEPGM = 0.

BYTE an d ROW have no effect when ERASE = 0

If BYTE = 1 an d test m ode is not enabl ed, on ly the l ocation specif ie d

by the address written to the programming latches will be erased. The

operation wi ll be a byte or an aligned word erase depending on the

size of written data.

ERASE — Erase Cont rol

0 = EEPROM configuration for programming.

1 = EEPROM configuration for erasure.

Read anytime. Write anytime if EEPGM = 0.

Configures the EEPROM for erasure or programming.

EEPROG — EEPROM Control $00F3

Bit 7654321Bit 0

BULKP 0 0 BYTE ROW ERASE EELAT EEPGM

RESET:10000000

Table 8-2. Erase Select ion

BYTE ROW Block size

0 0 Bulk erase entire EEPROM array

0 1 Row erase 32 bytes

1 0 Byte or aligned word erase

1 1 Byte or aligned word erase

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EEPROM Memory

Technical Data MC68HC912DG128 — Rev 3.0

EEPROM Mem ory

When test mode is not enabled and unless BULKP is set, erasure is

by byte, aligned word, row or bulk.

EELAT — EEPROM Latch Control

0 = EEPROM set up for normal reads.

1 = EEPROM address and data bus latches set up for

prog r am m i ng or era sing.

Read anytime. Write anytime if EEPGM = 0.

BYTE, ROW, ERASE and EELAT bits can be written simultaneously

or in any sequence.

EEPGM — Pr og ra m and Erase Enable

0 = Disables program/erase voltage to EEPROM.

1 = Applies program/erase volt age to EEPRO M .

The EEPGM bit can be set only after EELAT has been set. When

EELAT and EEPGM are set simultaneously, EEPGM remains clear

but EELAT is set.

The BULKP, BYTE, ROW, ERASE and EELAT bits cannot be

changed whe n EEPG M is set. To comp l ete a progra m or era se, tw o

successive writes to clear EEPGM and EELAT bits are required

before reading the programmed data. A write to an EEPROM location

has no effect when EEPGM is set. Latched address and data cannot

be modified d uring program or erase.

A program or erase operation should follow th e sequence below:

1. Writ e BYTE, ROW an d ERASE to the d esired value, write EELAT

= 1

2. Write a byte or an aligned word to an EEPROM address

3. Write EEPGM = 1

4. Wait for programming (tPROG) or erase (terase) dela y tim e

5. Write EEPGM = 0

6. Write EELAT = 0

It is possible to program/erase more bytes or words without intermediate

EEPROM reads, by jumping from step 5 to step 2.

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MC68HC912DG128 — Rev 3.0 Technic al Data
Resets and Interrupts
 
Technical Data — MC68HC912DG128
Section 9. Resets and Interrupts
9.1  Contents
9.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
9.3 Maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
9.4 Latching of Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
9.5 Interrupt Control and Priority Registers  . . . . . . . . . . . . . . . . .135
9.6 Interrupt test registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 38
9.7 Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
9.8 Effects of Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
9.9 Register Stacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
9.10 Important User Information. . . . . . . . . . . . . . . . . . . . . . . . . . .142
9.2  Introduction
CPU12 exceptions include resets and interrupts. Each exception has an 
associat ed 16-bit  vector, which  points to t he memory l ocation where  the 
routine that handles the exception is located. Vectors are stored in the 
upper 128 bytes of the standard 64K byte address map. 
The six h ighest vector a ddresses are used  for resets and  non-maskable 
interrupt sources. The remainder of the vectors are used for maskable 
interrupts, and all must be initialized to point to the address of the 
appropriate service routine.
    
  
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Resets and Interrupts

Technical Data MC68HC912DG128 — Rev 3.0

Resets and Interrupts

9.2.1 Exception Priority

A hardware priority hierarchy determines which reset or interrupt is

serviced first when simultaneous requests are made. Six sources are not

maskable. The remaining sources are maskable, and any one of them

can be given priority over other maskable interrupts.

The priorities of the non-maskable sources are:

1. POR or RESET pin

2. Clo ck mo ni to r reset

3. COP watchdog reset

4. Unim pl e me nte d in str ucti o n tra p

5. Software interrupt instruction (SWI)

6. XIRQ signal (if X bit in CCR = 0)

9.3 Maskable interrupts

Maskable interrupt sources include on-chip peripheral systems and

external interrupt service requests. Interrupts from these sources are

recognized when the global interrupt mask bit (I) in the CCR is cleared.

The default state of the I bit out of reset is one, but it can be written at

any time.

Interrupt sources are prioritized by default but any one maskable

interrupt source may be assigne d the highest priority by means of the

HPRIO register. The relative priorities of the other sources remain the

same.

An interr upt that is assigned highes t priority is still subject to global

masking by the I bit in the CCR, or by any associated local bits. Interrupt

vectors are not affected by priority assignment. HPRIO can only be

written while the I bit is set (interrupts inhibited). Table 9-1 lists interrupt

sources and vectors in default order of priority.

Before masking an interrupt by clearing the corresponding local enable

bit, the I-bit should be set in order to avoid an SWI.

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Resets and Interrupts

Latching of Interrupts

MC68HC912DG128 — Rev 3.0 Technic al Data

Resets and Interrupts

9.4 Latching of Interrupts

XIRQ is always level triggered and IRQ can be selected as a level

triggered int errupt. These level triggered int errupt pins should only be

released during the appropriate interrupt service routine. Generally the

interrupt service routine will handshake with the interrupting logic to

release the pin. In this way, the MCU will never start the interrupt service

sequence only to determine that there is no longer an interrupt source.

In the event that this does occur the trap vector will be taken.

If IRQ is selected as an edge triggered interrupt, the hold time of the level

after the active edge is independent of when the interrupt is serviced. As

long as the minimum hold time is met, the interrupt will be latched inside

the MCU. In this case the IRQ edge interrupt latch is cleared

automatically when the interrupt is serviced.

All of the remain ing interrupts are latched by the MCU with a flag bit.

These interrupt flags should be cleared during an interrupt service

routine or wh en interrupts are mas ked by t he I bit. By doing this, the

MCU will never get an unknown interrupt source and take the trap vector.

Table 9-1. Interrupt Vector Map

Vector Address Interrupt Sour ce CCR

Mask Local Enable HPRIO Value to

Elevate

$FFFE, $FFFF Rese t None None –

$FFFC, $FFFD Clock monitor fail reset None COPCTL (CME, FCME) –

$FFFA, $FFFB COP failure reset None COP rate selected –

$FFF8, $FFF9 Unimplemented instruction trap None None –

$FFF6, $FFF7 SWI None None –

$FFF4, $FFF5 XIRQ X bit None –

$FFF2, $FFF3 IRQ I bit INTCR (IRQEN) $F2

$FFF0, $FFF1 Real time interrupt I bit RTICTL (RTIE) $ F0

$FFEE, $FFEF Timer channel 0 I bit TMSK1 (C0I) $EE

$FFEC, $FFED Timer channel 1 I bit TMSK1 (C1I) $EC

$FFEA, $FFEB Timer channel 2 I bit TMSK1 (C2I) $EA

$FFE8, $FFE9 Timer channel 3 I bit TMSK1 (C3I) $E8

$FFE6, $FFE7 Timer channel 4 I bit TMSK1 (C4I) $E6

$FFE4, $FFE5 Timer channel 5 I bit TMSK1 (C5I) $E4

$FFE2, $FFE3 Timer channel 6 I bit TMSK1 (C6I) $E2

$FFE0, $FFE1 Timer channel 7 I bit TMSK1 (C7I) $E0

$FFDE, $FFDF Timer overflow I bit TMSK2 (TOI) $DE

$FFDC, $FFDD Pulse accumulator overflow I bit PACTL (PAOVI) $DC

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Resets and Interrupts

Technical Data MC68HC912DG128 — Rev 3.0

Resets and Interrupts

$FFDA, $FFDB Pulse accumulator input edge I bit PACTL (PAI) $DA

$FFD8, $FFD9 SPI serial transfer complete I bit SP0CR1 (SPIE) $D8

$FFD6, $FFD7 SCI 0 I bit SC0CR2

(TIE, TCIE, RIE, ILIE) $D6

$FFD4, $FFD5 SCI 1 I bit SC1CR2

(TIE, TCIE, RIE, ILIE) $D4

$FFD2, $FFD3 ATD0 or ATD1 I bit ATDxCTL2 (ASCIE) $D2

$FFD0, $FFD1 MSCAN 0 wake-up I bit C0RIER (WUPIE) $D0

$FFCE, $FFCF Key wake-up J or H I bit KWIEJ[7:0] and

KWIEH[7:0] $CE

$FFCC, $FFCD Modulus down counter underflow I bit MCCTL (MCZI) $CC

$FFCA, $FFCB Pulse Accumulator B Overflow I bit PBCTL (PBOVI) $CA

$FFC8, $FFC9 MSCAN 0 errors I bit

C0RIER (RWRNIE,

TWRNIE,

RERRIE, TERRIE,

BOFFIE, OVRIE)

$C8

$FFC6, $FFC7 MSCAN 0 receive I bit C0RIER (RXFIE) $C6

$FFC4, $FFC5 MSCAN 0 transmit I bit C0TCR (TXEIE[2:0]) $C4

$FFC2, $FFC3 CGM lock and limp home I bit PLLCR (LOCKIE, LHIE) $C2

$FFC0, $FFC1 IIC Bus I bit IBCR (IBIE) $C0

$FFBE, $FFBF MSCAN 1 wake-up I bit C1RIER (WUPIE) $BE

$FFB C, $FFBD MSCAN 1 errors I bit

C1RIER (RWRNIE,

TWRNIE,

RERRIE, TERRIE,

BOFFIE, OVRIE)

$BC

$FFBA, $FFBB MSCAN 1 receive I bit C1RIER (RXFIE) $BA

$FFB8, $FFB9 MSCAN 1 transmit I bit C1TCR (TXEIE[2:0]) $B8

$FFB6, $FFB7 Reserved I bit $B6

$FF80–$FFB5 Reserved I bit $80–$B4

Table 9-1. Interrupt Vector Map

Vector Address Interrupt Sour ce CCR

Mask Local Enable HPRIO Value to

Elevate

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Resets and Interrupts

Interrupt Control and Priority Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

Resets and Interrupts

9.5 Interrupt Control and Priority Registers

IRQE — IRQ Select Edge Sensitive Only

0 = IRQ configured for low-level recognition.

1 = IRQ configur ed to respond only to fal l i ng edg es (o n pi n

PE1/IRQ).

IRQE can be read anytime and written once in normal modes. In

special modes, IRQE can be read anytime and written anytime,

except the first write is ignored.

IRQEN — External IRQ Enable

The IRQ pin has an active pul l-u p. See Table 3-4.

0 = External IRQ pin is disconnected fr om interrupt logic.

1 = External IRQ pin is con nect ed to inter r up t logi c.

IRQEN can be read and writ ten any time in all modes.

DLY — Enable Oscillator Start-up Delay on Exit from STOP

The delay time of about 4096 cycles is based on the X clock rate

chosen.

0 = No stabilization delay imposed on exit from STOP mode. A

stable external oscillator must be supplied.

1 = Stabilization delay is imposed before processing resumes after

STOP.

DLY can be read anytime and written once in normal modes. In

special modes, DLY can be read and written anytime.

INTCR — Interrupt Control Register $001E

Bit 7654321Bit 0

IRQE IRQEN DLY 0 0 0 0 0

RESET: 0 1 1 0 0 0 0 0

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Resets and Interrupts

Technical Data MC68HC912DG128 — Rev 3.0

Resets and Interrupts

Write only if I mask in CCR = 1 (interrupts inhibited). Read anytime.

To give a maskable interrupt source highest priority, write the low byte of

the vector address to the HPRIO register. For example, writing $F0 to

HPRIO wou ld a ssign highest maska ble inte rrup t p rior ity to th e re al-t ime

interrupt timer ($FFF0). If an un-implemented vector address or a non-I-

masked vect or a ddr e ss ( val u e hi gh er t ha n $ F2) is writ ten , then I RQ will

be the defaul t highest prior ity int er rupt.

9.6 Interrupt test regi sters

These r eg ister s a re used in sp eci al mo de s for testi ng the i nter rupt l og ic

and pr iori ty witho ut nee din g to know which modu les a nd what func tions

are used to generate the interrupts.Each bit is used to force a specific

interrupt vector by writing it to 1.Bits are named with B6 through F4 to

indicate vectors $FFB6 through $FFF4. These bits are also used in

special modes to view that an interrupt caused by a module has reached

the interrupt module.

These registers can only be read in special modes (read in normal mode

will return $00). Reading these registers at the same time as the interrupt

is changing will cause an indeterminate value to be read. These

registers can only be written in spec ial mode.

Bit 7654321Bit 0

1 PSEL6 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1 0

RESET:11110010

HPRIO — Highest Priority I Interrupt $001F

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Resets and Interrupts

Interrupt test registers

MC68HC912DG128 — Rev 3.0 Technic al Data

Resets and Interrupts

ITST0 — Interrupt Test Register 0 $0018

Bit 7654321Bit 0

ITE6 ITE8 ITEA ITEC ITEE ITF0 ITF2 ITF4

RESET: 0 0 0 0 0 0 0 0

ITST1 — Interrupt Test Register 1 $0019

Bit 7654321Bit 0

ITD6 ITD8 ITDA ITDC ITDE ITE0 ITE2 ITE4

RESET: 0 0000000

ITST2 — Interrupt Test Register 2 $001A

Bit 7654321Bit 0

ITC6 ITC8 ITCA ITCC ITCE ITD0 ITD2 ITD4

RESET: 0 0 0 00000

ITST3 — Interrupt Test Register 3 $001B

Bit 7654321Bit 0

ITB6 ITB8 ITBA ITBC ITBE ITC0 ITC2 ITC4

RESET: 0 0 0 0 0 0 0 0

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Resets and Interrupts

Technical Data MC68HC912DG128 — Rev 3.0

Resets and Interrupts

9.7 Resets

There are four possible sources of reset. Power-on reset (POR), and

external reset on the RESET pin share the normal reset vector. The

computer operating properly (COP) reset and the clock monitor reset

each has a vector. Entry into reset is asynchronous and does not require

a clock but the MCU cannot sequence out of reset without a system

clock.

9.7.1 Power-On Reset

A positive transition on VDD causes a power-on reset (POR). An external

voltage level detector, or other external reset circuits, are the usual

source of reset in a system. The POR circuit only initializes internal

circuitry during cold starts and cannot be used to force a reset as system

voltage drops.

It is important to use an external low voltage reset circuit (for example:

MC34064 or MC33464) to prevent power transitions or corruption of

RAM or EEPROM.

9.7.2 External Reset

The CPU distinguishes between internal and external reset conditions

by sensing whether the reset pin rises to a logic one in less than nine E-

clock cycles after an internal device releases reset. When a reset

condition is sensed, the RESET pin is driven low and a clocked reset

sequence controls when the MCU can begin normal processingby an

internal device for about 16 E-clock cycles, then released. In the case of

a clock monitor error, a 4096 cycle oscillator start-up delay is imposed

before the reset recovery sequence starts (reset is driven low throughout

this 4096 cycle delay). The internal reset recovery sequence then drives

reset low for 16 to 17 cycles and releases the drive to allow reset to rise.

Nine E-clock cycles later the reset pin it is sampled. If the pin is still held

low, the CPU assumes that an external reset has occurred. If the pin is

high, it indicates that the reset was initiated internally by either the COP

system or the clock monitor.

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Resets and Interrupts

Resets

MC68HC912DG128 — Rev 3.0 Technic al Data

Resets and Interrupts

To prevent a COP reset from being detected during an external reset,

hold the reset pin low for at least 32 cycles. To prevent a or clock monitor

reset from being detected during an external reset, hold the reset pin low

for at least 4096 + 32 cycles. An external RC power-up delay circuit on

the reset pin is not recommended as circuit charge time can cause the

MCU to misinterpret the type of reset that has occurred.

9.7.3 COP Reset

The MCU includes a computer operating p roperly (COP) system to help

protect ag ai nst software fai l ures. When CO P is en ab le d, softw are m u st

write $55 and $AA (in this order) to the COPRST register in order to keep

a watc hdog timer fr om timing out. Other instructions may be executed

between these writes. A write of any value other than $55 or $AA or

software failing to execute the sequence properly causes a COP reset to

occur. In addition, windowed COP operation can be selected. In this

mode, a write to the CO PRST registe r must occur in th e last 25% of th e

selected period. A premature write will also reset the part.

9.7.4 Clock Monitor Reset

If clock frequency falls belo w a prede termined limit whe n the clock

monito r is enabled, a reset occurs.

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Resets and Interrupts

Technical Data MC68HC912DG128 — Rev 3.0

Resets and Interrupts

9.8 Effects of Reset

When a reset occurs, MCU regi ster s and control bits are changed to

known start- up states, as follows .

9.8.1 Operating Mode and Memory Map

Operating mode and default memory mapping are determined by the

states of the BK GD, MODA, and MODB pins during reset. The SMODN,

MODA, and MODB bits in the MODE register reflect the status of the

mode-select inputs at the rising edge of reset. Operating mode and

default maps can subs equently be changed according to strictly defined

rules.

9.8.2 Clock and Watchdog Control Logic

The COP watchdog system is enabled, with the CR[2:0] bits set for the

longest duration time-out. The clock monitor is disabled. The RTIF flag

is cleared and automatic hardware interrupts are masked. The rate

control bits are cleared, and must be initialized before the RTI system is

used. The DLY control bit is set to specify an oscillator start-up delay

upon recovery from STOP mode.

9.8.3 Interrupts

PSEL is initialized in the HPRIO register with the value $F2, causing the

external IRQ pin to have the highest I-bit interrupt priority. The IRQ pin

is configured for level-sensitive operation (for wired-OR systems).

However, the interrupt mask bits in the CPU12 CCR are set to mask X-

and I-related interrupt requests.

9.8.4 Parallel I/O

If the MCU comes out of reset in a single-chip mode, all ports are

configured as general-purpose high-impedance inputs.

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Resets and Interrupts

Effects of Reset

MC68HC912DG128 — Rev 3.0 Technic al Data

Resets and Interrupts

If the MCU com es ou t of reset in an expa nd ed m od e, po rt A and po rt B

are used for the address/ data bus, and port E pins are no rmally used to

control th e ext ernal bus ( oper ation of p ort E pin s can b e affecte d by the

PEAR register). Out of reset, port J, port H, port K, port IB, port P, port

S, port T, port CAN[7:4], port AD0 and port AD1 are all configured as

gener al - pur p ose in puts.

9.8.5 Central Processing Unit

After reset, the CPU fetches a vector from the appropriate address, then

begins executing instructions. The stack pointer and other CPU registers

are inde terminate immediately after reset. The CCR X and I interrupt

mask bits are set to mask any inte rrupt request s. The S bit is also set t o

inhibi t the STOP in str uct io n.

9.8.6 Memory

After reset, the internal register block is located from $0000 to $03FF,

RAM is at $2000 to $3FFF, and EEPROM is located at $0800 to $0FFF.

In single chip mode, one 32-Kbyte Flash module is located from $4000

to $7FFF and $C000 to $FFFF, and the other three 32-Kbyte Flash

modules are accessible through the program page window located from

$8000 to $BFFF. The first 32-Kbyte FLASH EEPROM is also accessible

through the program page window.

9.8.7 Other Resources

The enhanced capture timer (ECT), pulse width modulation timer

(PWM), serial communications interfaces (SCI0 and SCI1), serial

periph eral interface (S PI), inter -IC bus (IIC), Freescale Scalable CAN

modules (FSCAN0 and FSCAN1) and analog-to-digital converters

(ATD0 and ATD1) are off after reset.

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Resets and Interrupts

Technical Data MC68HC912DG128 — Rev 3.0

Resets and Interrupts

9.9 Register Stacking

Once enabled , a n i nterru pt re quest c an be re cognized at any ti me after

the I bit in the CCR is cleared. When an interrup t service request is

recognized, the CPU responds at the completion of the instruction being

executed. Interrupt latency varies according to the number of cycles

required to complete the instruction. Some of the longer instructions can

be interrupted and will resume normally after servicing the interrupt.

When the CPU begins to service an interrupt, the instruction queue is

cleared, the return address is cal culated, and then it and the contents of

the CPU registers are stacked as shown in Table 9 -2.

After the CCR is stacked, the I bit (and the X bit, if an XIRQ interrupt

service request is pending) is set to prevent other interrupts from

disrupting the interrupt service routine. The interrupt vector for the

highe st priority sou rce that w as pending a t the begi nning of the interrupt

sequence is fetched, and execution continues at the referenced location.

At the end of the interrupt service routine, an RTI instruction restores the

content of all regi sters from in formation on t he stac k, and normal

prog ram execution resumes.

If another interrupt is pending at the end of an interrupt service routine,

the register unstacking and restacking is bypassed and the vector of the

interrupt is fetched.

Table 9-2. Stacking Order on Entry to Interrupts

Memory Location CPU Registers

SP – 2 RTNH : RTNL

SP – 4 YH : YL

SP – 6 XH : XL

SP – 8 B : A

SP – 9 CCR

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Resets and Interrupts

Technical Data MC68HC912DG128 — Rev 3.0

Resets and Interrupts

9.10 Important User Information

Before disabling an inter rupt using a local interrupt control bit, set the I

mask bit in the CCR. Failing to d o so may cause an SWI interrup t to b e

fetched instead of the vector for the interrupt source that was disabled.

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Resets and Interrupts

Technical Data MC68HC912DG128 — Rev 3.0

Resets and Interrupts

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MC68HC912DG128 — Rev 3.0 Technic al Data
I/O Ports with Key Wake-up
 
Technical Data — MC68HC912DG128
Section 10. I/O Ports with Key Wake-up
10.1  Contents
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
10.3 Key Wake-up and Port Registers . . . . . . . . . . . . . . . . . . . . . .148
10.4 Key Wake-Up Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
10.2  Introduction
The MC68HC912DG128 of fers 16 additional I/O ports with key wake-up 
capability.
The key wake-up feature of the MC68HC912DG128 issues an interrupt 
that will wake up the CPU when it is in the STOP or WAIT mode. Two 
ports are associated with the key wake-up function: port H and port J. 
Port H and port J wake-ups are triggered with a rising or falling signal 
edge. For each pin which has an int errupt enabled, there is a path to the 
interrupt request signal which has no clocked devices when the part is in 
stop mode. This allows an active edge to bring the part out of stop.
Digital filtering is included to prevent pulses shorter than a specified 
value from waking the part from STOP.
An interrupt is generated when a bit in the KWIFH or KWIFJ register and 
its corresponding KWIEH or KWIEJ bit are both set. All 16 bits/pins share 
the same interrupt vector. Key wake-ups can be used with the pins 
configured as inputs or outputs.
Default register addresses, as established after reset, are indicated in 
the following descriptions. For information on re-mapping the register 
block, refer to Operating Modes.
    
  
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I/O Ports with Key Wake-up

Technical Data MC68HC912DG128 — Rev 3.0

I/O Ports with Key Wake-u p

10.3 Key Wake-up and Port Registers

Read and write anytime.

Data direction register J is associated with port J and designates each

pin as an input or output.

Read and write anytime

DDRJ[7:0] — Data Direction Port J

0 = Associated pi n is an input

1 = Associated pin is an output

PORTJ — Port J Register $0028

Bit 7654321Bit 0

PORT PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0

KWU KWJ7 KWJ6 KWJ5 KWJ4 KWJ3 KWJ2 KWJ1 KWJ0

RESET: - - - - - - - -

Bit 7654321Bit 0

PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0

KWU KWH7KWH6KWH5KWH4KWH3KWH2KWH1KWH0

RESET: - - - -----

PORTH — Port H Register $0029

Bit 7654321Bit 0

DDJ7 DDJ6 DDJ5 DDJ4 DDJ3 DDJ2 DDJ1 DDJ0

RESET: 0 0 000000

DDRJ — Port J Data Direction Register $002A

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I/O Ports with Key Wake-up

Key Wake-up and Port Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

I/O Ports with Key Wake-up

Data dir ection re giste r H is associa ted with port H and de sign ates each

pin as an input or output. Read and write anytime.

DDRH[7:0] — Data Dir ec tion Por t H

0 = Associated pi n is an input

1 = Associated pin is an output

Read and write anytime.

KWIEJ[7:0] — Key Wake-up Port J Interrupt Enables

0 = Interrupt for the associated bit is disabled

1 = Interrupt for the associ a ted bit is enabl e d

Read and write anytime.

KWIEH[7:0] — Key Wake-up Port H Interrupt Enables

0 = Interrupt for the associated bit is disabled

1 = Interrupt for the associ a ted bit is enabl e d

Bit 7654321Bit 0

DDH7 DDH6 DDH5 DDH4 DDH3 DDH2 DDH1 DDH0

RESET: 0 0 000000

DDRH — Port H Data Direction Register $002B

KWIEJ — Key Wake-up Port J Interrupt Enable Register $002C

Bit 7654321Bit 0

KWIEJ7 KWIEJ6 KWIEJ5 KWIEJ4 KWIEJ3 KWIEJ2 KWIEJ1 KWIEJ0

RESET: 0 0000000

Bit 7654321Bit 0

KWIEH7 KWIEH6 KWIEH5 KWIEH4 KWIEH3 KWIEH2 KWIEH1 KWIEH0

RESET: 0 0 000000

KWIEH — Key Wake-up Port H Interrupt Enable Register $002D

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I/O Ports with Key Wake-up

Technical Data MC68HC912DG128 — Rev 3.0

I/O Ports with Key Wake-u p

Read and write anytime.

Each flag is set by an active edge on its associated input pin. This could

be a rising or falling edge based on the state of the KWPJ registe r. To

clear the flag, write one to the corresponding bit in KWIFJ.

Initialize this register after initializing KWPJ so that illegal fla gs ca n be

cleared.

KWIFJ[7:0] — Key Wake-up Port J Flags

0 = Active edge on the associated bit has not occurred

1 = Active edge on the associated bit has occurred (an interrupt will

occur if the associated enable bit is set).

Read and write anytime.

Each flag is set by an active edge on its associated input pin. This could

be a rising or falling edge based on the state of the KWPH register. To

clear the flag, write one to the corresponding bit in KWIFH.

Initialize this register after initializing KWPH so that illegal flags can be

cleared.

KWIFH[7:0] — Key Wake-up Port H Flags

0 = Active edge on the associated bit has not occurred

1 = Active edge on the associated bit has occurred (an interrupt will

occur if the associated enable bit is set)

KWIFJ — Key Wake- up Port J Flag Registe r $002E

Bit 7654321Bit 0

KWIFJ7 KWIFJ6 KWIFJ5 KWIFJ4 KWIFJ3 KWIFJ2 KWIFJ1 KWIFJ0

RESET: 00000000

Bit 765432 1Bit 0

KWIFH7 KWIFH6 KWIFH5 KWIFH4 KWIFH3 KWIFH2 KWIFH1 KWIFH0

RESET: 0 0 0 0 0 0 0 0

KWIFH — Key Wake-up Port H Flag Register $002F

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I/O Ports with Key Wake-up

Key Wake-up and Port Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

I/O Ports with Key Wake-up

Read and write anytime. It is best to clear the flag s after initializing this

flag to become set.

KWPJ[7:0] — Key Wake-up Port J Polarity Selects

0 = Falling edge on the associated port J pin sets the associated

flag bit in the KWIFJ register and a resistive pull-up device is

connected to associated port J input pin.

1 = Risi ng edge on the associated port J pin sets the ass ocia ted

flag bit in the KWIFJ register and a resistive pull-down device

is connected to associated port J input pin.

Read and write anytime. It is best to clear the flag s after initializing this

flag to become set.

KWPH[7:0] — Key Wake-up Port H Polarity Selects

0 = Falling edge on the associated port H pin sets the associated

flag bit in the KWIFH register and a resistive pull-up device is

connecte d to associ ate d port H in put pin.

1 = Risi ng edge on the associated port H pi n sets the associa ted

flag bit in the KWIFH register and a resistive pull-down device

is connected to associated port H input pin.

KWPJ — Key Wake-u p Port J Polarity Register $0030

Bit 7654321Bit 0

KWPJ7 KWPJ6 KWPJ5 KWPJ4 KWPJ3 KWPJ2 KWPJ1 KWPJ0

RESET: 0 0 0 00000

KWPH — Key Wake-up Port H Polarit y Register $0031

Bit 7654321Bit 0

KWPH7 KWPH6 KWPH5 KWPH4 KWPH3 KWPH2 KWPH1 KWPH0

RESET: 00000000

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I/O Ports with Key Wake-up

Technical Data MC68HC912DG128 — Rev 3.0

I/O Ports with Key Wake-u p

10.4 Key Wake-Up Input Filter

The KWU input signals are filtered by a digital filter which is active only

during S TOP m ode. The pu rpose of the fi lte r is to pr event sing le pu lses

shorter than a specified value from waking the part from STOP.

The filter is composed of an internal oscillator and a majority voting logic.

The filter oscillator starts oscillation by detecting a triggering edge on an

input i f the corr espo ndin g inte rrup t enabl e bit is set. The ma jor ity voti ng

logic takes three samples of an asserted input pin at each filter oscillator

period and if two samples are taken at the triggering level, the filter

recognizes a valid triggering level and sets the corresponding interrupt

flag. In this way, the majority vo ting logic rejects the short non-triggering

state between two incoming triggering pulses. As the filter is shared with

all KW U in puts, the fi lter co nsid ers any p ulse comi ng from any in put p in

for which the corresponding interrupt enable bit is set.

The timing specification is given for a single pulse. The time interval

between the triggering edges of two following pulses should be greater

than th e tKWSP in order to be considered as a single pulse by the filter. If

this time interval is shorter than tKWSP, the majority voting logic may treat

the two consecutive pulses as a single valid pulse.

The filter is shared by all the KWU pins. Hence any valid triggering level

on any KWU pin is seen by the filter. The timing specification applies to

the input of the filter.

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I/O Ports with Key Wake-up

Key Wake-Up Input Filter

MC68HC912DG128 — Rev 3.0 Technic al Data

I/O Ports with Key Wake-up

Figure 10-1. STOP Key Wake-up Filter

Glitch, filtered out, no STOP wake-up

Valid STOP Wake-Up pulse

tKWSTP min.

tKWSTP max.

Minimum time interval between pulses to be recognized as single pulses

tKWSTP

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I/O Ports with Key Wake-up

Technical Data MC68HC912DG128 — Rev 3.0

I/O Ports with Key Wake-u p

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MC68HC912DG128 — Rev 3.0 Technic al Data
Clock Functions
 
Technical Data — MC68HC912DG128
Section 11. Clock Func tions
11.1  Contents
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
11.3 Clock Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
11.4 Phase-Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . .157
11.5 Acquisition and Tracking Modes. . . . . . . . . . . . . . . . . . . . . . .159
11.6 Limp-Home and Fast STOP Recovery modes. . . . . . . . . . . .161
11.7 System Clock Frequency formulas. . . . . . . . . . . . . . . . . . . . .179
11.8 Clock Divider Chains  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
11.9 Computer Operating Properly (COP) . . . . . . . . . . . . . . . . . . .184
11.10 Real-Time Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
11.11 Clock Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
11.12 Clock Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
11.2  Introduction
Clock generation circuitry generates the internal and external E-clock 
signals as well as internal clock signals used by the CPU and on-chip 
peripherals. A clock monitor circuit, a computer operating properly 
(COP) watchdog circuit, and a periodic interrupt circuit are also 
incorporated into the 68HC(9)12DG128.
    
  
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Clock Functions

Technical Data MC68HC912DG128 — Rev 3.0

Clock Functions

11.3 Clock Sources

A compatible external clock signal can be applied to the EXTAL pin or

the MCU can generate a clock signal using an on-chip oscillator circuit

and an external crystal or ceramic resonator. The MCU uses several

types of internal clock signals derived from the primary clock signal:

TxCLK clocks are used by the CPU.

ECLK a nd PC LK a r e u sed b y th e b us inte r face s , SP I, PW M , ATD0 and

ATD1.

MCLK is either PCLK or XCLK, and drives on-chip modules such as

SCI0, SCI1 and ECT.

XCLK drives on-chip modules such as RTI, COP and restart-from-stop

delay time.

SLWCLK is used as a calibration output signal.

The MSCAN module is clocked by EXTALi or SYSCLK, under control of

an MSCAN bit.

The clock monitor is clocked by EXTALi.

The BDM system is clocked by BCLK or ECL K, unde r control of a BDM

bit.

A slow mode clock divider is included to deliver a lower clock freque ncy

for the SCI baud rate generators, the ECT timer module, and the RTI and

COP clocks. The slow clock bus frequencies divide the crystal frequency

in a programmable range of 4 to 252, with steps of 4.

Figure 11-1 shows some of the timing relationships. See the Clock

Divider Chains section for furthe r details.

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Clock Functions

Phase-Locked Loop (PLL)

MC68HC912DG128 — Rev 3.0 Technic al Data

Clock Functions

Figure 11-1. Internal Clock Relationships

11.4 Phase-Locked Loop (PLL)

The phase-locked loop (PLL) of the 68HC(9)12DG128 is designed for

robust operation in an Automotive environment. The allowed PLL crystal

or ceramic resonator reference of 0.5 to 8MHz is selected for the wide

availability of components with good stability over the automotive

temper a tur e rang e. Please r efe r to Figure 11-6 in section Clock Divider

Chains for an overview of system clocks.

NOTE: When sele cting a crystal, i t is recom mended to use one with t he lowe st

possible frequency in order to minimise EMC emissions.

An oscillator design with reduced power consumption al lows fo r slow

wait operation with a typical powe r supply current less than a milli-

ampere. The PLL circuitry can be bypassed when the VDDPLL supply is

at VSS level. In this case, the PLL module is powered down and the

oscillator output transistor has a stronger transconductance for improved

drive of higher frequency resonators (as the crystal frequency needs to

be twice the maximum bus frequency). Refer to Figure 3-3 in Pinout and

Signal Descriptions.

T1CLK

T2CLK

T3CLK

T4CLK

INT ECLK

PCLK

XCLK

CANCLK

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Clock Functions

Technical Data MC68HC912DG128 — Rev 3.0

Clock Functions

Figure 11-2. PLL Functional Diagram

The PLL may be used to run the MCU from a different time base than the

incoming crystal value. It creates an integer multiple of a reference

frequency. For increased flexibility, the crystal clock can be divided by

values in a range of 1 – 8 (in unit step s) to generate the reference

frequency. The PLL can multiply this reference clock in a range of 1 to

64. Although it is possible to set the divider to command a very high clock

freque ncy, do no t exceed th e speci fied bus fr equen cy limi t for the MCU .

If the PLL is selected, it will continue to run when in WAIT mode resulting

in more power cons umptio n than normal. To t ak e full adv antage of the

reduced power consumption of WAIT mode, turn off the PLL before

going into WAIT. Please note that in this case the PLL stabilization time

applies.

The PLL operation is suspended in STOP mode. After STOP exit

followed by the stabilization time, it resumes operation at the same

frequency, provided the AUTO bit is set.

A passive external loop filter mus t be placed on the control line (XFC

pad). The filter is a second-order, low-pass filter to eliminate th e VCO

input ripple. Values of components in the diagram are dependent upon

the desired VCO operation. See XFC description.

REDUCED

CONSUMPTION

OSCILLATOR

EXTAL

XTAL EXTALi

PLLCLK

REFERENCE

PROGRAMMABLE

DIVIDER PDET

PHASE

DETECTOR

REFDV <2:0>

LOOP

PROGRAMMABLE

DIVIDER

SYN <5:0>

CPUMP VCO

LOCK

LOOP

FILTER XFC

PAD

DOWN

LOCK

DETECTOR

REFCLK

DIVCLK

SLOW MODE

PROGRAMMABLE

CLOCK DIVIDER

SLDV <5:0>

XCLK

EXTALi

÷2

SLWCLK VDDPLL

× 2

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Clock Functions

Acquisition and Tracking Modes

MC68HC912DG128 — Rev 3.0 Technic al Data

Clock Functions

11.5 Acquisition and Tracking Modes

The lock detector compares the frequencies of the VCO feedback clock,

DIVCLK, and the final reference clock, REFCLK. Therefore, the speed

of the lock detector is directly proportional to the final reference

frequency. The circuit determines the mode of the PLL and the lock

condition based on this comparison.

The PLL filter is manually or automatically configurable into one of two

operating modes:

•Acquisi tion mode — In acquisition mode, the filter can make large

freque ncy corrections to the VCO . This mod e is used at PLL start-

up or whe n th e PL L has suffer ed a sever e noise hit and the VCO

freque ncy is fa r off the desire d freq uency. Thi s mod e can also b e

desired in harsh environments when the leakage levels on the

filter pin (XFC) can overcome the tracking currents of the PLL

charge pump. When in acquisition mode, the ACQ bit in the PLL

control register is clear.

•Tracking mode — In tracking mode, the filter makes only small

correc tions t o the fr eque ncy of th e VCO. The PLL enters trackin g

mode when the VCO frequency is nearly correct. The PLL is

automatically in tracking mode when no t in acquisition mo de or

when the ACQ bit is set.

The PLL can change the bandwidth or operational mode of the loop filter

manually or automatically. With an identical filtering time constant, the

PLL bandwidth is larger in acquisition mode than in tracking by a ratio of

about 3.

In automatic bandwidth control mode (AUTO = 1), the lock detector

automatically switches between acquisition and tracking modes.

Automatic bandwidth control mode also is used to determine when the

VCO clock, PLLCLK, is safe to use as the source for the base clock,

SYSCLK. If PLL LOCK interrupt requests are enabled, the software can

wait for an interrupt request and then check the LOCK bit. If CPU

interrupts are disabled, software can poll the LOCK bit continuously

(during PLL start-up, usually) or at periodic intervals. In either case,

when the LOCK bit is set, the PLLCLK clock is safe to use as the source

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Clock Functions

Technical Data MC68HC912DG128 — Rev 3.0

Clock Functions

for the base clock. Se e Clock Divider Chains. If the VCO is selected as

the source for the base clock and the LOCK bit is clear, the PLL has

suffered a severe noise hit and the software must take appropriate

action, depending on the application.

The following conditions apply when the PLL is in automatic bandwidth

control mode:

•The ACQ bit is a read-only indicator of the mode of the filter.

•The ACQ bit is set when the VCO frequency is within a certain

tolerance, ∆trk, and is cleared when the VCO frequency is out of a

certain tolerance, ∆unt. See 19 Electr ical Charact erist ics.

•The LOCK bit is a read-only indicator of the locked state of the PLL.

•The LOCK bit is set when t he VCO frequency is within a certain

tolerance, ∆Lock, and is cleared w hen the VCO fr equency is out of

a cert ain tolerance, ∆unl. See 19 Electrical Characteristics.

•CPU interrupts can occur if enabled (LOCKIE = 1) when the lock

condition changes, toggling the LOCK bit.

The PLL also can operate in manual mode (AUTO = 0). All LOCK

feat ures described above are active in this mode, only the bandwidth

control is disabled. Manual mode is used mainly for systems operating

under harsh conditions (e.g.uncoated PCBs in automotive

environments). When this is the case, the PLL is likely to remain in

acquisi tion mo de. The fo llowin g conditi ons app ly when in m anual mode :

•ACQ is a writable control bit that controls the mode of the filter.

Before turning on the PLL in manual mode, the ACQ bit must be

clear.

•In case tracking is desired (ACQ = 1), the software must wait a

given time, tacq, aft er turning on the PLL by settin g PLLON in the

PLL control register. This is to avoid switching to tracking mode

too early while the XFC voltage level is still too far away from its

quiescent value corresponding to the target frequency. This

operation would be very detrime nta l to the stabilization time.

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Clock Functions

Limp-Home and Fast STOP Recovery modes

MC68HC912DG128 — Rev 3.0 Technic al Data

Clock Functions

11.6 Limp-Home and Fast STOP Recovery modes

If the crystal frequency is not available due to a crystal failure or a long

crystal start-up time, the MCU system clock can be supplied by the VCO

at it s minimum operating frequ ency, f VCOMIN. This mode o f operation is

called Limp-Home Mode and is only available when the VDDPLL supply

voltage is at VDD level (i.e. power supply for the PLL module is present).

Upon power-up, the ability of the system to start in Limp-Home Mode is

restricted to norma l MCU modes only.

The Clock Monitor circuit (see section Clock Monitor) can detect the loss

of EXTALi, the external clock input signal, regardless of whether this

signal is used as the source for MCU clocks or as the PLL reference

clock. The clock monitor control bits, CME and FCME, are used to

enable or disable external clock detection.

A missing external clock may occur in the three following instances:

•During n ormal clock operation.

•At Power-On Reset.

•In the STOP exit sequence

11.6.1 Clock Loss during Normal Operation

The ‘no limp-home mode’ bit, NOLHM, determines how the MCU

responds to an external clock loss in this case.

With limp home mode disabled (NOLHM bit set) and the clock monitor

enabled (CME or FCME bits set), on a loss of clock the MCU is reset via

the clock monitor reset vector. A latch in the PLL control section prevents

the chip exiting reset in Limp Home Mode (this is required as the NOLHM

bit gets cleared by reset). Only external clock activity can bring the MCU

out from this reset state. Once reset has been exited, the latch is cleared

and another session, with or without Limp Home Mode enabled, can

take place. This is the same behavior as standard M68HC12 circuits

without PLL or operation with VDDPLL at VSS level.

With limp home mode enabled (NOLHM bit cleared) and the clock

monitor enabled (CME or FCME bits set), on a loss of clock, the PLL

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Clock Functions

Technical Data MC68HC912DG128 — Rev 3.0

Clock Functions

VCO clock at its minimum frequency, f VCOMIN, is provided as the system

clock, allowing the MCU to c ontinue oper ating.

The MCU is said to be oper atin g in “limp-home” mode with the forced

VCO clock as the system clock. PLLON and BCSP (‘bus clock select

PLL’) signals are force d high and the MCS (‘module clock select’) si gnal

is force d l ow. The LHOME flag in th e PL LFLG registe r is se t to in di cat e

that the MCU is running in limp-home mode. A change of this flag sets

the limp-home interrupt flag, LHIF, and if enabled by the LHIE bit, the

limp-home mode interrupt is requested. The Clock Monitor is enabled

irrespective of CME an d FCME bit settin gs. Module clocks to the RTI &

COP (XCLK), BDM (BCLK) and ECT & SCI (MCLK) are forced to be

PCLK (at f VCOMIN) and ECLK is also equal to f VCOMIN. MSCAN clock

select is unaffected.

Figure 11-3. Clock Loss during Normal Operation

The clock moni tor is polle d each time the 13 -stage free ru nning cou nter

reaches a count of 4096 XCLK cycles i.e. mid-count, hence the clock

status ge ts checked once every 8192 XCLK cycles. When the pres ence

of an ext ernal clock is detected , the MCU exits lim p-home mo de,

clearin g the LHOME flag and se tting the li mp-home inte rru pt flag. Upon

leaving limp-home mode, BCSP and MCS signals are restored to their

0 --> 4096

Limp-Home

(Clocked by XCLK)

BCSP Restore BCSP

SYSCLK PLLCLK (Limp-Home) Restore PLLCLK or EXTALi

EXTALi

13-stage counter

Clock Monitor Fail

0 --> 4096

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Clock Functions

Limp-Home and Fast STOP Recovery modes

MC68HC912DG128 — Rev 3.0 Technic al Data

Clock Functions

values before the clock loss. All clocks return to their normal settings and

Clock Monitor control is returned to the CME & FCME bits. If AUTO and

BCSP bits were set before the clock loss (selecting the PLL to provide a

system clock) the SYSCLK ramps-up and the PLL locks at the previously

selected frequency. To prevent PLL operation when the external clock

frequency comes back, software should clear the BCSP bit while running

in lim p- h om e mo de.

The two shaded regio ns A and B in Figure 11-3 present a of code run

away due to incorrect clocks on SYSCLK if the MCU is clocked by

EXTALi and the PLL is not used.

In region A, there is a delay between the loss of clock and its detection

by the clock monitor. When the EXTALi clock signal is disturbed, the

clock generation circuitry may receive an out of spec signal and drive the

CPU with irregular clocks. This may lead to code runaway.

In region B, as the 13-stage counter is free running, the count of 4096

may be reached when the amplitude of the EXTALi clock has not

stabilized. In this case, an improper EXTALi is sent to the clock

generation circuitry when limp-home mode is exited. This may also

cause code runaway.

If the MCU is clocked by the PLL, the risk of code runaway is very

low, but it can still occur under certain conditions due to irregular

clocks from the clock source appearing on the SYSCLK.

CAUTION: The COP watch dog should always be enabled in order to reset the MCU

in case of a code runaway situation.

NOTE: It is always advisable to take additional precautions within the

application software to trap such situations.

11.6.2 No Clock at Power-On Reset

The voltage level on VDDPLL determines how the MCU responds to an

external clock loss in this case.

With the VDDPLL supply voltage at VDD level, any reset sets the Clock

Monitor Enable bit (CME) and the PLLON bit and clears the NOLHM bit.

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Clock Functions

Technical Data MC68HC912DG128 — Rev 3.0

Clock Functions

Therefore, if the MCU is powered up without an external clock, limp -

home mode is entered provided the MCU is in a normal mode of

operation.

Figure 11-4. No Clock at Power-On Reset

VDD

Power-On Detector

Clock Monitor Fail

EXTALi

13-stage counter

Internal reset

0 --> 4096

Limp-Home

(Clocked by XCLK)

BCSP Reset: BCSP = 0

SYSCLK PLLCLK (L.H.) EXTALi

SYSCLK PLLCLK (Software check of Limp-Home Flag) EXTALi

(Slow EXTALi)

0 --> 4096

(Slow EXTALi)

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Clock Functions

Limp-Home and Fast STOP Recovery modes

MC68HC912DG128 — Rev 3.0 Technic al Data

Clock Functions

During this power up sequence, after the POR pulse falling edge, the

VCO supplies the limp-home clock frequency to the 13-stage counter, as

the BCSP output is forced high and MCS is forced low. XCLK, BCLK and

MCLK are forced to be PC LK, which is suppli ed by the VCO at fVCOMIN.

The initial period taken for the 13-stage counter to reach 4096 defines

the internal reset period.

If the clock monitor indicates the presence of an external clock during the

internal reset period, limp-home mode is de-asserted and the 13-stage

counter is then driven by EXTALi clock. After the 13-stage counter

reaches a co unt of 4096 XCLK cycle s, the internal reset is relea sed, the

13-stage counter is reset and the MCU exits reset normally using

EXTALi clock.

However, if the crystal start-up time is longer than the initial count of

4096 XCLK cycles, or in the absence of an exte rnal clock, the MCU will

leave the reset state in limp-home mode. The LHOME flag is set and

LHIF l i mp- hom e interrupt r equ est is se t, to i ndi ca te i t is no t o per a ti ng at

the desired frequency. Then after yet another 4096 XCLK cycles

follow ed reg ularl y by 81 92 XC LK cy cles (corr espon ding to the 13-sta ge

counter timing out), a check of the clock monitor status is performed.

When the presence of an external clock is detected limp-home mode is

exited generating a limp-home interrupt if enabled.

CAUTION: The clock monitor circuit can be misled by the EXTALi clock into

reporting a good signal before it has fully stabilised. Under these

conditions improper EXTALi clock cycles can occur on SYSCLK. This

may lead to a code runaway. To ensure that this situation does not

occur, the external Reset period should be longer than the oscillator

stabilisation time - this is an applic ation dependent parameter.

With the VDDPLL supply voltage at VSS level, the PLL module and

hence limp-home mode are disabled, the device will remain effectively

in a static state whilst there is no activity on EXTALi. The internal reset

period and MCU o pe ration will execute only on EXTALi clock.

NOTE: The exte rnal clock signal must stabilise within the initial 4096 re set

counter cycles.

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Clock Functions

Technical Data MC68HC912DG128 — Rev 3.0

Clock Functions

11.6.3 STOP Exit and Fast STOP Recovery

Stop mode is entered when a STOP instruction is executed. Recovery

from STOP depends primarily on the state of the three status bits

NOLHM, CME & DLY.

The DLY bit controls the duration of the waiting period between the

actual exit for some key blocks (e.g. clock monitor, clock generators) and

the effective exit from stop for all the rest of the MCU. DLY=1 enables

the 13- stage counter to generat e a 4096 count dela y. DLY=0 selects no

delay. As the XCLK is derived from the slow mode divider, the value in

the SLOW register modifies the actual delay time.

NOTE: DLY=0 is only recommended when there is a good signal available

at the EXTAL pin (e.g. an external square wave source).

STOP mode is exited with an external reset, an external interrupt from

IRQ or XIRQ, a Key Wake-Up interrupt from port J or port H, or an

MSCAN Wake-Up interrupt.

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Clock Functions

Limp-Home and Fast STOP Recovery modes

MC68HC912DG128 — Rev 3.0 Technic al Data

Clock Functions

Figure 11-5. STOP Exit and Fast STOP Recovery

11.6.4 STOP exit without Limp Home mode, clock monitor disabled

(NOLHM=1, CME=0, DLY=X)

If Limp home mode is disabled (VDDPLL=VSS or NO LHM bi t set) a nd the

CME (or FCME) bit is cleared, the MCU go es into STOP mode when a

STOP instruction is executed.

If EXTALi clock is present then exit from STOP will occur normally using

this clock. Under this condition, DLY should always be set to allow the

crystal to stabil i se an d mini m ise the ri sk of code ru na way. Wi th DLY= 1

execution re sumes afte r a delay of 4096 XCLK cycles.

NOTE: The external clock signal should stabilise within the 4096 reset counter

cycles. Use of DLY=0 is not recommended due to this requirement.

Clock Monitor Fail

EXTALi

13-stage counter 0 --> 4096

Limp-Home

(Clocked by XCLK)

BCSP Restore BCSP

SYSCLK PLLCLK (L.H.) Restore PLLCLK or EXTALi

STOP (D L Y = 1)

STOP (D L Y = 0)

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Clock Functions

Technical Data MC68HC912DG128 — Rev 3.0

Clock Functions

11.6.5 Executing the STOP instruction without Limp Home mode, clock monitor enabled

(NOLHM=1, CME=1, DLY=X)

If the NOLHM bit and the CME (or FCME) bits are set, a clock monitor

failure is de tected when a STOP instruction is executed an d the MCU

resets via the clock monitor reset vector.

11.6.6 STOP exit in Limp Home mode with Delay

(NOLHM=0, CME=X, DLY=1)

If the NOLHM bit is cleared, then the CME (or FCME) bit is masked when

a STOP instruction is executed to prevent a clock monitor failure. When

comin g o ut o f STO P m od e, t he M C U go es i n to l im p- ho me m od e whe r e

CME and FCME signals are asserted.

When using a crystal oscilla to r, a norm al STOP exi t se que nce requi res

the DLY bit to be set to allow for the crystal stabilization period.

With the 13-stage counter clocked by the VCO (at fVCOMIN), following a

delay of 4096 XCLK cycles at the limp-home frequency, if the clock

monitor indicates the presence of an external clock, the limp-home mode

is de-asserted and the MCU exits STOP normally using EXTALi clock.

Wher e the cry stal st art-up time i s longer than the initial count of 4096

XCLK cycles, or in the a bsence of a n ex tern al clock, the MCU recove rs

from STOP following the 4096 count in limp-home mode with both the

LHOME flag set and the LHIF limp-home interrupt request set to indicate

it is not operating at the desired frequency. Each time the 13-stage

counter reaches a count of 4096 XCLK cycles, a check of the clock

monitor status is performed.

When th e presence of a n external clock is d etected, limp- home mode is

exited and the LHOME flag is cleared. This sets the limp-home interrupt

flag and if enabled by the LHIE bit, the limp-home mode interrupt is

requested.

CAUTION: The clock monitor circuit can be misled by EXTALi clock int o reporting a

good signal before it has fully stabilised. Under these conditions,

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Clock Functions

Limp-Home and Fast STOP Recovery modes

MC68HC912DG128 — Rev 3.0 Technic al Data

Clock Functions

improper EXTALi cloc k cycles ca n occ ur on SYS CLK. This may lea d t o

a code runa way.

11.6.7 STOP exit in Limp Home mode without Delay (Fast Stop Recovery)

(NOLHM=0, CME=X, DLY=0)

Fast STOP recovery refers to any exit from STOP using DLY=0.

If the NOLHM bit is cleared, then the CME (or FCME) bit is masked when

a STOP instruction is executed to prevent a clock monitor failure. When

comin g o ut o f STO P m od e, t he M C U go es i n to l im p- ho me m od e whe r e

CME and FCME signals are asserted.

When using a crystal oscillator, it is possible to exit STOP with the DLY

bit cleared. In this case, STOP is de-asserted without delay and the MCU

will execute software in limp-home mode, giving the crystal oscillator

time to stablise.

CAUTION: This mode is not recommended since the risk of the clock monitor

detecting incorrect clocks is high.

Each time the 13-stage counter reaches a count of 4096 XCLK cycles

(every 8192 cycles), a check o f the clock monitor st atus is performed . If

the clock mon itor indicates the presence of an e xternal clock limp-home

mode is de-asserted, the LHOME flag is cleared and the limp-home

inter rupt flag is set. Up on leavin g limp-h ome mode , BCSP and MCS are

restored to their values before the loss of clock, and all clocks return to

their previous frequencies. If AUTO and BCSP were set before the clock

loss, the SYSCLK ramps-up and the PLL locks at the previously selected

frequency.

To prevent PLL operation when the external clock frequency comes

back, the software should clear the BCSP bit while running in limp-home

mode.

When using an external clock, i.e. a square wave source, it is possible

to exit STOP with the DLY bit cleared. In this case the LHOME flag is

never set and ST OP is de- as serted without delay.

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Clock Functions

Technical Data MC68HC912DG128 — Rev 3.0

Clock Functions

11.6.8 Pseudo-STOP

Pseud o-STOP i s a lo w powe r mod e similar to STO P wher e the e xternal

oscillator is allowed to run (at r educed amplitude) w hilst the rest o f the

part is in STOP. This increases the c urrent consumption over STOP

mode by the amount of current in the oscillator, but reduces wear and

mechanical stress on the crystal.

If the P STP bit in th e PLLCR registe r is set , the MCU goes in to Pseud o-

STOP mode when a STOP instruction is executed.

Pseudo-STOP mode is exited the same as STOP with an external reset,

an external interrupt from IRQ or XIRQ, a Key Wake-Up interrupt from

port J or port H, or an MSCAN Wake-Up interrupt.

The effect of the DLY bit is the same as noted above in STOP Exit and

Fast STOP Recovery.

11.6.9 Pseudo-STOP exit in Limp Home mode with Delay

(NOLHM=0, CME=X, DLY=1)

When coming out of Pseudo-STOP mode with the NOLHM bit cleared

and the D LY bi t set, the M CU goes i nto li mp-ho me mo de (reg ardle ss of

the state of the CME or FCME bits).

The VCO supplies the limp-home clock frequency to the 13-stage

counter (XCLK). The BCSP output is forced high and MCS is forced low.

After the 13-stage counter reaches a count of 4096 XCLK cycles, a

check of the clock monitor is performed and as the crystal oscillator was

kept running due to the Pseudo-stop mode, the MCU exits ST OP

normally, using the EXTALi clock. In the case where a crystal failure

occurred during pseudo-stop, then the MCU exits STOP using the limp

home clock (fVCOMIN) with both the LHOME flag set and the LHIF limp-

home interrupt request set to indicate it is not operating at the desired

frequency. Each time the 13-stage counter reaches a count of 4096

XCLK cycles, a check of the clock monitor is performed. If the clock

monitor indicates th e presence of an externa l clock, limp-h ome mode is

de-asserted, the LHOME flag is cleared and the LHIF limp-home

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Clock Functions

Limp-Home and Fast STOP Recovery modes

MC68HC912DG128 — Rev 3.0 Technic al Data

Clock Functions

interrupt request is set to indicate a return to normal operation using

EXTALi clock.

11.6.10 Pseudo-STOP exit in Limp Home mode without Delay (Fast Stop Recovery)

(NOLHM=0, CME=X, DLY=0)

If Pseudo-STOP is exited with the NOLHM bit set to 0 and the DLY bit is

cleared t hen the exit from P seudo-STO P is accompl ished wit hout delay

as in Fast STOP recovery.

CAUTION: Where Pseudo-STOP recovers using the Limp Home Clock the VCO -

which has been held i n STOP - m ust be re starte d in orde r to suppl y the

limp home frequency. This restart, which occurs at a high frequency and

ramps toward the limp home frequency, is almost immediately supplied

to the C PU b efo re i t ma y h ave r each ed th e steady state fr e que ncy. It i s

possible that the initial clock frequency may be high enough to cause the

CPU to function incorrectly with a resultant risk of code runaway.

11.6.11 Pseudo-STOP exit without Limp Home mode, clock monitor enabled

(NOLHM=1, CME=1, DLY=X)

If the NOLHM bit is set and the CME (or FCME) bits are set, a clock

monitor failure is detected when a STOP instruction is executed and the

MCU resets via the clock monitor reset vector.

11.6.12 Pseudo-STOP exit without Limp Home mode, clock monitor disabled

(NOLHM=1, CME=0, DLY=1)

If NOLH M is se t to 1 and the CM E and FCM E b its ar e cl ea r ed, the lim p

home clock is not used. In th is mode, crystal activity is the only method

by which the device may recover from Pseudo -STOP. The device will

start execution with the EXTALi clock following 4096 XCLK cycles.

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Clock Functions

Technical Data MC68HC912DG128 — Rev 3.0

Clock Functions

(NOLHM=1, CME=0, DLY=0)

If NOLH M is se t to 1 and the CM E and FCM E b its ar e cl ea r ed, the lim p

home clock is not used. In th is mode, crystal activity is the only method

by which the device may recover from Pseudo -STOP. The device will

start execution with the EXTALi clock following 16 XCLK cycles.

CAUTION: Due to switching of the clock this configuration is not recommended.

11.6.13 Summary of STOP and pseudo-STOP Mode Exit Conditions

Table 11-1 and Table 11-2 summarise the exit conditions from STOP

and pseudo-STOP modes using Interrupt, Key-interrupt and XIRQ.

A short RESET pulse should not be used to exit stop or pseudo-STOP

mode be caus e Limp H ome mode is auto ma ticall y enter ed afte r RE SET

(when VDDPLL=VDD). The RESET wakeup pulse must be longer than the

oscillator startup time (as in power on reset) in order to remove the risk

of code runaway.

Table 11-1. Summary of STOP Mode Exit Conditions

Mode Conditions Summary

STOP exit without Limp Home

mode,

clock monitor disabled

NOLHM=1

CME=0

DLY=X

Oscillator must be stable within 4096 XCLK cycles. XCLK

can be modified by SLOW divider register.

Use of DLY=0 only recommended with external clock.

Executing the STOP instruction

without Limp Home mode,

clock monitor enabled

NOLHM=1

CME=1

DLY=X

When a STOP instruction is executed the MCU resets via

the clock monitor reset vector.

STOP exit in Limp Home mode

with Delay

NOLHM=0

CME=X

DLY=1

Oscillator must be stable within 4096

fVCOMIN cycles or there is a possibility of code runaway as

the clock monitor circuit can be misled by EXTALi clock

into reporting a good signal before it has fully stabilised

STOP exit in Limp Home mode

without Delay (Fast Stop

Recovery)

NOLHM=0

CME=X

DLY=0

This mode is only recommended for use with an external

clock source.

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Clock Functions

Limp-Home and Fast STOP Recovery modes

MC68HC912DG128 — Rev 3.0 Technic al Data

Clock Functions

11.6.14 PLL Register Descriptions

Read anytime, write anytime, except when BCSP = 1 (PLL selected as

bus clock).

If the PL L is o n, the count in th e lo op di vider (SY NR) regi ster e ffectivel y

multiplies up the bus frequency from the PLL reference frequency by

SYNR + 1. Internally, SYS CLK runs at twice the bus frequency. Caution

should be used not to exceed the maximum rated operating frequency

for the CPU.

Table 11-2. Summary of Pseudo ST OP Mode Exit Conditions

Mode Conditions Summary

Pseudo-STOP exit in Limp Home

mode with Delay

NOLHM=0

CME=X

DLY=1

CPU exits stop in limp home mode and oscillator running. If

the oscillator fails during pseudo-STOP and then recovers

there is a possibility of code runaway as the clock monitor

circuit can be misled by EXTALi clock into reporting a

good signal before it has fully stabilised

Pseudo- S TOP exit

in Limp Home mode without

Delay (Fast Stop Recovery)

NOLHM=0

CME=X

DLY=0

This mode is not recommended as it is possible that the

initial VCO clock frequency may be high enough to cause

code runaway.

Pseudo-STOP exit without Limp

Home mode, clock monitor

enabled

NOLHM=1

CME=1

DLY=X

When a STOP instruction is executed the MCU resets via

the clock monit or reset vecto r.

Pseudo-STOP exit without Limp

Home mode, clock monitor

disabled, with Delay

NOLHM=1

CME=0

DLY=1

Oscillator starts operation following 4096 XCLK cycles

(actual controlled by SLOW mode divider).

Pseudo-STOP exit without Limp

Home mode, clock monitor

disabled, without Delay

NOLHM=1

CME=0

DLY=0

This mode is only recommended for use with an external

clock source.

Bit 765432 1Bit 0

0 0 SYN5 SYN4 SYN3 SYN2 SYN1 SYN0

RESET: 0 0 0 0 0 0 0 0

SYNR — Synthesizer Register $0038

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Clock Functions

Technical Data MC68HC912DG128 — Rev 3.0

Clock Functions

Read anytime, write anytime, except when BCSP = 1.

The reference divider bits provides a finer granularity for the PLL

multiplier steps. The reference frequency is divided by REFDV + 1.

Always reads zero, except in test modes.

Read anytime, refer to each bit for write conditions.

LOCKIF — PLL Lock Interrupt Flag

0 = No change in LOCK bit.

1 = LOCK condit io n has changed, eith er f ro m a lo cked state to an

unlocked state or vice versa.

To clear the flag, write one to this bit in PLLFLG. Cleared in limp-home

mode.

Bit 7654321Bit 0

0 0 0 0 0 REFDV2 REFDV1 REFDV0

RESET: 0 0 000000

REFDV — Reference Divider Register $0039

Bit 7654321Bit 0

TSTOUT7 TSTOUT6 TSTOUT5 TSTOUT4 TSTOUT3 TSTOUT2 TSTOUT1 TSTOUT0

RESET: 0 0 000000

CGTFLG — Clock Generat or Test Re gister $003A

Bit 765432 1Bit 0

LOCKIF LOCK 0 0 0 0 LHIF LHOME

RESET: 0 0 0 0 0 0 0 0

PLLFLG — PLL Flags $003B

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Clock Functions

Limp-Home and Fast STOP Recovery modes

MC68HC912DG128 — Rev 3.0 Technic al Data

Clock Functions

LOCK — Locked Phase Lock Loop Circuit

Regardless of the bandwidth control mode (aut omatic or manual):

0 = PLL VCO is not within the desired tolerance of the target

frequency.

1 = After th e phase lock loo p circui t is tu rned o n, indi cates the PLL

VCO is within the desired tolerance of the target frequency.

Write has no effe ct on LOCK bit. This bit is cleared in limp-home mode as

the lo ck detector cannot ope rate wi thout the r eferen ce frequenc y.

LHIF — Limp-Home Interrupt Flag

0 = No change in LHOME bit.

1 = LHOME condition has changed, either entered or exited limp-

home mode.

To clear the flag, write one to this bit in PLLFLG.

LHOME — Limp-H ome Mode Status

0 = MCU is operat ing normally, with EXTALi clock available for

generating clocks or as PLL reference.

1 = Loss of reference clock. CGM delivers PLL VCO limp-home

freque ncy to the MC U.

For Limp-Home mode, see Limp-Hom e and Fast STOP Recovery m odes.

Read an d write any time. Exc eptions are listed below f or each bit.

LOCKIE — PLL LOCK Interrupt Enable

0 = PLL LOCK interrupt is disabled

1 = PLL LOCK interrupt is enabled

Forced to 0 when VDDPLL=0.

Bit 7654321Bit 0

LOCKIE PLLON AUTO ACQ 0 PSTP LHIE NOLHM

RESET: 0 —(1) 10000

—(2)

PLLCR — PLL Control Register $003C

1. Set when VDDPLL power supply is high. Forced to 0 when VDDPLL is low.

2. Cleared when VDDPLL power supply is high. Forced to 1 when VDDPLL is low.

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Clock Functions

Technical Data MC68HC912DG128 — Rev 3.0

Clock Functions

PLLON — Phase Lock Loop On

0 = Turns the PLL off.

1 = Turns on the phase lock loop circuit. If AUTO is set, the PLL will

lock automatically.

Cannot be cleared when BCSP = 1 (PLL selected as bus clock).

Forced to 0 when VDDPLL is at VSS lev el. In limp-home mode , the

output of PLLON is forced to 1, but the PLLON bit reads the latched

value.

AUTO — Automatic Bandwidth Control

0 = Automatic Mode Control is disabled and the PLL is under

software control, using ACQ bit.

1 = Automatic Mode Control is enabled. ACQ bit is read only.

Automatic bandwidth control selects either the high bandwidth

(acquisition) mode or the low bandwidth (tracking) mode depending

on how cl ose to the desired frequ ency the VCO is runn ing. See

Electrical Spe c ifications.

ACQ — Not in Acquisition

If AUTO = 1 (ACQ is Read Only)

0 = PLL VCO is not within the desired tolerance of the target

frequency. The loop filter is in high bandwidth, acquisition

mode.

1 = After th e phase lock loo p circui t is tu rned o n, indi cates the PLL

VCO is within the desired tolerance of the target frequency.

The loop filter is in low bandwidth, tracking mode.

If AUTO = 0

0 = High bandwidth PLL loop se lected

1 = Low bandw i dt h P LL lo op sele cted

PSTP — Pseudo-STOP Ena ble

0 = Pseudo-STOP oscil lat or mo de is disabl ed

1 = Pseudo-STOP oscil lat or mo de is enable d

In Pseudo-STOP mode, the oscillator is still running while the MCU is

maintained in STOP mode. This allows for a faster STOP recovery

and reduces the mechanical stress and aging of the resonator in case

frequent STOP conditions at th e expense of a slightly increased

power consumption.

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Clock Functions

Limp-Home and Fast STOP Recovery modes

MC68HC912DG128 — Rev 3.0 Technic al Data

Clock Functions

LHIE — Limp-Home Interrupt Enable

0 = Limp-Home interrupt is disabled

1 = Limp-Home interrupt is enabled

Forced to 0 when VD DPLL is at VSS level.

NOLHM —No Limp-Home Mode

0 = Loss of reference clock forces the MCU in limp-home mode.

1 = Loss of reference clock causes standard Clock Monitor reset.

Read anytime; Normal modes: write once; Special modes: write

anytime. Forced to 1 when VDDPLL is at VSS level.

Read an d write any time. Exc eptions are listed below f or each bit.

BCSP and BCSS bits determine the clock used by the main system

including the CPU and buses.

BCSP — Bus Clock Select PLL

0 = SYSCLK is derived from the crystal clock or from SLWCLK.

1 = SYSCLK source is the PLL.

Cannot be set when PLLON = 0. In limp - home mode, th e output of

BCSP is forced to 1, but the BCSP bit reads the latched value.

BCSS — Bus Clock Select Slow

0 = SYSCLK is derived from the crystal clock EXTALi.

1 = SYSCLK source is t he Slow clock SLWC LK.

This bit has no effect when BCSP is set.

MCS — Module Clock Select

0 = M clock is the same as PCLK.

1 = M clock is derived from Slow clock SLWCLK.

This bit de ter mi nes the clo ck used by the EC T mod ul e and the baud

rate generators of the SCIs. In limp-home mode, the output of MCS is

forced to 0, but the MCS bit reads the latched value.

Bit 765432 1Bit 0

0 BCSP BCSS 0 0 MCS 0 0

RESET: 0 0 0 0 0 0 0 0

CLKSEL — Clock Generator Clock select Register $003D

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Clock Functions

Technical Data MC68HC912DG128 — Rev 3.0

Clock Functions

Read and write anytime.

A write to this register changes the SLWCLK frequency with minimum

delay (less than one SLWCLK cycle), thus allowing immediate tune-

up of the performa nce versus power consumption for the modu les

using this clock. The frequency divide ratio is 2 times (SLOW), hence

the divide range is 2 to 126 (not on first pass products). When

SLOW = 0, the divider is bypassed. The generation of E, P and

M clocks further divides SLWCLK by 2. Hence, the final ratio of Bus

to EXTALi Freq uency is prog rammable to 2, 4, 8, 12, 16, 20, ..., 252,

by steps of 4. SLWCLK is a 50% duty cycle signal.

Bit 765432 1Bit 0

0 0 SLDV5 SLDV4 SLDV3 SLDV2 SLDV1 SLDV0

RESET: 0 0 0 0 0 0 0 0

SLOW — Slow mode Divider Register $003E

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Clock Functions

System Clo ck Frequency formul as

MC68HC912DG128 — Rev 3.0 Technic al Data

Clock Functions

11.7 System Clock Frequency formulas

See Fig ur e 11- 6 :

SLWCLK = EXTALi / ( 2 x SLOW ) SLOW = 1,2,..63

SLWC LK = EXTALi SLOW = 0

PLLCLK = 2 x EXTALi x (SYNR + 1) / (REFDV + 1)

ECLK = SYSCLK / 2

XCLK = SLWCLK / 2

PCLK = SYSCLK / 2

BCLK(1) = EXTALi / 2

Boole an equations:

SYSCLK = (BCSP & PLLCLK) | (BCSP & BCSS & EXTALi) | (BCSP &

BCSS & SLWCLK)

MCLK = (PCLK & MCS) | (XCLK & MCS)

MSCAN system = (EXTALi & CLKSRC) | (SYSCLK & CLKSRC)

BDM system = (BCLK & CLKSW) | (ECLK & CLKSW)

NOTE: During limp-home mode PCLK, ECLK, BCLK, MCLK and XCLK are

supplied by VCO (PLLCLK).

1. If SYSCLK is slower than EXTALi (BCSS=1, BCSP=0, SLOW>0), BCLK becomes ECLK.

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Clock Functions

Technical Data MC68HC912DG128 — Rev 3.0

Clock Functions

11.8 Clock Divider Chains

Figure 11-6, Figure 11- 7 , Figure 11-8, and Figure 11-9 summarize the

clock divider chains for the various peripherals on the

68HC(9)12DG128.

Figure 11-6. Clock Generation Chain

REDUCED

CONSUMPTION

OSCILLATOR

PHASE

LOCK

LOOP

EXTAL

XTAL

0:0

SYSCLK

BUSES,

SPI,

PWM,

ATD0, ATD1

RTI, COP

BCSP BCSS

SLOW MODE

CLOCK

DIVIDER

EXTALi

SLWCLK

PLLCLK

0:1

BCSP BCSS

1:x

BCSP BCSS

MCS = 0

MCS = 1

÷ 2

÷2

MSCAN

CLKSRC = 1

TCLKs

T CLOCK

GENERATOR

E AND P

CLOCK

GENERATOR PCLK

ECLK

XCLK

SCI0, SCI1,

ECT

TO CPU

SYNC

MCLK

TO BDM

÷ 2 SYNC

TO CAL

TO CLOCK

MONITOR

CLKSRC = 0

CLKSW = 0

CLKSW = 1 BDMCLK

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Clock Functions

Clock Divider Chains

MC68HC912DG128 — Rev 3.0 Technic al Data

Clock Functions

Bus clock select bits BCSP and BCSS in the clock select register

(CLKSEL) determine which clock drives SYSCLK for the main system

including the CPU and buses. BCSS has no effect if BCSP is set. During

the transition, the clock select output will be held low and all CPU activity

will cease until the transition is comple te.

The Module Clock Select bit MCS determines the clock used by the ECT

module and the baud rate generators of the SCIs. In limp-home mode,

the output of MCS is forced to 0, but the MCS bit reads the latched value.

It allows normal operation of the serial and timer subsystems at a fixed

reference frequency while allowing the CPU to operate at a higher,

variable frequency.

Figure 11-7. Clock Chain for SCI0, SCI1, RTI, COP

XCLK

SC0BD

MODULUS DIVIDER:

÷ 1, 2, 3, 4, 5, 6,...,8190, 8191

SCI0

RECEIVE

BAUD RATE (16x)

SCI0

TRANSMIT

BAUD RATE (1x)

BITS: RTR2, RTR1, RTR0

TO RTI

BITS: CR2, CR1, CR0

TO COP

÷ 16

SCI1

RECEIVE

BAUD RATE (16x)

SCI1

TRANSMIT

BAUD RATE (1x)

÷ 16

0:0:0

0:0:1

0:1:0

0:1:1

1:0:0

1:0:1

1:1:0

1:1:1

÷ 2

0:0:0

0:0:1

0:1:0

0:1:1

1:0:0

1:0:1

1:1:0

1:1:1

÷ 4

÷ 2

÷ 4

÷ 2

÷4REGISTER: COPCTL

SC1BD

MODULUS DIVIDER:

÷ 1, 2, 3, 4, 5, 6,...,8190, 8191

BIT:RTBYP

÷ 2048

MCLK

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Clock Functions

Technical Data MC68HC912DG128 — Rev 3.0

Clock Functions

Figure 11-8. Clock Chain for ECT

BITS: PR2, PR1, PR0

MCLK

PAMOD

PACLK

PULSE ACC

LOW BYTE PACLK/256

PULSE ACC

HIGH BYTE

PACLK/65536

(PAOV)

GATE

LOGIC

BITS: PAEN, CLK1, CLK0

TEN

PAEN

0:0:0

0:0:1

÷ 2

0:1:0

÷ 2

0:1:1

÷ 2

1:0:0

÷ 2

1:0:1

÷ 2

1:1:0

÷ 2

1:1:1

÷ 2

BITS: MCPR1 , MCP R0

MCEN REGISTER: MCCTL

0:0

0:1

÷ 4

1:0

÷ 2

1:1

÷ 2

0:x:x

1:0:0

1:0:1

1:1:0

1:1:1

TO TIMER

MAIN

COUNTER

(TCNT)

MODULUS

DOWN

COUNTER

PORT T7

Prescaled MCLK

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Clock Functions

Clock Divider Chains

MC68HC912DG128 — Rev 3.0 Technic al Data

Clock Functions

Figure 11-9. Clock Chain for MSCAN, SPI, ATD0, ATD1 and BDM

PCLK

BITS: SPR2, SPR1, SPR0

SPI

BIT RATE

5-BIT MODULUS

COUNTER (PR0-PR4) TO ATD0

and ATD1

BKGD

BDM BIT CLOCK:

Receive: Detect falling edge,

count 12 ECLKs, Sample input

Transmit 1: Detect falling edge,

count 6 ECLKs while out put is

high impedance, Drive out 1 E

cycle pulse high , high imped-

ance output again

Transmit 0: Detect falling edge,

Drive out low, count 9 ECLKs,

Drive out 1 E cycle pulse high,

high impedance output

SYNCHRONIZER

LOGIC

BKGD IN

BKGD OUT

BKGD DIRECTION

÷ 2

0:0:0

0:0:1

0:1:0

0:1:1

1:0:0

1:0:1

1:1:0

1:1:1

÷ 2

÷ 2 REGIS TE R: SP0 BR

MSCAN

CLOCK

CLKSRC

EXTALi

SYSCLK

CLKSW

ECLK

BCLK

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Clock Functions

Technical Data MC68HC912DG128 — Rev 3.0

Clock Functions

11.9 Computer Operating Properly (COP)

The COP or watchdog timer is an added check that a program is running

and sequencing properly. When the COP is being used, software is

responsible for keeping a free running wat chdog timer from timing out. If

the watchdog timer times out it is an indication that the software is no

longer being exe cuted in the inten ded sequence; thu s a system reset is

initiated. Three control bits allow selection of seven COP time-out

periods. When COP is enabled, sometime during the selected period the

program must write $55 and $AA (in this order) to the COPRST register.

If the program fails to do this the part will reset. If any value other than

$55 or $AA is written, the part is reset.

In addition, windowed COP operation can be selected. In this mode,

writes to the COPRST register must occur in the last 25% of the selected

period. A premature write will a lso reset the part.

11.10 Real-Time Interr upt

There is a real time (periodic) interrupt available to the user. This

interrupt will occur at one of seven selected rates. An interrupt flag and

an interrupt enable bit are associated with this function. There are three

bits for the rate select.

11.11 Clock Monitor

The clock monito r circuit is based on an internal resistor-capaci tor (RC)

time delay. If no EXTALi clock edges are detected within this RC time

delay, the clock monitor can optiona lly ge nera te a system reset. The

clock monito r f unction is enabl ed /d isabled by the C ME con t rol bi t in the

COPCTL register. This time-out is based on an RC delay so that the

clock monitor can operate without any EXTALi clock.

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Clock Functions

Clock Func tio n Regis te rs

MC68HC912DG128 — Rev 3.0 Technic al Data

Clock Functions

Clock mo nitor time -o uts are shown in Table 11- 3. The corresponding

EXTALi clock period with an ideal 50% duty cycle is twice this time-out

value.

11.12 Clock Function Registers

All register addresses shown reflect the reset state. Registers may be

mapped to any 2K byte space.

RTIE — Real Time Interrupt Enable

Read and write anytime.

0 = Interrupt requests from RTI are disabled.

1 = Inte rrupt wi ll be requested whenever RTIF is set.

RSWAI — RTI and COP Stop While in Wait

Write once in normal modes, anyti me in special modes. Read

anytime.

0 = Allows the RTI and COP to continu e ru nning in wait.

1 = Disables both the RTI and COP whenever the part goes into

Wait.

RSBCK — RTI and COP Stop While in Backg round Debug Mod e

Write once in normal modes, anyti me in special modes. Read

anytime.

0 = Allows the RTI and COP to continu e ru nning while in

background mode.

1 = Disables both the RTI and COP when the part is in background

mode. This is useful for em ulation.

Table 11-3. Clock Monitor Time-Outs

Supply Range

5 V +/– 10% 2–20 µS

Bit 7654321Bit 0

RTIE RSWAI RSBCK Reserved RTBYP RTR2 RTR1 RTR0

RESET:00000000

RTICTL — Real-Time Interrupt Control Register $0014

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Clock Functions

Technical Data MC68HC912DG128 — Rev 3.0

Clock Functions

RTBYP — Real Time Interrupt Divider Chain Bypass

Write not allowed in normal modes, anytime in special modes. Read

anytime.

0 = Divider chain functions no rmally.

1 = Divider chain is bypassed, allows fast er testi ng (the div i der

chain is normally XCLK divi ded by 213, when bypassed

becomes XCLK divided by 4).

RTR2, RTR1, RTR0 — Real-Time Interrupt Rate Select

Read and write anytime.

Rate select for real-time inte rrupt. The clock used for this module is

the XCLK.

RTIF — Real Time Interrupt Flag

This bit is cleared automatically by a write to this register with this bit

set.

0 = Time-o ut has not yet occurre d.

1 = Set when the time-out period is met.

Table 11-4. Real Time Interrupt Rates

RTR2 RTR1 RTR0 Divide X By: Time-Out Period

X = 125 KHz Time-Out Period

X = 500 KHz Time-Out Period

X = 2.0 MHz Time-Out Period

X = 8.0 MHz

0 0 0 OFF OFF OFF OFF OFF

001 213 65.536 ms 16.384 ms 4.096 ms 1.024 ms

010 214 131.72 ms 32.768 ms 8.196 ms 2.048 ms

011 215 263.44 ms 65.536 ms 16.384 ms 4.096 ms

100 216 526.88 ms 131.72 ms 32.768 ms 8.196 ms

101 217 1.05 s 263.44 ms 65.536 ms 16.384 ms

110 218 2.11 s 526.88 ms 131.72 ms 32.768 ms

111 219 4.22 s 1.05 s 263.44 ms 65.536 ms

Bit 765432 1Bit 0

RTIF0000000

RESET: 0 0 0 0 0 0 0 0

RTIFLG — Real Time Interrupt Flag Register $0015

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Clock Functions

Clock Func tio n Regis te rs

MC68HC912DG128 — Rev 3.0 Technic al Data

Clock Functions

CME — Clock Moni tor Enable

Read and write anytime.

If FCME is set, this bit has no meaning nor effect.

0 = Clock monitor is disabled. Slow clocks and stop instruction may

be used.

1 = Slow or stopped clocks (including the stop instruction) will

cause a clock reset sequence or limp-home mode. See Limp-

Home and Fast STOP Recovery modes.

On reset

CME is 1 if VDDPLL is hig h

CME is 0 if VDDPLL is low.

NOTE: The VDDPLL-dependent reset operation is not implemented on first

pass products.

In this case the state of CME on reset is 0.

FCME — Force Clock Monitor Enable

Write once in normal modes, anyti me in special modes. Read

anytime.

In normal modes, when this bit is set, the clock monitor function

cannot be disabled un til a reset occurs.

0 = Clock moni tor follows the stat e of the CME bit.

1 = Slow or stopped clocks will cause a clock reset sequence or

limp-home mode.

See Limp-Home and Fast STOP Recovery modes.

Bit 7654321Bit 0

CME FCME FCMCOP WCOP DISR CR2 CR1 CR0

RESET: 0/1 0 000111Normal

RESET: 0/1 0 001111Special

COPCTL — COP Control Register $0016

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Clock Functions

Technical Data MC68HC912DG128 — Rev 3.0

Clock Functions

FCMCOP — Force Clock Monitor Reset or COP Watchdog Reset

Writes are not allowed in normal mo des, anytime in s pecial modes.

Read anyt ime .

If DISR is set, this bit has no effect.

0 = Normal operation.

1 = A clock monitor failure reset or a COP failure reset is forced

depending on the state of CME and if COP is enabled.

WCOP — Window COP mode

Write once in normal modes, anyti me in special modes. Read

anytime.

0 = Normal COP operation

1 = Window COP operation

When se t, a write to th e COPRST regi ster must occur i n the last 25%

of the selected period. A premature write will also reset the part. As

long as all writes occur during this window, $55 can be written as often

as desired. Once $AA is written the time-out logic restarts and the

user must wait until the next window before writing to COPRST.

Please note, there is a fixed time uncertainty about the exact COP

counter state when reset, as the initial prescale clock divider in the

RTI section is not cleared when the COP coun ter is cleared. This

means the effect ive window is reduced by this uncertainty. Table 1 1-

5 below shows the exact duration of this window for the seven

available COP rates.

CME COP enabled Forced res et

0 0 none

0 1 COP failure

1 0 Clock monitor failure

11 Both(1)

1. Highest priority interrupt vector is serviced.

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Clock Functions

Clock Func tio n Regis te rs

MC68HC912DG128 — Rev 3.0 Technic al Data

Clock Functions

DISR — Disable Re sets fr om COP Watchd og and Clock Monito r

Writes are not allowed in normal mo des, anytime in s pecial modes.

Read anyt ime .

0 = Normal operation.

1 = Regardless of other control bit states, COP and clock monitor

will not generate a system reset.

CR2, CR1, CR0 — COP Watchd og Timer Rate select bits

These bits select the COP time-out rate. The clock used for this

module is the XCLK.

Write once in normal modes, anyti me in special modes. Read

anytime.

Table 11 -5. COP Watchdog Rates

CR2 CR1 CR0 Divide

X clock

8.0 MHz X clock.

Time-out

Window COP enabled:

Window start

(1) Window end Effective

Window (2)

0 0 0 OFF OFF OFF OFF OFF

0012 13 1.024 ms -0/+0.256 ms 0.768 ms 0.768 ms 0%

(3)

0102 15 4.096 ms -0/+0.256 ms 3.072 ms 3.840 ms 18.8 %

0112 17 16.384 ms -0/+0.256 ms 12.288 ms 16.128 ms 23.4 %

1002 19 65.536 ms -0/+1.024 ms 49.152 ms 64.512 ms 23.4 %

1012 21 262.144 ms -0/+1.024 ms 196.608 ms 261.120 ms 24.6 %

1102 22 524.288 ms -0/+1.024 ms 393.216 ms 523.264 ms 24.8 %

1112 23 1.048576 ms -0/+1.024 ms 786.432 ms 1.047552 ms 24.9 %

1. Time for writing $55 following previous COP restart of time-out logic due to writing $AA.

2. Please refer to WCOP bit description above.

3. Window COP cannot be used at this rate.

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Clock Functions

Technical Data MC68HC912DG128 — Rev 3.0

Clock Functions

Always reads $00.

Writing $55 to this address is the first step of the COP watchdog

sequence.

Writ in g $AA to th is ad dr ess i s the second ste p o f the C OP wa tchd og

sequence . Other i nstruction s may be exe cuted betw een the se writ es

but both must be completed in the correct order prior to time-out to

avoid a watchdog reset. Writing anything other than $55 or $AA

causes a COP reset to occur.

Bit 7654321Bit 0

RESET: 00000000

COPRST — Arm/Reset COP Timer Register $0017

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MC68HC912DG128 — Rev 3.0 Technic al Data
Pulse Width Modulator
 
Technical Data — MC68HC912DG128
Section 12. Pulse Width Modulator
12.1  Contents
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
12.3 PWM Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . .195
12.4 PWM Boundary Cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
12.2  Introduction
The pulse-width modulator (PWM) subsystem provides four 
independent 8-bit P WM waveforms or two 16-bit PWM waveforms or a  
combination of one 16-bit and two 8-bit PWM waveforms. Each 
waveform channel has a programmable period and a programmable 
duty-cycle as well as a dedicated counter. A flexible clock select scheme 
allows four differe nt clock sources to be used  with the count ers. Each of 
the modulators can create independent, continuous waveforms with 
software- selectable d uty rates fr om 0 perce nt to 100 per cent. The PWM  
outputs can be programmed as left-aligned outputs or center-aligned 
outputs. 
The period and duty registers are double buffered so that if they change 
while the channel is enabled, the change wi ll not take effect until the 
counter rolls over or the channel is disabled. If the channel is not 
enabled, then writes to the pe riod and/or duty regi ster will go directly to 
the lat ches as well  as the buff er, thus ensur ing tha t the PWM ou tput will 
always be either the old waveform or the new waveform, not some 
varia ti on in between.
A change in duty or period can be forced into immediate effect by writing 
the new value to the duty and/or period registers and then writing to the 
counter. This causes the counter to reset and the new duty and/or period 
values to be latched. In addition, since the counter is readable it is 
    
  
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Pulse Width Modulator

Technical Data MC68HC912DG128 — Rev 3.0

Pulse Width Modulator

possible to know where the count is with respect to the duty value and

software can be u sed to ma ke a dj ust me nts b y tu rn i ng t he ena bl e bit off

and on.

The four PWM channel outputs share general-purpose port P pins.

Enabling PWM pins takes precedence over the general-purpose port.

When PWM channels are not in use, the port pins may be used for

discrete input/out put.

Figure 12-1. Block Diagram of PWM Left-Aligned Output Channe l

GATE PWCNTx

8-BIT COMPARE =

PWDTYx

8-BIT COMPARE =

PWPERx

UP/DOWN FROM PO RT P

DATA REGISTER

TO PIN

DRIVER

PPOLx

CLOCK SOURCE

(ECLK or Sca l ed EC LK)

(CLOCK EDGE SYNC) RESET

CENTR = 0

MUX MUX

PWPER

PWDTY

PWENx

PPOL = 0

PPOL = 1

SYNC

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Pulse Wi dth Mod ula tor

Introduction

MC68HC912DG128 — Rev 3.0 Technic al Data

Pulse Width Modulator

Figure 12-2. Block Diagram of PWM Center-Aligned Output Channel

GATE PWCNTx

8-BIT COMPARE =

PWDTYx

8-BIT COMPARE =

PWPERx

RESET FROM PORT P

DATA REGISTER

TO PIN

DRIVER

PPOLx

CLOCK SOURCE

(ECLK or Scaled ECLK)

(CLOCK EDGE SYNC)

UP/DOWN

CENTR = 1

MUX MUX

PWDTY

PWENx

PPOL = 1

PPOL = 0

(DUTY CYCLE)

(PERIOD)

PWPER × 2

(PWPER − PWDTY) × 2 PWDTY

SYNC

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Pulse Width Modulator

Technical Data MC68HC912DG128 — Rev 3.0

Pulse Width Modulator

Figure 12-3. PWM Clock Sources

8-BIT DOWN COUNTER

PCLK2

MUX

PCLK3

MUX

CLOCK TO PW M

CHANNEL 2

CLOCK TO PWM

CHANNEL 3

÷ 2

PWSCNT1

8-BIT SCALE REGISTER

PWSCAL1

CLOCK B

CLOCK S1**

**CLOCK S1 = (CLOCK B)/2, (CLOCK B)/4, (CLOCK B)/6,... (CLOCK B)/512

÷ 2

0:0:0

0:0:1

0:1:0

0:1:1

1:0:0

1:0:1

1:1:0

1:1:1

÷ 2

0:0:0

0:0:1

0:1:0

0:1:1

1:0:0

1:0:1

1:1:0

1:1:1

8-BIT DOWN COUNTER

PCLK0

MUX

PCLK1

MUX

CLOCK TO PWM

CHANNEL 0

CLOCK TO PW M

CHANNEL 1

÷ 2

PWSCNT0

8-BIT SCALE REGISTER

PWSCAL0

CLOCK A

CLOCK S0*

*CLOCK S0 = (CLOCK A)/2, (CLOCK A)/4, (CLOCK A)/6,... (CLOCK A)/512

PCKB2,

PCKB0

PCKB1,

= 0

BITS:

PCKA2,

PCKA0

PCKA1,

PWPRES

PSBCK

LIMBDM

ECLK

PSBCK IS BIT 0 OF PWCTL REGISTER.

INTERNAL SIGNAL LIMBDM IS ONE IF THE MCU IS IN BACKGROUND DEBUG MODE.

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Pulse Wi dth Mod ula tor

PWM Register Description

MC68HC912DG128 — Rev 3.0 Technic al Data

Pulse Width Modulator

12.3 PWM Register Descript ion

Read and write anytime.

CON23 — Concatenate PWM Channels 2 and 3

When concatenated, channel 2 becomes the high-order byte and

channel 3 become s the l ow - or de r byte . C h annel 2 o utput pi n i s u sed

as the output for this 16-bit PWM (bit 2 of port P). Channel 3 clock-

select control b its determines the clo ck source. Cha nnel 3 output p in

becomes a general purpose I/O.

0 = Channels 2 and 3 are separate 8-bit PWMs.

1 = Chan nels 2 and 3 a re concat enated to create one 16 -bit PWM

channel.

CON01 — Concatenate PWM Channels 0 and 1

When concatenated, channel 0 becomes the high-order byte and

channel 1 become s the l ow - or de r byte . C h annel 0 o utput pi n i s u sed

as the output for this 16-bit PWM (bit 0 of port P). Channel 1 clock-

select control bits determine the clock source. Channel 1 output pin

becomes a general purpose I/O.

0 = Channels 0 and 1 are separate 8-bit PWMs.

1 = Chan nels 0 and 1 a re concat enated to create one 16 -bit PWM

channel.

PCKA2 – PCKA0 — Prescaler for Clock A

Clock A is o ne o f t wo clock so urce s which may b e used f or chan ne ls

0 and 1. These three bits determine the rate of clock A, as shown in

Table 12-1.

PWCLK — PWM Clocks and Concatenate $0040

Bit 7 6 5 4 3 2 1 Bit 0

CON23 CON01 PCKA2 PCKA1 PCKA0 PCKB2 PCKB1 PCKB0

RESET: 0 0 0 0 0 0 0 0

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Pulse Width Modulator

Technical Data MC68HC912DG128 — Rev 3.0

Pulse Width Modulator

PCKB2 – PCKB0 — Prescaler for Clock B

Clock B is o ne o f t wo clock so urce s which may b e used f or chan ne ls

2 and 3. These three bits determine the rate of clock B, as shown in

Table 12-1.

Read and write anytime.

PCLK3 — PWM Channel 3 Clock Select

0 = Clock B is the clock source for channel 3.

1 = Clock S1 is the clock source for channel 3.

PCLK2 — PWM Channel 2 Clock Select

0 = Clock B is the clock source for channel 2.

1 = Clock S1 is the clock source for channel 2.

PCLK1 — PWM Channel 1 Clock Select

0 = Clock A is the clock source for channel 1.

1 = Clock S0 is the clock source for channel 1.

Table 12-1. Clock A and Clock B Prescaler

PCKA2

(PCKB2) PCKA1

(PCKB1) PCKA0

(PCKB0) Value of

Clock A (B)

000 P

001 P

÷ 2

010 P

÷ 4

011 P

÷ 8

100P

÷ 16

101P

÷ 32

110P

÷ 64

111P

÷ 128

Bit 765432 1Bit 0

PCLK3 PCLK2 PCLK1 PCLK0 PPOL3 PPOL2 PPOL1 PPOL0

RESET: 0 0 0 0 0 0 0 0

PWPOL — PWM Clock Sele ct and Pol ar it y $0041

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Pulse Wi dth Mod ula tor

PWM Register Description

MC68HC912DG128 — Rev 3.0 Technic al Data

Pulse Width Modulator

PCLK0 — PWM Channel 0 Clock Select

0 = Clock A is the clock source for channel 0.

1 = Clock S0 is the clock source for channel 0.

If a clock se lect is changed while a PWM sign al is being g enerated, a

truncated or stretched pulse may occur during the transition.

The following four bits apply in left-aligned mode only:

PPOL3 — PWM Channel 3 Polarity

0 = Channel 3 output is low at the beginning of the period; high

when the duty count is reached.

1 = Channel 3 output is high at the beginning of the period; low

when the duty count is reached.

PPOL2 — PWM Channel 2 Polarity

0 = Channel 2 output is low at the beginning of the period; high

when the duty count is reached.

1 = Channel 2 output is high at the beginning of the period; low

when the duty count is reached.

PPOL1 — PWM Channel 1 Polarity

0 = Channel 1 output is low at the beginning of the period; high

when the duty count is reached.

1 = Channel 1 output is high at the beginning of the period; low

when the duty count is reached.

PPOL0 — PWM Channel 0 Polarity

0 = Channel 0 output is low at the beginning of the period; high

when the duty count is reached.

1 = Channel 0 output is high at the beginning of the period; low

when the duty count is reached.

Depending on the polarity bit, the duty registers may contain the count

of either the high time or the low time. If the polarity bit is zero and left

alignm ent is se lected, t he duty r egisters con tain a coun t of the l ow time .

If the polarit y bit is one, the duty registers contain a count of the high

time.

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Pulse Width Modulator

Technical Data MC68HC912DG128 — Rev 3.0

Pulse Width Modulator

Setting any of the PWENx bits causes the associated port P line to

become an out put re gardless of the state of the associated data

direction register (DDRP) bit. This does not change the state of the data

direction bit. When PWENx returns to zero, the data direction bit controls

I/O direction. On the front end of the PWM channel, the scaler clock is

enabl ed to the PWM ci rcuit by the PWENx ena ble bit be ing hig h. When

all four PWM channels are disabled, the prescaler counter shuts off to

save power. There is an edge-synchronizing gate circuit to guarantee

that the clock will only be enabled or disable d at an edge.

Read and write anytime.

PWEN3 — PWM Channel 3 Enable

The pulse modulated signal will be available at port P, bit 3 when its

clock source begins its next cycle.

0 = Channel 3 is disabled.

1 = Chann el 3 is enabled.

PWEN2 — PWM Channel 2 Enable

The pulse modulated signal will be available at port P, bit 2 when its

clock source begins its next cycle.

0 = Channel 2 is disabled.

1 = Chann el 2 is enabled.

PWEN1 — PWM Channel 1 Enable

The pulse modulated signal will be available at port P, bit 1 when its

clock source begins its next cycle.

0 = Channel 1 is disabled.

1 = Chann el 1 is enabled.

Bit 7654321Bit 0

0000PWEN3PWEN2PWEN1PWEN0

RESET: 00000000

PWEN — PWM Enable $0042

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Pulse Wi dth Mod ula tor

PWM Register Description

MC68HC912DG128 — Rev 3.0 Technic al Data

Pulse Width Modulator

PWEN0 — PWM Channel 0 Enable

The pulse modulated signal will be available at port P, bit 0 when its

clock source begins its next cycle.

0 = Channel 0 is disabled.

1 = Chann el 0 is enabled.

PWPRES is a fr ee-running 7-bit counter. Read anytime. Write only in

special mo de (SMO D = 1) .

Read and write anytime. A write will cause the scaler counter PWSCNT0

to load the PW SCAL 0 val ue unless i n spe cia l mo de with DISC AL = 1 in

the PWTST register.

PWM channels 0 and 1 can select clock S0 (scaled) as its input clock by

setting the control bit PCLK0 and PCLK1 respectively. Clock S0 is

gener ated by dividi ng clock A by the value in the PWSC AL0 register + 1

and dividing again by two. When PWSCA L0 = $FF, clock A is divided by

256 then divided by two to generate clock S0.

Bit 765432 1Bit 0

0Bit 654321Bit 0

RESET: 0 0 0 0 0 0 0 0

PWPRES — PWM Prescale Counter $0043

Bit 765432 1Bit 0

RESET: 0 0 0 0 0 0 0 0

PWSCAL0 — PWM Scale Register 0 $0044

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Pulse Width Modulator

Technical Data MC68HC912DG128 — Rev 3.0

Pulse Width Modulator

PWSCNT0 is a down-counter that, upon reaching $00, loads the value

of PWSCAL0 . Read any time .

Read and write anytime. A write will cause the scaler counter PWSCNT1

to load the PW SCAL 1 val ue unless i n spe cia l mo de with DISC AL = 1 in

the PWTST register.

PWM channels 2 and 3 can select clock S1 (scaled) as its input clock by

setting the control bit PCLK2 and PCLK3 respectively. Clock S1 is

gener ated by dividi ng clock B by the value in the PWSC AL1 register + 1

and dividing again by two. When PWSCA L1 = $FF, clock B is divided by

256 then divided by two to generate clock S1.

PWSCNT1 is a down-counter that, upon reaching $00, loads the value

of PWSCAL1 . Read any time .

Bit 7654321Bit 0

RESET: 0 0 0 0 0 0 0 0

PWSCNT0 — PWM Scale Counter 0 Value $0045

Bit 7654321Bit 0

RESET: 0 0 000000

PWSCAL1 — PWM Scale Register 1 $0046

Bit 7654321Bit 0

RESET: 0 0 000000

PWSCNT1 — PWM Scale Counter 1 Value $0047

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Pulse Wi dth Mod ula tor

PWM Register Description

MC68HC912DG128 — Rev 3.0 Technic al Data

Pulse Width Modulator

Read a nd wr ite an ytime. A w rit e will cause th e PWM co un ter to rese t to

$00.

In special mode, if DISCR = 1, a write does not reset the PWM counter.

The PWM counters are not reset when PWM channels are disabled. The

counters must be reset prior to a new enable.

Each counter may be read any time without affecting the count or the

operation of the corresponding PWM channel. Writes to a counter cause

the counte r to be reset to $00 a nd force an imme dia te loa d of both duty

and period registers with new values. To avoid a truncated PWM period,

write to a counter while the counter is disa bled. In left-aligned output

mode, resetting the counter and starting the waveform output is

controlled by a match between the period register and the value in the

counter. In center-aligned output mode the counters operate as up/down

counters, where a match in period changes the counter direction. The

duty register changes the state of the output during the period to

determine t he duty.

When a channel is enabled, the ass ocia ted PWM counter starts at the

count in th e PWCNTx register using the clock select ed for that chann el.

In special mode, when DISCP = 1 and configured for left-aligned output,

a match of period does not reset the associated PWM counter.

Bit 7654321Bit 0

PWCNT0 Bit 7654321Bit 0$0048

PWCNT1 Bit 7654321Bit 0$0049

PWCNT2 Bit 7654321Bit 0$004A

PWCNT3 Bit 7654321Bit 0$004B

RESET:00000000

PWCNTx — PWM Channel Counters

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Pulse Width Modulator

Technical Data MC68HC912DG128 — Rev 3.0

Pulse Width Modulator

Read and write anytime.

The valu e in the per iod regi ster determ ines the pe riod of the associate d

PWM channel. If written while the channel is enabled, the new value will

not take e ffect until the exist ing period terminates, forcin g the counter to

reset. The new period is then latched and is used until a new period

value is wr i tte n. Re ad i ng this regi ster ret ur ns the most recent valu e

written. To start a new period immediately, write t he new period value

and then write the counter forcing a new period to start with the new

period value.

Perio d = Ch an nel - Cl ock- Pe ri od × (PWPER + 1) (CENTR = 0)

Perio d = Ch an nel - Cl ock- Pe ri od × (2 × PWPER) (CENTR = 1)

Read and write anytime.

Bit 7654321Bit 0

PWPER0 Bit 7654321Bit 0$004C

PWPER1 Bit 7654321Bit 0$004D

PWPER2 Bit 7654321Bit 0$004E

PWPER3 Bit 7654321Bit 0$004F

RESET: 11111111

PWPERx — PWM Channel Period Registers

Bit 7654321Bit 0

PWDTY0 Bit 7654321Bit 0$0050

PWDTY1 Bit 7654321Bit 0$0051

PWDTY2 Bit 7654321Bit 0$0052

PWDTY3 Bit 7654321Bit 0$0053

RESET:11111111

PWDTYx — PWM Channel Duty Registers

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Pulse Wi dth Mod ula tor

PWM Register Description

MC68HC912DG128 — Rev 3.0 Technic al Data

Pulse Width Modulator

The value in each duty register determines the duty of the associated

PWM channel. When the duty value is equal to the counter value, the

output chan ge s state. If the registe r is written whi le the chan nel is

enabled, the new value is held in a buffer until the counter rolls over or

the channel is disabled. Reading this register returns the most recent

value wri t ten.

If the duty register is greater than or equal to the value in the period

regist er, th ere wi ll be no duty change in st ate. If the duty register is set

to $FF the output will always be in the state which would normally b e the

state opposite the PPOLx value.

Left-A li g ned - Output Mode ( C ENTR = 0) :

Duty cycle = [(PWDTYx + 1) / (PWPERx + 1 )] × 100% (PPOLx = 1)

Duty cycle = [(PWPERx−PWDTYx)/( PWPERx+ 1) ] × 100% (PPOLx = 0)

Center-Alig ned-Output Mode (CENTR = 1):

Duty cycle = [(PWPERx−PWDTYx)/PWPERx] × 100% (PPOLx = 0)

Duty cycle = [PWDTYx / PWPERx] × 100% (PPOLx = 1)

Read and write anytime.

PSWAI — PWM Halts while in Wa it Mode

0 = Allows PWM main clock generator to continue wh ile in wait

mode.

1 = Halt PWM main clock generator when the part is in wait mode.

CENTR — Center-Aligned Output Mode

To avoid i rregu lari ties in th e PWM outp ut mo de, writ e the CEN TR bit

only when PWM channels are disabled.

0 = PWM channels operate in left-aligned output mode

1 = PWM channels operate in center-aligned output mode

Bit 7654321Bit 0

0 0 0 PSWAI CENTR RDPP PUPP PSBCK

RESET: 00000000

PWCTL — PWM Control Register $0054

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Pulse Width Modulator

Technical Data MC68HC912DG128 — Rev 3.0

Pulse Width Modulator

RDPP — Redu ced Drive of Port P

0 = All port P output pins have normal drive capability.

1 = All port P output pins have reduced drive capabilit y.

PUPP — Pull-Up Port P Enable

0 = All port P pins have an active pull-up device disabled.

1 = All port P pins have an active pull-up device enabled.

PSBCK — PWM Stops while in Background Mode

0 = Allows PWM to continue while in background mode .

1 = Disable P WM input clock when t he part is in background mode.

Read anytime but write only in special mode (SMODN = 0). These bits

are available only in special mode and ar e reset in normal mode.

DISCR — Disable Reset of Channel Counter on Write to Channel

Counter

0 = Normal ope ration. Write to PW M channel counter will reset

channel counter.

1 = Wr ite to PWM cha nnel counter do es not reset ch annel counter .

DISCP — Disable Compare Count Period

0 = Normal operation

1 = In left-al igned o utput mo de, match of per iod does not rese t the

associat ed PW M coun te r re gister.

DISCAL — Disable Load of Scale-Counters on Write to the Associated

Scale-Registers

0 = Normal operation

1 = Write to PWSCAL0 and PWSCAL 1 does no t load scale

counters

Bit 765432 1Bit 0

DISCR DISCP DISCAL 0 0 0 0 0

RESET: 0 0 0 0 0 0 0 0

PWTST — PWM Special Mode Register (“Test”) $0055

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Pulse Wi dth Mod ula tor

PWM Register Description

MC68HC912DG128 — Rev 3.0 Technic al Data

Pulse Width Modulator

PORTP can be re ad anytime.

PWM functions share port P pins 3 to 0 and take precedence over the

gener al - pur p ose po rt w hen enabled.

When configured as input, a read will return the pin level. Port P[7:4] will

read as zero because there are no available external pins.

When configured as output, a read will return the latched output data.

Port P[7:4] will read the last value written.

A write will drive associated pins only if configured for output and the

corresponding PWM channel is not enabled.

After reset, all pins are general-purpose, high-impedance inputs.

DDRP determines pin direction of port P when used for general-purpose

I/O.

Read and write anytime.

DDRP[7:4] — Data Direction Port P pin 7–4

Serve as mem ory locations sin ce there are no corresponding port pins.

DDRP[3:0] — Data Direction Port P pin 3–0

0 = I/O pin configured as high impedance input

1 = I/O pin configured for output.

Bit 7654321Bit 0

PP7 PP6 PP5 PP4 PP3 PP2 PP1 PP0

PWM ––––PWM3 PWM2 PWM1 PWM0

RESET: ––––––––

PORTP — Port P Data Register $0056

Bit 7654321Bit 0

DDP7 DDP6 DDP5 DDP4 DDP3 DDP2 DDP1 DDP0

RESET: 00000000

DDRP — Port P Data Direction Register $0057

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Pulse Width Modulator

Technical Data MC68HC912DG128 — Rev 3.0

Pulse Width Modulator

12.4 PWM Boundary Cases

The boundary co nditions for the PWM channel duty registe rs and the

PWM channel period registers cause these results:

Table 12-2. PWM Left-Aligned Boundary Conditions

PWDTYx PWPERx PPOLx Output

$FF >$00 1 Low

$FF >$00 0 High

≥PWPERx –1High

≥PWPERx –0Low

–$00 1 High

–$00 0 Low

Table 12-3. PWM Center-Aligned Boundary Conditions

PWDTYx PWPERx PPOLx Output

$00 >$00 1 Low

$00 >$00 0 High

≥PWPERx –1High

≥PWPERx –0Low

–$00 1 High

–$00 0 Low

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MC68HC912DG128 — Rev 3.0 Technic al Data
Enhanced Capture Timer
 
Technical Data — MC68HC912DG128
Section 13. Enhanced Capture Timer
13.1  Contents
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
13.3 Enhanced Capture Timer Modes of Operation. . . . . . . . . . . .214
13.4 Timer Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217
13.5 Timer and Modulus Counter Operation in Different Modes . .247
13.2  Introduction
The HC12 Enhanced Capture Timer module has the features of the 
HC12 Standard Timer module enhanced by additional features in order 
to enlarge the field of applications, in particular for automotive ABS 
applications.
The additional features permit the operation of this timer module in a 
mode similar to the Input Control Timer implemented on 
MC68HC11NB4.
These additional features are:
•16-Bit Buffer Register for four Input Capture (IC) channels.
•Four 8-Bit Pulse Accumulators with 8-bit buffer registers 
associated with the four buffered IC channels. Configurable also 
as two 16-Bit Pulse Accumulato rs.
•16-Bit Modulus Down-Counter with 4-bit Prescaler.
•Four user selectable Delay Counters for input noise immunity 
increase.
•Main Timer Prescaler extended to 7-bit.
    
  
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Enhanced Capture Timer

Technical Data MC68HC912DG128 — Rev 3.0

Enhanced Capture Timer

This design specification describes the standard timer as well as the

additional features.

The basi c timer consists of a 16-bit , software-program mable counter

driven by a prescaler. This timer can be used for many purposes,

includ ing input wavef orm measurements while simultaneously

generating an out put waveform. Pul se widths can vary from

microseconds to many seconds.

A full access for the counter registers or the input capture/output

compare registe rs should t ake place in one clock cycle . Accessing high

byte and low byte separately for all of these registers may not yield the

same result as accessing them in one word.

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Enhanced Capture Timer

Introduction

MC68HC912DG128 — Rev 3.0 Technic al Data

Enhanced Capture Timer

Figure 13-1. Timer Block Diagram in Latch Mode

16 BIT MAIN TIMER

PT1

Comparator

TC0H ho ld re gi s t e r

PT0

PT3

PT2

PT4

PT5

PT6

PT7

EDG0

EDG1

EDG2

EDG3

MUX

Prescaler

M clock

16-bit load register

16-bit modulus

0RESET

EDG0

EDG1

EDG2

EDG4

EDG5

EDG3

EDG6

EDG7

÷ 1, 2, ..., 128

÷ 1, 4, 8, 16

16-bit Free-running

LATCH

Under flow

main timer

Prescaler

TC0 capture/compare register

Comparator

TC1 capture/compare register

Comparator

TC2 capture/compare register

Comparator

TC3 capture/compare register

Comparator

TC4 capture/compare register

Comparator

TC5 capture/compare register

Comparator

TC6 capture/compare register

Comparator

TC7 capture/compare register

Pin logic

Delay counter

M clock

TC1H hold register

TC2H ho ld re gi s t e r

TC3H hold register

MUX

PA0H hold register

PAC0

0RESET

PA1H hold register

PAC1

0RESET

PA2H hold register

PAC2

0RESET

PA3H hold register

PAC3

Wri te $0 00 0

to modulus counter

ICLAT, LATQ, BUFEN

(force latch)

LATQ

(MDC latch enable)

down counter

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Enhanced Capture Timer

Technical Data MC68HC912DG128 — Rev 3.0

Enhanced Capture Timer

Figure 13-2. Timer Block Diagram in Queue Mode

16 BIT MAIN TIMER

PT1

Comparator

TC0H ho ld re gi s t e r

PT0

PT3

PT2

PT4

PT5

PT6

PT7

EDG0

EDG1

EDG2

EDG3

MUX

Prescaler

M clock

16-bit load register

16-bit modulus

0RESET

EDG0

EDG1

EDG2

EDG4

EDG5

EDG3

EDG6

EDG7

÷1, 2, ..., 128

÷ 1, 4, 8, 16

16-bit Free-running

LATCH0

main timer

Prescaler

TC0 capture/compare register

Comparator

TC1 capture/compare register

Comparator

TC2 capture/compare register

Comparator

TC3 capture/compare register

Comparator

TC4 capture/compare register

Comparator

TC5 capture/compare register

Comparator

TC6 capture/compare register

Comparator

TC7 capture/compare register

Pin logic

Delay counter

M clock

TC1H hold register

TC2H ho ld re gi s t e r

TC3H hold register

MUX

PA0H hold regi s ter

PAC0

0RESET

PA1H hold regi s ter

PAC1

0RESET

PA2H hold regi s ter

PAC2

0RESET

PA3H hold regi s ter

PAC3

LATCH1

LATCH3 LATCH2

LATQ, BUFEN

(queue mode)

Read TC3H

hold register

Read TC2H

hold register

Read TC1H

hold register

Read TC0H

hold register

down counter

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Enhanced Capture Timer

Introduction

MC68HC912DG128 — Rev 3.0 Technic al Data

Enhanced Capture Timer

Figure 13-3. 8-Bit Pulse Accumulators Block Diagram

Host CPU data bus

PT0

Load holding register and reset pulse accumulator

EDG3

EDG2

EDG1

EDG0

Edge detector Delay counter

Interrupt

PT1 Edge detector Delay counter

PT2 Edge detector Delay counter

PT3 Edge detector Delay counter

8-bit PAC0 (PA CN0 )

PA0H holding register

8-bit PAC1 (PA CN1 )

PA1H holding register

8-bit PAC2 (PA CN2 )

PA2H holding register

8-bit PAC3 (PA CN3 )

PA3H holding register

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Enhanced Capture Timer

Technical Data MC68HC912DG128 — Rev 3.0

Enhanced Capture Timer

Figure 13-4. 16-Bit Pulse Accumulators Block Diagram

Edge detector

8-bit PAC2

Intermodule Bus

8-bit PAC3

PT7

PT0

M clock

Divide by 64

Clock select

CLK0

CLK1 4:1 MUX

TIMCLK

PACLK

PACLK / 256

PACLK / 65536

Prescaled MCLK

(Timer clock)

Interrupt

MUX

(PAMOD)

Edge detector

PACA

Delay counter

(PACN3) (PACN2)

8-bit PAC08-bit PAC1

Interrupt

PACB

(PACN1) (PACN0)

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Enhanced Capture Timer

Introduction

MC68HC912DG128 — Rev 3.0 Technic al Data

Enhanced Capture Timer

Figure 13-5. Block Diagram for Port7 with Output compare / Pulse Accumulator A

Figure 13-6. C3F-C0F Interrupt Flag Setting

Pulse accumulator A PAD

(OM7=1 or OL7=1) or (OC7M7 = 1)

OC7

PTn Edge detector Delay counter

16-bit Main Timer

TCn Input Capture Reg.

TCnH I.C. Holding Reg. BUFEN • LATQ • TFMOD

Set CnF Interru pt

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Enhanced Capture Timer

Technical Data MC68HC912DG128 — Rev 3.0

Enhanced Capture Timer

13.3 Enhanced Capture Timer Modes of Operation

The Enhanced Capture Timer has 8 Input Capture, Output Compare

(IC/OC) chann els sam e as on the H C12 stan dard timer (tim er cha nnels

TC0 to TC7). When channels are selected as input capture by selecting

the IOSx bit in TIOS register, they are called Input Capture (IC)

channels.

Four IC channels are the same as on the standard timer with one capture

associat ed in pu t pin .

Four other IC channels, in addition to the capture register, have also one

buffer called holding register. This permits to memorize two different

timer values without generation of any interrupt.

Four 8-bit pulse accumulators are associated with the four buffered IC

channels. Each pulse accumulator has a holding register to memorize

their value by an action on its external input. Each pair of pulse

accumulators c an be used as a 16-bit puls e accumulator.

The 16-bit modulus d own-counter can control the transfer of the IC

registers contents and the pulse accumulators to the respective holding

regist ers for a given period, every time the count reaches zero.

The modulus down-counter can also be used as a stand-alone time base

with periodic interrupt capability.

13.3.1 IC Channels

The IC channels are composed of four standard IC registers and four

buffered IC channels.

An IC regi ster is empty when it has been read or latched into the

holding register.

A holding register is empty when it has been read.

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Enhanced Capture Timer

Enhanced Capture Timer Modes of Operation

MC68HC912DG128 — Rev 3.0 Technic al Data

Enhanced Capture Timer

13.3.1.1 Non-Buffered IC Channels

The main timer value is memorized in the IC register by a valid input pin

transition. If the corresponding NOVWx bit of the ICOVW register is

cleared, with a new o ccurr ence of a ca pture, th e co nte nts o f IC reg i ster

are o verwrit ten by the new value.

If the corresponding NOVWx bit of the ICOVW register is set, the capture

This will pr event the captur ed value to be overwritten until it is read.

13.3.1.2 Buffered IC Channels

There are two modes of operations for the buffered IC channels.

•IC Latch Mode:

When enable d (LATQ=1), the main timer value is memori zed in the IC

The valu e o f the bu ffer e d IC r eg is ter i s latched t o i ts h ol ding r egister by

the Modulus counter for a given period when the count reaches zero, by

a write $0000 to the modulus counter or by a write to ICLAT in the

MCCTL register.

If the corresponding NOVWx bit of the ICOVW register is cleared, with a

new occurr ence of a captur e, the conten ts of IC register are overwritt en

by the new value. In case of latching, the contents of its holding register

are o verwrit ten.

If the corresponding NOVWx bit of the ICOVW register is set, the capture

are empty (see IC Chan nels). This will prevent the captured value to be

overwritten until it is read or latched in the holding register.

•IC Queue Mode:

When enable d (LATQ=0), the main timer value is memori zed in the IC

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Enhanced Capture Timer

Technical Data MC68HC912DG128 — Rev 3.0

Enhanced Capture Timer

If the corresp on di ng N O VWx bit of the IC O VW re gister i s cleared, with a

new occurrence of a capture, the value of the IC register will be transferred

to its holding r eg ister an d the IC re giste r m e m o ri zes the ne w tim e r va lu e.

If the corresponding NOVWx bit of the ICOVW register is set, the capture

are e m pty (se e IC Channels).

In queue mode, reads of holding register will latch the corresponding

pulse accumulator value to its holding register.

13.3.2 Pulse Accumulators

There a re fo ur 8- b it pu lse a ccum ul at or s w ith four 8 - bit h ol ding r eg is ter s

associated with the four IC buffered channels. A pulse accumulator

counts the number of active edges at the input of its channel.

The user can prevent 8-bit pulse accumulators counting further than $FF

by PACMX control bit in ICSYS ($AB). In this case a value of $FF means

that 255 counts or more have occurred.

Each pair of pulse accumulators can be used as a 16-bit pulse accumulator.

There are two modes of operation for the pulse accumulators.

13.3.2.1 Pulse Accumulator latch mode

The value of the pulse accumulator is transferred to its holding register

when the modulus down-counter reaches zero, a write $0000 to the

modulus counter or when the force latch con trol bit ICLAT is written.

At the same time the pulse accumulator is cleared.

13.3.2.2 Pulse Accumulator queue mode

When queue mode is enabled, reads of an input capture holding register

will transfer the contents of the associated pulse accumulator to its

holding register.

At the same time the pulse accumulator is cleared.

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Enhanced Capture Timer

Timer Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

Enhanced Capture Timer

13.3.3 Modulus Down-Counter

The modulus down-counter can be used as a time base to generate a

periodic interrupt. It can also be used to latch the values of the IC

registers and the pulse accumulators to their holding registers.

The action of latching can be programmed to be periodic or only once.

13.4 Timer Regi sters

Input/output pins default to general-purpose I/O lines until an internal

functio n which us es that pin is speci fica lly enab led. The timer overri des

the state of the DDR to fo rce the I/O state of each associated port line

when an output compare using a port line is enabled. In these cases the

data directi on bits will have no affe ct on the s e lines.

When a pi n i s a ssi gn ed to o utp ut an o n- chi p p er iphe r al f un cti on, w r iti ng

to this PORTT bit does not affect the pin but the data is stored in an

interna l latch such tha t if the pin become s available fo r general-pur pose

output the driven level will be the last value written to the PORTT bit.

Read or wr ite anytime.

IOS[7:0] — Input Capture or Output Compare Channel Configuration

0 = The corresponding channel acts as an input capture

1 = The corresponding channel acts as an output compare.

Bit 7654321Bit 0

IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0

RESET: 0 0 000000

TIOS — Timer Input Capture/Output Compare Select $0080

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Enhanced Capture Timer

Technical Data MC68HC912DG128 — Rev 3.0

Enhanced Capture Timer

Read anytime but will always return $0 0 (1 state is transient). Write

anytime.

FOC[7:0] — Force Output Compare Action for Channel 7-0

A write to this register with the corresponding data bit(s) set causes

the action which is programmed for output compare “n” to occur

immediately. The action taken is the same as if a successful

comparison had just taken place with the TCn register except the

interrupt flag does not get set.

Read or wr ite anytime.

The bits of OC7M correspond bit-for-bit with the bits of timer port

(PORTT). Setting the OC7Mn will set the correspo nd ing port to be an

output port regardless of the state of the DDRTn bit whe n the

corresponding IOSn bit is set to be an output compare. This does not

change the state of the DDRT bits. At successful OC7, for each bit that

is set in OC7M, the corresponding data bit OC7D is stored to the

corresponding bit of the timer port.

NOTE: OC7M has priority over output action on the timer port enabled by OMn

and OLn bi ts in TCTL1 and TCTL2. If an OC7M bit is set, it pr events the

action of corresponding OM and OL bits on the selected timer port.

Bit 7654321Bit 0

FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0

RESET: 0 0 000000

CFORC — Timer Compare Force Register $0081

Bit 7654321Bit 0

OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0

RESET: 0 0 000000

OC7M — Output Compare 7 Mask Register $0082

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Enhanced Capture Timer

Timer Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

Enhanced Capture Timer

Read or wr ite anytime.

The bits of OC7D correspond bit-for-bit with the bits of timer port

(PORTT). When a successful OC7 compare occurs, for each bit that is

set in OC7M, the corresponding data bit in OC7D is stored to the

corresponding bit of the timer port.

When the OC7Mn bit is set, a successful OC7 action will override a

successful OC[6:0] compare action during the same cycle; therefore, the

OCn action taken will depend on the co rresponding OC7D bit.

The 16-bit main timer is an up counter.

A full access for the counter register should take place in one clock cycle.

A separate read/write for high byte and low byte will give a different result

than accessing them as a word.

Read anyt ime .

Write has no meaning or effect in the normal mode; only writable in

special mo des (SMO DN = 0) .

Bit 7654321Bit 0

OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0

RESET: 0 0 000000

OC7D — Output Compare 7 Data Register $0083

Bit 7654321Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7654321Bit 0

RESET: 0 0 000000

TCNT — Timer Count Register $0084–$0085

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Enhanced Capture Timer

Technical Data MC68HC912DG128 — Rev 3.0

Enhanced Capture Timer

The per iod of the f irst count after a write to the TCNT registers ma y be a

different size because the write is not synchronized with the prescaler

clock.

Read or wr ite anytime.

TEN — Timer Enable

0 = Disables the main timer, including the counter. Can be used for

reduci ng power c onsumpt ion.

1 = Allows the timer to function normally.

If for any reason the timer is not active, there is no ÷64 clock for the

pulse accumulator since the E÷64 is generated by the timer prescaler.

TSWAI — Timer Module Stops While in Wait

0 = Allows the timer module to continue running du ring wait.

1 = Disables the timer module when the MCU is in the wait mode.

Timer interrupts cannot be used to get the MCU out of wait.

TSWAI also a ffects pu lse accu mulator s and modu lus dow n count ers.

TSBCK — Timer and Modulus Counter Stop While in Background Mode

0 = Allows the timer and modulus counter to continue running while

in backgr ound mode .

1 = Disabl es the time r and mod ulus counter whenever t he MCU is

in backgr ound mode . This is useful for em ulation.

TBSCK does not stop the pulse accumulator.

TFFCA — Timer Fast Flag Clear All

0 = Allows the timer flag clearing to function normally.

1 = For TFLG1 ($8E), a read from an inp ut capture or a writ e to the

output compare channel ($90–$9F) causes the corresponding

channel flag, CnF, to be cleared. For TFLG2 ($8F), any access

Bit 7654321Bit 0

TEN TSWAI TSBCK TFFCA

RESET: 0 0 0 0 0 0 0 0

TSCR — Timer System Control Register $0086

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Enhanced Capture Timer

Timer Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

Enhanced Capture Timer

to the TCNT register ($84, $85) clears the TOF flag. Any

access to the PACN3 an d PACN2 registers ($A2, $A3 ) clears

the PAOVF and PAIF flags in the PAFLG register ($A1). Any

access to the PACN1 an d PACN0 registers ($A4, $A5 ) clears

the PBOVF flag in the PBFLG register ($B1). Any access to the

MCCNT regi ste r ($ B6, $B7) clears the MCZF flag in the

MCFLG register ($A7). This has the advantage of eliminating

software ove rhead in a separate clear sequence. Extra care is

required to avoid accidental flag clearing due to unintended

accesses.

Bit 7654321Bit 0

RESET: 00000000

TQCR — Reserved $0087

Bit 76 5 4 3 2 1Bit 0

OM7OL7OM6OL6OM5OL5OM4OL4

RESET: 0 0 0 0 0 0 0 0

TCTL1 — Timer Control Register 1 $0088

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Enhanced Capture Timer

Technical Data MC68HC912DG128 — Rev 3.0

Enhanced Capture Timer

Read or wr ite anytime.

OMn — Output Mode

OLn — Output Level

These eight pairs of control bits are encoded to specify the output

action to be taken as a result of a successful OCn compare. When

either OMn or OLn is one, the pin associated with OCn becomes an

output tied to OCn r egardless of the state of th e associated DDRT bit.

NOTE: To enable output action by OMn and OLn bits on the timer port, the

corresponding bit in OC 7M shou ld be cl eared.

To operate the 16 -bit pulse accumulators A and B (PACA and PACB)

independently of input capture or output compare 7 and 0 respectively

the user must set th e corresponding bits IOSn = 1, OMn = 0 a nd OLn

= 0. OC7M7 or OC7M0 in the OC7M register must also be cleared.

Bit 7654321Bit 0

OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0

RESET: 00000000

TCTL2 — Timer Control Register 2 $0089

Table 13-1. Compare Re sult Output Action

OMn OLn Action

0 0 Timer disconnected from output pin logic

0 1 Toggle OCn output line

1 0 Clear OCn output line to zero

1 1 Set OCn output line to one

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Enhanced Capture Timer

Timer Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

Enhanced Capture Timer

Read or wr ite anytime.

EDGnB, EDGnA — Input Capture Edge Co ntrol

These eight pairs of control bits configure the input capture edge

detector circuits.

Read or wr ite anytime.

Bit 7654321Bit 0

EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A

RESET: 0 0 000000

TCTL3 — Timer Control Register 3 $008A

Bit 76 5 4 3 2 1Bit 0

EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A

RESET: 0 0 0 0 0 0 0 0

TCTL4 — Timer Control Register 4 $008B

Table 13- 2Edge Detector Circuit Configuration

EDGnB EDGnA Configuration

0 0 Capture disabled

0 1 Capture on rising edges only

1 0 Capture on falling edges only

1 1 Capture on any edge (rising or falling)

Bit 7654321Bit 0

C7I C6I C5I C4I C3I C2I C1I C0I

RESET: 0 0 000000

TMSK1 — Timer Interrupt Mask 1 $008C

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Enhanced Capture Timer

Technical Data MC68HC912DG128 — Rev 3.0

Enhanced Capture Timer

The bits in TMSK1 correspond bit-for-bit with the bits in the TFLG1 status

hardware interrupt. If set, the corresponding flag is enabled to cause a

hardware interrupt.

Read or wr ite anytime.

C7I–C0I — Input Capture/Output Compare “x” Interrupt Enable.

Read or wr ite anytime.

TOI — Timer Overflow Interrupt Enable

0 = Interrupt inhibited

1 = Hardware inter rupt requested when TOF flag set

PUPT — Timer Port Pull-Up Resistor Enable

This enable b it controls p ull-u p resistors on the timer port pins when

the pins are configured as inputs.

0 = Disable pull-up resist or func tion

1 = Enable pull-up re sistor function

RDPT — Timer Port Drive Reduction

This bit reduces the effective output driver size which can reduce

power supply current and generated noise depending upon pin

0 = Normal output drive capability

1 = Enable output drive reductio n function

TCRE — Timer Counter Reset Enable

This bit allows the timer counter to be reset by a successful output

compar e 7 ev ent. This mode of operat ion is simil ar to an up-cou nting

modulus counter.

Bit 7654321Bit 0

TOI 0 PUPT RDPT TCRE PR2 PR1 PR0

RESET:00000000

TMSK2 — Timer Interrupt Mask 2 $008D

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Enhanced Capture Timer

Timer Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

Enhanced Capture Timer

0 = Counter reset inhibited and counter free runs

1 = Counter reset by a successful output compare 7

If TC7 = $0000 and TCRE = 1, TCNT will stay at $0000 continuously.

If TC7 = $FFFF and TCRE = 1, TOF will never be set when TCNT is

reset from $FFFF to $0000.

PR2, PR1, PR0 — Timer Prescaler Se lect

These three bits specify the number of ÷2 stages that are to be

inserted between the module clock and the main timer counter.

The newly selected prescale factor will not take effect until the next

synchronized edge where all prescale counter stages equal zero.

Table 13-3. Prescaler Selection

PR2 PR1 PR0 Prescale

Factor

000 1

001 2

010 4

011 8

100 16

101 32

110 64

111 128

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Enhanced Capture Timer

Technical Data MC68HC912DG128 — Rev 3.0

Enhanced Capture Timer

TFLG1 indicat es when interrupt conditions have occurred. To clear a bit

in the flag register, write a one to the bit.

Use of the TFMOD bit in the ICSYS register ($AB) in conjunction with the

use of the ICOVW register ($AA) allows a timer interrupt to be generated

after capturing two values in the capture and holding registers instead of

generating an interrupt f or ever y capt ure.

Read anytime. Write used in the clearing mechanism (set bits cause

corresponding bits to be cleared). Writing a zero will not affect current

status of the bit.

When TFFCA bit in TSCR register is set, a read from an input capture or

a write into an outpu t compare channel ($ 90–$9F) will cause the

corresponding channel flag CnF to be cleared.

C7F–C0F — Input Capture/Output Compare Channel “n” Flag.

TFLG2 indicat es when interrupt conditions have occurred. To clear a bit

in the flag register, set the bit to one.

Read anytime. Write used in clearing mechanism (set bits cause

corresponding bits to be cleared).

Bit 765432 1Bit 0

C7F C6F C5F C4F C3F C2F C1F C0F

RESET: 0 0 0 0 0 0 0 0

TFLG1 — Main Timer Interrupt Flag 1 $008E

Bit 765432 1Bit 0

TOF0000000

RESET: 0 0 0 0 0 0 0 0

TFLG2 — Main Timer Interrupt Flag 2 $008F

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Enhanced Capture Timer

Timer Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

Enhanced Capture Timer

Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR

TOF — Timer Overflow Flag

Set when 16-bit free-running timer overflows from $FFFF to $0000.

This bi t is clea red a utom aticall y by a wri te to t he TFLG2 registe r wi th

bit 7 set. (See also TCRE control bit explanation.)

Bit 765432 1Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 765432 1Bit 0

TC0 — Timer Input Capture/Output Compare Register 0 $0090–$0091

Bit 7654321Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7654321Bit 0

TC1 — Timer Input Capture/Output Compare Register 1 $0092–$0093

Bit 7654321Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7654321Bit 0

TC2 — Timer Input Capture/Output Compare Register 2 $0094–$0095

Bit 7654321Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7654321Bit 0

TC3 — Timer Input Capture/Output Compare Register 3 $0096–$0097

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Enhanced Capture Timer

Technical Data MC68HC912DG128 — Rev 3.0

Enhanced Capture Timer

Depending on the TIOS bit for the corresponding channel, these

registers are used to latch the value of the free-running counter when

a defined transition is sensed by the corresponding input capture

edge detector or to trigger an output action for output compare.

Bit 7654321Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7654321Bit 0

TC4 — Timer Input Capture/Output Compare Register 4 $0098–$0099

Bit 7654321Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7654321Bit 0

TC5 — Timer Input Capture/Output Compare Register 5 $009A–$009B

Bit 765432 1Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 765432 1Bit 0

TC6 — Timer Input Capture/Output Compare Register 6 $009C–$009D

Bit 765432 1Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 765432 1Bit 0

TC7 — Timer Input Capture/Output Compare Register 7 $009E–$009F

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Enhanced Capture Timer

Timer Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

Enhanced Capture Timer

Read anytime. Write anytime for output compare function. Writes to

these registers have no meaning or effect during input capture. All

timer input capture/output compare registers are reset to $0000.

16-Bit Pulse Accumulator A (PACA) is formed by cascading the 8-bit

pulse accum ulator s P AC3 and PAC2.

When PAEN is set, the PACA is enabled. The PACA shares the input pin

with IC7.

Read: any time

Write: any time

PAEN — Pulse Accumulator A System Enable

0 = 16-Bit Pulse Accumulator A system disabled. 8-bit PAC3 and

PAC2 c an be en abled when their related enable bits in

ICPACR ($A8) are set.

Pulse Accumulator Input Edge Flag (PAIF) function is

disabled.

1 = Pulse Accumulator A system enabled. The two 8-bit pulse

accumulators PAC3 and PAC2 are cascaded to form the

PACA 16-bit pulse accumulator. When PACA in enabled, the

PACN3 and PACN2 registers contents are respectively the

high and low byte of the PACA.

PA3EN and PA2EN control bits in ICPACR ($A8) have no

effect.

Pulse Accumulator Input Edge Flag (PAIF) function is enabled.

PAEN is independent from TEN. With timer disabled, the pulse

accumulator can still function unless pulse accumulator is disabled.

BIT 7654321BIT 0

0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI

RESET: 00000000

PACTL — 16-Bit Pulse Accumulator A Control Register $00A0

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Enhanced Capture Timer

Technical Data MC68HC912DG128 — Rev 3.0

Enhanced Capture Timer

PAMOD — Pulse Accumulator Mode

0 = event counter mo de

1 = gated time accumulation mode

PEDGE — Pulse Accumulator Edge Control

For PAMOD bit = 0 (event counter mode).

0 = falling edges on PT7 p in cause the count to be incremented

1 = rising edges on PT7 pin cause the co unt to be incremented

For PAMOD bit = 1 (gated time accumul ation mode).

0 = PT7 input pin high enables M divided by 64 clock to Pulse

Accumulat or and the trailing falling edge on PT7 sets the PAIF

flag.

1 = PT7 input pin low enables M divided by 64 cl ock to P uls e

Accumulat or and the tra iling rising e dge on PT7 se ts the PAIF

flag.

If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64

since the E÷64 clock is generated by the timer prescaler.

CLK1, CLK0 — Clock Select Bits

If the pulse accumulator is disabled (PAEN = 0), the prescaler clock

from the timer is always used as an input clock to the timer counter.

The change from one selected clock to the other happens

immediately after these bits are written.

PAMOD PEDGE Pin Action

0 0 Fal ling edge

0 1 Rising edge

1 0 Div. by 64 clock enabled with pin high level

1 1 Div. by 64 clock enabled with pin low level

CLK1 CLK0 Clock Source

0 0 Use timer prescaler clock as timer counter clock

0 1 Use PACLK as input to timer counter clock

1 0 Use PACLK/256 as timer counter clock frequency

Use PACLK/65536 as timer counter clock

frequency

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Enhanced Capture Timer

Timer Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

Enhanced Capture Timer

PAOVI — Pulse Accumulator A Overflow Interrupt enable

0 = interrupt inhibited

1 = interrupt requested if PAOVF is set

PAI — Pulse Accumulato r Inp ut Inte rru pt ena ble

0 = interrupt inhibited

1 = interrupt requested if PAIF is set

Read or write anytime. When the TFFCA bit in the TSCR register is set,

any access to the PACNT register will clear all the flags in the PAFLG

PAOVF — Pulse Accumulator A Overflow Flag

Set when the 16-bit pulse accumulator A overflows from $FFFF to

$0000, or when 8- bit pulse acc umulator 3 (PAC3) ove rflow s from $FF

to $00.

This bi t is cl eared aut omatical ly by a write to the PAFL G register with

bit 1 set.

PAIF — Pulse Accumulat or Input edge Flag

Set when the selected edge is detected at the PT7 inp ut pin. In event

mode the event edge triggers PAIF an d in gat ed time accumulation

mode the trailing edge of the gate signal at the PT7 input pin triggers

PAIF.

This bit is cleared by a write to the PAFLG register with bit 0 set.

Any access to the PACN3, PACN2 registers will clear all the flags in

this register when TFFCA bit in register TSCR($86) is set.

BIT 7654321BIT 0

0 0 0 0 0 0 PAOVF PAIF

RESET: 0 0 0 0 0 0 0 0

PAFLG — Pulse Accumulator A Flag Register $00A1

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Enhanced Capture Timer

Technical Data MC68HC912DG128 — Rev 3.0

Enhanced Capture Timer

Read: any time

Write: any time

The two 8-bit pulse accumulators PAC3 and PAC2 are cascaded to form

the PACA 16-bit pulse accumulator. When PACA in enabled (PAEN=1

in PACTL, $A0) the PACN3 and P ACN2 registers contents are

respe ctively the h igh and low byte of the PACA.

When PACN3 overflows from $FF to $00, the Interrupt flag PAOVF in

PAFL G ($ A1 ) is s et.

Full count register access should take place in one clock cycle. A

separa te rea d/write f or hi gh byte and low byte will give a di fferent re sult

than accessing them as a word.

Read: any time

Write: any time

The two 8-bit pulse accumulators PAC1 and PAC0 are cascaded to form

the PACB 16-bi t pul se accumu lator . When PACB i n enabl ed, (PBE N= 1

BIT 7654321BIT 0

$00A2BIt 7654321Bit 0PACN3 (hi)

$00A3Bit 7654321Bit 0PACN2 (lo)

RESET: 00000000

PACN3, PACN2 — Pulse Accumulators Count Registers $00A2, $00A 3

BIT 765432 1BIT 0

$00A4BIt 7654321Bit 0PACN1 (hi)

$00A5Bit 7654321Bit 0PACN0 (lo)

RESET: 0 0 0 0 0 0 0 0

PACN1, PACN0 — Pulse Accumulators Count Registers $00A4, $00A 5

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Enhanced Capture Timer

Timer Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

Enhanced Capture Timer

in PBCTL, $B0) the PACN1 and P ACN0 registers contents are

respe ctively the h igh and low byte of the PACB.

When PACN1 overflows from $FF to $00, the Interrupt flag PBOVF in

PBFL G ($ B1 ) is s et.

Full count register access should take place in one clock cycle. A

separa te rea d/write f or hi gh byte and low byte will give a di fferent re sult

than accessing them as a word.

Read: any time

Write: any time

MCZI — Modulus Counter Underflow Interrupt Enable

0 = Modulus counter interrupt is disabled.

1 = Modulus counter interrupt is enabled.

MODMC — Modulus Mode Enable

0 = The counter cou nts on ce from the value wr itten to it and will

stop at $0000.

1 = Mod ulus mode is enabled. When the coun ter reaches $0000,

the counter is loaded with the latest value written to the

modulus count register.

NOTE: For prope r oper atio n, the MCEN bit shou ld b e clear ed be fore mo difyi ng

the MODMC bit in order to reset the modulus counter to $FF.

RDMCL — Read Modulus Down-Counter Load

0 = Reads of the modulus count register will return the pr esent

value of the cou nt re gi ster.

1 = Read s of the m odulu s coun t re gister will re turn th e con tents of

the load register.

BIT 7654321BIT 0

MCZI MODMC RDMCL ICLAT FLMC MCEN MCPR1 MCPR0

RESET: 0 0 0 0 0 0 0 0

MCCTL — 16-Bit Modulus Down-Counter Control Register $00A6

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Enhanced Capture Timer

Technical Data MC68HC912DG128 — Rev 3.0

Enhanced Capture Timer

ICLAT — Input Capture Force Latch Action

When input capture latch mode is enabled (LATQ and BUFEN bit in

ICSYS ($AB) are set), a write one to this bit immediately forces the

contents of the input capture registers TC0 to TC3 and their

corresponding 8-bit pulse accumulators to be latched into the

associated holding registers. The pulse accumula tors will be

automatically cleared when the latch action occurs.

Writing zero to this bit has no effect. Read of this bit will return always

zero.

FLMC — Forc e Lo ad Reg ister i nto t he M odulus Coun ter Co unt R egister

This bit is active only whe n the modulus do wn-counter is en abled

(MCEN=1).

A write one into this bit loads the load register into the modulus

counter count register. This also resets the modulus counter

prescaler.

Write zero to this bit has no effect.

When MODMC=0, counter starts co unting and st ops at $0000.

Read of this bit wi ll return always zero.

MCEN — Modulus Down-Counter Enable

0 = Modulus counter disabled.

1 = Modulus counter is enabled.

When MCEN=0, the counter is preset to $FFFF. This will prevent an

early interrupt flag whe n the mo dulus down-counter is enabled.

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Enhanced Capture Timer

Timer Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

Enhanced Capture Timer

MCPR1, MCPR0 — Modulus Counter Prescaler select

These two bits specify the division rate of the modulus counter

prescaler.

The new ly selecte d presca ler divi sion rat e will no t be effe ctive u ntil a

load of the load register into the modulus counter count register

occurs.

Read: any time

Write: Only for clearing bit 7

MCZF — Modulus Counter Underflow Interrupt Flag

The flag is set when the modulus down-counter reaches $0000.

Writing a1 to this bit clears the flag (if TFFCA=0). Writing a zero has

no effect.

Any access to the MCCNT register will clear the MCZF flag in this

MCPR1 MCPR0 Prescaler divi sion

rate

00 1

01 4

10 8

11 16

BIT 7654321BIT 0

MCZF 0 0 0 POLF3 POLF2 POLF1 POLF0

RESET: 0 0 000000

MCFLG — 16-Bit Modulus Down-Counter FLAG Register $00A7

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Enhanced Capture Timer

Technical Data MC68HC912DG128 — Rev 3.0

Enhanced Capture Timer

POLF3 – POLF0 — First Input Capture Polarity Status

These are read only bits. Write to these bits has no effect.

Each status bit gi ves th e polarit y of the first edge which has caused

an input capture to occur afte r capt ur e la tch has be en re ad .

Each POLFx corresponds to a timer PORTx input.

0 = The first input capture has been caused by a falling edge.

1 = The first input capture has been caused by a rising edge.

The 8-bit pulse accumulators PA C3 and PAC2 can be enabled only if

PAEN in PATCL ($A0) is cleared. If PAEN is set, PA3EN and PA2EN

have no effect.

The 8-bit pulse accumulators PA C1 and PAC0 can be enabled only if

PBEN in PBTCL ($B0) is cleared. If PBEN is set, PA1EN and PA0EN

have no effect.

Read: any time

Write: any time

PAxEN — 8-Bit Pulse Accumulator ‘x’ Enable

0 = 8-Bit Pulse Ac cumulator is disabled .

1 = 8-Bit Pulse Ac cumulator is en abled.

BIT 7654321BIT 0

0 0 0 0 PA3EN PA2EN PA1EN PA0EN

RESET: 0 0 0 0 0 0 0 0

ICPACR — Input Control Pulse Accumulators Control Register $00A8

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Enhanced Capture Timer

Timer Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

Enhanced Capture Timer

Read: any time

Write: any time

If enabl ed, after detecti on of a valid ed ge on input captu re pin, th e delay

counter counts the pre-selected number of M clock (module clock)

cycles, then it will generate a pulse on its output. The pulse is generated

only if the level of input signal, after the preset delay, is the opposite of

the level before the transition.Th is will avoid reaction to narrow input

pulses.

After counting, the cou nte r will be cleared automatically.

Delay between two active edges of the input signal period should be

longer than the selected counter delay.

DLYx — Del ay Co unter Select

BIT 7654321BIT 0

000000DLY1DLY0

RESET: 0 0 000000

DLYCT — Delay Counter Control Register $00A9

DLY1 DLY0 Delay

0 0 Disabled (bypassed)

0 1 256 M clock cycles

1 0 512 M clock cycles

1 1 1024 M clock cycles

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Technical Data MC68HC912DG128 — Rev 3.0

Enhanced Capture Timer

Read: any time

Write: any time

An IC register is empty when it has been read or latched into the holding

A holding register is empty when it has been read.

NOVWx — No Input Capture Overwrite

0 = The contents of the related capture register or holding register

can be overwritten when a new input capture or latch occurs.

1 = The relate d captu re reg ister or hold in g re gister cannot be

written by an even t unl e ss they ar e empty (see IC Channels).

This will prevent the captured value to be overwritten until it is

read or latched in the holding register.

BIT 7654321BIT 0

NOVW7 NOVW6 NOVW5 NOVW4 NOVW3 NOVW2 NOVW1 NOVW0

RESET: 0 0 000000

ICOVW — Input Contr ol Overwr it e Regis ter $00AA

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Enhanced Capture Timer

Timer Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

Enhanced Capture Timer

Read: any time

Write: May be written once (SMODN=1). Writes are always permitted

when SMODN=0.

SHxy — Share Input action of Input Capture Channels x and y

0 = Normal operation

1 = The channel input ‘x’ causes t he same action on the channel

‘y’. The po rt pin ‘x’ and the corresponding edge detector is

used to be active on the chann el ‘y’.

TFMOD — Timer Flag-setting Mode

Use of the TFMOD bit in the ICSYS register ($AB ) in conjunction with

the use of the ICOVW register ($AA) allows a timer interrupt to be

generated after capturing two values in the capture and holding

registers instead of generating an interrupt for every capture.

By setting TFMOD in queue mode, when NOVW bit is set and the

corresponding capture and holding registers are emptied, an input

capture event will first update the related input capture register with

the main timer contents. At the next event the TCn data is transferred

to the TCnH register, The TCn is updated an d the CnF interrupt flag

is set. See Figure 13-6.

In all other input capture cases the interrupt flag is set by a valid

externa l event on PTn.

0 = The timer flags C3F–C0F in TFLG1 ($8E) are set w hen a va lid

input cap ture tr ansi ti o n on the corr espo nd i ng port pi n occur s.

1 = If in queue mode (BUFEN=1 and LATQ=0), the timer flags

C3F–C0F in TFLG1 ($8E) are set only when a latch on the

corresponding holding register occurs.

If the queue mode is not engaged, the timer flags C3F–C0F are

set the same way as for TFMOD=0.

BIT 7654321BIT 0

SH37 SH26 SH15 SH04 TFMOD PACMX BUFEN LATQ

RESET: 0 0 000000

ICSYS — Input Control System Control Register $00AB

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Enhanced Capture Timer

Technical Data MC68HC912DG128 — Rev 3.0

Enhanced Capture Timer

PACMX — 8-Bit Pulse Accumula tors Maximum Count

0 = Normal operation. When the 8-bit pulse accumulator has

reached the value $FF, with the next active edge, it will be

incremented to $00.

1 = When the 8-bit pulse accumulator has reached the value $FF,

it will not be incremented further. The value $FF indicates a

count of 255 or more.

BUFEN — IC Buffer Enable

0 = Input Capture and pul se accumulator holding registers are

disabled.

1 = Input Capture and pul se accumulator holding registers are

enabled. The latching mode is defined by LATQ control bit.

Write one into ICLAT bit in MCCTL ($A6), when LATQ is set

will produc e latching of input capture and pulse accumulators

registers into their ho lding re gisters .

LATQ — Input Control Latch or Queue Mode Enab l e

The BUFEN control bit should be set in order to enable the IC and

pulse accumulators holding registers. Otherwise LATQ latching

modes are di sabled.

Write one into ICLAT bit in MCCTL ($A 6), when LATQ and B U FEN

are set will produce latching of input capture and pulse accumulators

registers into their holding registers.

0 = Queue Mode of Input Capture is enabled.

The main timer value is memorized in the IC register by a valid

input pin tr ansit io n.

With a new occurrence of a capture, the value of the IC register

will be transferred to its holding register and the IC register

memorize s the new timer value.

1 = Latch Mode is enabled. Latching function occurs when

modulus down-counter reaches zero or a zero is written into

the count register MCCNT (see Buffered IC Channels).

With a latching e vent the co ntent s of IC registers and 8-bit

pulse accumulators are transferred to their holding registers.

8-bit pulse accumulators are c l eared.

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Enhanced Capture Timer

Timer Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

Enhanced Capture Timer

Read: any time

Write: only in special mode (SMOD = 1).

TCBYP — Main Timer Divider Chain Bypass

0 = Normal operation

1 = For testing only. The 16-bit free-running timer counter is divided

into two 8-bit halves and the prescaler is bypassed. The clock

drives both halves directly.

When the high byte of timer counter TCNT ($84) overflows

from $FF to $00, the TOF flag in TFLG2 ($8F) will be set.

Read: any time (inputs return pin level; outputs return data register

contents)

Write: data stored in an internal latch (drives pins only if configured for

output)

Since the Output Compare 7 shares the pin with Pulse Accumulator

input, the only way for Pulse accumulator to receive an independent

input from Output Compare 7 is setting both OM7 & OL7 to be zero, and

also OC7M7 in OC7M register to be zero.

BIT 7654321BIT 0

000000TCBYP0

RESET: 0 0 000000

TIMTST — Timer Test Register $00AD

BIT 7654321BIT 0

PORT PT7 PT6 PT5 PT4 PT3 PT2 PT1 PT0

TIMER I/OC7 I/OC6 I/OC5 I/OC4 I/OC3 I/OC2 I/OC1 I/OC0

RESET: 0 0 000000

PORTT — Timer Port Data Regist er $00AE

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Enhanced Capture Timer

Technical Data MC68HC912DG128 — Rev 3.0

Enhanced Capture Timer

OC7 is still able to reset the counter if enabled while PT7 is used as input

to Pulse Accumulator.

PORTT can be rea d a nytime . When configured as an input, a read will

return the pin level. When configured as an output, a read will return the

latched output data.

NOTE: Wri tes do not change pin state when the pin is configured for timer

output. The minimum pulse width for pulse accumulator input should

always be greater than the width of two module clocks due to input

synchronizer circuitry. The minimum pulse width for the input capture

should always be greater than the width of two module clocks due to

input synchronizer circuitry.

Read or write an y time.

0 = Configures the corresponding I/O pin for input only

1 = Configures the corresponding I/O pin for output.

The timer for ces th e I/O state to be an o utp ut for each t ime r p or t l ine

associat ed with an enabl ed output com par e. In these case s the data

directi on bi ts wi ll not be chan ge d, bu t have no effe ct on the direction

of these pins. The DDRT will revert to controlling the I/O direction of

a pin when the associated timer output compare is disabled. Input

captures do not override the DDRT settings.

BIT 7654321BIT 0

DDT7 DDT6 DDT5 DDT4 DDT3 DDT2 DDT1 DDT0

RESET: 00000000

DDRT — Data Direction Register for Timer Port $00AF

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Enhanced Capture Timer

Timer Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

Enhanced Capture Timer

Read: any time

Write: any time

16-Bit Pulse Accumulator B (PACB) is formed by cascading the 8-bit

pulse accum ulator s P AC1 and PAC0.

When PBEN is set, the PACB is enabled. The PACB shares t he input

pin with IC0.

PBEN — Pulse Accumulator B System Enable

0 = 16-bit Pulse Accumulator system disabled. 8-bit PAC1 and

PAC0 c an be en abled when their related enable bits in

ICPACR ($A8) are set.

1 = Pulse Accumulator B system enabled. The two 8-bit pulse

accumulators PAC1 and PAC0 are cascaded to form the

PACB 16-bit pulse accumulator. When PACB in enabled, the

PACN1 and PACN0 registers contents are respectively the

high and low byte of the PACB.

PA1EN and PA0EN control bits in ICPACR ($A8) have no

effect.

PBEN is independent from TEN. With timer disabled, the pulse

accumulator can still function unless pulse accumulator is disabled.

PBOVI — Pulse Accumulator B Overflow Interrupt enable

0 = interrupt inhibited

1 = interrupt requested if PBOVF is set

BIT 7654321BIT 0

0 PBEN 0 0 0 0 PBOVI 0

RESET: 0 0 0 0 0 0 0 0

PBCTL — 16-Bit Pulse Accumulator B Control Register $00B0

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Enhanced Capture Timer

Technical Data MC68HC912DG128 — Rev 3.0

Enhanced Capture Timer

Read: any time

Write: any time

PBOVF — Pulse Accumulator B Overflow Flag

This bit is set when the 16-bit pulse accumulator B overflows from

$FFFF to $0000, or when 8-bit pulse accumulator 1 (PAC1) overflows

from $FF to $00.

This bit is cleared by a write to the PBFLG register with bit 1 set.

Any access to the PACN1 and PACN0 registers will clear the PBOVF

flag in this register when TFFCA bit in register TSCR($86) is set.

Read: any time

Writ e: has no effe ct.

These registers are used to latch the value of the corresponding pulse

accumulator when the related bits in register ICPACR ($A8) are enabled

(see Pulse Accumu lators).

BIT 7654321BIT 0

000000PBOVF0

RESET:00000000

PBFLG — Pulse Accumulator B Flag Register $00B1

BIT 7654321BIT 0

$00B2BIt 7654321Bit 0PA3H

$00B3Bit 7654321Bit 0PA2H

$00B4BIt 7654321Bit 0PA1H

$00B5Bit 7654321Bit 0PA0H

RESET:00000000

PA3H–PA0H — 8-Bit Pulse Accumulators Holding Registers $00B2–$00B5

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Enhanced Capture Timer

Timer Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

Enhanced Capture Timer

Read: any time

Write: any time

A full access for the counter register should take place in one clock cycle.

A separate read/write for high byte and low byte will give different result

than accessing them as a word.

If the RDMCL bit in MCCTL register is cleared, reads of the MCCNT

bit is set, reads of the MCCNT will return the contents of the load

If a $000 0 is wr itte n into M CCNT an d modul us coun ter whil e LATQ an d

BUFEN in ICSYS ($AB) register are set, the input capture and pulse

accumulator registers will be latche d.

With a $0000 write to the MCCNT, the modulus counter will stay at zero

and does not set the MCZF flag in MCFLG register.

If modulus mode is enabled (MODMC=1), a write to this address will

update the load register with the value written to it. The count register will

not be updated with the new value until the next counter underflow.

The FLMC bit in MCCTL ($A6) can be used to immediately update the

count register with the new value if an immediate load is desired.

If modulus mode is not enabled (MODMC=0), a write to this address will

clear the prescaler and will immediate ly update the counter registe r with

the value written to it and down-counts once to $0000.

BIT 7654321BIT 0

$00B6 BIt 15 14 13 12 11 10 9 Bit 8 MCCNTH

$00B7Bit 7654321Bit 0MCCNTL

RESET: 1 1111111

MCCNTH/L — Modulus Down-Counter Count Register $00B6, $00B 7

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Enhanced Capture Timer

Technical Data MC68HC912DG128 — Rev 3.0

Enhanced Capture Timer

Read: any time

Writ e: has no effe ct.

These registers are used to la tch the value of the input cap ture registers

TC0 – TC3. The corresponding IOSx bits in TIOS ($80) should be

cleared (see IC Channels).

Bit 7654321Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7654321Bit 0

TC0H — Timer Input Capture Holding Register 0 $00B8–$00B9

Bit 7654321Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7654321Bit 0

TC1H — Timer Input Capture Holding Register 1 $00BA–$00BB

Bit 7654321Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7654321Bit 0

TC2H — Timer Input Capture Holding Register 2 $00BC–$00BD

Bit 765432 1Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 765432 1Bit 0

TC3H — Timer Input Capture Holding Register 3 $00BE–$00BF

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Enhanced Capture Timer

Technical Data MC68HC912DG128 — Rev 3.0

Enhanced Capture Timer

13.5 Timer and Modulus Counter Operation in Different Modes

STOP: Timer and modulus counter are off since clocks are stopped.

BGDM: Timer and modulus counter keep on running, unless TSBCK

(REG$86, bit5) is set to one.

WAIT: Counter s kee p on r unn i ng , un le ss TSW AI in TSCR ($ 86 ) i s

set to one.

NORMAL : Tim er and modu lus counter ke ep on runni ng, unless TEN in

TSCR($86) respectively MCEN in MCCTL ($A6) are

cleared.

TEN=0: All 16 -bit time r opera tions are stop ped, can only access the

registers.

MCEN= 0: Modulus counte r is stop pe d.

PAEN=1: 16-bit Pulse Accumulator A is active.

PAEN=0: 8-Bit Pulse Accumulators 3 and 2 can be enabled. (see

ICPACR)

PBEN=1: 16-bit Pulse Accumulator B is active.

PBEN=0: 8-Bit Pulse Accumulators 1 and 0 can be enabled. (see

ICPACR)

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Enhanced Capture Timer

Technical Data MC68HC912DG128 — Rev 3.0

Enhanced Capture Timer

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MC68HC912DG128 — Rev 3.0 Technic al Data
Multiple Serial Interface
 
Technical Data — MC68HC912DG128
Section 14. Multiple Serial Interface
14.1  Contents
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
14.3 Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250
14.4 Serial Communication Interface (SCI) . . . . . . . . . . . . . . . . . .2 50
14.5 Serial Peripheral Interface (SPI). . . . . . . . . . . . . . . . . . . . . . .262
14.6 Port S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271
14.2  Introduction
The multiple serial interface (MSI) module consists of three independent 
serial I/O sub-systems: two serial communication interfaces (SCI0 and 
SCI1) and the serial peripheral interface (SPI). Each serial pin shares 
function with the general-purpose port pins of port S. The SCI 
subsystems are NRZ type systems that are compatible with standard 
RS-232 systems. These  SCI systems have a new single wire opera tion 
mode which al lows the unused pin t o be available as general-purpose 
I/O. The SPI subsystem, which is compatible with the M68HC11 SPI, 
includes new features such as SS output and bidirectional mode.
    
  
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Multiple Serial Interface

Technical Data MC68HC912DG128 — Rev 3.0

Multiple Serial Interface

14.3 Block diagra m

Figure 14-1. Multiple Serial Interface Block Diagram

14.4 Serial Communication Interface (SCI)

Two serial communication interfaces ar e available on the

MC68HC912DG128. These are NRZ format (one start, eight or nine

data, and one stop bit) asynchronous communication systems with

independent internal baud ra te generation circuitry and SCI transmit ters

and r eceivers. The y can be configu red for e ight or nine da ta bits (one of

which may be de signat ed as a par ity bit, odd or ev en). If en able d, parity

is generated in hardware for transmitted and received data. Receiver

parity er rors are fl agged in har dware. The bau d rat e gene rator i s base d

on a modulus counter, allowing flexibility in choosing baud rates. There

is a receiver wake-up fea ture, an idle line detect feature, a loop-back

mode, and various error detection featur es. Two port pins for ea ch SCI

provide the external interface for the transmitted data (TXD) and the

received data (RXD).

For a faster wake-up out of WAIT mode by a received SCI message,

both SCI have the capability of sending a receiver interrupt, if enabled,

when RAF (rece iver active flag) is set. For compatibility with other

M68HC12 products, this feature is active only in WAIT mode and is

disab l ed when VDDPLL supply is at VSS level.

PS0

PS1

PS2

PS3

PS4

PS5

PS6

PS7

SCI0

SCI1

SPI

DDRS/IOCTLR

PORT S I/O DRIVERS

MSI RxD0

TxD0

RxD1

TxD1

MISO/SISO

MOSI/MOMI

SCK

CS/SS

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Multiple Serial Interface

Serial Communication Interface (SCI)

MC68HC912DG128 — Rev 3.0 Technic al Data

Multiple Serial Interface

Figure 14-2. Serial Communications Interface Block Diagram

Rx Baud Rate

Tx Baud Rate

MCLK

DIVIDER 10-11 Bit SHIFT REG

MSB

TxD BUFFER/SCxDRL

TxMTR CO NTR OL

SCxCR2/S CI CTL 2

SCxCR1/S CI CTL 1

SCxSR1/INT STATUS

DATA RECOVERY

10-11 BIT SHIFT REG

TxD BUFFER/SCxDRL

SCxBD/SELECT

LSB

RxD

TxD

PIN CONTROL / DDRS / PORT S

WAKE-UP LOGIC

SCxCR1/SCI CTL 1

SCxSR1/IN T STATUS

SCxCR2/S CI CTL 2

INT REQUEST LOGIC

MSB LSB

INT REQUEST LOGIC

SCI RECEI VE R

SCI TRANSMITTER

BAUD RATE

CLOCK

INTERNAL

LOGIC

DATA BUS

PARITY

DETECT

PARITY

GENERATOR

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Multiple Serial Interface

Technical Data MC68HC912DG128 — Rev 3.0

Multiple Serial Interface

14.4.1 Data Format

The serial data format requires the following conditions:

•An idle-line in the high state before transmission or reception of a

message.

•A start bit (logic zero), transmitted or received, that indicates the

start of each character.

•Data that is transmit ted or received lea st significant bit (L SB) first.

•A stop bit (logic one), used to indicate the end of a frame. (A frame

consists of a start bit, a character of eight or nine data bits and a

stop bit.)

•A BREAK is defined as the transmission or reception of a logic

zero for one frame or more.

•This SCI supports hardware parity for transmit and receive.

14.4.2 SCI Baud Rate Generation

The basis of the SCI baud rate generator is a 13-bit modulus counter.

This counter gives the generator the flexibility necessary to achieve a

reasonable level of independence from the CPU operating frequency

and sti ll b e a bl e t o produce sta nda r d b aud r ate s wit h a mi ni mal a m oun t

of error. The clock source for the generator comes from the M Clock.

Table 14-1. Baud Rate Generation

Desired

SCI Baud Rate BR Divisor for

M = 4.0 MHz BR Divisor for

M = 8.0 MHz

110 2273 4545

300 833 2273

600 417 833

1200 208 417

2400 104 208

4800 52 104

9600 26 52

14400 17 35

19200 13 26

38400 —13

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Multiple Serial Interface

Serial Communication Interface (SCI)

MC68HC912DG128 — Rev 3.0 Technic al Data

Multiple Serial Interface

14.4.3 SCI Register Descriptions

Control and data registers for the SCI subsystem are described below.

The memory address indicated for each register is the default address

that is in use after reset. Both SCI have identical control registers

mapped in two blocks of eight bytes.

SCxBDH and SCxBDL are considered together a s a 16-bit baud rate

control register.

Read any time. Write SBR[12:0] anytime. Low order byte must be written

for change to take effect. Write SBR[15:13] only in special modes. The

value in SBR[ 12 :0] det er m in es the baud rate of the SCI. The de sir e d

baud rate is determined by the following formula:

which is equivalent to:

BR is the value written to bits SBR[12:0] to establish baud rate.

NOTE: The baud rate generator is disabled until TE or RE bit in SCxCR2

is disabled when SBR[12:0] = 0.

BTST — Reserved for test function

BSPL — Reserved for test function

BRLD — Reserved for test function

Bit 7654321Bit 0

BTST BSPL BRLD SBR12 SBR11 SBR10 SBR9 SBR8 High

RESET: 00000000

SC0BDH/SC1BDH — SCI Baud Rate Control Register $00C0/$00C8

Bit 7654321Bit 0

SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 Low

RESET:00000100

SC0BDL/SC1BDL — SCI Baud Rate Control Register $00C1/$00C9

SCI Baud Rate MCLK

16 BR×

--------------------=

BR MCLK

16 SCI Baud Rate×

------------------------------------------------=

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Multiple Serial Interface

Technical Data MC68HC912DG128 — Rev 3.0

Multiple Serial Interface

Read or wr ite anytime.

LOOPS — SCI LOOP Mode/Single Wire Mode Enable

0 = SCI transmit and receive sections operate normally.

1 = SC I recei ve secti on is disconn ected fr om the RXD pin an d the

RXD pin is available as general purpose I/O. The receiver input is

determ ined by t he RSRC bit. The transmit ter outpu t is contro lled

by the associated DDRS bit. Both the transmitter and the receiver

must be enab led t o use t he LOOP o r the single wire m ode.

If the DDRS bit associated with the TXD pin is set during the LOOPS

= 1, the TXD pin outputs the SCI waveform. If the DDRS bit

associat ed wit h the TXD pi n is clea r durin g t he LOOPS = 1, the TXD

pin becomes high (IDLE line state) for RSRC = 0 and high impedance

for RSRC = 1. Refer to Table 14-2.

WOMS — Wired-Or Mode for Serial Pins

This bit controls the two pins (TXD and RXD) associated with the SCIx

section.

0 = Pins operate in a nor mal mode with both high and low drive

capability. To affect the RXD bit, that bit w ould have to be

configured as an output (via DDS0/2) which is the single wire

case when using the SCI. WOMS bit still affects general-pur pose

output on TXD and RXD pins when SCIx is not using these pins.

1 = Each pin operates in an open drain fashion if that pin is

declared as an output.

RSRC — Receiver Source

When LOOPS = 1, the RSRC bit determines the internal feedback

path for the rec eiver.

0 = Receiver input is connected to the transmitter internally (not

TXD pin)

1 = Receiver input is connected to the TXD pin

Bit 765432 1Bit 0

LOOPS WOMS RSRC M WAKE ILT PE PT

RESET: 0 0 0 0 0 0 0 0

SC0CR1/SC1CR1 — SCI Control Register 1 $00C2/$00CA

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Multiple Serial Interface

Serial Communication Interface (SCI)

MC68HC912DG128 — Rev 3.0 Technic al Data

Multiple Serial Interface

M — Mode (select character for mat)

0 = One start, ei ght data, one stop bit

1 = One start, eight data, ninth data, one stop bit

WAKE — Wake-up by Address Mark/Idle

0 = Wake up by I DLE line recognition

1 = Wake up by address mark (last da ta bit set)

ILT — Idle Line Type

Determine s which of two types of idle line detection will be used by

the SCI receiver.

0 = Short idle l in e mo de is en abl e d.

1 = Long i dle line mode is det ec ted.

In the short mode, the SCI circuitry begins counting ones in the search

for the idle line condition immediately after the start bit. This means

that the st op b it and an y bits th at were ones be fore the stop bit cou ld

be counte d in tha t string of on es, result ing in ea rlier re cogniti on of an

idle line.

In the long mode, the SCI circuitry does not begin counting ones in the

search for the idle line condition until a st op bit is received. Therefore,

the last byte’s stop bit and preceding “1” bits do not a ffect how quickly

an idle line condition can be d etecte d.

PE — Parity Enable

0 = Parit y is disabled.

1 = Parit y is enabled.

Table 14-2. Loop Mode Functions

LOOPS RSRC DDSI(3) WOMS Function of Port S Bit 1 /3

0 x x x Normal Operations

1 0 0 0/1 LOOP mode without TXD output(TXD = High Impedance)

1 0 1 1 LOOP mode with TXD output (CMOS)

1 0 1 1 LOOP mode with TXD output (open-drain)

11 0 x

Single wire mode without TXD output

(the pin is used as receiver input only, TXD = High Impedance)

11 1 0

Single wire mode with TXD output

(the output is also fed back to receiver input, CMOS)

1 1 1 1 Single wire mode for the receiving and transmitting(open-drain)

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Multiple Serial Interface

PT — Parity Type

If parity i s enabled , this bit det ermin es even or odd p arity for bo th the

receiver and the transmitter.

0 = Even parity is selected. An even number of ones in the data

character causes the parity bit to be zero and an odd number

of ones causes the parity bit to be one.

1 = Odd parity is selected. An odd number of ones in the data

characte r causes the parity bit to be zero and a n even numb er

of ones causes the parity bit to be one.

Read or wr ite anytime.

TIE — Transmit Interrupt Ena ble

0 = TDRE interrupts disabled

1 = SCI interrupt will be requested whenever the TDRE status flag

is set.

TCIE — Transmit Complete Interrupt Enable

0 = TC interrupts disabled

1 = SCI interrupt will be requested whenever the TC status flag is

set.

RIE — Receiver Interrupt Enable

0 = RDRF and OR interrupts disabled, RAF interrupt in WAIT mode

disabled

1 = SCI interrupt will be requested wh enever the RDRF or OR

status flag is set, or when RAF is set while in WAIT mode with

VDDP LL hi gh .

ILIE — Idle Line Interrupt Enable

0 = IDLE interrupts disable d

1 = SCI interrupt will be requested whenever the IDLE s tatus f lag

is set.

Bit 7654321Bit 0

TIE TCIE RIE ILIE TE RE RWU SBK

RESET: 00000000

SC0CR2/SC1CR2 — SCI Control Register 2 $00C3/$00CB

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Serial Communication Interface (SCI)

MC68HC912DG128 — Rev 3.0 Technic al Data

Multiple Serial Interface

TE — Transmitter Enable

0 = Transmitter disabled

1 = SCI transmit logic is enabled and the TXD pin (Port S bit 1/bit

3) is dedicated to the transmitter. The TE bit can be used to

queu e an id l e pre am b le.

RE — Receiver Enable

0 = Receiver disabled

1 = Enables the SCI r eceive ci rcuit ry.

RWU — Receiver Wake-Up Control

0 = Normal SCI Receiver

1 = Enables the wake-up function and inhibits further receiver

interrupts. Norma lly hardware wakes the receiver by

automatically clearing this bit.

SBK — Sen d Break

0 = Break generator off

1 = Generate a break code (at least 10 or 11 c ontig uous zeros).

As long as SBK remains set the transmitter will send zeros. When

SBK is changed to zero, the current frame of all zeros is finished

before the TxD line goes to the idle state. If SBK is toggled on and off,

the transmitter will send only 10 (or 11) zeros and then revert to mark

idle or sending data.

The bi ts in these register s are set by variou s conditions in the SCI

hardware and are automatically cleared by special acknowledge

sequence s. Th e receive rela ted flag bits in SCxSR1 (RDRF, IDLE, OR,

NF, FE, and PF) are all cleared by a read of the SCxSR1 register

followed by a read of the transmit/rec eive data register low byte .

However, only those bits which were set when SCxSR1 was read will be

Bit 7654321Bit 0

TDRE TC RDRF IDLE OR NF FE PF

RESET: 11000000

SC0SR1/SC1SR1 — SCI Sta tus Regis ter 1 $00C4/$00CC

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Multiple Serial Interface

Technical Data MC68HC912DG128 — Rev 3.0

Multiple Serial Interface

cleared b y the subsequent rea d of the tran smit/receive dat a register low

byte. The transmit related bits in SCxSR1 (TDRE and TC) are cleared by

a read of the SCxSR1 register followed by a write to the transmit/receive

data registerl low byte.

Read anytime (used in auto clearing mechanism). Write has no meaning

or effect.

TDRE — Transmit Data Register Empty Flag

New data will not be transmitted unless SCxSR1 is read before writing

to the transmit data register. Reset sets this bit.

0 = SCxDR busy

1 = Any byte in the tran smit data register is t ransferred to t he serial

shift register so new data may now be written to the transmit

data register.

TC — Transmit Comp lete Flag

Flag is set when the transmitter is idle (no data, preamble, or break

transmission in progress). Clear by reading SCxSR1 with TC set and

then writing to SCxDR.

0 = Transmitter busy

1 = Transmitter is idle

RDRF — Receive Data Register Full Flag

Once cleared, IDLE is not set again until the RxD line has been active

and becomes idle again. RDRF is set if a received character is ready

to be read from SCxDR. Clear the RDRF flag by reading SCxSR1 with

RDRF set and then read ing SCxDR.

0 = SCxDR empty

1 = SCxDR full

IDLE — Idle Line Detected Flag

Receiver idle line is detected (the receipt of a minimum of 10/11

consecutive ones). This bit will not be set by the idle line condition

when the RWU bit is set. Once cleared, IDLE will not be set again until

after RDRF has been set (after the line has been active and becomes

idle again).

0 = RxD line is idle

1 = RxD line is active

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Multiple Serial Interface

Serial Communication Interface (SCI)

MC68HC912DG128 — Rev 3.0 Technic al Data

Multiple Serial Interface

OR — Overrun Error Fla g

New byte is ready to be transferred from the receive shift register to

the receive data register and the receive data register is already full

(RDRF bit is set). Data transfer is inhibited until this bit is cleared.

0 = No overrun

1 = Overrun detected

NF — Noise Error Flag

Set during the same cycle as the RDRF bit but not set in the case of

an overrun (OR).

0 = Unanimous decisi on

1 = Noise on a valid sta rt bit, an y of the da ta bits, or on th e stop bit

FE — Framing Error Flag

Set when a zero is detected where a stop bit was expected. Clear the

FE flag by reading SCxSR1 with FE set and then reading SCxDR.

0 = Stop bit detected

1 = Zero detected rather than a stop bit

PF — Parity Error Flag

Indicates if received data’s parity matches parity bit. This feature is

active only when parity is enabled. The type of parity tested for is

determined by the PT (parity type) bit in SCxCR1.

0 = Parity correct

1 = Incorrect parity detected

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Technical Data MC68HC912DG128 — Rev 3.0

Multiple Serial Interface

Read anytime. Write has no meaning or effect.

RAF — Receiver Active Flag

This bit is controlled by the receiver front end. It is set during the RT1

time period of the start bit search. It is cleared when an idle state is

detected or when the receiver circuitry detects a false start bit

(gene ra l ly due to noi se or ba ud rate mismatch).

0 = A character is n ot being received

1 = A character is being received

If enabled with RIE = 1, RAF set generates an interrupt when

VDDPLL is hig h wh ile in WAIT mode.

Bit 7654321Bit 0

0I000000RAF

RESET: 0 0 000000

SC0SR2/SC1SR2 — SCI Status Register 2 $00C5/$00CD

Bit 7654321Bit 0

R8T8000000

RESET: ————————

SC0DRH/SC1DRH — SCI Data Register High $00C6/$00CE

Bit 7654 321Bit 0

R7/T7 R6/T6 R5/T5 R4/T4 R3/T3 R2/T2 R1/T1 R0/T0

RESET: ————————

SC0DRL/SC1DRL — SCI Data Register Low $00C7/$00CF

Bit 7654321Bit 0

R8T8000000

RESET: ————————

SC0DRH/SC1DRH — SCI Data Register High $00C6/$00CE

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Multiple Serial Interface

Serial Communication Interface (SCI)

MC68HC912DG128 — Rev 3.0 Technic al Data

Multiple Serial Interface

R8 — Receive Bit 8

Read anytime. Write has no meaning or affect.

This bit is the ninth serial data bit received when the SCI system is

configured for nine-data-bit operation.

T8 — Transmit Bit 8

Read or wr ite anytime.

This bit is the ninth serial data bit transmitted when the SCI system is

configured for nine-data-bit operation. When using 9-bit data format

this bit does not have to be written for each data word. The same

value will be transmitted as the ninth bit until this bit is rewritten.

R7/T7–R0/T0 — Receive/Transmit Data Bits 7 to 0

Reads access the eight bits of the read-only SCI receive data register

(RDR). Writes access the eight bits of the write-only SCI transmit data

SCI. If the SCI is being used with a 7- or 8-bit data word, only SCxDRL

needs to be accessed. If a 9-bit format is used, the upper register

should be writte n first to ensure that it is transferred to the transmitter

shift registe r with the lower registe r.

Bit 7654321Bit 0

R7/T7 R6/T6 R5/T5 R4/T4 R3/T3 R2/T2 R1/T1 R0/T0

RESET: ————————

SC0DRL/SC1DRL — SCI Data Register Low $00C7/$00CF

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Technical Data MC68HC912DG128 — Rev 3.0

Multiple Serial Interface

14.5 Serial Peripheral Interface (SPI)

The ser i al perip heral interface allows the MC68HC912DG128 to

communicate synchronously wi th peri pheral devices and other

microprocessors. The SPI system in the MC68HC912DG128 can

operate as a master or as a slave. The SPI is also capable of

interprocessor communications in a multiple master system.

When the SPI is enabled, all pins that are defined by the configuration

as inputs will be inputs regardless of the state of the DDRS bits for those

pins. All pins that are defined as SPI outputs will be outputs only if the

DDRS bits for those pins are set. Any SPI output whose corresponding

DDRS bit is cleared can be used as a general-purpose input.

A bidirecti on al se rial pin is possible using the DDRS as the direction

control.

14.5.1 SPI Baud Rate Generation

The E Clock is input to a divider series and the resulting SPI clock rate

may be selected to be E divided b y 2, 4, 8, 16, 32, 64, 128 or 256. Three

bits in the SP0BR register control the SPI clock rate. This baud rate

generator is activated only when SPI is in the master mode and serial

transfe r is taking place. Oth erwise this divi der is disabled to save power.

14.5.2 SPI Operation

In the S PI system the 8 -bit data re gister in the mast er and the 8-bit data

a data transfer operation is performed, this 16-bit register is serially

shifted eigh t bit p osi tions by the SC K cl ock f ro m t he ma ster so the dat a

is effectively exchanged between the master and the slave. Data written

to the SP0DR register of the master becomes the output data for the

slave and data read from the SP0DR register of the master after a

transfer operation is the input data from the slave.

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Multiple Serial Interface

Serial Peripheral Interface (SPI)

MC68HC912DG128 — Rev 3.0 Technic al Data

Multiple Serial Interface

Figure 14-3. Serial Peripheral Interface Block Diagram

A clock phase co ntrol bit (CPH A) and a clock p olarity control b it (CPOL )

in the SP0CR1 register select one of four possible clock formats to be

used by the SPI system. The CPOL bit simply selects non-inverte d or

inverted clock. The CPHA bit is used to accommodate two

fundamentally different protocols by shifting the clock by one half cycle

or no phase shift.

CONTROL

LOGIC

8-BIT SHIFT REGISTER

READ DATA BUFFER

SHIFT CONTROL LOGIC

CLOCK

LOGIC

SPI CONTR OL

SP0SR SPI STATUS REGISTER

SP0DR SPI DATA REGISTER

SPIF

WCOL

MODF

DIVIDER

SELECT

SP0BR SPI BAUD RATE REGISTER

÷2÷4÷8÷16 ÷32 ÷64 ÷128 ÷256

SPI

INTERRUPT

INTERNAL BUS

MCU P CLOCK

(SAME AS E RATE) S

SPR2

SPR1

SPR0

REQUEST

SPIE

SPE

MSTR

CPOL

CPHA

LSBF

PUPS

RDS

SWOM

SPC0

SSOE

SPE

CLOCK

MSTR

SWOM

MISO

PS4

SCK

PS6

PS7

MOSI

PS5

SP0CR1 SPI CONTROL REGISTER 1 SP0CR2 SPI CONTROL REGISTER 2

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Technical Data MC68HC912DG128 — Rev 3.0

Multiple Serial Interface

Figure 14-4. SPI Clock Format 0 (CPHA = 0)

Begin End

SCK (CPOL=0)

SAMPL E I

CHANGE O

SEL SS (O)

Transfer

SCK (CPOL=1)

MSB first (LSBF=0):

LSB first (LSBF=1): MSB

LSB LSB

MSB

Bit 5

Bit 2

Bit 6

Bit 1 Bit 4

Bit 3 Bit 3

Bit 4 Bit 2

Bit 5 Bit 1

Bit 6

CHANGE O

SEL SS (I)

(MOSI pin)

(MISO pin)

(Master only)

(MOSI/MISO)

If next transfer begins here

for tT, tl, tL

Minimum 1/2 SCK

tItL

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Serial Peripheral Interface (SPI)

MC68HC912DG128 — Rev 3.0 Technic al Data

Multiple Serial Interface

Figure 14-5. SPI Clock Format 1 (CPHA = 1)

14.5.3 SS Output

Available in master mode only, SS output is enabled with the SSOE bit

in the SP0CR1 register if the corresponding DDRS is set. The SS output

pin will be connected to the SS input pin of the external slave device. The

SS output automatically goes low for each transmission to select the

external device and it goes high during each idling state to deselect

external devices.

tLtT

for tT, tl, tL

Minimum 1/2 SCK

tItL

If next transfer begins here

Begin End

SCK (CPOL=0)

SAMPL E I

CHANGE O

SEL SS (O)

Transfer

SCK (CPOL=1)

MSB first (LSBF=0):

LSB first (LSBF=1): MSB

LSB LSB

MSB

Bit 5

Bit 2

Bit 6

Bit 1 Bit 4

Bit 3 Bit 3

Bit 4 Bit 2

Bit 5 Bit 1

Bit 6

CHANGE O

SEL SS (I)

(MOSI pin)

(MISO pin)

(Master only)

(MOSI/MISO)

Table 14-3. SS Output Selection

DDS7 SSOE Master Mode Slave Mode

00SS

Input with MODF Feature SS Input

01 Reserved SS

Input

1 0 General-Purpose Output SS Input

11 SS

Output SS Input

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Technical Data MC68HC912DG128 — Rev 3.0

Multiple Serial Interface

14.5.4 Bidirectional Mode (MOMI or SISO)

In bidir ectional mode , the SPI uses only on e ser ial dat a pi n fo r external

device interface. The MSTR bit decides which pin to be used. The MOSI

pin becomes serial data I/O (MOMI) pin for the master mode, and the

MISO pin becomes serial data I/O (SISO) pin for the slave mode. The

direction of each serial I/O pin depends on the corresponding DDRS bit.

When SPE=1 Master Mode

MSTR=1 Slave Mod e

MSTR=0

Normal

Mode

SPC0=0

SWOM enables open drain output. SWOM enables open drain output.

Bidirectional

Mode

SPC0=1

SWOM enables open drain output. PS4 becomes GPIO. SWOM enables open drain output. PS5 becomes GPIO.

Figure 14-6. Normal Mode and Bidirectional Mode

SPI

DDRS5

Serial Out

Serial In

SPI

DDS5

Serial Out

Serial In

SPI

Serial In

Serial Out

DDRS4

SPI

Serial In

Serial Out

DDS4

SPI

MOMI

PS4

DDRS5

Serial Out

Serial In

SPI

MOMI

PS4

DDS5

Serial Out

Serial In

SPI

PS5

SISO

DDRS4

Serial In

Serial Out

SPI

PS5

SISO

DDS4

Serial In

Serial Out

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Serial Peripheral Interface (SPI)

MC68HC912DG128 — Rev 3.0 Technic al Data

Multiple Serial Interface

14.5.5 Register Descriptions

Control and data registers for the SPI subsystem are described below.

The memory address indicated for each register is the default address

that is in use after reset. For more information refer to Operat ing Modes.

Read or wr ite anytime.

SPIE — SPI Interrupt Enable

0 = SPI interrupts are in hibited

1 = Hardware interrupt sequence is requested each time the SPIF

or MODF status flag is set

SPE — SPI System Enable

0 = SPI internal hardware is initialized and SPI system is in a low-

power disabled st ate.

1 = PS[4:7] are dedicated to the SPI function

When MODF is set, SPE always reads zero. SP0CR1 must be written

as part of a mode fault recovery sequence.

SWOM — Port S Wired-OR Mode

Controls not only SPI output pins but also the general-purpose output

pins (PS[4:7]) whic h are not used by SPI.

0 = SPI and/or PS[4:7] output buffers operate normally

1 = SPI and/or PS[4:7] output buffers behave as open-drain

outputs

MSTR — SPI Master/Slave Mode Select

0 = Sla ve mode

1 = Master mod e

When MODF is set, MSTR always reads zero. SP0CR1 must be

written as part of a mo de fault recovery sequence.

Bit 7654321Bit 0

SPIE SPE SWOM MSTR CPOL CPHA SSOE LSBF

RESET: 00000100

SP0CR1 — SPI Control Register 1 $00D0

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Technical Data MC68HC912DG128 — Rev 3.0

Multiple Serial Interface

CPOL, CPHA — SPI Clock Polarity, Clock Phase

These tw o bits a re us ed to specify the clock format to be used in SPI

operations. When the clock polarity bit is cleared and data is not being

transferred, the SCK pin of the master device is low. When CPOL is

set, SCK idles high. See Figur e 14- 4 and Figure 14-5.

SSOE — Slave Select Output Enable

The SS output feature is enabled only in the master mode by

asserting the SSOE and DDS7.

LSBF — SPI LSB First enable

0 = Data is transferred most significant bit first

1 = Data is transferred least significant bit first

Normall y data is tran sferred most sign ificant bit first.This bit do es not

affect the position of the MSB and LSB in the data register. Reads and

writes of the data register will always have MSB in bit 7.

Read or wr ite anytime.

PUPS — Pull-Up Port S Enable

0 = No internal pull-ups on port S

1 = All port S input pins have an active pull-up device. If a pin is

programmed as output, the pull-up device becomes inactive

RDPS — Redu ce Drive of Port S

0 = Port S output drivers operate normally

1 = All port S output pins have reduced driv e capability for lower

power and less noise

SPSWAI — Serial Interface Stop in WAIT mode

0 = Serial interface clock operates normally

1 = Halt serial interface clock generation in WAIT mode

SP0CR2 — SPI Control Register 2 $00D1

Bit 7654321Bit 0

0 0 0 0 PUPS RDPS SPSWAI SPC0

RESET: 0 0001000

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Serial Peripheral Interface (SPI)

MC68HC912DG128 — Rev 3.0 Technic al Data

Multiple Serial Interface

SPC0 — Serial Pin Control 0

This bit decides serial pin configurations with MSTR control bit.

Read anytime. Write anytime.

At reset, E Clock divided by 2 is selected.

SPR[2:0] — SPI Clock (SCK) Rate Select Bits

These bits are used to specify the SPI clock rate.

Pin Mode SPC0(1) MSTR MISO(2) MOSI(3) SCK(4) SS(5)

#1 Normal 0 0 Slave Out Slave In SCK In SS In

#2 1 Master In Master Out SCK Out SS I/O

#3 Bidirectional 1 0 Slave I/O GPI/O SCK In SS In

#4 1 GPI/O Master I/O SCK Out SS I/O

1. The serial pin control 0 bi t enables bidirectional configurations.

2. Slave output is enabled if DDS4 = 1, SS = 0 and MSTR = 0. (#1, #3)

3. Master output is enabled if DDS5 = 1 and MSTR = 1. (#2, #4)

4. SCK output is enabled if DDS6 = 1 and MSTR = 1. (#2, #4)

5. SS output is enabled if DDS7 = 1, SSOE = 1 and MSTR = 1. (#2, #4)

Bit 765432 1Bit 0

0 0 0 0 0 SPR2 SPR1 SPR0

RESET: 0 0 0 0 0 0 0 0

SP0BR — SPI Baud Rate Register $00D2

Table 14-4. SPI Clock Rate Selection

SPR2 SPR1 SPR0 E Clock

Divisor Frequency at

E Clo ck = 4 MHz Frequency at

E Clock = 8 MHz

0 0 0 2 2.0 MHz 4.0 MHz

0 0 1 4 1.0 MHz 2.0 MHz

0 1 0 8 500 kHz 1.0 MHz

0 1 1 16 250 kHz 500 KHz

1 0 0 32 125 kHz 250 KHz

1 0 1 64 62.5 kHz 125 KHz

1 1 0 128 31.3 kHz 62.5 KHz

1 1 1 256 15.6 kHz 31.3 KHz

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Technical Data MC68HC912DG128 — Rev 3.0

Multiple Serial Interface

Read anytime. Write has no meaning or effect.

SPIF — SPI Interrupt Request

SPIF is set after the eighth SCK cycle in a data transfer and it is

cleared by readi ng the SP 0SR regist er (with SP IF set) fol lowed by an

acce ss (read or w rite) to the SPI data register.

WCOL — Write Collision Status Fla g

The MCU write is disabled to avoid writing over the data being

transferred. No interrupt is generated be cause t he error status flag

can be read upon completion of the transfer that was in progress at

the time of the error. Automatically cleared by a read of the SP0SR

(with W COL set) fol lowed by an a ccess (rea d or wr ite) to the S P0DR

0 = No write collision

1 = In dicate s th at a serial tra nsfe r was in pr og r ess wh en th e MC U

tried to write new data into the SP0DR data register.

MODF — SPI Mode Error Interrupt Status Flag

This bit is set automatically by SPI hardware if the MSTR control bit is

set and th e slave select input pin be comes zero. Th is condition is not

permitted in normal operation. In the case where DDRS bit 7 is set,

the PS7 pin is a genera l-purpose o utput pin or SS output pin rather

than being dedicated as the SS input for the SPI system. In this

special case the mode fault function is inhibited and MODF remains

cleared. This flag is automatically cleared by a read of the SP0SR

(with MODF set) followed by a write to the SP0CR1 register.

Bit 7654321Bit 0

SPIF WCOL 0 MODF 0 0 0 0

RESET: 0 0 000000

SP0SR — SPI Status Register $00D3

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Port S

MC68HC912DG128 — Rev 3.0 Technic al Data

Multiple Serial Interface

Read anytime (normally only after SPIF flag set). Write anytime (see

WCOL write collision flag).

Reset does not affect this address.

This 8-bit register is both the input and output register for SPI data.

Reads of this register are double buffered but writes cause data to be

written directly into the serial shifter. In the SPI system the 8-bit data

by the MOSI and M ISO wire s to form a distribut ed 16-b it registe r. When

a data transfer operation is performed, this 16-bit register is serially

shifted eigh t bit p osi tions by the SC K cl ock f ro m t he ma ster so the dat a

is effectively exchanged between the master and the slave. Note that

some slave devices are very simple and either accept data from the

master without returning data to the master or pass data to the master

without requiring data from the master.

14.6 Port S

In all mode s, por t S bi ts PS[ 7:0] ca n be used f or e ither g ener al-pu rpose

I/O, or with the SCI and SPI subsystems. During reset, port S pins are

configured as high-impedance inputs (DDRS is cleared).

Read an ytime (inputs return pin level; outputs return pin driv er input

level). Write data stored in internal latch (drives pins only if configured for

output). Writ es do not change pin state when pin c onfig ured for SPI or

SCI output.

Bit 7654321Bit 0

SP0DR — SPI Data Register $00D5

PORTS — Port S Data Register $00D6

Bit 7654 321Bit 0

PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0

Function SS

CS SCK MOSI

MOMI MISO

SISO TXD1 RXD1 TXD0 RXD0

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Technical Data MC68HC912DG128 — Rev 3.0

Multiple Serial Interface

After reset all bits are configured as general-purpose inputs.

Port S sha res function with the on-ch ip serial systems (SP I and SCI0/ 1).

Read or wr ite anytime.

After reset, all general- purpose I/O are co nfigured for input only.

0 = Configure the correspon ding I/O pin for input only

1 = Configure the correspon ding I/O pin for output

DDS2, DDS0 — Data Direction for Port S Bit 2 and Bit 0

If the SCI receiver is configured for two-wire SCI operation,

corresponding port S pins will be input regardless of the state of these

bits.

DDS3, DDS1 — Data Direction for Port S Bit 3 and Bit 1

If the SCI transmitter is configured for two-wire SCI operation,

corresponding port S pins will be outpu t regardl ess of the state of

these bits.

DDS[6:4] — Data Direction for Port S Bits 6 through 4

If the SPI is enabled and expects the corresponding port S pin to be

an input, it will b e a n in put regardless of the state of the DDRS bit. If

the SPI is enabled and expects the bit to be an output, it will be an

output ONLY if the DDRS bit is set.

DDS7 — Data Direction for Port S Bit 7

In SPI slave mode, DDRS7 has no meaning or effect; the PS7 pin is

dedicated as the SS input. In SPI master mode, DDRS7 determines

whether PS7 is an error detect input to the SPI or a general-purpose

or slave sel ect out pu t line.

NOTE: If mode fault error occurs, bits 5, 6 and 7 are forced to zero. .

Bit 7654321Bit 0

DDS7 DDS6 DDS5 DDS4 DDS3 DDS2 DDS1 DDS0

RESET: 0 0 000000

DDRS — Data Direction Register for Port S $00D7

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MC68HC912DG128 — Rev 3.0 Technic al Data
Inter-IC Bus
 
Technical Data — MC68HC912DG128
Section 15. Inter-IC Bus
15.1  Contents
15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273
15.3 IIC Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274
15.4 IIC System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . .276
15.5 IIC Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .276
15.6 IIC Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . .281
15.7 IIC Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . .290
15.2  Introduction
The Inter-IC Bus (IIC or I2C) is a two-wire, bidirectional serial bus that 
provi des  a si mpl e,  efficient metho d of  data excha ng e b etw e en  devi ce s. 
Being a two-wire device, the IIC minimizes the need for large numbers 
of connections between devices, and eliminates the need for an address 
decoder.
This bus is suita ble for  appli cations re qu ir i ng  occasion al  
communications over a short distance between a number of devices. It 
also provides flexibility, allowing additional devices to be connected to 
the bus for further expansion and system development.
The interface is designed to operate up to 100kbps with maximum bus 
loading and timing. The device is capable of operating at higher baud 
rates, up to a maximum of clock/20, with reduced bus loading. The 
maximum  communication  length an d the number  of devices that can be 
conn ected are limited by a maximum bus ca pacitance of 400pF.
    
  
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Inter-IC Bus

Technical Data MC68HC912DG128 — Rev 3.0

Inter-IC Bus

15.3 IIC Features

The IIC module has the following key features:

•Compatib le with I2C Bus standard

•Multi- maste r op er ation

•Software programmable for one of 64 different serial clock

frequencies

•Software selectable ack nowledge bit

•Inte rrupt driven byte-b y-byt e data transfer

•Arbitr ation lost interrupt with a uto matic mode switching fro m

master to slave

•Calling address identification interrupt

•Star t and stop signa l generation/detect ion

•Repeated start signal generation

•Acknowledge bit generation/detection

•Bus busy detection

•Eight-bit general purpose I/O port

A block diagram of the IIC module is shown in Figure 15-1.

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Inter-IC Bus

IIC Features

MC68HC912DG128 — Rev 3.0 Technic al Data

Inter-IC Bus

Figure 15-1. IIC Block Diagram

Input

Sync

In/Out

Data

Shift

Address

Compare

SCL SDA

INTERRUPT

ADDR & CONTROL DATA

Clock

Control

Start,

Stop &

Arbitration

Control

CTRL_REG FREQ_REG ADDR_REG STATUS_REG DATA_REG

ADDR_DECODE DATA_MUX

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Inter-IC Bus

Technical Data MC68HC912DG128 — Rev 3.0

Inter-IC Bus

15.4 IIC System Configuration

The IIC system uses a Serial Data line (SDA) and a Serial Clock Line

(SCL) for data transfer. All devices connected to it must have open drain

or open collector outputs. Logic “and” function is exercised on both lines

with external pull-up resistors, the value of these resistors is system

dependent.

15.5 IIC Protocol

Normall y, a standard comm unication is comp osed of four parts : START

signal, slave address transmission, data transfer and STOP signal. They

are described briefly in the following sections and illustrated in Figure 15-

Figure 15-2. IIC Transmission Signals

SCL

SDA

Start

Signal Ack

Bit

12345678

MSB LSB 12345678

MSB LSB

Stop

Signal

SCL

SDA

12345678

MSB LSB 12 5 678

MSB LSB

Repeated

9 9

AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W XXX D7 D6 D5 D4 D3 D2 D1 D0

Calling Address Read/ Data Byte

AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W

New Calling Address

Ack

Bit

Write

Start

Signal

Start

Signal Ack

Bit

Calling Address Read/

Write Stop

Signal

Ack

Bit

Read/

Write

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Inter-IC Bus

IIC Protocol

MC68HC912DG128 — Rev 3.0 Technic al Data

Inter-IC Bus

15.5.1 START Signal

When the bus is free, i.e. no master device is engaging the bus (both

SCL and SDA lines are at logical high), a master may initiate

commu nication b y sending a START signal . As shown in Figure 15-2, a

START si gnal is de fined a s a high-to -low tr ansition o f SDA whi le SCL is

high. This signal denotes the beginning of a new data transfer (each data

transfer may cont ain several bytes of data) and wa kes up all slaves.

15.5.2 Slave Address Tr ansmissi on

The firs t byte of d ata transf er i mmediate ly afte r the S TART sig nal is th e

slave address transmitted by the master. This is a seven-bit calling

address followed by a R/W bit. The R/W bit tells the slave the desired

directi on of dat a tra nsfe r.

1 = Read transfer, the slave transmits data to the master.

0 = Write transfer, the master transmits data to the slave.

Only the slave with a calling address that matches the one transmitted

by th e ma ster w ill r e spon d by sendi ng b ack a n ackn ow led ge bi t. Thi s i s

done by pulling the SDA low at the 9th clock (see Figure 15-2).

Slave addre ss - No two slaves in the system may have the same

address. If the IIC is master, it must not transmit an address that

is equal to its own slave address . The IIC cannot be mast er and

slave at the same time. If however arbitration is lost during an

address cycle the IIC will revert to slave mode and operate

correctly even if it is being addressed by another master.

15.5.3 Data Transfer

Once successful slave addressing is achieved, the data transfer can

proceed byte-by-byte in a directio n specified by the R/W bit sent by the

calling master.

NOTE: All transfers that come after an address cycle are referred to as data

transfers, even if they carry sub-address information for the slave

device.

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Inter-IC Bus

Technical Data MC68HC912DG128 — Rev 3.0

Inter-IC Bus

Each data byte is 8 bits long. Data may be changed only while SCL is low

and must be held stable while SCL is high as shown in Figure 15-2. There

is one clock pulse on SCL for each data bit, the MSB being transferred

first. Each data byte has to be followed by an acknowledge bit, which is

signalled from the receiving device by pulling the SDA low at the ninth

clock. So one complete data byte transfer needs nine clock pulses.

If the slave recei ver does not acknowledge the master, th e SDA line

must be left high by the slave. The master can then generate a stop

signal to abort the data transfer or a start signal (repeated start) to

commence a new calling.

If the master receiver does not acknowledge the slave transmitter after

a byte transmission, it means ’end of data’ to the slave, so the slave

releases the SDA line for the master to generate STOP or START signal.

15.5.4 STOP Signal

The master can terminate the communication by generating a STOP

signal to free the bus. However, the master may generate a START

signal f ollowed by a calling comm and withou t generatin g a STOP signal

first. Thi s i s cal led r ep ea ted START. A STOP si gn al is de fi ne d a s a low-

to-high transition of SDA while SCL at logical “1” (see Figure 15-2).

The master can generate a STOP even if the slave has generated an

acknowledge at which point the slave must release the bus.

15.5.5 Repeated START Signal

As shown in Figure 15-2, a repeated START signal is a START signal

generated without first generating a STOP signal to terminate the

communication. This is used by the master to communicate with another

slave or with the same slave in different mode (transmit/receive mode)

without releasing the bus.

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Inter-IC Bus

IIC Protocol

MC68HC912DG128 — Rev 3.0 Technic al Data

Inter-IC Bus

15.5.6 Arbitration Procedure

IIC is a true multi-master bus that allows more than one master to be

connected on it. If two or more masters try to control the bus at the same

time, a clock synchronization procedure determines the bus clock, for

which the low period is equal to the longest clock low period and the high

is equal to the shortest one among the masters. The relative priority of

the c ontending m asters is deter mined by a d ata arbitrati on procedu re, a

bus master loses arbitration if it transmits logic “1” while ano ther ma ster

transmits logic “0”. The losi ng masters immed iately switch ov er to slave

receive mode and stop driving SDA output. In this case the transition

from master to slave mode does not generate a STOP condition.

Meanwhile, a sta tus bit is set by hardware to indicat e loss of arbitration.

15.5.7 Clock Synchronization

Since wire-AND logic is performed on SCL line, a high-to-low transition

on SCL line affects all the devices connected on the bus. The devices

start counting their low period and once a device’s clock has gone low, it

holds the SCL line low until the clock high state is reached. However, the

change of low to high in this device clock may not change the state of the

SCL line if another device clock is still within its low period. Therefore,

synchronized clock SCL is held low by the device with the longest low

period. Devices with shorter low periods enter a high wait state during this

time (see Figure 15-3). When all devices concerned have counted off

their low period, the synchronized clock SCL line is released and pulled

high. There is then no difference between the device clocks and the state

of the SCL line and all the devices start counting their high periods. The

first device to complete its high period pulls the SCL line low again.

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Inter-IC Bus

Technical Data MC68HC912DG128 — Rev 3.0

Inter-IC Bus

Figure 15-3. IIC Clock Synchronization

15.5.8 Handshaking

The clock synchronization mechanism can be used as a handshake in

data t r ansfer. Sla ve devices ma y hold the SCL low after completion of

one byte transf er (9 bit s). In su ch case, it h alts t he bus clo ck and fo rces

the master clock into wait states until the slave releases the SCL line.

15.5.9 Clock Stretching

The clock synchronization mechanism can be used by slaves to slow

down the bit rate of a transfer. After the master has driven SCL low the

slave can drive SCL low for the required period and then release it. If the

slave SCL low period is greater than the master SCL low period then the

resulti ng SC L bus sig na l low per iod is str etch ed.

SCL1

SCL2

SCL

Internal Counter Reset

WAIT Start Counting High Period

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Inter-IC Bus

IIC Register Descripti ons

MC68HC912DG128 — Rev 3.0 Technic al Data

Inter-IC Bus

15.6 IIC Register Descr iptions

Read and write anytime

This register con tains the address the IIC will resp ond to when

addresse d as a sl ave; note t hat it is not the ad dress sent on the bus

during the addr ess tr ansf er

ADR7–ADR1 — Slave Address

Bit 1 to bit 7 contain the specific slave address to be used by the IIC

module.

The default mode of IIC is slave mode for an address match on the

bus.

Read and write anytime

IBC5–IBC0 — IIC Bus Clock Rate 5–0

This field is used to prescale the clock for bit rate selection. The bit

clock generator is implemented as a prescaled shift register - IBC5-3

select the prescaler divider and IBC2-0 select the shift register tap

point. The IBC b its are de coded to give the Tap and P rescale va lues

as shown in Table 15-1.

IBAD — IIC Bus Address Register $00E0

Bit 7654 321Bit 0

ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 0

RESET: 0 0 0 0 0 0 0 0

IBFD — IIC Bus Frequency Divider Register $00E1

Bit 7654321Bit 0

00IBC5 IBC4 IBC3 IBC2 IBC1 IBC0

RESET: 0 0000000

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Inter-IC Bus

Technical Data MC68HC912DG128 — Rev 3.0

Inter-IC Bus

The number of clocks from the falling edge of SCL to the first tap

(Tap[1]) is defined by the values shown in the scl2tap column of Table

15-1, all subseq uent t ap po ints a re se para ted by 2IBC5-3 as shown in

the tap2ta p column in Table 15-1. The SCL Tap is used to gener ated

the SCL p eriod and the SDA Tap i s used to determine th e delay from

the falling edge of SCL to SDA changing, the SDA hold time.

The serial bit clock frequency is equal to the CPU clock frequency

divided by the divider shown in Tabl e 15-2. The equation used to

generate the divider values from the IBFD bits is:

SCL Divider = 2 x ( scl2tap + [ ( SCL_Tap -1 ) x tap2tap ] + 2 )

The SDA hold delay is equal to the CPU clock period multiplied by the

SDA Hold value shown in Figure 15-2. The equation used to generate

the SDA Hold value from the IBFD bits is:

SDA Hold = scl2tap + [ ( SDA_Tap - 1 ) x tap2tap ] + 3

Table 15-1. IIC Tap and Prescale Values

IBC2-0

(bin) SCL Tap

(clocks) SDA Tap

(clocks) IBC5-3

(bin) scl2tap

(clocks) tap2tap

(clocks)

000 5 1 000 4 1

001 6 1 001 4 2

010 7 2 010 6 4

011 8 2 011 6 8

100 9 3 100 14 16

101 10 3 101 30 32

110 12 4 110 62 64

111 15 4 111 126 128

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Inter-IC Bus

IIC Register Descripti ons

MC68HC912DG128 — Rev 3.0 Technic al Data

Inter-IC Bus

Ta ble 15-2. IIC Divider and SDA Hold values

IBC5-0

(hex) SCL Divider

(clocks) SDA Hold

(clocks) IBC5-0

(hex) SCL Divider

(clocks) SDA Hold

(clocks)

00 20 7 20 160 17

01 22 7 21 192 17

02 24 8 22 224 33

03 26 8 23 256 33

04 28 9 24 288 49

05 30 9 25 320 49

06 34 10 26 384 65

07 40 10 27 480 65

08 28 7 28 320 33

09 32 7 29 384 33

0A 36 9 2A 448 65

0B 40 9 2B 512 65

0C 44 11 2C 576 97

0D 48 11 2D 640 97

0E 56 13 2E 768 129

0F 68 13 2F 960 129

10 48 9 30 640 65

11 56 9 31 768 65

12 64 13 32 896 129

13 72 13 33 1024 129

14 80 17 34 1152 193

15 88 17 35 1280 193

16 104 21 36 1536 257

17 128 21 37 1920 257

18 80 9 38 1280 129

19 96 9 39 1536 129

1A 112 17 3A 1792 257

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Inter-IC Bus

Technical Data MC68HC912DG128 — Rev 3.0

Inter-IC Bus

Read and write anytime

IBEN — IIC Bus Enable

This bit controls the software reset of the entire IIC module.

0 = The module is reset and disabled. This is the power-on reset

situation. When low the IIC system is held in reset but registers

can still be accessed.

1 = The IIC system is enabled. This bit must be set before any other

IBCR bits have any effect.

If the IIC module is enabled in the middle of a byte transfer the

interface behaves as follows: slave mode ignores the current transfer

on the bus and starts operating whenever a subsequent start

condition is detected. Master mode will not be aware that the bus is

busy, hence if a start cycle is initiat ed then the current bus cycle may

become corrup t. This would ultim atel y resul t in either the curr ent bus

master or the IIC mod ule lo sing arbitr ation, afte r which bus operati on

would return to normal.

IBIE — IIC Bus Interrupt Enable

0 = Interrupts from the IIC module are disabled. Note that this does

not clear any currentl y pendin g interr upt condition.

1 = Interrupts from the IIC module are enabled. An IIC interrupt

occurs provided the IBIF bit in the status register is also set.

1B 128 17 3B 2048 257

1C 144 25 3C 2304 385

1D 160 25 3D 2560 385

1E 192 33 3E 3072 513

1F 240 33 3F 3840 513

Ta ble 15-2. IIC Divider and SDA Hold values

IBC5-0

(hex) SCL Divider

(clocks) SDA Hold

(clocks) IBC5-0

(hex) SCL Divider

(clocks) SDA Hold

(clocks)

IBCR — IIC Bus Control Register $00E2

Bit 7654321Bit 0

IBEN IBIE MS/SL Tx/Rx TXAK RSTA 0 IBSWAI

RESET: 00000000

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Inter-IC Bus

IIC Register Descripti ons

MC68HC912DG128 — Rev 3.0 Technic al Data

Inter-IC Bus

MS/SL — Master/Slave mode select bit

Upon re set, this b it is clea red. Wh en this b it is chang ed from 0 to 1, a

START signal is generated on the bus, and the master mode is

selec ted. When this bit is changed fro m 1 to 0, a STOP s i gnal is

generated and the operation mode changes from master to slave.

MS/SL is cleared witho ut generating a STOP signal w hen the master

loses arbitration.

0 = Sla ve Mode

1 = Master Mod e

Tx/Rx — Transmit/R ec ei ve mode sel ect bit

This bit selects the direction of master and slave transfers. When

addressed as a slave this bit should be set by software according to

the SRW bit in the status register. In master mode this bit should be

set accordin g to the ty pe of tran sfer re qu ire d. The re for e , for addr e ss

cycles, this bit will always be high.

0 = Receive

1 = Transmit

TXAK — Transmit A cknowledge enable

This bit spec ifies the value driven onto SDA during acknowledge

cycles for both master and slave receivers. Note that values written to

this bit are only used when the IIC is a receiver, not a transmitter.

0 = An acknowledge signal will be sent out to the bus at the 9th

clock bit after receiving one byte data

1 = No acknowledge signal response is sent (i.e., acknowledge bit

= 1)

RSTA — Repe at Start

Writing a 1 to this bit will generate a repeated START condition on the

bus, provid ed it is the current bus master. This bi t will always be read

as a low. Attempting a repeated start at the wr ong time, if th e bus is

owne d by another master , will result in los s of arbitr ation.

1 = Generate repeat start cycle

IBSWAI — IIC Stop in WAIT mode

0 = IIC module operates normally

1 = Halt clock generation of IIC module in WAIT mode

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Inter-IC Bus

Technical Data MC68HC912DG128 — Rev 3.0

Inter-IC Bus

This status register is read-o nly with exception of b it 1 (IBIF) and bit 4

(IBAL ) , whic h are so ftware clearable

TCF — Data transferring bit

While one byte of data is bei ng transfer red, th is bit i s cleared. It is set

by th e falling edge of the 9th clock of a byte transfe r .

0 = Transfer in progres s

1 = Transfer complete

IAAS — Addr esse d as a slav e bit

When its own specific address (IIC Bus Address Register) is matched

with the calling address, this bit is set. The CPU is interrupted

provided the IBIE is set. Then the CPU needs to check the SRW bit

and set its Tx/Rx mode accordingly. Writing to the IIC Bus Control

0 = Not addressed

1 = Ad dressed as a slave

IBB — IIC Bus busy bit

This bit indicates the status of the bus. When a START signal is

detected, the IBB is set. If a STOP signal is detected, it is cleared.

0 = Bus is idle

1 = Bus is busy

IBAL — Arbitration Lost

The arbitration lost bit (IBAL) is set by hardware when the arbitration

procedure is lost. Arbitratio n is lost in the following circu mstances:

1. SDA sampled as low when the master drives a high during an

address or data transmit cycle.

2. SDA sampled as a low when the master drives a high during the

acknowledge bit of a data receive cycle.

3. A start cycle is attempted when the bus is busy.

4. A repeated start cycle is requested in slave mode.

IBSR — IIC Bus Status Register $00E3

Bit 76 5 4 3 2 1Bit 0

TCF IAAS IBB IBAL 0 SRW IBIF RXAK

RESET: 1 0 0 0 0 0 0 0

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Inter-IC Bus

IIC Register Descripti ons

MC68HC912DG128 — Rev 3.0 Technic al Data

Inter-IC Bus

5. A stop condition is detected when the master did not request it.

This bit must be cleared by software, by writing a one to it.

SRW — Slave Read/Write

When IAA S is set this bit indicat es the value of the R/W comma nd bit

of the call ing address sent from the mas ter.

CAUTION: This bit is only val id wh en the IIC is in slave mode, a com p le te ad dr ess

transfer has occurred with an address match and no other transfers have

been initiated.

Checking this bit, the CPU can select slave transmit/receive mode

according to the command of the ma ster.

0 = Sla ve receive, master writing to slave

1 = Slave transmit, master reading from slave

IBIF — IIC Bus Interrupt Flag

The IBIF bit is set when an interrupt is pending, which will cause a

processor interrupt request provided IBIE is set. IBIF is set when one

of the following events occurs:

1. Complete one byte tran sfer (se t at the falling edge of the 9th

clock).

2. Receive a calling address that matches its own specific address in

slave receive mode.

3. Arbitration lost.

This bit must be cleared by software, writing a one to it, in the interrupt

routine.

RXAK — Received Acknowledge

The value of SDA during the acknowledge bit of a bus cycle. If the

received acknowledge bit (RXAK) is low, it indicates an acknowledge

signal has been received after the completion of 8 bits data

transmission on the bus. If RXAK is high, it means no acknowledge

signal is detected at the 9th clock.

0 = Acknowledge received

1 = No acknowledge received

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Inter-IC Bus

Technical Data MC68HC912DG128 — Rev 3.0

Inter-IC Bus

Read and write anytime

In master transmit mode, when data is written to the IBDR a data transfer

is initi ated. The most si gnific ant bit is se nt first. In mast er receive m ode,

reading this register initiates next byte data receiving. In slave mode, the

same functions are available after an address match has occurred.

NOTE: In master transmit mode, the first byte of data writ ten to IBDR following

assertion of MS/SL is used for the address transfer and should comprise

of the calling address (in position D7-D1) concatenated with the required

R/W bit ( i n positi on D0).

Read and write anytime

RDPIB — Reduced Drive of Port IB

0 = All port IB output pins have full drive enabled.

1 = All port IB output pins have reduced drive capability.

PUPIB — Pull-Up Port IB Enable

0 = Port IB pull-ups are disabled.

1 = Enable pull-up devices for port IB input pins [7:4]. Pull-ups for

port IB input pins [3:0] ar e always enabled.

IBDR — IIC Bus Data I/O Register $00E4

Bit 7654321Bit 0

D7 D6 D5 D4 D3 D2 D1 D0 High

RESET: 0 0000000

IBPURD — Pull-Up and Reduced Drive for Port IB $00E5

Bit 7654321Bit 0

000RDPIB000PUPIB

RESET: 0 0 000000

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Inter-IC Bus

IIC Register Descripti ons

MC68HC912DG128 — Rev 3.0 Technic al Data

Inter-IC Bus

Read and write anytime.

IIC functions SCL and SDA share port IB pins 7 and 6 and take

precedence over the general-purpose port when IIC is enabled. The

SCL a nd SDA ou tput buffers behave as open-dra in outp uts.

When port is configured as input, a read will return the pin level. Port bits

3-0 have internal pull ups when configured as inputs so they will read ones.

When configured as output, a read will return the latched output data.

Port bits 5 through 0 will read the last value written . A write will drive

associated pins only if configured for output and IIC is not enabled.

Port bits 3-0 do not have available external pins.

Read and write anytime

DDRIB[7:4] — Port IB [7:4] Data direction

Each bit determines the primary direction for each pin config ured as

general-purp ose I/O.

0 = Associated pin is a high-impedance input.

1 = Associated pin is an output.

DDRIB[3:0] — These bits serve as mem ory locations sinc e there are no

corresponding external port pins.

PORTIB — Port Data IB Register $00E6

Bit 7654321Bit 0

PIB7 PIB6 PIB5 PIB4 PIB3 PIB2 PIB1 PIB0

IICSCLSDA------

RESET: --------

DDRIB — Data Direction for Port IB Register $00E7

Bit 7654321Bit 0

DDRIB7 DDRIB6 DDRIB5 DDRIB4 DDRIB3 DDRIB2 DDRIB1 DDRIB0

RESET: 0 0 0 00000

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Inter-IC Bus

Technical Data MC68HC912DG128 — Rev 3.0

Inter-IC Bus

15.7 IIC Programming Examples

15.7.1 Initialization Sequence

Reset will put the IIC Bus Control Register to its default status. Before

the interface can be used to transfer serial data, an initialization

procedure must be carried out, as follows:

1. Update the Frequency Divider Register (IBFD) and select the

required division ratio to obtain SCL freque ncy from system clock.

2. Update the IIC Bus Address Register (IBAD) to define its slave

address.

3. Set t he IBEN bi t of the IIC B us Co ntr ol R egi ste r (I BCR ) to enable

the IIC interface system.

4. Modify the bits of the IIC Bus Control Register (IBCR) to select

Master/Slave mo de, Transmit/Receive mode a nd interrupt enable

or not.

15.7.2 Generation of START

After completion of the initialization procedure, serial data can be

transmitted by selecting the ’master transmitter’ mode. If the device is

connected to a multi-master bus system, the state of the IIC Bus Busy

bit (IBB) must be tested to check whether the serial bus is free.

If the b us is f ree ( IBB= 0), the start co ndi tion an d the first byte ( the slave

address) can be sent. The data written to the data register comprises the

slave calling address and the LSB set to indicate the direction of transfer

required from the slave.

The bus free time (i.e., the time between a STOP condition and the

follo wing STAR T condit ion) is bui lt into th e hardwar e that gene rates the

START cycle. Depending on the relative frequencies of the system clock

and the SCL period it may be necessary to wait until the IIC is busy afte r

writing the calling address to the IBDR before p roceeding with the

following instru ctions. This is illustrated in the following example.

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Inter-IC Bus

IIC Programming Examples

MC68HC912DG128 — Rev 3.0 Technic al Data

Inter-IC Bus

An example of a program which generates the START signal and

transmits the first byte of data (slave address) is shown below:

15.7.3 Post-Transfer Software Response

Transmission or reception of a byte will set the data transferring bit (TCF)

to 1, which indicates one byte communication is finished. The IIC Bus

interrupt bit (IBIF) is set also; an interrupt will be generated if the interrupt

function is enabled duri ng initia lization by se tting the IBIE bit. Software

must clear the IBIF bit in the interrup t routine first. The TCF bit will be

cleared by reading from t he IIC Bus D ata I/O Regi ster (I BDR) in r eceive

mode or writing to IBDR in transmit mode.

Software may service the IIC I/O in the main program by monitoring the

IBIF bit if the interrupt function is disabled. Note that polling should

monitor the IBIF bit rather than the TCF bit since their operation is

different when arbitration is lost.

Note that when an interrupt occurs at the end of the address cycle the

master will always be in transmit mode, i.e. the address is transmitted. If

master receive mode is required, indicated by R/W bit in IBDR, th en the

Tx/Rx bit should be toggled at this stage.

During slave mode address cycles (IAAS=1) the SRW bit in the status

the Tx/Rx bit is programmed accordingly. For slave mode data cycles

(IAAS=0) the SRW bit is not valid, the Tx/Rx bit in the control register

shou ld be read to determine the direction of the current transfer.

CHFLAG BRSET IBSR,#$20,* ;WAIT FOR IBB FLAG TO CLEAR

TXSTART BSET IBCR,#$30 ;SET TRANSMIT AND MASTER MODE

;i.e. GENERATE START CONDITION

MOVB CALLING,IBDR ;TRANSMIT THE CALLING

;ADDRESS, D0=R/W

IBFREE BRCLR IBSR,#$20,* ;WAIT FOR IBB FLAG TO SET

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Inter-IC Bus

Technical Data MC68HC912DG128 — Rev 3.0

Inter-IC Bus

The following is an example of a software response by a ’master

transmitter’ in the interrupt routine (see Figure 15-4).

15.7.4 Generation of STOP

A data transfer ends with a STOP signal generated by the ’master’

device. A master transmitter can simply generate a STOP signal after all

the data has been transmitted. The following is an example showing how

a stop condition is generated by a master transmitter.

If a master receiver wants to terminate a data transfer, it must inform the

slave transmitter by not acknowledging the last byte of data which can

be done b y setting the transm it ackn owled ge bit (TXA K) befo re read ing

the 2nd last byte of data. Before reading the last byte of data, a STOP

signal must be generated first. The following is an example showing how

a STOP signal is generated by a master receiver.

ISR BCLR IBSR,#$02 ;CLEAR THE IBIF FLAG

BRCLR IBCR,#$20,SLAVE ;BRANCH IF IN SLAVE MODE

BRCLR IBCR,#$10,RECEIVE ;BRANCH IF IN RECEIVE MODE

BRSET IBSR,#$01,END ;IF NO ACK, END OF TRANSMISSION

TRANSMIT MOVB DATABUF,IBDR ;TRANSMIT NEXT BYTE OF DATA

MASTX TST TXCNT ;GET VALUE FROM THE

;TRANSMITING COUNTER

BEQ END ;END IF NO MORE DATA

BRSET IBSR,#$01,END ;END IF NO ACK

MOVB DATABUF,IBDR ;TRANSMIT NEXT BYTE OF DATA

DEC TXCNT ;DECREASE THE TXCNT

BRA EMASTX ;EXIT

END BCLR IBCR,#$20 ;GENERATE A STOP CONDITION

EMASTX RTI ;RETURN FROM INTERRUPT

MASR DEC RXCNT ;DECREASE THE RXCNT

BEQ ENMASR ;LAST BYTE TO BE READ

MOVB RXCNT,D1 ;CHECK SECOND LAST BYTE

DEC D1 ;TO BE READ

BNE NXMAR ;NOT LAST OR SECOND LAST

LAMAR BSET IBCR,#$08 ;SECOND LAST, DISABLE ACK

;TRANSMITTING

BRA NXMAR

ENMASR BCLR IBCR,#$20 ;LAST ONE, GENERATE ‘STOP’ SIGNAL

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Inter-IC Bus

IIC Programming Examples

MC68HC912DG128 — Rev 3.0 Technic al Data

Inter-IC Bus

15.7.5 Generation of Repeated START

At the end of da ta transfer, if the master still wants to communicat e on

the bus, it can generate another START signal followed by another slave

address without first generating a STOP signal. A program example is

as shown.

15.7. 6 Slave Mode

In the slave interrupt service routine, the module addressed as slave bit

(IAAS) should be te sted to ch eck if a calling o f its own a ddress ha s just

been r ece ive d ( see Fi gu re 15-4). If IAAS is set, so ftware sho uld se t th e

transmit/receive mode select bit (Tx/Rx bit of IBCR) according to the

R/W command bit (SRW). Writing to the IBCR clears the IAAS

automatically. Note that the only time IAAS is read as set is from the

interrupt at the end of the address cycle where an address match

occurred, interrupts resulting from subsequent data transfers will have

IAAS cleared. A data transfer may now be initiated by writing information

to IBDR, for slave transmits, or dummy reading from IBDR, in slave

receive mode. The slave will drive SCL low in-between byte transfers,

SCL is rele ased when the IBDR is accessed in the re quired mode.

In the slave transmitter routine, the received acknowledge bit (RXAK)

must be tested before transmitting the next byte of data. Setting RXAK

means an ’end of data ’ signal from the master receiver, after which it

must be switched from transmitter mode to receiver mode by software.

A dumm y read then releases the SCL line so that the master can

gener ate a STOP signa l.

NXMAR MOVB IBDR,RXBUF ;READ DATA AND STORE

RTI

MASR DEC RXCNT ;DECREASE THE RXCNT

RESTART BSET IBCR,#$04 ANOTHER START (RESTART)

MOVB CALLING,IBDR ;TRANSMIT THE CALLING ADDRESS

;D0=R/W

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Inter-IC Bus

Technical Data MC68HC912DG128 — Rev 3.0

Inter-IC Bus

15.7.7 Arbitration Lost

If several masters try to engage the bus simultaneously, only one master

wins and the others lose arbitration. The devices which lost arbitration

are immediately switched to slave receive mode by the hardware. Their

data output to the SDA line is stopped, but SCL is still generated until the

end of the byte dur ing wh i ch arb itr ati o n was lost. An in ter r up t occur s at

the falling edge of the ninth clock of this transfer with IBAL=1 and

MS/SL=0. If one master attempts to start transmission while the bus is

being engaged by another master, the hardware will inhibit the

transmission; switch the MS/SL bit fr om 1 to 0 w ithout gene rating STOP

condition; generate an interrupt to CPU and set the IBAL to ind icate that

the attempt to engage the bus is failed. When considering these cases,

the slave service routine should test the IBAL first and the software

should clear the IBAL bit if it is set.

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Inter-IC Bus

Technical Data MC68HC912DG128 — Rev 3.0

Inter-IC Bus

Figure 15-4. Flow-Chart of Typical IIC Interrupt Routine

Clear

Master

Mode

Tx/Rx

Last Byte

Transmitted

RXAK=0

End Of

Addr Cycle

(Master Rx)

Write Next

Byte To IBDR

Switch To

Rx Mode

Dummy Re ad

From IBDR Generate

Stop Signal Read Data

From IBDR

And Store

Set TXAK =1 Generate

Stop Signal

2nd Last

Byte To Be Read

Last

Byte To Be Read

Arbitration

Lost

Clear IBAL

IAAS=1

SRW=1

?TX/RX

Set TX

Mode

Write Data

To IB DR

Set RX

Mode

Dummy Read

From IBDR

ACK From

Receiver

Tx Next

Byte Read Data

From IBDR

And Store

Switch To

Rx Mode

Dummy Read

From IBDR

RTI

TX RX

(Write)

(Read)

IBIF

Address Transfer Data Transfer

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Inter-IC Bus

Technical Data MC68HC912DG128 — Rev 3.0

Inter-IC Bus

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MC68HC912DG128 — Rev 3.0 Technic al Data
Analog-to-Digital Converter
 
Technical Data — MC68HC912DG128
Section 16. Analog-to-Digital Converter
16.1  Contents
16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297
16.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298
16.4 ATD Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299
16.5 ATD Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .310
16.2  Introduction
The MC68HC912DG128 has two identical ATD modules identified as 
ATD0 and ATD1. Except for the VDDA and VSSA Analo g sup ply vo ltag e, 
all pins are duplicated and indexed with ‘0’ or ‘1’ in the following 
descr iption. An ‘x’ indicates either ‘0’ or ‘1’.
The ATD module is an 8-channel, 10-bit or 8-bit, multiplexed-input 
successive-approximation analog-to-digital converter. It does not 
require external sample and hold circuits because of the type of charge 
redistributi on technique used. The ATD converter timing can be 
synchronized to the system P clock. The ATD module consists of a 16-
word (32-byte) memory-mapped control register block used for con trol, 
testing and configuration.
    
  
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Analog-to-Digital Converter

Technical Data MC68HC912DG128 — Rev 3.0

Analog-to-Digital Converter

Figure 16-1. Analog-to-Digital Converter Block Diagram

16.3 Functional Description

A single conver sion sequence consists o f four or eight conversions,

depending on the state of the select 8 channel mode (S8CM) bit when

ATDxCTL5 is written. There are eight basic conversion modes. In the

non-scan modes, the SCF bit is set after the sequence of four or eight

conversions has been performed and the ATD module halts. In the scan

modes, the SCF bit is set after the first sequence of four or eight

conversions has been performed, and the AT D module contin ues to

restart the sequence. In both modes, the CCF bit associated with each

conversion result. That flag is cleared automatically when that result

registers.

MODE AND TIMING CONTROLS

ATD 0

ATD 1

ATD 2

ATD 3

ATD 4

ATD 5

ATD 6

ATD 7

SAR

RC DAC ARRAY

AND COMPARATOR

INTERNAL BUS

VDDA

VSSA

VRLx

VRHx

CLOCK

SELECT/PRESCALE

ANALOG MUX

AND

SAMPLE BUFFER AMP

PORT AD

DATA INPUT REGISTER

ANx7/PADx7

ANx6/PADx6

ANx5/PADx5

ANx4/PADx4

ANx3/PADx3

ANx2/PADx2

ANx1/PADx1

ANx0/PADx0

REFERENCE

SUPPLY

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Analog-to-Digital Converter

ATD Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

Analog-to-Digital Converter

16.4 ATD Registers

Control and data registers for the ATD modules are described below.

Both ATDs have identical control registers mapped in two blocks of 16

bytes.

Writes to this register will abort current conversion sequence.

READ: any time WRITE: any time.

WRITE: Write to this register has no meaning.

READ: Special Mode only.

Bit 7654321Bit 0

RESET:00000000

ATD0CTL0/ATD1CTL0 — Reserved $0060/$01E0

Bit 7654321Bit 0

RESET: 0 0 000000

ATD0CTL1/ATD1CTL1 — Reserved $0061/$01E1

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Analog-to-Digital Converter

Technical Data MC68HC912DG128 — Rev 3.0

Analog-to-Digital Converter

The ATD con trol register 2 and 3 are used to select the powe r up mode,

interr upt contro l, and fr e eze co ntrol . W rite s to th ese r eg ister s abo r t any

current conversion sequence.

Read or write an ytime except ASCIF bit, which cann ot be written.

Bit positions ATDCTL2[4:2] and ATDCTL3[7:2] are unused and always

read as zeros.

ADPU — ATD Disable

0 = Disables the ATD, including the analog section for reduction in

power consumption.

1 = Allows the ATD to function normally.

Softwa re can disable the clock signal to the A/D con verter and power

down the analog circuits to reduce power consumption. When reset

to zero, the A D PU bit ab or ts an y con v er sion sequ en ce i n pr o gress.

Because the bias currents to the analog circuits are turned off, the

ATD re quires a peri od of recovery ti me to stab ilize the an alog circuits

after setting the ADPU bit.

AFFC — ATD Fast Flag Clear All

0 = ATD flag clearing oper ates normally (read t he status register

before rea din g the resu l t regi ster to clear the associ at ed C CF

bit).

1 = Changes all ATD conversion complete flags to a fast clear

sequence. Any access to a result register (ATD0–7) will cause

the associated CCF flag to clear automatically if it was set at

the time.

AWAI — ATD Wait Mode

0 = ATD continues to ru n when the MCU is in wait mode

1 = ATD stops to save powe r when the MCU is in wait mode

Bit 765432 1Bit 0

ADPU AFFC AWAI 0 0 0 ASCIE ASCIF

RESET: 0 0 0 0 0 0 0 0

ATD0CTL2/ATD1CTL2 — ATD Control Register 2 $0062/$01E2

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Analog-to-Digital Converter

ATD Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

Analog-to-Digital Converter

When the AWAI bit is set and the module enters wait mode, most of

the clocks stop and the analog portion powers down. When the

module comes out of wait, it is recommended that a stabilisation delay

(stop and ATD powe r up recovery time, tSR) is allowed before new

conversions are started. Additionally, the ATD does not re-initialise

automatically on leaving wait mode.

ASCIE — ATD Sequence Complete Interrupt Enable

0 = Disables ATD interrupt

1 = Enables ATD interrupt on sequence complete

ASCIF — ATD Sequence Complete Interrupt Flag

Cannot be written in any mode.

0 = No ATD interrupt o ccurred

1 = ATD se quence complete

FRZ1, FRZ0 — Background Debug (Freeze) Enable (suspend module

operation at breakpoint)

When debugging an application, it is useful in many cases to have the

ATD pause when a breakpoint is encountered. These two bits

determ i ne how the ATD w ill re spo nd w he n backg r oun d debug mo de

becomes active.

Bit 765432 1Bit 0

000000FRZ1FRZ0

RESET: 0 0 0 0 0 0 0 0

ATD0CTL3/ATD1CTL3 — ATD Control Register 3 $0063/$01E3

Table 16-1. ATD Response to Background Debug Enable

FRZ1 FRZ0 ATD Response

0 0 Continue conver sions in active background mode

01 Reserved

1 0 Finish current conversion, then freeze

1 1 Freeze when BDM is active

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Analog-to-Digital Converter

Technical Data MC68HC912DG128 — Rev 3.0

Analog-to-Digital Converter

The ATD control register 4 is used to select the clock source and set up

the prescaler. Writes to the ATD control registers initiate a new

conversion sequence. If a write occurs while a conversion is in progress,

the conversion is aborted and ATD acti vity halts until a write to

ATDxCTL5 occurs.

RES10 — 10 bit Mode

0 = 8 bit operation

1 = 10 bi t operation

SMP1, SMP0 — Select Sample Time

Used to select one of four sample times after the buffered sample and

transfe r has occurr ed .

Bit 765432 1Bit 0

RES10 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0

RESET: 0 0 0 0 0 0 0 1

ATD0CTL4/ATD1CTL4 — ATD Control Register 4 $0064/$01E4

Table 16-2. Final Sample Time Selection

SMP1 SMP0 Fina l Samp l e Time

0 0 2 A/D clock periods

0 1 4 A/D clock periods

1 0 8 A/D clock periods

1 1 16 A/D cl ock periods

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ATD Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

Analog-to-Digital Converter

PRS4, PRS3, PRS2, PRS1, PRS0 — Select Divide-By Factor for ATD

P-Clock Prescaler.

The binary value written to these bits (1 to 31) selects the divide-by

factor for the modulo cou nter-based prescaler. The P clock is divide d

by th is value p lus one and th en fed into a ÷2 circuit to generate the

ATD module clock. The divide-by-two circuit insures symmetry of the

output clock signal. Clearing these bits causes the prescale value

default to one which results in a ÷2 prescale factor. This signal is then

fed into the ÷2 logic. The reset state divides the P clock by a total of

four and is appropriate for nominal operation at 2 MHz. Ta ble 16- 3

shows the divide-by operation and the appropriate range of system

clock frequen ci es.

Table 16-3 . Clock Presca ler Values

Prescale

Value Total Divisor Max P Clock(1)

1. Max im um c onve rsi o n fre q uenc y is 2 MHz. Ma xi mum P cloc k di vi sor v alu e w il l be come

maximum conversion rate that can be used on this ATD module.

Min P Clock(2)

2. Minimum conversion frequency is 500 kHz. Minimum P clock divisor value will become

minimum conversion rate that this ATD can perform.

00000 ÷24 MHz 1 MHz

00001 ÷48 MHz 2 MHz

00010 ÷68 MHz 3 MHz

00011 ÷88 MHz 4 MHz

00100 ÷10 8 MHz 5 MHz

00101 ÷12 8 MHz 6 MHz

00110 ÷14 8 MHz 7 MHz

00111 ÷16 8 MHz 8 MHz

01xxx Do Not Use

1xxxx

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Analog-to-Digital Converter

Technical Data MC68HC912DG128 — Rev 3.0

Analog-to-Digital Converter

The ATD control register 5 is used to select the conversion modes, the

conversion channel(s), and initiate conversions.

Read or write any time. Writes to the ATD control registers initiate a new

conversion sequence. If a conversion sequence is in progress when a

write occ urs, th at sequence is a borted and the SC F and CCF bit s are

reset.

S8CM — Select 8 Channel Mode

0 = Conversion sequence consists of four conversions

1 = Conversion sequence consists of eight conversions

SCAN — Enabl e Continuous Cha nnel Scan

0 = Single conversion sequence

1 = Continuous conversion sequences (scan mode)

When a convers i on sequ ence is initiated by a writ e to the ATDxCTL

eight, depending on the S8CM bit) conversions or cont inuous ly

performing four (or eight) conversion sequences.

MULT — Enable Multichannel Conversion

0 = ATD s equencer runs all four or ei ght conversions on a single

input channel selected via the CD, CC, CB, and CA bits.

1 = ATD sequencer runs each of the four or eight conversions on

sequential channels in a s pecific group. Refer to Tabl e 16-4.

Bit 7654321Bit 0

0 S8CM SCAN MULT CD CC CB CA

RESET: 0 0 000000

ATD0CTL5/ATD1CTL5 — ATD Control Register 5 $0065/$01E5

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Analog-to-Digital Converter

ATD Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

Analog-to-Digital Converter

CD, CC, CB, and CA — Channel Select for Co nversion

Table 16-4. Multichannel Mode Result Register Assignment

S8CM CD CC CB CA Channel Signal Result in ADRxx

if MULT = 1

000

00 AN0 ADRx0

01 AN1 ADRx1

10 AN2 ADRx2

11 AN3 ADRx3

001

00 AN4 ADRx0

01 AN5 ADRx1

10 AN6 ADRx2

11 AN7 ADRx3

010

00 Reserved ADRx0

01 Reserved ADRx1

10 Reserved ADRx2

11 Reserved ADRx3

011

0 0 VRH ADRx0

0 1 VRL ADRx1

1 0 (VRH + VRL)/2 ADRx2

11 TEST/Reserved ADRx3

0 0 0 AN0 ADRx0

0 0 1 AN1 ADRx1

0 1 0 AN2 ADRx2

0 1 1 AN3 ADRx3

1 0 0 AN4 ADRx4

1 0 1 AN5 ADRx5

1 1 0 AN6 ADRx6

1 1 1 AN7 ADRx7

0 0 0 Reserved ADRx0

0 0 1 Reserved ADRx1

0 1 0 Reserved ADRx2

0 1 1 Reserved ADRx3

1 0 0 VRH ADRx4

1 0 1 VRL ADRx5

1 1 0 (VRH + VRL)/2 ADRx6

1 1 1 TEST/Reserved ADRx7

Shaded bits are “don’t care” if MULT = 1 and the entire block of four or eight

channels make up a conversion sequence. When MULT = 0, all four bits (CD,

CC, CB, and CA) must be specified and a conversion sequence consists of

four or eight consecutive conversions of the single specified channel.

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Technical Data MC68HC912DG128 — Rev 3.0

Analog-to-Digital Converter

NOTE: Conversion of (VRH-VRL)/2 returns $7F, $80 or $81 in 8-bit mode.

The ATD status registers contain the flags indicating the completion of

ATD conversions.

Normally, it is read-only. In special mode, the SCF bit and the CCF bits

may also be wri tte n.

SCF — Sequence Complete Flag

This bit is set at the end of the conv ersion sequence wh en in the

single conver sion sequence mode (SCAN = 0 in ATDxCTL5) an d is

set at the end of the first conversion sequence when in the continuous

conversion mode (SCAN = 1 in ATDxCTL5). When AFFC = 0, SCF is

cleared when a write is performed to ATDxCTL5 to initiate a new

conversio n se que nce . Whe n AFFC = 1 , SC F is cl ea red after the fir st

result regi ster is read.

CC[2:0] — Conversion Counter for Current Sequence of Four or Eight

Conversions

This 3-bit value reflects the contents of the conversion counter pointer

in a four or eight count sequence. This value also reflects which result

converted.

CCF[7:0] — Conversion Complete Flags

Bit 7654321Bit 0

SCF 0 0 0 0 CC2 CC1 CC0

RESET:00000000

ATD0STAT0/ATD1STAT0 — ATD Status Register $0066/$01E6

ATD0STAT1/ATD1STAT1 — ATD Status Register $0067/$01E7

Bit 7654321Bit 0

CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0

RESET: 0 0000000

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Analog-to-Digital Converter

ATD Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

Analog-to-Digital Converter

Each of these bits are associated with an individual ATD result

the associated ATD channel and remains set until that ATD result

of whether a s tatus register rea d has been performed (i.e., a stat us

AFFC = 1). Otherwise the status register must be read to clear the

flag.

The test registers control various special modes which are used

duri ng ma nufact uri ng. The test r egi ster ca n be read or wri tten o nly in

the special modes. In the normal modes, reads of the test register

return zero and writes have no effect.

SAR[9:0] — SAR Data

Reads of this byte return the current value in the SAR. Writes to this

byte change the SAR to the value written. Bits SAR[9:0] reflect the ten

SAR bits used during the resolution process for a 10-bit result.

Bit 7654321Bit 0

SAR9 SAR8 SAR7 SAR6 SAR5 SAR4 SAR3 SAR2

RESET: 0 0 000000

ATD0TESTH/ATD1TESTH — ATD Test Register $0068/$01E8

Bit 765432 1Bit 0

SAR1 SAR0 RST TSTOUT TST3 TST2 TST1 TST0

RESET: 0 0 0 0 0 0 0 0

ATD0TESTL/ATD1TESTL — ATD Test Register $0069/$01E9

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Analog-to-Digital Converter

Technical Data MC68HC912DG128 — Rev 3.0

Analog-to-Digital Converter

RST — Module Reset Bit

When set, this bit causes all registers and activity in the module to

assume the same state as out of power-on reset (except for ADPU bit

in ATDCTL2, which remains set, allowing the ATD module to remain

enabled).

TSTOUT — Multiplex Output of TST[3:0] (Factory Use)

TST[3:0] — Test Bits 3 to 0 (Reserved)

Selects one of 16 reserved factory testing modes

PADx[7:0] — Port AD Data Input Bits

After reset these bits reflect the state of the input pins.

May be used for general-purpose digital input. When the software

reads PORTADx, it obtains the digital levels that appear on the

correspondi ng por t AD pi ns . P ins wi th signals not m eeting VIL or VIH

specifications will have an indeterminate value. Writes to this register

have no mean i ng at any ti me .

Bit 765432 1Bit 0

PADx7 PADx6 PADx5 PADx4 PADx3 PADx2 PADx1 PADx0

RESET: - - - - - - - -

PORTAD0/PORTAD1 — Port AD Data Input Register $006F/$01EF

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Analog-to-Digital Converter

ATD Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

Analog-to-Digital Converter

ADRxxH[7:0] — ATD Conversion result (high)

The reset condition for these registers is undefined.

In 8-bit mode, these registers contain the left-justified, unsigned result

from the 8-bit ATD conversion.

In 10-bit mode these registers contain the high order bits of the

conversion result.

ADRxxL[7:0] — ATD Conversion result (low )

The reset condition for these registers is undefined.

In 8-bit mode, these registers bits are reserved.

In 10-bit mode these registers contain the remaining two low order

bits of the conversion result in bits 6 and 7.

8-bit mode Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

10-bit mode Bit 9Bit 8Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2

RESET: uuuuuuuu

ADRx0H — A/D Conversion Result Register High 0 $0070/$01F0

ADRx1H — A/D Conversion Result Register High 1 $0072/$01F2

ADRx2H — A/D Conversion Result Register High 2 $0074/$01F4

ADRx3H — A/D Conversion Result Register High 3 $0076/$01F6

ADRx4H — A/D Conversion Result Register High 4 $0078/$01F8

ADRx5H — A/D Conversion Result Register High 5 $007A/$01FA

ADRx6H — A/D Conversion Result Register High 6 $007C/$01FC

ADRx7H — A/D Conversion Result Register High 7 $007E/$01FE

8-bit mode ————————

10-bit mode Bit 1 Bit 0 ——————

RESET: uuuuuuuu

ADRx0L — A/D Conversion Result Register Low 0 $0071/$01F1

ADRx1L — A/D Conversion Result Register Low 1 $0073/$01F3

ADRx2L — A/D Conversion Result Register Low 2 $0075/$01F5

ADRx3L — A/D Conversion Result Register Low 3 $0077/$01F7

ADRx4L — A/D Conversion Result Register Low 4 $0079/$01F9

ADRx5L — A/D Conversion Result Register Low 5 $007B/$01FB

ADRx6L — A/D Conversion Result Register Low 6 $007D/$01FD

ADRx7L — A/D Conversion Result Register Low 7 $007F/$01FF

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Analog-to-Digital Converter

Technical Data MC68HC912DG128 — Rev 3.0

Analog-to-Digital Converter

The channel from which this result was obtained is dependent on the

conversion mode selected. The registers are always read-only in normal

mode.

16.5 ATD Mode Operation

STOP — causes all clocks to halt (if the S bit in the CCR is zero). The

system is placed in a minimum-power standby mode. This aborts any

conversion sequence in progress.

WAIT — ATD conversion continues unless AWAI bit in ATDxCTL2

BDM — D ebug opt i ons ava ilable as set in register ATDxCTL3.

USER — ATD continues running unless ADPU is cleared.

ADPU — ATD operations are stopped if ADPU = 0, but registers are

accessible.

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MC68HC912DG128 — Rev 3.0 Technic al Data
MSCAN Controller
 
Technical Data — MC68HC912DG128
Section 17. MSCAN Controller
17.1  Contents
17.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311
17.3 External Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312
17.4 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313
17.5 Identifier Acceptance Filter. . . . . . . . . . . . . . . . . . . . . . . . . . .318
17.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322
17.7 Protocol Violation Protection. . . . . . . . . . . . . . . . . . . . . . . . . .324
17.8 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325
17.9 Timer Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
17.10 Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
17.11 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332
17.12 Programmer’s Model of Message Storage. . . . . . . . . . . . . . .332
17.13 Programmer’s Model of Control Registers . . . . . . . . . . . . . . .338
17.2  Introduction
The MC68HC912DG128 has two iden tical msCAN12 modules, 
identified  as CAN0 and CAN1. The information to follow describes one  
fsCAN unless specifically  noted and re gister locations specifically 
relate to CAN0. CAN1 registers a re located 512 bytes from CAN0.
The fsCAN12 is the specific implementation of the Freescale scalable 
CAN (fsCAN) concept targeted for the Freescale M68HC12 
microcontroller family. 
    
  
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MSCAN Controller

Technical Data MC68HC912DG128 — Rev 3.0

MSCAN Controller

The module is a communication controller implementing the CAN 2.0

A/B protocol as defined in the BOSCH specification dated September

1991.

The CAN p roto col was p rim arily , but not on ly, de signe d to b e used as a

vehicle serial data bus, meeting the specific requirements of this field:

real-time processing, reliable operation in the EMI environment of a

vehicle, cost-effectiveness and required bandwidth.

msCAN12 utilizes an advanced buffer arrangement resulting in a

predictable real-time behavior and simplifies the application software.

17.3 Extern al Pins

The msCAN12 uses 2 external pins, 1 input (RxCAN) and 1 output

(TxCAN). The TxCAN output pin represents the logic level on the CAN:

0 is for a dominant st ate, and 1 is for a recessive state.

RxCAN is on bit 0 of Port CAN, TxCAN is on bit 1. The remaining six pins

of Port CA N are co ntroll ed by re gisters i n the msCAN1 2 addr ess spa ce

(see msCAN12 Port CAN Control Register (PCTLCAN) and msCAN12

Port CAN Data Direction Register (DDRCAN)).

A typical CAN system with msCAN12 is shown in Figure 17-1.

Each CAN station is connected physically to the CAN bus lines through

a transceiver chip. The transceiver is capable of driving the large current

needed for the CAN and has current protection, against defective CAN

or defecti ve statio ns.

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MSCAN Controller

Message Storage

MC68HC912DG128 — Rev 3.0 Technic al Data

MSCAN Controller

Figure 17-1. The CAN System

17.4 Message Storage

msCAN12 facilitates a sophisticated message storage system which

addresse s the requirements of a broad range of network applications.

17.4.1 Background

Modern application layer software is built upon two fundamental

assumptions:

1. An y CAN node is able to send out a stream of sched uled

messages without releasing the bus between two messages.

Such nodes will arbitrate for the bus right after sending the

previous message and will only release the bus arbitr ation is lost.

2. The internal message queue within any CAN node is organized

such that if more than one message is ready to be sent, the

highest priority message will be sent out first.

Transceiver

msCAN12

CAN system

CAN station 1 CAN station 2 CAN station n

CAN

TxCAN RxCAN

.....

Controller

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MSCAN Controller

Technical Data MC68HC912DG128 — Rev 3.0

MSCAN Controller

The bove behavior cannot be achieved with a single transmit buffer. That

buffer must be reloaded right after the previous message has been sent.

This l oading pr ocess lasts a definite amount of time and has to be

completed within the inter-frame sequence (IFS) in order to be able to

send an uninterrupted stream of messages. Even if this is feasible for

limited CAN bus speeds it requires that the CPU reacts with short

latencies to the transmit interrupt.

A double buffer scheme would de-couple the re-loading of the transmit

buffers from the actual message sending and as such reduces the

reactivene ss requirements on the CPU. Problems may arise if the

sendin g of a me ssage woul d be fin ished just w hile th e CPU re- loads the

second buffer, no buffer would then be ready for transmission and the

bus would be released.

At least three transmit buffers are required to meet the first of above

requirements under all circumstances. The msCAN12 has three transmit

buffers.

The second requirement calls for some sort of internal prioritization

which the msCAN12 implements with the local priority concep t

describe d below.

17.4.2 Receive Structures

The received messages are stored in a two stage input FIFO. The two

message buffers are alternately mapped into a single memory area (see

Figure 17-2). While t he background receive buffer (RxBG) is exclusively

associated to the msCAN12, the foreground receive buffer (RxFG) is

addressable by the CPU12. This scheme simplifies the handler software

as only o ne addr ess area is applicable for the re ceive proc ess.

Both buffers have a size of 13 bytes to store the CAN control bits, the

identifier (standard or extended) and the data contents (for details see

Programmer’s Model of Message Storage ).

The receiver full flag (RXF) in the msCAN12 receiver flag register

(CRFLG) (see msCAN12 Receiver Flag Register (CRFLG)) signals the

status of the foreground receive buffer. When the buffer contains a

correctly received message with matching identifier this flag is set.

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MSCAN Controller

Message Storage

MC68HC912DG128 — Rev 3.0 Technic al Data

MSCAN Controller

On reception, each messag e is checked to see if it passes the filter (for

details see Identifier Acceptance Filter) and in paralle l is written into

RxBG. The msCAN12 copies the content of RxBG into RxFG(1), sets the

RXF flag, and generates a receive interrupt to the CPU(2). The user’s

receiv e han dler has to rea d the rec eived m essage fro m RxFG a nd th en

reset the RXF flag in order to acknowledge the interrupt and to release

the foreground buffer. A new message, which can follow immediately

after the IFS field of the CAN frame, is received into RxBG.

The over-writing of the background buffer is independent of the identifier

filter function.

1. Only if the RXF flag is not set.

2. The receive interrupt is g enerated only if not masked. A polling sche me can be applied on RXF

also.

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MSCAN Controller

Technical Data MC68HC912DG128 — Rev 3.0

MSCAN Controller

Figure 17-2. User Model for Message Buffer Organization

When the msCAN12 module is transmitting, the msCAN12 receives its

own messages into the background receive buffer, RxBG, but does NOT

overwrite RxFG, genera te a receive interrupt or acknowledge its own

messages on the CAN bus. The exception to this rule is in loop-back

mode (see msCAN12 Module Control Register 0 (CMCR0)) where the

msCAN12 treats its own messages exactly like all other incoming

messages. The msCAN12 receives its own transmitted messages in the

event that it loses arbitration. If arbitrat ion is lost, the msCAN12 must be

prepared to become receiver.

RxFG

RxBG

Tx0

RXF

TXE

PRIO

Tx1 TXE

PRIO

Tx2 TXE

PRIO

msCAN12 CPU bus

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MSCAN Controller

Message Storage

MC68HC912DG128 — Rev 3.0 Technic al Data

MSCAN Controller

An overrun condition occurs when both the foreground and the

background receive message buffers are filled with correctly received

messages with accepted identifiers and another message is correctly

receiv ed from the bus with an a ccepted i dentifier. Th e latter message is

discarded and an error interrupt with overrun indication is generated if

enabled. The msCAN12 is still able to transmit messages with both

receive message buffers filled, but all incoming messages are

discarded.

NOTE: The msCAN12 will receive its own messages into the background

receive buffer RxBG but will not overwrite RxFG and will not emit a

receive interrupt nor will it acknowledge (ACK) its own messages on the

CAN bus. The except ion to this rule is tha t when in loop-back mode

msCAN12 will trea t its own messages exactly like all other incoming

messages.

17.4.3 Transmit Structures

The msCAN12 has a triple transmit buffer scheme in order to allow

multi ple messa ges to be set up in advan ce and to achiev e an opt imized

real-time performance. The three buffers are arranged as sh own in

Figure 17-2.

All three buffers have a 13 byte data structure similar to the outline of the

receive buffers (see Programmer’s Model of Message Storage). An

additional transmit buffer priority register (TBPR) contains an 8-bit so

called loca l priority field (PRIO) (s ee Transmit Buffer Priority Registers

(TBPR)).

In order to transmit a message, the CPU12 has to identify an available

transmit buffer which is indicated by a set transmit buffer empty (TXE)

flag in the msCAN12 transmitter flag register (CTFLG) (see msCAN12

Transmitter Flag Register (CTFLG)).

The CPU12 then stores the identifier, the control bits and the data

content into one of the transmit buffers. Finally, the buffer has to be

flagged as being ready for transmission by clearing the TXE flag.

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MSCAN Controller

Technical Data MC68HC912DG128 — Rev 3.0

MSCAN Controller

The msCAN12 will then schedule the message for transmission and will

signal th e su ccessf ul tran sm issio n o f th e b uffe r by se tting th e TXE fl ag .

A transmit interrupt will be emitted(1) when TXE is set and this can be

used to drive the application software to re-load the buffer.

If more than one buffer is scheduled for transmission when the CAN bus

becomes available for arbitration, the msCAN12 uses the local priority

setting of the three buffers for prioritisation. For this purpose every

transmit buffer has an 8-bit local priority field (PRIO). The application

softw are sets this field when the message is se t up. Th e local priori ty

reflects the priority of this particular message relative to the set of

messages being emitted from this node. The lowest binary value of the

PRIO field is defined to be the highest priority.

The internal scheduling process takes places whenever the msCA N12

arbitrates for the bus. This is also the case after the occurrence of a

transmission err or.

When a high priority message is schedu l ed by the applicati on software

it may become necessary to abort a lower priority message being set up

in one of the three transmit buffers. As messages that a re alread y under

transmission cannot be aborted, the user has to request the abort by

setting the corresponding abort request flag (ABTRQ) in the

transmission control register (CTCR). The msCAN12 grants the request,

if pos sible, by setting the correspond ing abort request acknowledg e

(ABTAK) and the TXE flag in order to release the buffer and by

generating a transmit interrupt. The transmit interrupt handler software

can tell from the setting of the ABTAK flag whether the message was

aborted (ABTAK=1) or sent in the meantime (ABTAK=0).

17.5 Identif ier Acceptance Filter

The identifier acceptance registers (CIDAR0–7) define the acceptable

patter ns of th e sta nd ar d or exte nd ed ident if ie r (ID1 0–I D0 or ID 28–ID0).

Any of these bits can be marked don’t care in the identifier mask

registers (CIDMR 0–7).

1. The tra nsmi t inte rrup t wi ll o ccur onl y if not mask ed . A poll ing sc hem e c an be appl ie d on TXE

also.

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MSCAN Controller

Identifie r Acce ptan ce Filter

MC68HC912DG128 — Rev 3.0 Technic al Data

MSCAN Controller

A filter hit is indicated to the application software by a set RXF (receive

buffer full flag, see msCAN12 Receiver Flag Register (CRFLG)) and

three bits in the identifier acceptance control register (see msCAN12

Identifier Acceptance Control Register (CIDAC)). These identifier hit

flags (IDHIT2–0) clearly identify the filter section that caused the

accept ance. Th ey simp lif y the appli cati on softwa re ’s task to ide ntify the

cause of the receiver interrupt. When more than one hit occurs (two or

more filters match) the lower hit has priority.

A very flexible programmable generic identifier acc epta nce fi lter has

been introduced in order to reduce the CPU interrupt loading. The filter

is programmable to operate in four different modes:

•Two identifier acceptance filters, each to be applied to:

a) the full 29 bits of the extended iden tifier and to the fo llowing bits

of the CAN frame: RTR, IDE, SRR or

b) the 11 bits of the standard identifier, the RTR and IDE bits of

CAN 2.0A/B messages.

This mode implements two filters for a full length CAN 2.0B

compl iant extend ed iden tifier . Figure 17-3 shows how the first 32-

bit filter bank (CIDAR0–3, CIDMR0–3) produces a filter 0 hit.

Similarly, the second filter bank (CIDAR4–7, CIDMR4–7)

prod uces a f ilter 1 hit.

•Four identifier acceptance filters, each to be applied to:

a) the 14 most significant bits of t he extended identifier plus the

SRR an d IDE bit s of CAN 2.0B mes sages or

b) the 11 bits of the standard identifier, the RTR and IDE bits of

CAN 2.0A/B messages.

Figure 17-4 shows how the first 32-bit filter bank (CIDAR0–3,

CIDMR0–3) produces filter 0 and 1 hits. Similarly, the second filter

bank (CID A R4 –7, CIDMR4–7) produces filter 2 and 3 hits.

•Eight identifier acceptance filters, each to be applied to the first 8

bits of the identi fier. This mode implements eight independent

filters for the first 8 bits of a CAN 2.0A/B compliant standard

identifier or of a CAN 2.0B compliant extended identifier. Figure

17-5 shows how the first 32-bit filter bank (CIDAR0–3, CIDMR0–3)

produces filter 0 to 3 hits. Similarly, the second filt er bank

(CIDAR4–7, CIDMR4–7) produces filter 4 to 7 hits.

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MSCAN Controller

•Close d filter. No CAN messag e will be copi ed into the fo regrou nd

buffer RxFG, and the RXF fl ag will never be set.

Figure 17-3. 32-bit Maskable Identifier Acceptance Filters

Figure 17-4. 16-bi t Maskab le Acceptance Filters

CIDMR2

ID28 ID21 ID20 ID15 ID14 ID7 ID6 RTR

ID10 ID3 ID2 IDE

AM7

IDR0

IDR1

IDR2 IDR3

AM0 AM7 AM0 AM7 AM7AM0 AM0

AC7 AC0 AC7 AC0 AC7 AC0 AC7 AC0

CIDMRO CIDMR1 CIDMR3

CIDAR3CIDAR2CIDAR1CIDARO

ID accepted (Filter 0 hit)

ID28 ID21 ID20 ID15 ID14 ID7 ID6 RTR

ID10 ID3 ID2 IDE

AM7

IDR0

IDR1

IDR2 IDR3

AM0 AM7 AM0

AC7 AC0 AC7 AC0

CIDMRO CIDMR1

CIDAR1CIDARO

ID accepted (Filter 0 hit)

ID accepted (Filter 1 hit)

AM7 AM0 AM7 AM0

AC7 AC0 AC7 AC0

CIDMR2 CIDMR3

CIDAR3CIDAR2

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MSCAN Controller

Identifie r Acce ptan ce Filter

MC68HC912DG128 — Rev 3.0 Technic al Data

MSCAN Controller

Figure 17-5. 8-bit Maskable Acceptance Filters

The identifier acceptance registers (CIDAR0–7) define the acceptable

patter ns of th e sta nd ar d or exte nd ed ident if ie r (ID1 0–I D0 or ID 28–ID0).

Any of these bits can be marked don’t care in the identifier mask

registers (CIDMR 0–7).

A filter hit is indicated to the application software by a set RXF (receive

buffer full flag, see msCAN12 Receiver Flag Register (CRFLG)) and

ID28 ID21 ID20 ID15 ID14 ID7 ID6 RTR

ID10 ID3 ID2 IDE

AM7

IDR0

IDR1

IDR2 IDR3

AM0

AC7 AC0

CIDMRO

CIDARO

ID accepted (Filter 0 hit)

AM7 AM0

AC7 AC0

CIDMR1

CIDAR1

AM7 AM0

AC7 AC0

CIDMR2

CIDAR2

ID accepted (Filter 1 hit)

ID accepted (Filter 2 hit)

AM7 AM0

AC7 AC0

CIDMR3

CIDAR3

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Technical Data MC68HC912DG128 — Rev 3.0

MSCAN Controller

three bits in the identifier acceptance control register (see msCAN12

Identifier Acceptance Control Register (CIDAC)). These identifier hit

flags (IDHIT2–0) clearly identify the filter section that caused the

accept ance. Th ey simp lif y the appli cati on softwa re ’s task to ide ntify the

cause of the receiver interrupt. In case that more than one hit occurs (two

or more filters match) the lower hit has priority.

A hit will also cause a receiver interrupt if enabled.

17.6 Interru p t s

The msCAN12 supports f our interrupt vectors m apped onto eleven

different interrupt sources, any of which can be individually masked (for

details see msCAN12 Receiver Flag Register (CRFL G) to msCAN12

Transmitter Control Register (CTCR)):

•Transmit interrupt: At least one of the three transmit buffers is

empty (not scheduled) and can be loaded to schedule a message

for transmission. The TXE flags of the empty message buffers are

set.

•Receive interrupt: A message has been successfully received and

loaded into the foreground receive buffer. This interrupt is

gener ated imm ediate ly afte r receiv ing the EO F symbo l. The RXF

flag is set.

•Wake-up interrupt: An activity on the CAN bus occurred during

msCAN12 internal SLEEP mode.

•Error interrupt: An overrun, error or warning condition occurred.

The receiver flag register (CRFLG) indicates one of the following

conditions:

–Overrun: an overrun condition as described in Receive

Structures has occurred.

–Receiver warning: the receive error counter has reached the

CPU warning limit of 96.

–Transmitter warning: the transmit error counter has reached

the CPU warn ing limit of 96 .

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Interrupts

MC68HC912DG128 — Rev 3.0 Technic al Data

MSCAN Controller

–Receiver error passive: the receive error counter has

exceeded the error passive limit of 127 and msCAN12 has

gone to error passive state.

–Transmitter error passive: the transmit error counter has

exceeded the error passive limit of 127 and msCAN12 has

gone to error passive state.

–Bus off: the transmit error counter has exceeded 255 and

msCAN12 has gone to BUSOFF state.

17.6.1 Interrupt Acknowledge

Interr up ts a re di r ectly a ssociated w ith o ne or mo re sta t us flags in ei th er

the msCAN12 receiver flag register (CRFLG) or the msCAN12

transmi tter flag r egister ( CTFLG). Inte rrupts ar e pending as long as one

of the corresponding flags is set. The flags in above registers must be

reset within the interrupt handler in order to handshake the interrupt. The

flags are reset through writing a 1 to the corresponding bit position. A flag

cann ot be cleared if the respectiv e condition still prevails.

NOTE: Bit manipulatio n instruction s ( BSE T) shall n ot be used to cl ea r i n terr up t

flags.

17.6.2 Interrupt Vectors

The msCAN12 supports four interrupt vectors as shown in Table 17-1.

The vector addresses and the relative interrupt priority are dependent on

the chip integration and to be defined.

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MSCAN Controller

17.7 Protocol Violation Protection

The msCAN12 will protect the user from accidentally violating the CAN

protocol through programming errors. The protection logic implements

the following featur es:

•The receive and transmit error counters cannot be written or

othe rwi s e ma ni p ul ate d.

•All registers which control the configuration of the msCAN12

cannot be modified while the msCAN12 is on-line. The SFTRES

bit in CMCR0 (se e msCAN12 Module Control Register 0

(CMCR0)) serves as a lock to protect the following registers:

–msCAN12 module control register 1 (CMCR1)

–msCAN12 bus timing register 0 and 1 (CBTR0, CBTR1)

–msCAN12 identifier acc eptanc e contr ol regist er (CID AC)

–msCAN12 identifier acceptance registers (CIDAR0–7)

–msCAN12 identifier mask regis ters (CIDMR0–7)

•The TxCAN pin is forced to recessive when the msCAN12 is in any

of the low power modes.

Table 17-1. msCAN12 Interrupt Vectors

Function Source Local Mask Global Mask

Wake-Up WUPIF WUPIE

I Bit

Error

Interrupts

RWRNIF RWRNIE

TWRNIF TWRNIE

RERRIF RERRIE

TERRIF TERRIE

BOFFIF BOFFIE

OVRIF OVRIE

Receive RXF RXFIE

Transmit TXE0 TXEIE0

TXE1 TXEIE1

TXE2 TXEIE2

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MSCAN Controller

Low Power Modes

MC68HC912DG128 — Rev 3.0 Technic al Data

MSCAN Controller

17.8 Low Power Modes

In addition to normal mode, the msCAN12 has three modes with

reduced power c onsumption: S LEEP, SOFT_RESET and

POWER_DOWN. In SLEEP and SOFT_RESET modes, power

consumption is reduced by stopping all clocks except those to access

the registers. In POWER_DOWN mode, all clocks are stopped and no

power is consum ed.

The WAI and STOP instructions put the MCU in low power consumption

stand-by modes. Table 17-2 summarizes the combinations of msCAN12

and CPU modes. A particular combination of modes is entered for the

given setti ngs of the bits C SWAI, SLPA K, and SFTRES. For all modes,

an msCAN wake-up interrupt can occur only if SLPAK=WUPIE=1. While

the CPU is in Wait Mode, the msCAN12 can be operated in Nor mal

Mode and generate interrupts (registers can be accessed via

background debug mode).

Table 17-2. msCAN12 vs. CPU operating modes

msCAN Mode CPU Mode

STOP WAIT RUN

POWER_DOWN CSWAI = X(1)

SLPAK = X

SFTRES = X

1. X means don’t care.

CSWAI = 1

SLPAK = X

SFTRE S = X

SLEEP CS WAI = 0

SLPAK = 1

SFTRES = 0

CSWAI = X

SLPAK = 1

SFTRES = 0

SOFT_RESET CSWAI = 0

SLPAK = 0

SFTRES = 1

CSWAI = X

SLPAK = 0

SFTRES = 1

Normal CSWAI = 0

SLPAK = 0

SFTRES = 0

CSWAI = X

SLPAK = 0

SFTRES = 0

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17.8.1 msCAN12 SLEEP Mode

The CPU can request the msCAN12 to enter this low-power mode by

asserting the SLPRQ bit in the Module Configuration Register (see

Figure 17-6). The time when the msCAN12 enters Sleep Mode depends

on its activity:

•If one or more message buffers are scheduled for transmission

(TXEx = 0), the msCAN will continue to transmit until all transmit

message buffers are empty (TXEx = 1, transmitted successfully or

aborted) and then goes into Sleep Mode

•If it is receiving, it continues to receive and goes into Sleep Mode

as soon as the CAN bus next becomes idle

•If it is neither transmitting nor receiving, it will immediately go into

Sleep Mode

NOTE: The application software must avoid setting up a transmission (by

clearin g one or m ore TXE fl ag(s)) an d immedia tely reque st Sleep Mode

(by setting SLPRQ). It then depends on the exact sequence of

opera tions wheth er the ms CAN12 starts tr ansmit ting or goe s into Sleep

Mode directly.

During Sleep Mode, the SLP AK fla g is set. The ap pli cati on softwar e

should use SLPAK as a handshake indication for the request (SLPRQ)

to go into Sleep Mode. When in Sleep Mode, the msCAN12 stops its

internal clocks. However, clocks to allow register accesses still run. If the

msCAN12 is in bus-off state, it stops counting the 128*11 consecutive

recessive bits due to the stopped clock. The TxCAN pin stays in

recessive state. If RXF=1, the message can be read and RXF can be

cleared. Copying o f RxBG into RxFG d oes not take pl ace while in Sleep

Mode. It is possible to access the tran smit bu ffe rs and to clear the TXE

flags. No message abort takes place while in sleep mode.

The msCAN12 leaves Sleep mode (wake-up) when

•bus activity occurs or

•the MCU clears the SLPRQ bit or

•the MCU sets SFTRES.

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MSCAN Controller

Low Power Modes

MC68HC912DG128 — Rev 3.0 Technic al Data

MSCAN Controller

NOTE: The MCU cannot clear the SLPRQ bit before the msCAN12 is in Sleep

Mode (SLPAK = 1 ).

After wake-up , the msCAN12 waits f or 11 co nsecu tive recessive bits to

synchronize to the bus. As a consequence, if the msCAN12 is woken-up

by a CAN frame, this frame is not received. The receive message buffers

(RxBG and RxFG) contain messages if they were received before sleep

mode was entered. All pending actions are executed upon wake-up:

copying of RxBG into RxFG, message aborts and message

transmissions. If the msCAN12 is still in b us-off sta te after leavin g Sleep

Mode, it cont inues counting the 128*11 consecutive rec essive bits.

Figure 17-6. SLEEP Request / Acknowledge Cycle

17.8.2 msCAN12 SOFT_RESET Mode

In SOFT_RESET mode, the msCAN12 is stopped. Registers can still be

accessed. This mode is used to initialize the module configuration, bit

timing, and the CAN message filter. See ms CA N 12 Module Con tr o l

mode.

msCAN12 Sleeping

SLPRQ = 1

SLPAK = 1

msCAN12 Running

SLPRQ = 0

SLPAK = 0

SLEEP Request

SLPRQ = 1

SLPAK = 0

MCU

msCAN12

MCU

or m sCA N12

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MSCAN Controller

NOTE: When setting the SFTRES bit, the msCAN12 immediately stops all

ongoing transmissions and receptions, potentially causing the CAN

protocol violations. The user is responsiblefor ensuring that the

msCAN12 is not active when SOFT_RESET mode is entered. The

recomm ended procedure is to bring the msCAN12 in to SLEEP mode

before the SFTRES bit is set.

17.8.3 msCAN12 POWER_DOWN Mode

The msCAN12 is in POWER_DOWN mode when

•the CPU is in STOP mode or

•the CPU is in WAIT mode and the CSWAI bit is set (see msCAN12

Module Control Register 0 (CMCR0)).

When enteri ng the POWER_DOWN mode, the msCAN12 immediatel y

stops all ongoing transmissions and receptions, potentially causing CAN

protocol violations.

NOTE: The user is responsible to take care that the msCAN12 is not active

when POW ER_ DOWN mode is enter ed. The re comm ende d proce dure

is to bring the msCAN12 into SLEEP mode before the STOP instruction

(or the WAI instruction, if CSWAI is set) is executed.

To protect the CAN bus system from fatal consequenc es of violations to

the abo ve rule, th e msCAN12 d rives the TxCAN pin into re cessive state.

In POWER_DOWN mode, no registers can be accessed.

17.8.4 Programmable Wake-Up Function

The msCA N12 can be prog rammed to ap ply a low-pass filt er function to

the RxCAN input line while in SLEEP mode (see control bit WUPM in the

module control register, msCAN12 Module Control Register 0

(CMCR0)). This feature can be used to protect the msCAN12 from

wake-up due to short glitches on the CAN bus lines. Such glitches can

result f r om elect r omagn etic inte rference within noisy environments .

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MSCAN Controller

Timer Link

MC68HC912DG128 — Rev 3.0 Technic al Data

MSCAN Controller

17.9 Timer Link

The msCAN12 generates a timer signal whenever a valid frame has

been received. Because the CAN specification defines a frame to be

valid if no errors occurred before the EOF field has been transmitted

successfully, the timer signal is generated right after the EOF. A pulse of

one bit time is generated. As the msCAN12 receiver engine also

receiv es the frames bein g sent by itself, a timer sig nal is also generat ed

after a successful transmission.

The previously described timer signal can be routed into the on-chip

timer interface module (ECT). This signal is connected to the Timer n

Chann el input under the contr ol of the timer link enable ( TLNKEN) bi t in

the CMCR0(1).

After timer n has been programmed to capture rising edge events, it ca n

be used under software control to generate 16-bit time stamps which can

be stored with the received message.

17.10 Clock Syste m

Figure 17-7 shows the structure of the msCAN12 clock generation

circuitry. With this flexible clocking scheme the msCAN12 is able to

handle CAN bus rates ranging from 10 kbps up to 1 Mbps.

Figure 17-7. Clocking Scheme

1. The tim er channel be ing used for the timer link for CAN0 is channel 4 and for CAN1 is c hannel

msCAN12CGM

SYSCLK

EXTALi

CGMCANCLK Prescaler

(1...64)

Time quanta

clock

CLKSRC

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The clock source bit (CLKSRC) in the msCAN12 module control register

(CMC R1) (s ee msCAN12 Bus Timing Register 0 (CBTR0)) defines

whether the msCAN12 is connected to the output of the crystal oscillator

(EXTALi) or to a clock twice as fast as the system clock (ECLK).

The clock source has to be chosen such that the tight oscillator tolerance

requi rements (up to 0.4 %) of the CAN prot ocol are met. Add itionall y, for

high CAN bus rates (1 Mbps), a 50% duty cycle of the clock is required.

NOTE: If the system clock is generated from a PLL, it is recommend ed to select

the crystal clock source rather than th e system clock source due to jitter

consid eratio ns, especiall y at faster CAN bus rates.

For microcontrollers without the CGM module, CGMCANCLK is driven

from the crystal oscillator (EXTALi).

A programmable prescaler is used to generate out of msCA NCLK the

time quanta (Tq) clock. A time quantum is the atomic unit of time handled

by the ms CAN12.

A bit time is subdivided into three segments(1):

•SYNC_SEG: This segment has a fixed length of one time

quantum. Signal edges are expected to happen within this section.

•Time segment 1: This segment includes the PROP_SEG and the

PHASE_SEG1 of the CAN standard. It can be programmed by

setting the parameter TSEG1 to consist of 4 to 16 time quanta.

•Time segment 2: This segment represents the PHASE_SEG2 of

the CAN standard. It can be programmed by setting the TSEG2

parameter to be 2 to 8 time quanta long.

The synchronization jump width can be programmed in a range of 1 to 4

time quanta by setting the SJW parameter.

1. For furthe r exp la nati on of the und er-ly in g c onc ept s pl ea se re fer to ISO /D IS 115 19 -1, Sec tio n

10.3.

fTqfCGMCANCLK

Presc value

⋅

-------------------------------------------=

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MSCAN Controller

Clock System

MC68HC912DG128 — Rev 3.0 Technic al Data

MSCAN Controller

The above parameters can be set by programming the bus timing

registers (CBTR0–1, see msCAN12 Bus Timing Register 0 (CBTR0) and

msCAN12 Bus Timing Register 1 (CBTR1)).

NOTE: It is the user ’s responsibility to make sure that his bit time settings are in

complian ce with the CAN standard. Figure 17-9 gives an overview on

the CAN conforming segment settings and the related parameter values.

Figure 17-8. Segments within the Bit Time

Figure 17-9. CAN Standard Compliant Bit Time Segment Settings

Time Segment 1 TSEG1 Time Segment 2 TSEG2 Synchron.

Jump Width SJW

5 .. 10 4 .. 9 2 1 1 .. 2 0 .. 1

4 .. 11 3 .. 10 3 2 1 .. 3 0 .. 2

5 .. 12 4 .. 11 4 3 1 .. 4 0 .. 3

6 .. 13 5 .. 12 5 4 1 .. 4 0 .. 3

7 .. 14 6 .. 13 6 5 1 .. 4 0 .. 3

8 .. 15 7 .. 14 7 6 1 .. 4 0 .. 3

9 .. 16 8 .. 15 8 7 1 .. 4 0 .. 3

SYNC

_SEG Time segm ent 1 Time Seg. 2

1 4 ... 16 2 ... 8

8... 25 Time Quanta

= 1 Bit Time

NRZ Signal

Sample point

(single or triple sampling)

(PROP_SEG + PHASE_SEG1) (PHASE_SEG2)

Transmit point

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Technical Data MC68HC912DG128 — Rev 3.0

MSCAN Controller

17.11 Memory Map

The msCAN12 occupies 128 bytes in the CPU12 memory space. The

background receive buffer can only be read in test mode.

17.12 Prog rammer’s Model of Message Storage

The following section details the organisation of the receive and transmit

message buffers and the associated control registers. For reasons of

programmer interface simplification the receive and transmit message

buffers have the sa me out line. Each messa ge buffer al locates 16 bytes

in the memory map cont aining a 13 byte data structure. An add i tional

transmit buffer priority register (TB PR) is defined for the transmit buffers.

Figure 17-10. m sCAN12 Memory Map

$0100 Control registers

9 bytes

$0108

$0109 Reserved

5 bytes

$010D

$010E Error counters

2 bytes

$010F

$0110 Identi fie r filter

16 bytes

$011F

$0120 Reserved

29 bytes

$013C

$013D Port CAN registers

3 bytes

$013F

$0140 Foreground Receive buffer

$014F

$0150 Transmit buffer 0

$015F

$0160 Transmit buffer 1

$016F

$0170 Transmit buffer 2

$017F

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MSCAN Controller

Programmer’s Model of Mes sag e Stor ag e

MC68HC912DG128 — Rev 3.0 Technic al Data

MSCAN Controller

17.12.1 Message Buffer Outline

Figure 17-12 shows the common 13 byte data structure of receive and

transmit buffers for extended identifiers . The ma pping of standard

identif ie rs i nto th e ID R r egiste r s i s sh ow n i n Figure 17-13. All bits of the

13 byte data structure are undefined out of reset.

NOTE: The foreground receive buffer can be read anytime but cannot be

written. The transmit buffers can be read or written anytime.

Figure 17-11. Message Buffer Organization

Address

(1)

1. x is 4, 5, 6, or 7 depending on which buffer RxFG,

Tx0, Tx1, or Tx2 respectively.

01x0 Identifier register 0

01x1 Identifie r re gister 1

01x2 Identifie r re gister 2

01x3 Identifie r re gister 3

01x4 Data segment register 0

01x5 Data segment register 1

01x6 Data segment register 2

01x7 Data segment register 3

01x8 Data segment register 4

01x9 Data segment register 5

01xA Data segment register 6

01xB Data segment register 7

01xC Data length regis te r

01xD Transmit buffer priority register(2)

2. Not applicable for receive buffers

01xE Unused

01xF Unused

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Figure 17-12. Receive/Transmit Message Buffer Extended Identifier

ADDR(1) REGISTERR/WBIT 7654321BIT 0

$01x0 IDR0 RID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21

$01x1 IDR1 RID20 ID19 ID18 SRR (1) IDE (1) ID17 ID16 ID15

$01x2 IDR2 RID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7

$01x3 IDR3 RID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR

$01x4 DSR0 RDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

$01x5 DSR1 RDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

$01x6 DSR2 RDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

$01x7 DSR3 RDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

$01x8 DSR4 RDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

$01x9 DSR5 RDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

$01xA DSR6 RDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

$01xB DSR7 RDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

$01xC DLR RDLC3 DLC2 DLC1 DLC0

1. x is 4, 5, 6, or 7 depending on which buffer RxFG, Tx0, Tx1, or Tx2 respectively.

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Programmer’s Model of Mes sag e Stor ag e

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MSCAN Controller

17.12.2 Identifier Registers (IDRn)

The identifiers consist of either 11 bits (ID10–ID0) for the standard, or 29

bits (ID28–ID0) for the extended format. ID10/28 is the most significant

bit and is transmitted first on the bus during the arbitration procedure.

The priority of an identifier is defined to be highest for the smallest binary

number.

SRR — Substitute Remote Request

This fixed recessive bit is used only in extended format. It must be set

to 1 by the user for transmission buffers and will be stored as received

on the CAN bus for receive buffers.

IDE — ID Extended

This fla g indicates wheth er the extended or stand ard identif ier format

is applied in this buffer. In the case of a receive buffer the flag is set

as being received and indicates to the CPU how to process the buffer

identifier registers. In the case of a transmit buffer the flag indicates to

the msCAN12 what type of identifier to send.

0 = Standard format (11-bi t)

1 = Extended for m at (2 9- bi t)

Figure 17-13. Standard Identifier Mapping

ADDR(1) REGISTERR/WBIT 7654321BIT 0

$01x0 IDR0 RID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3

$01x1 IDR1 RID2 ID1 ID0 RTR IDE(0)

$01x2 IDR2 R

$01x3 IDR3 R

1. x is 4, 5, 6, or 7 depending on which buffer RxFG, Tx0, Tx1, or Tx2 respectively.

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RTR — Remote transmission request

This flag reflects the status of the Remote Transmission Request bit

in the CAN frame. In the case of a receive buffer it indicates the status

of the r eceived fra me and su pports the tr ansmissio n of an answ ering

frame in software. In the case of a transmit buffer, this flag defines the

setting of the RTR bit to be sent.

0 = Data frame

1 = Remote frame

17.12.3 Data Length Register (DLR)

This register kee ps the data length field of the CAN frame.

DLC3 – DLC0 — Data length code bits

The data length co de con tains the num ber of bytes ( data byte coun t)

of the respective message. At the transmission of a remote frame, the

data length code is transmitted as programmed while the number of

transmitted data bytes is always 0. The data byte count ranges from

0 to 8 for a data frame. Table 17-3 shows the effect of setting the DLC

bits.

Table 17-3. Data length codes

Data length code Data

byte

count

DLC3 DLC2 DLC1 DLC0

00000

00011

00102

00113

01004

01015

01106

01117

10008

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MSCAN Controller

17.12.4 Data Segment Regi sters ( D SRn)

The eight data segment registers contain the data to be transmitted or

being received. The number of bytes to be transmitted or being received

is determined by the data length code in the corresponding DLR.

17.12.5 Transmit Buffer Priority Registers (TBPR)

PRIO7 – PRIO0 — Local Priori ty

This field defi ne s the l oca l pr ior ity of the associat ed messa ge buffer.

The local priority is used for the internal prioritisation process of the

msCAN12 and is defined to be highest for the smallest binary number.

The msCAN12 implements the following internal prioritisation

mechanism:

•All transmission buffers with a cleared TXE flag participate in the

priori ti sa tion immed i ate ly bef or e t he SOF ( Sta r t of Fram e) i s sent.

•The transmission buffer with the lowest local priority field wins the

prioritisation.

•In cases of more than o ne bu ffer ha vin g the same l owe st p ri o rity,

the message buffer with the l ower index number wins.

NOTE: To ensure data integrity, no registers of the transmit buffers shall be

written while the associa ted TXE flag is cleared.

To ensur e da ta i nte gr it y, no r eg ister s o f the r ece ive b uff er sh al l b e read

while the RXF flag is cleared.

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

TBPR(1)

1. x is 5, 6, or 7 depending on which buffer Tx0, Tx1, or Tx2 respectively.

RPRIO7 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1 PRIO0

$01xD W

RESET - - - - - - - -

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17.13 Prog rammer’s Model of Control Registers

17.13.1 Overvi ew

The prog ram mer’s model has been laid out for maximum simplicity and

efficiency.

17.13.2 msCAN12 Module Control Register 0 (CMCR0)

CSWAI — CAN Stops in Wait Mode

0 = The module is not affected during WAIT mode.

1 = The module ceases to be clocked during WAIT mode.

SYNCH — Synchroniz ed Stat us

This bi t indi ca tes w h eth er the m sCA N 12 is syn chr on ized to the C AN

bus and as such can participate in the communication process.

0 = msCAN12 is not synchronized to the CAN bus

1 = msCAN12 is synchronized to the CAN bus

TLNKEN — Timer Enable

This flag is used to establish a link between the msCAN12 and the on-

chip timer (see Timer Link).

0 = The port is connected to the timer inpu t.

1 = The msCAN12 timer signal output is connected to the timer

input.

SLPAK — SLEEP Mode Acknowledge

This flag indicates whether the msCAN12 is in module internal

SLEEP Mode. It shall be used as a handshake for the SLEEP Mode

request (see msCAN12 SLEEP Mode).

0 = Wake-up – The msCAN12 is not in SLEEP Mode.

1 = SLEEP – The msCAN12 is in SLEEP Mode.

Bit 7654321Bit 0

CMCR0 R 0 0 CSWAI SYNCH TLNKEN SLPAK SLPRQ SFTRES

$0100 W

RESET 00100001

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Programmer’s Model of Control Registers

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MSCAN Controller

SLPRQ — SLEEP request

This fla g allows to request the ms CAN12 to go into an internal powe r-

saving mode (see msCAN12 SLEEP Mode).

0 = Wake-up – The msCAN12 will function normally.

1 = SLEEP re qu est – The msCAN12 will go into SLEEP Mode

when the CAN bus is idle, i.e. the module is not receiving a

message and all transmit buffers are empty.

SFTRES— SOFT_RESET

When this bit is set by the CPU, the msCAN12 immediately enters the

SOFT_RESET state. Any ongoing transmission or reception is

aborted and synchronisation to the bus is lost.

The followin g registers will go into and stay in the same state as out

of hard reset: CMCR0, CRFLG, CRIER, CTFLG, CTCR.

The registers CMCR 1, CBTR0, CBTR1, CIDAC, CIDAR0–3,

CIDMR0–3 can onl y b e w r itten by th e C P U w hen th e msCAN 1 2 i s in

SOFT_RESET state. The values of the error counters are not affected

by SOFT_RESET.

When this bit is cleared by the CPU, the msCAN12 will try to

synchronize to the CAN bus: If the msCAN12 is not in BUSOFF state

it will be synchronized after 11 recessive bits on the bus; if the

msCAN12 is in BUSOFF state it continues to wait for 128 occurrences

of 11 recessive bits.

Clearing SFTRES and writing to other bits in CMCR0 must be in

separate instructions.

0 = Normal operation

1 = msCAN12 in SOFT_RESET state.

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17.13.3 msCAN12 Module Control Register (CMCR1)

LOOPB — Loop Back Self Test Mode

When this bit is set the msCAN12 performs an internal loop back which

can be used for self test operation: the bit stream output of the

transmitter is fed back to the receiver internally. The RxCAN input pin

is ignored and the TxCAN output goes to the recessive state (1). The

msCAN12 behaves as it normally does while transmitting and treats its

own transmitted message as a message received from a remote node.

In this state the msCAN12 ignores the bit sent during the ACK slot of

the CAN frame Acknowledge field to ensure proper reception of its

own message. Both transmit and receive interrupts are generated.

0 = Normal operation

1 = Activate loop back self test mode

WUPM — Wake-Up Mode

This flag de fines w het her the in tegrate d low- p ass filte r is appli ed to

protect the msCAN12 f rom spurious wake-ups (see Programmable

Wake- U p Function).

0 = msCAN12 will wake up the CPU after any recessive to

dominant edge on th e CAN bus.

1 = msCAN12 will wake up the CPU only in the case of dominant

pulse on the b us which has a len gth of at least appr oximately

Twup.

CLKSRC — msCAN12 Clo ck Source

This flag defines which clock source the msCAN12 module is driven

from (only for system with CGM module; see Clock System, Figure

17-7).

0 = The msCAN12 clock source is EXTALi.

1 = The msCAN12 clock source is SYSCLK, twice the frequency of

ECLK.

NOTE: The CMCR1 register can be written only if the SFTRES bit in CMCR0 is

set.

Bit 7654321Bit 0

CMCR1 R 0 0 0 0 0 LOOPB WUPM CLKSRC

$0101 W

RESET 0 0 0 0 0 0 0 0

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Programmer’s Model of Control Registers

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MSCAN Controller

17.13.4 msCAN12 Bus Timing Register 0 (CBTR0)

SJW1, SJW0 — Synchronization Jump Width

The synchronization jump width defines the maximum number of time

quanta (Tq) clock cycles by which a bit may be shortened, or

lengthened, to achieve resynchronization on data transitions on the

bus (see Table 17-4).

BRP5 – BRP0 — Baud Rate Prescaler

These bits determine the time quanta (Tq) clock, which is used to

build up the individual bit timing, according to Table 17-5.

NOTE: The CBTR0 register can only be written if the SFTRES bit in CMCR0 is

set.

Bit 7654321Bit 0

CBTR0 R SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0

$0102 W

RESET 0 0000000

Table 17-4. Synchronization jump width

SJW1 SJW0 Synchronization jump width

0 0 1 Tq clock cycl e

0 1 2 Tq clock cycles

1 0 3 Tq clock cycles

1 1 4 Tq clock cycles

Table 17- 5. Baud rate prescaler

BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Prescaler value (P)

000000 1

000001 2

000010 3

000011 4

:::::: :

111111 64

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17.13.5 msCAN12 Bus Timing Register 1 (CBTR1)

SAMP — Sampling

This bit determines the number of samples of the serial bus to be

taken per bit time. If set three samples per bit are taken, the regular

one ( sample p oint) and two preced ing samp les, using a majori ty rule.

For higher bit rates SAMP should be cleared, which means that only

one sample will be taken per bit.

0 = One sample per bit.

1 = Three samples per bit(1).

TSEG22 – TSEG10 — Time Segment

Time segments within the bit time fix the number of clock cycles per

bit time, and the location of the sample point.

Time segment 1 (TSE G1) and t i me segment 2 (TSEG2) are

prog rammable as sh own in Table 17-7.

Bit 7654321Bit 0

CBTR1 R SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10

$0103 W

RESET 00000000

1. In this case, PHASE_SEG1 must be at least two time quanta.

Table 17-6. T i me se gm ent syntax

SYNC_SEG System expects transitions to occur on the bus during this period.

Transmit point A node in transmit mode will transfer a new value to the CAN bus at this point.

Sample poi nt A node in receive mode will sample the bus at this point. If the three samples per bit option is

selected then this point marks the position of the third sample.

Table 17-7. Time segment values

TSEG13 TSEG12 TSEG11 TSEG10 Time segment 1 TSEG2 2 TSEG21 TSEG20 Time segment 2

0 0 0 0 1 Tq clock c ycle 0 0 0 1 Tq clock cycle

0 0 0 1 2 Tq clock cycles 0 0 1 2 Tq clock cycles

0 0 1 0 3 Tq clock cycles . . . .

0 0 1 1 4 Tq clock cycles . . . .

. . . . . 1 1 1 8 Tq clock cycles

.... .

1 1 1 1 16 Tq clock cycles

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MC68HC912DG128 — Rev 3.0 Technic al Data

MSCAN Controller

The bi t time is determined by the oscillator fr equency, the baud rate

prescaler, and the number of time quanta (Tq) clock cycles per bit (as

shown abo ve) .

NOTE: The CBTR1 register can only be written if the SFTRES bit in CMCR0 is

set.

17.13.6 msCAN12 Receiver Flag Register (CRFLG)

All bits of th is r egister are rea d an d clear on ly. A flag can be cle ared by

writing a 1 to th e corresponding bi t position. A flag can only be cleared

when t he co nd i tion whi ch ca used th e setting is n o m o re vali d. W r iti ng a

0 has no effect on the flag setting. Every flag has an associated interrupt

enable flag in the CRIER register. A hard or soft reset clears the register.

WUPIF — Wake-up Interrupt Flag

If the msCAN12 de tects bus activity while in SLEEP Mode, it sets the

WUPIFflag. If not masked, a Wake - Up i nte rr u pt i s pendin g w h il e thi s

flag is set.

0 = No wake- up act ivit y ha s been o bserve d wh ile in SLEEP Mode .

1 = msCAN1 2 has det ecte d ac tivi ty on the bus and reque sted

wake-up.

RWRNIF — Receiver Warning Interrupt Flag

This flag is set when the msCAN 12 goes in to war ning status due to

the Receive Error counter (REC) exceeding 96 and neither one of the

Error interrupt flags or the Bus-Off interrupt flag is set(1). If not

masked, an Error inter rup t is pending while this flag is set.

0 = No receiver warning status has been reached.

1 = msCAN12 went in t o rec ei v er war n i ng status.

BitTime Presc value⋅

fCGMCANCLK

-------------------------------------------number

•of TimeQuantaÞÞ=

Bit 7654321Bit 0

CRFLG R WUPIF RWRNIF TWRNIF RERRIF TERRIF BOFFIF OVRIF RXF

$0104 W

RESET00000000

1. Condition to set the flag: RWRNIF = (96 < REC ≤ 127) & RERRIF& TERRIF & BOFFIF

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TWRNIF — Transm itter Warning Interrupt Flag

This flag is set when the msCAN 12 goes in to war ning status due to

the Transmit Error counter (TEC) exceeding 96 and neither one of the

Error interrupt flags or the Bus-Off interrupt flag is set(1). If not

masked, an Error inter rup t is pending while this flag is set.

0 = No transmitter warning status has been reached.

1 = msCAN12 went into transmitter warning status.

RERRIF — Receiver Error Passive Interrupt Flag

This flag is set when the msCAN12 goes into error passive status due

to the Receive Error counter (REC) exceeding 127 and the Bus-Off

interru pt fl ag is not set(2). If not masked, an Error interrupt is pending

while this flag is set.

0 = No receiver error passive status has been reached.

1 = msCAN1 2 went into recei v e r error passive status.

TERRIF — Transmitter Error Passive Interrupt Flag

This flag is set when the msCAN12 goes into error passive status due

to the Transmit Error counter (TEC) exceeding 127 and the Bus-Off

interru pt fl ag is not set(3). If not masked, an Error interrupt is pending

while this flag is set.

0 = No transmitter error passive status has been reached.

1 = msCAN12 went into transmitter error passive status.

BOFFIF — BUSOFF Interrupt Flag

This flag is set when the msCAN12 goes into BUSOFF status, due to

the Transmit Error counter exceeding 255. It cannot be cleared before

the msCAN12 has monitored 128 times 11 consecutive recessive bits

on the bus. If not masked, an Error interrupt is pending while this flag

is set.

0 = No BUSOFF status has been re ach ed.

1 = msCAN12 went in t o BUSOF F s tat u s .

1. Condition to set the flag: TWRNIF = (96 < TEC ≤ 127) & RERRIF& TERRIF & BOFFIF

2. Condition to set the flag: RER RIF = (128 < REC < 255) & BOFFI F

3. Condition to set the flag: TERRIF = (128 < TEC < 255) & BOFFIF

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Programmer’s Model of Control Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

MSCAN Controller

OVRIF — Overrun Interrupt Flag

This fla g is set wh en a data ove r ru n con di ti o n occu r s. If no t m aske d,

an Error interrupt is pending while this flag is set.

0 = No data overrun ha s occu rred.

1 = A da ta overrun has be en detected.

RXF — Receive Buffer Full

The RXF flag is set by the msCAN12 when a new message is

available in the foregrou nd receive buffer. This flag indicates whether

the buffer is loaded with a correctly received message. After the CPU

has rea d tha t m essa ge f ro m the r ece i ve bu ffe r the RXF fla g m ust b e

handshaken (cleared) in order to release the buffer. A set RXF flag

proh ibits th e exchange of the background receive b uffer i nto the

foreground buffer. If not masked, a Receive interrupt is pending while

this flag is set.

0 = The receive buffer is released (not full).

1 = The receive buffer is full. A new message is available.

WARNING: To ensure da ta i nte gr ity, no r eg ister s o f the r ece ive b uff er sh al l be re ad

while the RXF flag is cleared.

NOTE: The CRFLG register is held in the reset state when the SFTRES bit in

CMCR0 is set.

17.13.7 msCAN12 Receiver Interrupt Enable Register (CRIER)

WUPIE — Wake-up Interrupt Enable

0 = No interruptis generated from this event.

1 = A wake-up even t results in a wake-up interrupt.

RWRNIE — Receiver Warning Interrupt Enable

0 = No interruptis generated from this event.

1 = A receiver warning status event results in an error interrupt.

Bit 7654321Bit 0

CRIER R WUPIE RWRNIE TWRNIE RERRIE TERRIE BOFFIE OVRIE RXFIE

$0105 W

RESET 00000000

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TWRNIE — Transmitter Warning Interrupt Enable

0 = No interruptis generated from this event.

1 = A transmitter warning status event results in an error interrupt.

RERRIE — Receiver Error Passive Interrupt Enable

0 = No interruptis generated from this event.

1 = A receiver error passive status event results in an error

interrupt.

TERRIE — Transmitter Error Passive Interrupt Enab le

0 = No interruptis generated from this event.

1 = A transmitter error passive status event results in an error

interrupt.

BOFFIE — BUSOFF Interrupt Enable

0 = No interruptis generated from this event.

1 = A BU SOFF event results in an error interrupt.

OVRIE — Overrun Interrupt Enable

0 = No interruptis generated from this event.

1 = An ov errun event results in an error interrupt.

RXFIE — Receiver Full Interrupt Enable

0 = No interruptis generated from this event.

1 = A receive buffer full (successful message reception) event

results in a receive interrupt.

NOTE: The CRIER register is held in the reset state when the SFTRES bit in

CMCR0 is set.

17.13.8 msCAN12 Transmitter Flag Register (CTFLG)

The Abort Acknowledge flags are read only. The Transmitter Buffer

Empty f lags are re ad a nd clear only. A flag can b e cle ared by w rit ing a1

to the corresponding bit position. Writing a zero has no effect on the flag

setting. The Transmitter Buffer Empty flags each have an associated

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MSCAN Controller

interrupt enable flag in the CTCR register. A hard or soft reset will reset

the register.

ABTAK2 – ABTAK0 — Abort Acknowledge

This flag acknowledges that a message has been aborted due to a

pending abort request from the CPU. After a particular message

buffer has been flagged empty, this flag can be used by the

application softw are to identify whet her the m essage has been

aborted successfully or has been sent in the meantime. The ABTAKx

flag is cleared implicitly whenever the corresponding TXE flag is

cleared.

0 = The massage has not been ab or ted , thus has bee n sent out.

1 = The messa ge has been aborted.

TXE2 – TXE0 —Transmitter Buffer Empty

This flag indicates that the associated transmit message buffer is

empty, thus not scheduled for transmission. The CPU must

handshake (clear) the flag after a message has been set up in the

transmit buffer and is due for transmission. The msCAN12 sets the

flag after the message has been sent successfully. The flag is also set

by the msCAN12 when the transmission request was successfully

aborted due to a pending abort request (msCAN12 Transmitter

Control Register (CTCR)). If not masked, a transmit interrupt is

pending while this flag is set.

Clearing a TXEx flag also clears the corresponding ABTAKx flag (see

above). When a TXEx flag is set, the corresponding ABTRQx bit is

cleared (see msCAN12 Transmitter Control Register (CTCR)).

0 = The associated message buffer is full (loaded with a message

due for transmission).

1 = The associated messa ge buffe r is empty (not schedul e d).

WARNING: To ensure data integrity, no registers of the transmit buffers should be written

to while the associated TXE fla g is cleared.

Bit 7654321Bit 0

CTFLG R 0 ABTAK2 ABTAK1 ABTAK0 0 TXE2 TXE1 TXE0

$0106 W

RESET 0 0 0 0 0 1 1 1

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NOTE: The CTFLG register is held in the reset state if the SFTRES bit in

CMCR0 is set.

17.13.9 msCAN12 Transmitter Control Register (CT CR)

ABTRQ2 – ABTRQ0 — Abort Request

The CPU sets an ABTRQx bit to request that a scheduled message

buffer (TXEx = 0) shall be aborted. The msCAN12 grants the request

if the message has not already started transmission or if the

transmission is not succ essfu l (lost ar bitration or error). When a

message is aborted, the associated TXE and the Abort Acknowledge

flag (ABTAK , see msCA N12 Tran smitter Flag Registe r (CTFLG) ) are

set and an TXE interrupt is generated if enabled. The CPU cannot

reset ABTRQx. ABTRQx is cleared implicitly whenever the

associated TXE flag is set.

0 = No abort request.

1 = Abort request pending.

NOTE: The software must not clear one or more of the TXE flags in CTFGL and

simultaneously set the respective ABTRQ bit(s).

TXEIE2 – TXEIE0 — Transmitter Empty Interru pt Ena ble

0 = No interruptis generated from this event.

1 = A transmitter empty (tra nsmit buffer ava ilable fo r transmissi on)

event results in a transmitter empty interrupt.

NOTE: The CTCR register is held in the reset state when the SFTRES bit in

CMCR0 is set.

Bit 7654321Bit 0

CTCR R 0 ABTRQ2 ABTRQ1 ABTRQ0 0TXEIE2 TXEIE1 TXEIE0

$0107 W

RESET 0 0 0 0 0 0 0 0

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Programmer’s Model of Control Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

MSCAN Controller

17.13.10 msCAN1 2 Identifier Accepta nce Control Register (CIDAC)

IDAM1 – IDAM0 — Identifier Acceptan ce Mo de

The CPU sets these flags to define the identifier acceptance filter

orga nisati on (see Identifier Acceptance Filter). Table 17-7

summarizes the different settings. In Filter Closed mode no

messages are accepted such that the foreground buffer is never

reloaded.

IDHIT2 – IDHIT0 — Identifier Acceptance Hit Indicator

The msCAN12 sets these flags to indicate an identifier acceptance hit

(see Identifier Acceptance Filter). Table 17-7 summarizes the

different settings.

The IDHIT indicators are always related to the message in the

foreground buffer. When a message gets copied from the background to

the foreground buffer the indicators are updated as well.

NOTE: The CIDAC reg ister can only be written if the SFTRES bit in CMCR0 is

set.

Bit 7654321Bit 0

CIDAC R 0 0 IDAM1 IDAM0 0 IDHIT2 IDHIT1 IDHIT0

$0108 W

RESET 0 0 0 0 0 0 0 0

Table 17-8. Identifier Acceptance Mode Settings

IDAM1 IDAM0 Identifier Acceptance Mode

0 0 Two 32 bit Acceptance Filters

0 1 Four 16 bit Acceptance Filters

1 0 Eight 8 bit Acceptance Filters

1 1 Filter Closed

Table 17-9. Identifier Acceptance Hit Indication

IDHIT2 IDHIT1 IDHIT0 Identifier Acceptance Hit

000 Filter 0 Hit

001 Filter 1 Hit

010 Filter 2 Hit

011 Filter 3 Hit

100 Filter 4 Hit

101 Filter 5 Hit

110 Filter 6 Hit

111 Filter 7 Hit

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17.13.11 msCAN1 2 Receive Error Counter (CRXERR)

This regi ste r re flects the status of the msC A N1 2 re cei ve er ro r counte r.

The register is read only.

17.13.12 msCAN1 2 Transmit Error Counter (C TXERR)

This re gi ste r reflects the stat us o f the msC AN1 2 tr an sm it er r or counter .

The register is read only.

NOTE: Both error counters must only be read when in SLEEP or SOFT_RESET

mode.

17.13.13 msCAN1 2 Identifier Accepta nce Registers (CIDAR0–7)

On reception each message is written into the background receive

buffer. The CPU is only signalled to read the message however, if it

passes the criteria in the identifier acceptance and identifier mask

regist ers (acc epte d); otherwise, the messa ge is overwritte n by the next

message (dropped).

The acceptance registers of the msCAN12 are applied on the IDR0 to

IDR3 registers of incoming messages in a bit by bit manner.

For extended identifiers all four acceptance and mask registers are

applied. For standard identifiers only the first two (CIDMR0/1 and

CIDAR0/1) are a pp lied. In the latter case it is required to pr ogram the

three la st bits ( AM2 – AM0) in the mask register CIDMR1 to ‘don’t care’.

Bit 7654321Bit 0

CRXERR R RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0

$010E W

RESET 00000000

Bit 7654321Bit 0

CTXERR R TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0

$010F W

RESET 0 0000000

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Programmer’s Model of Control Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

MSCAN Controller

AC7 – AC0 — Acceptance Code Bits

AC7 – AC0 compri se a user define d seq uence of bits wit h wh ic h the

corresponding bits of the related identifier register (IDRn) of the

receiv e message buffe r ar e comp ared . The resu lt of this co mpari son

is then masked with the corresponding identifier mask register.

NOTE: The CIDAR0–7 registers can only be written if the SFTRES bit in

CMCR0 is set.

17.13.14 msCAN1 2 Identifier Mask Re gisters (CIDMR0–7)

The identifier mask register specifies which of the corresponding bits in

the identifier acceptance register are relevant for acceptance filtering. To

receiv e stand ard identi fiers i n 32 bit fi lter m ode it is r equir ed to prog ram

the last three bits (AM2–AM0) in the mask registers CIDMR1 and

Figure 17-14. Identifier Acceptance Register s (1st bank)

Bit 7654321Bit 0

CIDAR0 R AC7AC6AC5AC4AC3AC2AC1AC0

$0110 W

CIDAR1 R AC7AC6AC5AC4AC3AC2AC1AC0

$0111 W

CIDAR2 R AC7AC6AC5AC4AC3AC2AC1AC0

$0112 W

CIDAR3 R AC7AC6AC5AC4AC3AC2AC1AC0

$0113 W

RESET--------

Figure 17-15. Identifier Acceptance Registers (2nd bank)

Bit 7654321Bit 0

CIDAR4 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0

$0118 W

CIDAR5 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0

$0119 W

CIDAR6 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0

$011A W

CIDAR7 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0

$011B W

RESET--------

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MSCAN Controller

CIDMR5 to ‘don’t care. To receive standard identifiers in 16 bit filter

mode it is required to program the last three bits (AM2–AM0) in the mask

registers CIDMR1, CIDMR3, CIDMR5 and CIDMR7 to ‘don’t care

AM7 – AM0 — Acceptance Mask Bits

If a particular bit in this register is cleared this indicates that the

corresponding bit in the identifier acceptance register must be the

same as i ts ident ifier bi t, before a m atch is d etected. The me ssage is

accepted if all such bits match. If a bit is set, it indicates that the state

of the cor respondi ng bit in t he iden tifier acce ptance regi ster does no t

affect whether or not the message is accepted.

0 = Match corresponding acceptance code register and identifier bits.

1 = Ignore corresponding acceptance code register bit.

NOTE: The CIDMR0 –7 registers can only be written if the SFTRES bit in

CMCR0 is set.

Figure 17-16. Ident if ier Ma sk Regis ter s (1 st bank)

Bit 7654321Bit 0

CIDMR0 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0

$0114 W

CIDMR1 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0

$0115 W

CIDMR2 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0

$0116 W

CIDMR3 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0

$0117 W

RESET--------

Figure 17-17. Identifier Mask Registers (2nd bank)

Bit 7654321Bit 0

CIDMR4 R AM7AM6AM5AM4AM3AM2AM1AM0

$011C W

CIDMR5 R AM7AM6AM5AM4AM3AM2AM1AM0

$011D W

CIDMR6 R AM7AM6AM5AM4AM3AM2AM1AM0

$011E W

CIDMR7 R AM7AM6AM5AM4AM3AM2AM1AM0

$011F W

RESET--------

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MSCAN Controller

17.13.15 msCAN1 2 Port CAN Control Register (PCTLCAN)

The following bits control pins 7 through 2 of Port CAN when they are

implemented externally.

PUPCAN — Pull-Up Enable Port CAN

0 = Pull mode disabled for Port CAN.

1 = Pull mod e enabled for Por t CA N .

RDPCAN — Reduced Drive Port CAN

0 = Reduced drive disabled for Port CAN.

1 = Reduced dri ve ena bl ed for Por t CAN.

17.13.16 msCAN1 2 Port CAN Data Register (PORTCAN )

Port bits 7 to 2 will read zero when configured as inputs because they

are not implemented externally.

When configured as output, port bits 7 to 2 will read the last value

written.

Reading bits 1 and 0 returns the value of the TxCan and RxCan pins,

respectively.

17.13.17 msCAN1 2 Port CAN Data Direction Register (DDRCAN)

DDCAN7 – DDCAN2 — This bits served as me mory locations since

there are no corresponding external port pins.

Bit 7654321Bit 0

PCTLCANR000000

PUPCAN RDPCAN

$013D W

RESET 0 0000000

Bit 765432 1Bit 0

PORTCAN R PCAN7 PCAN6 PCAN5 PCAN4 PCAN3 PCAN2 TxCAN RxCAN

$013E W

RESET -----

Bit 7654321Bit 0

DDRCAN R DDCAN7 DDCAN6 DDCAN5 DDCAN4 DDCAN3 DDCAN2 00

$013F W

RESET00000000

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MSCAN Controller

Technical Data MC68HC912DG128 — Rev 3.0

MSCAN Controller

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MC68HC912DG128 — Rev 3.0 Technic al Data
Development Support
 
Technical Data — MC68HC912DG128
Section 18. Development Support
18.1  Contents
18.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355
18.3 Instruction Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355
18.4 Background Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .357
18.5 Breakpoints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375
18.6 Instruction Tagging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382
18.2  Introduction
Developm ent support involves complex interactions betwe en  
MC68HC912DG128 resources and external development systems. The 
following section concerns instruction queue and queue tracking signals, 
background debug mode, and instruction tagging. 
18.3  Instruction Queue
The CPU12 instruction queue provides at least three bytes of program 
information to the CPU when instruction execution begins. The CPU12 
always com pletel y fin ishes ex ecuting  an in structio n befo re be ginnin g t o 
execute the next instruction. Status signals IPIPE[1:0] provide 
information about data movement in the queue and indicate when the 
CPU begins to execute instructions. This makes it possible to monitor 
CPU activity on a cycle-by-cycle basis for debugging. Information 
available on the IPIPE[1:0] pins is time multiplexed. External circuitry 
can latch data movement information on rising edges of the E-clock 
signal; execution start information can be latched on falling edges. Table 
18-1 shows the meaning of data on the pins.
    
  
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Development Support

Technical Data MC68HC912DG128 — Rev 3.0

Development Support

Program information is fetched a few cycles before it is used by the CPU.

In order to monitor cycle-by-cycle CPU activity, it is necessary to

externally reconstruct what is happening in the instruction queue.

Internally the MCU only needs to buffer the data from prog ram fetch es.

For system debug it is necessary to keep the data and its associated

address in the reconstructed instruction queue. The raw signals required

for rec onstruction of the queue are ADDR, DATA, R/W, ECLK, and

status signals IPIPE[1:0].

The instruct ion queue consists of two 16 -bit queue stages and a holding

latch on the input of the first stage. To advance the queue means to

move th e word in th e first stage to th e second st age and mo ve the wo rd

from either the holding latch or the data bus input buffer into the first

stage. To start even (or odd) instruction means to execute the opcode in

the hig h-or de r (or lo w -or der ) byte of the secon d stag e of the i nstr u ction

queue.

Table 18-1. IPIPE Decoding

Data Movement — IPIPE[1:0] Captured at Rising Edge of E Clock(1)

1. Refers to data that was on the bus at the previous E falling edge.

IPIPE[1:0] Mnemonic Meaning

0:0 —No Movement

0:1 LAT Latch Data From Bus

1:0 ALD Advance Queue and Load From Bus

1:1 ALL Advance Queue and Load From Latch

Execution Start — IPIPE[1:0] Captured at Falling Edge of E Clock(2)

2. Refers to bus cycle starting at this E falling edge.

IPIPE[1:0] Mnemonic Meaning

0:0 —No Start

0:1 INT Start Interrupt Sequence

1:0 SEV Start Even Instruction

1:1 SOD Start Odd Instruction

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Background Debug Mode

MC68HC912DG128 — Rev 3.0 Technic al Data

Development Support

18.4 Background Debug Mode

Background debug mode (BDM) is used for system development, in-

circuit testing, field testing, and programming. BDM is implemented in

on-chip hardware and provides a full set of debug options.

Becaus e BDM co ntrol lo gic do es not r eside in t he CP U, BD M hard ware

commands can be executed while the CPU is operating normally. The

control logic generally uses free CPU cycles to execute these

commands, but can steal cycles from the CPU when necessary. Other

BDM commands are firmware based, and require the CPU to be in active

background mode for execution. While BDM is active, the CPU executes

a firmware prog ram located in a small on-chip ROM th at is available in

the standard 64-Kbyte memory map only while BDM is active.

The BDM control logic communicates with an external host development

system serially, via the BKG D pin. This single-wire app roach minimizes

the number of pins needed for development support.

18.4.1 Enabling BDM Firmware Commands

BDM is available in all operating modes, but must be made active before

firmware commands can be executed. BDM is enabled by setting the

ENBDM bit in the BDM STATUS register via the single wire interface

(using a hardware command; WRITE_BD_BYTE at $FF01). BDM must

then be act iva ted to m ap BDM re gi ste rs an d ROM to ad dr esse s $FF00

to $FFFF and to put the MCU in active background mode.

After the firmware is enabled, BDM can be activated by the hardware

BACKGROUND command, by the BDM tagging mechanism, or by the

CPU BGND instruction. An attempt to activate BDM before firmware has

been enabled causes the MCU to resume normal instruction execution

after a brief delay.

BDM be comes active at the next instruction bo undary following

execution of the BDM BACKGROUND command, but tags activate BDM

before a tagged instruction is executed.

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In special single-chip mode, background operation is enabled and active

immediately out of rese t. This acti ve case replaces the M68HC11 bo ot

function, and allows programming a system with blank memory.

While BDM is acti ve , a set of BDM cont ro l registe r s are mapp ed to

addre sses $FF00 to $FF06. The BDM control lo gic uses these r egisters

which can be read anytime by BDM log i c, not us er prog r ams. Ref er to

BDM Registers for detailed descriptions.

Some on-chip p eripherals have a BDM control bit which allows

suspending the peripheral function during BDM. For example, if the timer

control is enabled, the timer counter is stopped while in BDM. Once

normal program flow is continued, the timer counter is re-enabled to

simulate real-time operations.

18.4.2 BDM Serial Interface

The BDM serial interface requires the external controller to generate a

falling edge on the BKGD pin to indicate the start of each bit time. The

external controller provides this falling edge whether data is transmitted

or received.

BKGD is a pseudo-open-drain pin that can be driven either by an

external controller or by the MCU. Data is transfe rre d MSB first at 16 B-

clock cycles per bit (nominal speed). The interface times out if 512 B-

clock cycles occur between falling edges from the host. The hardware

clears the command register when a time-out occurs.

The BKGD pin can receive a high or low level or transmit a high or low

level. The following di agrams show timing for eac h of th ese cases.

Interface t iming is synchronous to MCU clocks but asyn chronou s to the

external host. The internal clock signal is shown for reference in counting

cycles.

Figure 18-1 shows an external host transmitting a logic one or zero to the

BKGD pin of a target MC68HC912DG128 MCU. The host is

asynchronous to the target so there is a 0-to-1 cycle delay from the host-

generated falling edge to where the target perceives the beginning of the

bit time. Ten target B cycles later, the target senses the bit level on the

BKGD pin. Typically th e host actively drives the pseudo-ope n-drain

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BKGD pi n during host-to-tar get transmissi ons to spee d up r ising edges.

Since th e target does n ot drive the BKGD pi n during this p eriod, there is

no need to treat the line as an open-drain signal during host-to-target

transmissions.

Figure 18-1. BDM Host to Target Serial Bit Timing

Figure 18-2. BDM Target to Host Serial Bit Timing (Logic 1)

10 CYCLES

B CLOCK

(TARGET MCU)

HOST

TRANSMIT 1

TARGET SENSES BIT

EARLIEST

START OF

NEXT BIT

SYNCHRONIZATION

UNCERTAINTY

PERCEIVED

START

OF BIT TIME

HOST

TRANSMIT 0

10 CYCLES

B CLOCK

(TARGET

MCU)

EARLIEST

START OF

NEXT BIT

BKGD PIN

PERCEIVED

START OF BIT

TIME

10 CYCLES

HOST SAMPLES

BKGD PIN

HOST

DRIVE TO

BKGD PIN

TARGET MCU

SPEEDUP PULSE

R-C RISE

HIGH-IMPEDANCE

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Figure 18-2 shows the host receiving a logic one from the target

MC68HC912DG128 MCU. Since the host is asynchronous to the target

MCU, there is a 0-to-1 cycle delay from the host-generated falling edge

on BKGD to the perceived start of the bit time in the target MCU. The

host holds the BKGD pin low long enough fo r the target to recognize it

(at least two target B cycles). The host must release the low drive before

the target MCU drives a brief active-high speed-up pulse seven cycles

after the perceived start of the bit time. The host should sample the bit

level about ten cycles after it started the bit time.

Figure 18-3. BDM Target to Host Serial Bit Timing (Logic 0)

Figure 18-3 shows the host receiving a logic zero from the target

MC68HC912DG128 MCU. Since the host is asynchronous to the target

MCU, there is a 0-to-1 cycle delay from the host-generated falling edge

on BKGD to the start of the bit time as perceived by the target MCU. The

host initiates the bit time but the target MC68HC912DG128 finishes it.

Since the target wants the host to receive a logic zero, it drives the

BKGD pin low for 13 B-clock cycles, then briefly drives it high to speed

up the rising edge. The host sa mples t he bit le vel about te n cycles af ter

starting the bit time.

10 CYCLES

B CLOCK

(TARGET

MCU)

EARLIEST

START OF

NEXT BIT

BKGD PIN

PERCEIVED

START OF BIT TIME

10 CYCLES

HOST SAMPL ES

BKGD PIN

HOST

DRIVE TO

BKGD PIN

TARGET MCU

DRIVE AND

SPEEDUP PULSE

HIGH-IMPEDANCE

SPEEDUP PULSE

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18.4.3 BDM Commands

The BDM command set consists of two types: hardware and firmware.

Hardware commands allow target system memory to be read or written.

Target system memory includes all memory that is accessible by the

CPU12 including EEPROM, on-chip I/O and control registers, and

external memory that is connected to the target HC12 MCU. Hardware

commands are implemented in hardware logic and do not require the

HC12 MCU to be in BDM mode for execution. The control logic watches

the CPU12 buses to find a free bus cycle to execute the command so the

background access does not disturb the running application programs.

If a free cycle is not found within 128 B-clock cycles, the CPU12 is

momentarily frozen so the control logic can steal a cycle. Commands

implemented in BDM control logic are listed in Table 18-2.

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The second type of BDM comm ands ar e firmware commands

implemented in a small ROM within the HC12 MCU. The CPU must be

in back gr ou nd mo de to exec ute fir mwa re com m an ds. Th e u sual way to

get to background mode is by the hardware command BACKGROUND.

The BDM ROM is located at $FF20 to $FFFF while BDM is active. There

are also seven by tes of BDM registe rs located a t $FF00 to $ FF06 when

BDM is active. The CPU exec utes code in the BDM firm ware to perfor m

the requested operation. The BDM firmware watc hes for serial

commands and executes them as they are received. The firmware

commands are shown in Table 18-3.

Table 18-2. Hardware Commands(1)

Command Opcode (Hex) Data Description

BACKGROUND 90 None Enter background mode if firmware enabled.

READ_BD_BYTE(1) E4 16-bit address

16-bit data out

Read from memory with BDM in map (may steal

cycles if external access) data for odd address on

low byte, data for even address on high byte.

READ_BD_WORD(1) EC 16-bit address

16-bit data out Read from memory with BDM in map (may steal

cycles if external access). Must be aligned access.

READ_BYTE E0 16-bit address

16-bit data out

Read from memory with BDM out of map (may steal

cycles if external access) data for odd address on

low byte, data for even address on high byte.

READ_WORD E8 16-bit address

16-bit data out Read from memory with BDM out of map (may steal

cycles if external access). Must be aligned access.

WRITE_BD_BYTE(1) C4 16-bit address

16-bit data in

Write to memory with BDM in map (may steal cycles

if external access) data for odd address on low byte,

data for even address on high byte.

WRITE_BD_WORD(1) CC 16-bit address

16-bit data in Write to memory with BDM in map (may steal cycles

if external access). Must be aligned access.

WRITE_BYTE C0 16-bit address

16-bit data in

Write to memory with BDM out of map (may steal

cycles if external access) data for odd address on

low byte, data for even address on high byte.

WRITE_WORD C8 16-bit address

16-bit data in Write to memory with BDM out of map (may steal

cycles if external access). Must be aligned access.

1. Use these commands only for reading/writing to BDM locations

The BDM firmware ROM and BDM registers are not normally

in the HC12 MCU memory map

Since these location s have the same addres ses as som e of the normal application memory

map, there needs to be a way to decide which physica l locations are being accessed by the hardw are BDM commands

This

gives rise to needing separate memory access commands for the BDM locations as opposed to the normal application lo-

cations

In logic, this is accomp lished by momentarily enabling the BDM memory resources, just for the access cy cles of the

READ_BD and W R ITE_BD com m and s

This logic allows the debugging system to unobtrusively access the BD M locations

even if the application program is running out of the same memory area in the normal application memory map

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Each of the hardware and firmware BDM commands start with an 8-bit

command code (opcode). Depending upon the commands, a 16-bit

address and/or a 16-bit data word is required as indicated in the tables

by the comm an d. Al l the r ead com m an ds o utp ut 16- b its of dat a despit e

the byte/word implication in the command name.

The external host sh ould wait 150 BCLK cycles for a non-intrusive B DM

command to execute before another command is sent. This delay

includes 128 BCLK cycles for the maximum delay for a free cycle. For

data read commands, the host must insert this delay between sending

the address and attempting to read the data. In the case of a write

command, the host must delay after the data portion before sending a

new command to be sure that t he write has finished.

The externa l host sho uld delay about 32 targe t BCLK cycles betwe en a

firmware read command and the data portion of these commands. This

allows the BDM firmware to execute the instructions needed to get the

requested data into the BDM SHIFTER register.

Ta ble 18-3. BDM Firmware Commands

Command Opcode

(Hex) Data Description

READ_NEXT 62 16-bit data out X = X + 2; Read next word pointed to by X

READ_PC 63 16-bit data out Read program counter

READ_D 64 16-bit data out Read D accumulator

READ_X 65 16-bit data out Read X index register

READ_Y 66 16-bit data out Read Y index register

READ_SP 67 16-bit data out Read stack pointer

WRITE_NEXT 42 16-bit data in X = X + 2; Write next word pointed to by X

WRITE_PC 43 16-bit data in Write program counter

WRITE_D 44 16-bit data in Write D accumulator

WRITE_X 45 16-bit data in Write X index register

WRITE_Y 46 16-bit data in Write Y index register

WRITE_SP 47 16-bit data in Write stack pointer

GO 08 None Go to user program

TRACE1 10 None Execute one user instruction then return to

BDM

TAGGO 18 None Enable tagging and go to user program

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The external host should delay about 32 target BCLK cycles after the

data portion of firmware write commands to allow BDM firmware to

complete the requested write operatio n before a new serial command

disturbs the BDM SHIFTER register.

The external host should delay about 64 target BCLK cycles after a

TRACE1 or GO command before starting any new serial command. This

delay is needed because the BDM SHIFTER register is used as a

temporary data holding register during the exit sequence to user code.

BDM logic retains control of the internal buses until a read or write is

completed. If an operation can be completed in a single cycle, it does not

intrude on normal CPU12 operation. However, if an operation requires

multiple cycles, CPU12 clocks are frozen until the operation is complete.

18.4.4 BDM Lockout

The access to the MCU resources by BDM may be prevented by

enabling the BDM lockout feature. When enabled, the BDM lockout

mechanism prevents the BDM from being active. In this case the BDM

ROM is disabled and does not appear in the MCU memory map.

BDM lockout is enabled by clearing NOBDML bit of EEMCR register.

The NOBDML bit is loaded at reset from the SHADOW byte of EEPROM

module. Modifying the state of the NOBDML and corresponding

EEPROM SHADOW bit is only possible in special modes.

Please refer to EEPROM Memory for NOBDML information.

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18.4.4.1 Enabling BDM lockout

Enabl ing the BDM lockout fea tur e is onl y possib le in specia l mode s

(SMODN=0) and is accomplished by the following steps.

1. Remove the SHADOW byte protection by clearing SHPROT bit in

EEPROT register.

2. Clear NOSHB bit in EEMCR register to make the SHADOW byte

visible at $0FC0.

3. Program bit 7 of the SHADOW byte like a regular EEPROM

location at address $0FC0 (write $7F into address $0FC0). Do not

prog ram oth er bits of the SHADOW byte (location $0FC0);

otherwise some regular EEPROM array locations will not be

visible. At the next reset, the SHADOW byte is loaded into the

EEMCR register. NOBDML bit in EEMCR will be cleared and BDM

will not be operational.

4. Protect the SHADOW byte by setting SHPROT bit in EEPROT

18.4.4.2 Disabling BDM lockout

Disabling the BDM lockout is only possible in special modes

(SMODN=0). Follow the same steps as for enabling the BDM lockout,

but erase the SHADOW byte.

At the next reset, the SHADOW byte is load ed into the EEMCR register.

NOBDML bit in EEMCR will be set and BDM becomes operati on al.

NOTE: When the BDM lo ckout is e nabled it is not possibl e to ru n code fr om the

reset vector in special single chip mode.

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18.4.5 BDM Registers

Seven BDM registers are mapped into the standard 64-Kbyte address

space when BDM is active. Mapping is shown in Table 18-4.

•The INSTRUCTION register content is determined by the type of

background command being executed.

•The STATUS register indicates BDM operating conditions.

•The SHIFT regi ste r con tains data being rece iv ed or tran sm it ted

via the serial interface.

•The ADDRESS registe r is temporary storage for BDM commands.

•The CCRSAV register preserves the content of the CPU12 CCR

while BDM is active.

The only regi st er s of in ter e st to use rs ar e th e STATUS r eg is ter and the

CCRSAV register. The other BDM registers are only used by the BDM

firmware to execute commands. The registers are accessed by means

of the hardware READ_BD and WRITE_BD commands, but should not

be written during BDM operation (except the CCRSAV register which

could be written to modify the CCR value).

Table 18-4. BDM registers

Address Register

$FF00 BDM Instruction Register

$FF01 BDM Status Register

$FF02 – $FF03 BDM Shift Register

$FF04 – $FF05 BDM Address Register

$FF06 BDM CCR Holding Register

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18.4.5.1 STATUS

The STATUS registe r is read and written by the BDM hardware as a

result of serial data shifted in on the BKGD pin.

Read: all modes.

Write: Bits 3 through 5, and bit 7 are writable in all modes. Bit 6,

BDMACT, can only be written if bit 7 H/F in the INSTRUCTION register

is a zero. Bit 2, CLKSW, can only be written if bit 7 H/F in the

INSTRUCTION register is a one. A user would never w r ite one s to bits

3 through 5 because these bits are only used by BDM firmware.

ENBDM — Enable BDM (permit active background debug mode)

0 = BDM cannot be made active (hardware commands still

allowed).

1 = BDM can be made active to allow firmware commands.

BDMACT — Background Mo de Active Status

BDMACT becomes set as active BDM mode is entered so that the

BDM firmware ROM is enabled and put into the map. BDMACT is

cleared by a car efully ti med stor e instruct ion in the BD M firmwa re as

part o f the exi t sequence to retu rn to use r code and remove the BDM

memory from the map. This bit has 4 clock cycles write dela y.

0 = BDM is not active. BDM ROM and registers are not in map.

1 = BDM is active and waiting for serial commands. BDM ROM and

registers are in map

BIT 7654321BIT 0

ENBDM BDMACT ENTAG SDV TRACE CLKSW - -

RESET: 0

(NOTE 1) 1000000

Special

Single Chip

& Periph

RESET: 00000000

All other

modes

STATUS— BDM Status Register(1) $FF01

1. ENBDM is set to 1 by the firmware in Special Single Chip mode.

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The user should be careful that the state of the BDMACT bit is not

unintentionally changed with the WRITE_NEXT firmware command.

If it is unintentionally changed from 1 to 0, it will cause a system

runaway because it would disable t he BDM firmw are ROM while the

CPU12 was executing BDM firmware. The following two commands

show how BDMACT may unintentionally get changed from 1 to 0.

WRITE_X with data $FEFE

WRITE_NEXT with data $C400

The first command writes the d ata $FEFE to the X index register. The

second command writes the data $C4 to the $FF00 INSTRUCTION

ENTAG — Tagging Enable

Set by the TAGGO command and cleared when BDM mode is

entered. The serial system is disabled and the tag function enabled

16 cycles after this bit is written.

0 = Tagging not enabled, or BDM active.

1 = Tagging active. BDM cannot process serial commands while

taggin g is acti ve .

SDV — Shifter Data Valid

Shows that valid data is in the serial interface shift register. Used by

the BDM firmware.

0 = No valid data. Shift operation is not complete.

1 = Valid Data. Shift oper ation is complete.

TRACE — Asserted by the TRACE1 command

CLKSW — Clock Switch

0 = BDM system operates with BCLK.

1 = BDM system operates with ECLK.

The WRITE_BD_BYTE@FF01 command that changes CLKSW

including 150 cycles after the data portion of the command should be

timed at the old speed. Beginning with the start of the next BDM

command, the new clock can be used for timing BDM communications.

If ECLK rate is slower than BCLK rate, CLKSW is ignored and BDM

system is forced to operate with ECLK.

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18.4.5. 2 INSTRUCTION - Hardware Instru ction Decode

The INSTRUCTION register is written by the BDM hardware as a result

of serial data shifted in on the BKGD pin. It is readable and writable in

Specia l Peripher al mode on the p arallel bus. It is discussed h ere for two

condit io ns: wh en a hardware command is executed and when a

firmware command is exe cuted.

Read and write: all modes

The hardware clears the INSTRUCTION register if 512 BCLK cycles

occur between falling edges from the host.

The bits in the BDM instruction register have the following meanings

when a hardware command is executed.

H/F — Hardware/Firmware Flag

0 = Firmwar e command

1 = Hardware command

DATA — Data Flag - Shows that data accompanies the command.

0 = No data

1 = Data follows the command

R/W — Read/Write Flag

0 = Write

1 = Read

BKGND — Hardware request to enter active background mode

0 = Not a hardware background command

1 = Hardware background command (INSTRUCTION = $ 90 )

BIT 7654321BIT 0

H/F DATA R/W BKGND W/B BD/U 0 0

RESET: 0 0 0 0 0 0 0 0

INSTRUCTION — BDM Instruction Register (hardware command explanation) $FF00

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W/B — Word/Byte Transfer Flag

0 = Byte transfer

1 = Word transfer

BD/U — BDM Map/User Map Flag

Indicates whether BDM registers and ROM are mapped to addresses

$FF00 to $FFFF in the standard 64-Kbyte address space. Used only

by hardware read/write comma nds.

0 = BDM resources not in map

1 = BDM ROM and registers in map

The bits in the BDM instruction register have the following meanings

when a firmware command is execut ed.

H/F — Hardware/Firmware Flag

0 = Firmwar e command

1 = Hardware command

DATA — Data Flag - Shows that data accompanies the command.

0 = No data

1 = Data follows the command

R/W — Read/Write Flag

0 = Write

1 = Read

Bit 7654321Bit 0

H/F DATA R/W TTAGO REGN

INSTRUCTION — BDM Instruction Register (firmware command bit explanation) $FF00

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TTAGO — Trace, Tag, Go Field

REGN — Register/Next Field

Indica tes wh ich re gister is being a ffected by a comm and. I n the case

of a REA D_NEXT or WRITE_NEXT command, index register X is

pre-incriminated by 2 and the word point ed to by X is then read or

written.

Table 18-5. TTAGO Decoding

Table 18-6TTAGO Value Table 18-7Instruction

00 —

01 GO

10 TRACE1

11 TAGGO

Table 18-8. REGN Decoding

REGN Value Instruction

000 —

001 —

010 READ/WRITE NEXT

011 PC

100 D

101 X

110 Y

111 SP

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18.4.5.3 SHIFTER

This 16- b it shi ft re gi ste r contains dat a b ei ng r ece ive d o r tran smi tted via

the serial interface. It is also used by the BDM firmware for temporary

storage.

Read: all modes (but not normally access ed by users)

Write: all modes (but not normally accessed by users)

BIT 15 14 13 12 11 10 9 BIT 8

S15 S14 S13 S12 S11 S10 S9 S8

RESET: XXXXXXXX

SHIFTER— BDM Shift Register - High Byte $FF02

BIT 7654321BIT 0

S7 S6 S5 S4 S3 S2 S1 S0

RESET: XXXXXXXX

SHIFTER— BDM Shift Register - Low Byte $FF03

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18.4.5.4 ADDRESS

This 16-bit address register is temporary storage for BDM hardware and

firmware commands.

Read: all modes (but not normally access ed by users)

Write: only by BDM hardware (state machine)

BIT 15 1 4 13 12 11 10 9 BIT 8

A15 A14 A13 A12 A11 A10 A9 A8

RESET: XXXXXXXX

ADDRESS— BDM Address Register - High Byte $FF04

BIT 7654321BIT 0

A7 A6 A5 A4 A3 A2 A1 A0

RESET: XXXXXXXX

ADDRESS— BDM Address Register - Low Byte $FF05

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18.4.5.5 CCRSAV

The CCRSAV register is used to save the CCR of the users program

when ent er ing BD M . It is also used for tem po r ary stora ge in the BDM

firmware.

Read and write: all modes

BIT 7654321BIT 0

CCR7 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0

RESET:

NOTE 1 (1) XXXXXXXX

CCRSAV— BDM CCR Holding Register $FF06

1. Initialized to equal the CPU12 CCR register by the firmware.

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18.5 Breakpoints

Hardware breakpoints are used to debug software on the

MC68HC912DG128 by comparing actual address and data values to

predetermined data in setup registers. A successful comparison will

place the CPU in background debug mode (BDM) or initiate a software

interrupt (SWI). Breakpoint features designed into the

MC68H C 912DG128 in clude:

•Mode selection for BDM or SWI generation

•Program fetch tagging for cycle of execution breakpoint

•Second ad dress compare in dual address modes

•Range compare by disable of low byte address

•Data compare in full feature mode for non-tagged breakpoint

•Byte masking for high/low byte data compares

• R/W compare for non-tagged compares

•Tag inhibit on BDM TRACE

18.5.1 Breakpoint Modes

Three modes of operation determine the type of breakpoint in effec t.

•Dual address-only breakpoints, each of which will cause a

software interrup t (SWI)

•Sing le full-featur e breakpoint which will cause the part to enter

background debug mode (BDM)

•Dual add r ess-only break points, each of which will cause the part

to enter BDM

Breakpoints will not occur when BDM is active.

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18.5.1.1 SWI Dual Address Mode

In this mode, dual address-only breakpoints can be set, each of which

cause a software interrupt. This is the only breakpoint mo de which can

force the CPU to execut e a SWI. Progra m fetch taggi ng is the defau lt in

this mode; data breakpoints are not possible. In the dual mode each

addre ss bre akpoint is af fected by the BK PM bit and t he BKA LE bit. The

BKxRW and BKxRWE bits are ignored. In dual address mode the

BKDBE become s an enable fo r the second address break point. The

BKSZ8 bit will have no effect when in a dual address mode.

18.5. 1.2 BDM Full Bre akpoi nt Mode

A single full feature breakpoint which causes the part to enter

background debug mode. BDM mode may be entered by a breakpoint

only if an internal signal from the BDM indicates background debug

mode is enabled.

•Breakpoints are not allowed if the BDM mode is already active.

Active mode means the CPU is executing out of the BDM ROM.

•BDM should not be entered from a breakpoint unless the ENABLE

bit is set in the BDM. This is important because even if the

ENABLE bit in the BDM is negated the CPU actually does execute

the BDM ROM code. It ch ecks the ENABLE and returns if not set.

If the BDM is not serviced by the monitor then the breakpoint

would be re-asserted when the BD M returns to normal CPU flow .

•There is no hardware to enforce restriction of breakpoint operation

if the BDM is not enabled.

18.5.1.3 BDM Dual Address Mode

Dual address-only breakpoints, each of which cause the part to enter

backgro un d de bug mode . In th e du al mo de e ach add ress br eakp oint is

affected, consistent a cross modes, by the BKPM bit, the BKALE bit, and

the BKxRW and BKxRWE bits. In dual address mode the BKDBE

becomes an enable for the second address breakpoint. The BKSZ8 bit

will have no effect when in a dual add ress mode. BDM mode may be

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entered by a breakpoint only if a n internal sign al from the BDM indicates

background debug mode is enabled.

•BKDBE will be used as an enable for the second address only

breakpoint.

•Breakpoints are not allowed if the BDM mode is already active.

Active mode means the CPU is executing out of the BDM ROM.

•BDM should not be entered from a breakpoint unless the ENABLE

bit is set in the BDM. This is important because even if the

ENABLE bit in the BDM is negated the CPU actually does execute

the BDM ROM code. It ch ecks the ENABLE and returns if not set.

If the BDM is not serviced by the monitor then the breakpoint

woul d be r e-assert ed wh en the BDM retur ns to no rma l CP U flow .

There is no hardware to enforce restriction of breakpoint operation

if the BDM is not enabled.

18.5.2 Breakpoint Registers

Breakpoint operation consists of comparing data in the breakpoint

addre ss regist er s (BRKAH /B R KAL ) to the addr ess bus and comp ar ing

data in the breakpoint data registers (BRKDH/BRKDL) to the data bus.

The breakpoint data registers can also be compared to the address bus.

The scope of comparison can be expanded by ignoring the least

significant byte of address or data matches.

The scope of com parison can be lim ited to program data only by set ting

the BKPM bit in breakpoint control register 0.

To trace program flow, setting the BKPM bit causes address comparison

of prog ram data o nly. Cont rol bits are also avail able that a llow checkin g

read/write matche s.

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Read and write anytime.

This regi ste r is use d to control the brea kpoi n t log ic.

BKEN1, BKEN0 — Breakpoint Mode Enable

BKPM — Bre ak on Pr og ra m Addresses

This bit controls whether the breakpoint will cause a break on a match

(next instruction boundary) or on a match that will be an executable

opcode. Data and non-executed opcodes cannot cause a break if this

bit is set. This bit ha s no meaning in SWI dual address mode. The

SWI mode only performs program breakpoints.

0 = On match, break at the next instruction boundary

1 = On match, break if the match is an instruction that will be

executed. This uses tagging as its breakpoint mechanism.

BK1ALE — Breakpoint 1 Range Control

Only valid in dual address mode.

0 = BRKDL will not be use d to co mpare to the address bus.

1 = BRKDL will be used to compare to the address bus.

BK0ALE — Breakpoint 0 Range Control

Valid in all modes.

0 = BRKAL will not be used to compare to the address bus.

1 = BRKAL will be used to compare to the addre ss bus.

Bit 7654321Bit 0

BKEN1 BKEN0 BKPM 0 BK1ALE BK0ALE 0 0

RESET:00000000

BRKCT0 — Breakpoint Control Register 0 $0020

Table 18-9. Breakpoint Mode Control

BKEN1 BKEN0 Mode Selected BRKAH/L Usage BRKDH/L Usage R/W Range

0 0 Breakp oin ts Off ————

01SWI — Dual Address Mode Address Match Address Match No Yes

10BDM — Full Breakpoint Mode Address Match Data Match Yes Yes

11BDM — Dual Address Mode Address Match Address Match Yes Yes

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This regi ste r is re ad /wri te in all modes.

BKDBE — Enable Data Bus

Enables comparing of address or data bus values using the BRKDH/L

registers.

0 = The BRKDH/L registers are not used in any comparison

1 = The BRKDH/L registers are used to compare address or data

(depending upon the mode selections BKEN1,0)

BKMBH — Breakpoint Mask High

Disables the comparing of the high byte of data when in full breakpoint

mode. Used in conjunction with the BKDBE bit (which should be set)

0 = High byte of data bus (bits 15:8) are compared to BRKDH

1 = High byte is not used in comparisons

BKMBL — Breakpoint Mask Low

Disab les th e m atch in g o f the low byte of d ata wh en in full br ea kpo i nt

mode. Used in conjunction with the BKDBE bit (which should be set)

0 = Low byte of data bus (bits 7:0) are compared to BRKDL

1 = Low byte is not used in comparisons.

Table 18-10. Breakpoint Address Range Control

BK1ALE BK0ALE Address Range Selected

–0 Upper 8-bit address only for full mode or dual mode BKP0

–1 Full 16-bit address for full mode or dual mode BKP0

0 – Upper 8-bit address only for dual mode BKP1

1 – Full 16-bit address for dual mode BKP1

Bit 765432 1Bit 0

0 BKDBE BKMBH BKMBL BK1RWE BK1RW BK0RWE BK0RW

RESET: 0 0 0 0 0 0 0 0

BRKCT1 — Breakpoint Control Register 1 $0021

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BK1RWE — R/W Compare Enable

Enables the comparison of the R/W signal to further specify what

causes a match. This bit is NOT useful in program breakpoints or in

full breakpoi nt mode. This bit is used in conjunction with a secon d

address in dual address mode when BKDBE=1.

0 = R/W is not used in comparisons

1 = R/W is used in comparisons

BK1RW — R/W Compare Value

When BK1RWE = 1, this bit determines the type of bus cycle to

match.

0 = A write cycle will be matched

1 = A read cycle will be matched

BK0RWE — R/W Compare Enable

Enables the comparison of the R/W signal to further specify what

causes a match. This bit is n ot useful in progra m break points.

0 = R/W is not used in the comparisons

1 = R/W is used in comparisons

BK0RW — R/W Compare Value

When BK0RWE = 1, this bit determines the type of bus cycle to match

on.0 = Write cycle will be matched

1 = Read cycle will be matched

Table 18- 11. Breakpoint Read/Write Control

BK1RWE BK1RW BK0RWE BK0RW Read/Write Selected

––0XR/W

is don’t care for full mode or dual mode BKP0

––10R/W

is write for full mode or dual mode BKP0

––11R/W

is read for full mode or dual mode BKP0

0X––R/W is don’t care for dual mode BKP1

10––R/W is write for dual mode BKP1

11––R/W is read for dual mode BKP1

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These bits are used to compare against the most significant byte of the

address bus.

These bits are used to compare against the least significant byte of the

addre ss bus. These bi ts may be excl uded from b eing used in the match

if BK0ALE = 0.

These bits are compared to the most significant byte of the data bus or

the most significant byte of the address bus in dual address modes.

BKEN[1:0], BKDBE, and BKMBH control how this byte will be used in the

brea kpoint c omparison.

Bit 7654321Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

RESET: 0 0 000000

BRKAH — Breakpoint Address Register, High Byte $0022

Bit 7654321Bit 0

RESET: 0 0 000000

BRKAL — Breakpoint Address Register, Low Byte $0023

Bit 7654321Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

RESET: 0 0 000000

BRKDH — Breakpoint Data Register, High Byte $0024

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These bits are compared to the least significant byte of the data bus or

the least significant byte of the address bus in dual address modes.

BKEN[1:0], BKDBE, BK1ALE, and BKMBL control how this byte will be

used in the breakpoint comparison.

18.6 Instruction Tagging

The instruction queue and cycle-by-cycle CPU activity can be

reconstructed in real time or from trace history that was captured by a

logic analyzer. However, the reconstructed queue cannot be used to

stop the CPU at a specific instruction, because execution has already

begun by the time an operation is visible outside the MCU. A separate

instruction tagging mechanism is provided for this purpose.

Executing the BDM TAGGO command configures two MCU pins for

taggin g. The TAGLO sign al shares a p in with the LSTRB signal, and the

TAGHI signal sh ares a pin wi th the BKGD signal. Taggin g information is

latc he d on the fal li ng ed ge of E CLK.

Table 18-12 shows the functions of the two tagging pins. The pins

opera te independ ently - th e state of one pin does not a ffect the funct ion

of the other. The presence of logic level zero on either pin at the fall of

ECLK pe rforms the ind ica te d fun c ti on . Ta gg i ng i s al l ow ed in all m od es.

Tagging is disabled when BDM becomes active and BDM serial

commands are not processed while tagging is active.

Bit 7654321Bit 0

RESET: 0 0 000000

BRKDL — Breakpoint Data Register, Low Byte $0025

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Instruction Tagging

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The tag fol low s pr og ra m in form ati o n as it adva nce s t hrou gh the qu eu e.

When a tagged instruction reaches the head of the queue, the CPU

enters active background debugging mode rather than execute the

instruction.

Table 18-12. Tag Pin Function

TAGHI TAGLO Tag

1 1 no tag

10low byte

0 1 high byt e

0 0 both bytes

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MC68HC912DG128 — Rev 3.0 Technic al Data

Electrical Specifications

Technical Data — MC68HC912DG128

Section 19. Electrical Specifications

19.1 Contents

19.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .385

19.3 Tables of Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .386

19.2 Introduction

The MC68HC912DG128 mic rocontroller unit (MCU) is a16-bit device

composed of standard on-chip peripherals including a 16-bit central

processing unit (CPU12), 128-Kbyte flash EEPROM, 8K byte RAM, 2K

byte EEPROM, two asynchronous serial communications interfaces

(SCI), a serial peripheral interface (SPI), an 8-channel, 16-bit timer,

two16-bit pulse accumulators and 16-bit down counter (ECT), two 10-bit

analog-to-digital converter (ADC), a four-channel pulse-width modulator

(PWM), an IIC interface module, and two MSCAN modules. The chip is

the first 16-bit microcontroller to include both byte-erasable EEPROM

and flash EEPROM on the same device. System resource mapping,

clock generation, interrupt control and bus interfacing are managed by

the Lite integration module (LI M). The MC68HC912DG128 has full 16-

bit data paths throughout, however, the multiplexed external bus can

operate in an 8-bit narrow mode so single 8-bit wide memory can be

interfaced for lower cost systems.

This section contains the most accurate electrical information for the

MC68HC912DG128 microcontroller available at the time of publication.

The following characte ristics are cont ained in this docu ment:

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19.3 Tables of Data

Table 19-1. Maximum Ratings(1)

1. Permanent damage can occur if maximum ratings are exceeded. Exposures to voltages or currents in excess of recommend-

ed values affects dev ice reliabi lity. D evice m odules may not op erate normally while being exp osed to elec trical extrem es.

Rating Symbol Value Unit

Supply voltage VDD, VDDA, VDDX −0.3 to +6.5 V

Input voltage VIN −0.3 to +6.5 V

Operating temperature range

68HC912DG128PV8

68HC912DG128CPV8

68HC912DG128VPV8

68HC912DG128MPV8

TL to TH

0 to +70

−40 to +85

−40 to +105

−40 to +125

°C

Storage temperature range Tstg −55 to +150 °C

Current drain per pin(2)

Excluding VDD and VSS

2. One pin at a time, observing maximum power dissipation limits. Internal circuitry protects the inputs against damage

caused by high static voltages or electric fields; however, normal precautions are necessary to avoid application of any

voltage higher than maximum-rated voltages to this high-impedance circuit. Extended operation at the maximum ratings

can adversely affect device reliability. Tying unused inputs to an appropriate logic voltage level (either GND or VDD) en-

hances reliability of operation.

IIN ±25 mA

VDD differential voltage VDD−VDDX 6.5 V

Table 19-2. Thermal Characteristics

Characteristic Symbol Value Unit

Average junction temperature TJTA + (PD × ΘJA)°C

Ambient temperature TAUser-determined °C

Package therm al resistance (junction-to-ambient)

112-pin quad flat pack (QFP) ΘJA 40 °C/W

Total power dissipation(1)

1. This is an approximate value, neglecting PI/O.

PINT + PI/O or W

Device internal power dissipation PINT IDD × VDD W

I/O pin power dissipation (2)

2. For most applications PI/O « PINT and can be neglected.

PI/O User-determined W

A constant(3)

3. K is a constant pe rtai nin g to the dev ice. Sol ve fo r K with a kno w n TA and a measured PD (at equilibrium). U se this val ue of

K to solve for PD and TJ iteratively for any value of TA.

KPD × (TA + 273°C) + ΘJA × PD2 W · °C

TJ273°C+

--------------------------

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Table 19-3 . DC Electrical Characteristic s

VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted

Characteristic Symbol Min Max Unit

Input high voltage, all inputs VIH 0.7 × VDD VDD + 0.3 V

Input low voltage, all inputs VIL VSS−0.3 0.2 × VDD V

Output high voltage, all I/O and output pins except XTAL

Normal drive strength

IOH = −10.0 µA

IOH = −0.8 mA

Reduced drive strength

IOH = −4.0 µA

IOH = −0.3 mA

VOH

VDD − 0.2

VDD − 0.8

VDD − 0.2

VDD − 0.8

—

Output low voltage, all I/O and output pins except XTAL

Normal drive strength

IOL = 10.0 µA

IOL = 1.6 mA

Reduced drive strength

IOL = 3.6 µA

IOL = 0.6 mA

VOL

—

VSS+0.2

VSS+0.4

VSS+0.2

VSS+0.4

Input leakage current(1)

Vin = VDD or VSSAll input only pins except ATD(2) and VFP Iin —±5.0 µA

Three-state leakage, I/O ports, BKGD, and RESET IOZ — ±2.5 µA

Input capacitance

All input pins and ATD pins (non-sampling)

ATD pins (sampling)

All I/O pins

Cin —

—

Output load capacitance

All outputs except PS[7:4]

PS[7:4] when configured as SPI CL—

— 90

200 pF

Programmable active pull-up/pull-down current

IRQ, XIRQ, DBE, LSTR B, R/W. ports A, B, H, J, K, P, S, T, IB[7:4],

RXCAN1, .RXCAN0

MODA, MODB active pull down during reset

BKGD passive pull up

IAPU 50

500

µA

RAM standby voltage, power down Vsb 1.5 — V

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Ram standby current Isb — 50 µA

DC injection current(3) (4) (5) (6) (7)

(VNEGCLAMP=VSS–0.3V, V POSTCLAMP=VDDE+0.3)

Steady state single pin limit

Steady state package limit includes sum of all stressed pins (25

pins max.)

Transient single pin limit

T ransient package limit includes sum of all stressed pins (25 pins

max.)

IICsss

IICssP

IICTRs

IICTRP

–0.5

–10

–25

0.5

1. Specif ication is for parts in the -40 to +85°C range. Higher temperature ranges will result in increased

current leakage.

2. See Table 19-5.

3. It is recommended to tie VDD if standby mode is not being used.

4. All functional no-supply pins are internally clamped to VSS and VDD or VSS and VDDX.

5. Input must be current limited to the value specified. To determine the value of the requ ired current-limiting resistor, calculate

resistance values for positive and negative clamp voltages, then use the larger of the two values.

6. Power su pply mu st maintai n reg ulatio n within ope rating VDD or VDDX range during ins tantane ous and opera ting ma ximu m

current co nditions . If positive i njection curren t (Vin>VDD or Vin>VDDX) is great er than IDD or IDDX, injection cur rent may flow

out of VDD/VDDX and coul d result in external power supply going out of regulation. Ensure external VDD/VDDX load will shunt

current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Ex-

amples are: if no system clock is present, or if clock rate is very low, which would reduce overall power consumption.

7. Current injection specification does not include ATD pins.

Table 19-3 . DC Electrical Characteristic s

VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted

Characteristic Symbol Min Max Unit

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Table 19-4. Supply Current

VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted

Characteristic Symbol 8 MHz Unit

Maximum total supply current

RUN:

Single-chip mode

Expanded mode

IDD 60

100 mA

WAIT: (All peripheral functions shut down)

Single-chip mode

Expanded mode WIDD 15

20 mA

STOP:

Single-chip mode, no clocks SIDD 200 µA

Table 19-5. ATD DC Electrical Chara cteristics

VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH, ATD Clock = 2 MHz, unless otherwise noted

Characteristic Symbol Min Max Unit

Analog supply voltage VDDA 4.5 5.5 V

Analog supply currentNormal operation IDDA 1.0 mA

Reference voltage, low VRL VSSA VDDA/2V

Reference voltage, high VRH VDDA/2V

DDA V

VREF differential reference voltage(1) VRH−VRL 4.5 5.5 V

Input voltage(2) VINDC VSSA VDDA V

Input current, off channel(3) IOFF 100 nA

Reference supply current IREF 250 µA

Input capacitanceNot Sampling

Sampling CINN

CINS

15 pF

1. Accuracy is guaranteed at VRH − VRL = 5.0V ±10%.

2. To obtain full-scale, full-range results, VSSA ≤ VRL ≤ VINDC ≤ VRH ≤ VDDA.

3. Ma ximum leakage occurs at maxi mum operating temperature. C urrent decrease s by approximate ly one-half f or each 10°C

decr eas e from maxi mu m tem pera ture.

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Table 19-6. Analog Converter Characteristics (Operating)

VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH, ATD Clock = 2 MHz, unless otherwise noted

Characteristic Symbol Min Typical Max Unit

8-bit resolution(1) 1 count 20 mV

8-bit differential non-linearity(2) DNL −0.5 +0.5 count

8-bit integral non-linearity(2) INL −1+1 count

8-bit absolute error,(3)2, 4, 8, and 16 ATD sample clocks AE −1+1 count

10-bit resolution(1) 1 count 5 mV

10-bit differential non-linearity(2) DNL –2 2 count

10-bit integral non-linearity(2) INL –2 2 count

10-bit absolute error(3) 2, 4, 8, and 16 ATD sample clocks AE –2.5 2.5 count

Maximum so ur ce imped anc e RS20 See

note(4) KΩ

1. VRH − VRL ≥ 5.12V; VDDA − VSSA = 5.12V

2. At VREF = 5.12V, one 8-bit count = 20 mV, and one 10-bit count = 5mV.

INL and D NL are c ha rac teri zed usi ng the p r oces s window para me ters a ffe cti ng the ATD a ccurac y , b ut they are n ot tes ted .

3. These values include quantization error which is inherently 1/2 count for any A/D converter.

4. Maximum source impedance is application-dependent. Error resulting from pin leakage depends on junction leakage into

the pin and on leakage due to charge-sharing with internal capacitance.

Error from junction leakage is a function of external source impedance and input leakage current. Expected error in result

value due to juncti on lea ka ge is ex pres se d in vol tage (VERRJ):

VERRJ = RS × IOFF

where IOFF is a function of operatin g tempera ture. Charg e-shari ng effec ts with inte rnal cap acitors are a functio n of ATD clock

speed, the number of channels being scanned, and source impedance. Charge pump leakage is computed as follows:

VERRJ = .25pF × VDDA × RS × ATDCLK/(8 × number of channels)

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Table 19-7. ATD AC Characteristics (Operating)

VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH, ATD Clock = 2 MHz, unless otherwise noted

Characteristic Symbol Min Max Unit

MCU clock frequency (p-clock) fPCLK 2.0 8.0 MHz

ATD operating clock frequency fATDCLK 0.5 2.0 MHz

ATD 8-Bit conversion period

cloc k cycles (1)

conversion time(2)

nCONV8

tCONV8

932

16 cycles

µs

AT D 10- Bit conversion period

cloc k cycles (1)

conversion time(2) nCONV10

tCONV10

10 34

17 cycles

µs

Stop and ATD power up recovery time(3)

VDDA = 5.0V tSR 10 µs

1. The minim um t ime assum es a f inal sa mple pe riod of 2 ATD clock cycle s while th e maxim um tim e assu mes a fin al samp le

period of 16AT D clock s .

2. This assumes an ATD clock frequency of 2.0MHz.

3. From the time ADPU is asserted until the time an ATD conversion can begin.

Table 19-8. ATD Maximum Ratings

Characteristic Symbol Value Units

ATD reference voltage

VRH ≤ VDDA

VRL ≥ VSSA

VRH

VRL

−0.3 to +6.5

−0.3 to +6.5 V

VSS differential voltage |VSS−VSSA|0.1 V

VDD differentia l voltag e VDD−VDDA

VDDA−VDD

6.5

0.3 V

VREF differential vol tag e |VRH−VRL|6.5 V

Referenc e to suppl y differen tia l voltag e |VRH−VDDA|6.5 V

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Table 19-9. EEPROM Characteristics

VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted

Characteristic Symbol Min Typical Max Unit

Minimum programming clock frequency(1) fPROG 1.0 MHz

Programming time tPROG 10 10.5 ms

Clock recovery time, following STOP, to continue programming tCRSTOP tPROG+ 1 ms

Erase time tERASE 10 10.5 ms

Write/erase endurance 10,000 30,000(2) cycles

Data retent ion 10 10.5 year s

1. RC oscillator must be enabled if programming is desired and fSYS < fPROG.

2. If average TH is below 85° C.

Table 19-10. Flash EEPROM Characteristics

VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted

Characteristic Symbol Min Typical Max Units

Program/erase supply voltage:

Read only

Program / erase / verify VFP VDD−0.35

11.4 VDD

12 VDD+0.5

12.6 V

Program/erase supply current

Word program(VFP = 12V)

Erase(VFP = 12V) IFP 30

4mA

Number of programming pulses nPP 50 pulses

Programming pulse tPPULSE 20 25 µs

Program to verify time tVPROG 10 µs

Progra m margin pm100(1) %

Number of erase pul se s nEP 5pulses

Erase pulse tEPULSE 5 — 10 ms

Erase to verify time tVERASE 1 ms

Erase margin em100(1) %

Program/erase endurance 100 cycles

Data retention 10 years

1. The number of margin pulses required is the same as the number of pulses used to program or erase.

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MC68HC912DG128 — Rev 3.0 Technic al Data

Electrical Specifications

Use of an external circuit to condition VFP is recommended. Figure 19-1

shows a simple circuit that maintains required voltages and filters

transients. VFP is pulled to VDD via Schottky diode D2. Application of

program ming vo ltag e via dio de re verse-bi ases D 2, prote cting VDD from

excessive reverse current. D2 also protects the FLASH from damage

should programming voltage go to 0. Programming power supply

voltage must be adjusted to compensate for the forward-bias drop

acros s D1. The char ge time const ant of R1 and C1 filters trans ients,

while R2 provides a discharge bleed path to C1. Allow for RC charge and

discharge time constants when appl ying and removing power. Wh en

using this ci rcuit, keep leakage from extern al dev ices connect ed to the

VFP pin low, to minimize diode voltage drop.

Figure 19-1. VFP Conditioning Circuit

22kΩ

10Ω

4.5V

0.1µF

VDD VFP

PROGRAMMING VOLTAGE

POWER SUPPLY

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Technical Data MC68HC912DG128 — Rev 3.0

Electrical Specifications

Figure 19-2. VFP Operating Range

13.5V

12.8V

11.4V

6.5V

4.5V

4.15V

–0.30V POWER

NORMAL

READ POWER

DOWN

PROGRAM

ERASE

VERIFY

30ns MAXIMUM

VFP ENVELOPE

VDD ENVEL OPE

COMB INED VDD AND VFP

Table 19-11. Pulse Width Modulator Characteristics

VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted

Characteristic Symbol Min Max Unit

E-clock frequency feclk 0.004 8.0 MHz

A-clock frequency

Selectable faclk feclk/128 feclk Hz

B-clock frequency

Selectable fbclk feclk/128 feclk Hz

Left-aligned PWM frequency

8-bit

16-bit flpwm feclk/1M

feclk/256M feclk/2

feclk/2 Hz

Left-aligned PWM resolution rlpwm feclk/4K feclk Hz

Center-aligned PWM frequency

8-bit

16-bit fcpwm feclk/2M

feclk/512M feclk

feclk

Center-aligned PWM resolution rcpwm feclk/4K feclk Hz

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MC68HC912DG128 — Rev 3.0 Technic al Data

Electrical Specifications

1. RESET is recog nized during t he firs t cloc k cycle it is he ld low. In tern al circui try then drive s

the pin low for 16 clock cycles, releases the pin, and samples the pin level 8 cycles later

to determine the source of the interrupt.

Figure 19-3. Timer Inputs

Table 19-12. Control Timing

Characteristic Symbol 8.0 MHz Unit

Min Max

Frequency of operation fo0.004 8.0 MHz

E-cl oc k per io d tcyc 0.125 250 µs

External oscillator frequency feo 0.5 16.0(1) MHz

Processor control setup time

tPCSU = tcyc/2+ 20 tPCSU 82 —ns

Reset input pulse width

To guarantee external reset vector

Minimum input time (can be preempted by internal reset) PWRSTL 32

2—

—tcyc

tcyc

Mode prog ra mming setup time tMPS 4 — tcyc

Mode programming hold time tMPH 10 —ns

Interrupt pulse width, IRQ edge-sensitive mode

PWIRQ = 2tcyc + 20 PWIRQ 270 —ns

Wait recovery startup time tWRS —4cycles

Timer input capture pulse width (PWTIM = 2 tcyc + 20) PWTIM 270 —ns

1. When using a quartz crystal, operation should be restricted to 8MHz.

PT72

PT71

PT[7:0]2

PT[7:0]1

NOTES:

1. Rising edge sensitive input

2. Falling edge sensitive input

PWTIM

PWPA

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Technical Data MC68HC912DG128 — Rev 3.0

Electrical Specifications

Figure 19-4. POR and External Reset Timing Diagram

PCSU

INTERNAL

MODA , MODB

ECLK

EXTAL

RESET

4098 t

cyc

FREE

FFFEFFFE 3RD

1ST 2ND FREE

FFFE

MPH

RSTL

MPS

ADDRESS PIPE PIPE PIPE 1ST

EXEC 3RD

PIPE

2ND

PIPE

1ST

PIPE 1ST

EXEC

NOTE: Reset timing is subject to change.

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MC68HC912DG128 — Rev 3.0 Technic al Data

Electrical Specifications

Figure 19-5. STOP Recovery Timing Diagram

IRQ

STOPDELAY3

IRQ

or XIRQ

ECLK

1ST

ADDRESS

SP-9

FREE

VECTOR FREE

FREE

Resume program with instruction which follows the STOP instruction.

INTERNAL

ADDRESS

CLOCKS

NOTES:

1. Edge Sensitive IRQ pin (IRQ E bit = 1)

2. Level sensitive IRQ pin (IRQE bit = 0)

3. t

STOPDELAY

= 4098 t

cyc

if DLY bit = 1 or 2 t

cyc

if DLY = 0.

4. XIRQ with X bit in CCR = 1.

5. IRQ or (XIRQ with X bit in CCR = 0).

OPT 1ST

2ND 3RD 1ST

EXEC

PIPE PIPE EXEC

SP-8

SP-6 FETCH

PIPE

SP-6 SP-8 SP-9

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Technical Data MC68HC912DG128 — Rev 3.0

Electrical Specifications

Figure 19-6. WAIT Recovery Timing Diagram

PCSU

PC, IY, IX, B:A, , CCR

STACK REGISTERS

ECLK

R/W

ADDRESS

IRQ, XIRQ,

OR INTERNAL

INTERRUPTS

SP – 2 SP – 4 SP – 6 . . . SP – 9 SP – 9 SP – 9 . . . SP – 9 SP – 9 VECTOR FREE 1ST 2ND 3RD

PIPE

WRS

NOTE : RESET also causes recovery from WAIT.

ADDRESS PIPE PIPE 1ST

EXEC

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MC68HC912DG128 — Rev 3.0 Technic al Data

Electrical Specifications

Figure 19-7. Interrupt Timing Diagram

ECLK

IRQ

1ST

3RD

ADDRESS

IRQ

SP – 9

PCSU

IRQ

, XIRQ,

OR INTERNAL

INTERRUPT

VECTOR SP – 2 1ST SP – 4 SP – 6 2ND SP – 8

DATA

VECT PC IY IX B:A CCR

PROG

R/W

NOTES:

1. Edge sensitive IRQ pin (IRQE bit = 1)

2. Level sensitive IRQ pin (IRQE bit = 0)

FETCH

ADDR EXEC

PIPE

PROG

FETCH

PROG

FETCH

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Electrical Specifications

Technical Data MC68HC912DG128 — Rev 3.0

Electrical Specifications

Figure 19-8. Port Read Timing Diagram

Figure 19-9. Port Write Timing Diagram

Ta ble 19-13. Peripheral Port Timing

Characteristic Symbol 8.0 MHz Unit

Min Max

Frequency of operation (E-clock frequency) fo0.004 8.0 MHz

E-clock period tcyc 0.125 250 µs

Peripheral data setup time (tPDSU = tcyc/2 + 4 0)

MCU read of ports tPDSU 102 —ns

Peripheral data hold time

MCU read of ports tPDH 0 — ns

Delay time, peripheral data write

MCU write to ports tPWD —40 ns

PORT RD TI M

ECLK

MCU READ OF PORT

PORTS

tPDSU tPDH

PORT WR TIM

ECLK

MCU WRITE TO PORT

PREVIOUS PORT DATA NEW DATA VALID

PORT A

tPWD

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MC68HC912DG128 — Rev 3.0 Technic al Data

Electrical Specifications

Table 19-14. Multiplexed Expansion Bus Timing

VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted

Num Characteristic(1), (2), (3), (4)

1. All timings are cal cu lat ed for norm al port driv es.

2. Crystal input is required to be within 45% to 55% duty.

Delay Symbol 8 MHz Unit

Min Max

Frequenc y of oper ati on (E- cloc k freque nc y) fo0.004 8.0 MHz

1Cycle timetcyc = 1/fo—tcyc 0.125 250 µs

2Pulse width, E lowPWEL = tcyc/2 + delay −4PWEL 58 ns

3Pulse width, E high(5)PWEH = tcyc/2 + delay −2PWEH 60 ns

5Address delay timetAD = tcyc/4 + delay 27 tAD 58 ns

7Address valid time to ECLK risetAV = PWEL − tAD —tAV 0ns

8Multiplexed address hold timetMAH = tcyc/4 + delay −18 tMAH 13 ns

9Address Hold to Data Valid —tAHDS 20

10 Data Hold to High ZtDHZ = tAD − 20 —tDHZ 38

11 Read data setup time —tDSR 25 ns

12 Read data hold time —tDHR 10 ns

13 Write data delay time —tDDW 47 ns

14 Write data hold time —tDHW 20 ns

15 Write data setup time(5)tDSW = PWEH − tDDW —tDSW 13 ns

16 Read/write delay timetRWD = tcyc/4 + delay 18 tRWD 49 ns

17 Read/write valid time to E risetRWV = PWEL − tRWD —tRWV 9ns

18 Read/write hold time —tRWH 20 ns

19 Low strobe(6) delay timetLSD = tcyc/4 + delay 18 tLSD 49 ns

20 Low strobe(6) valid time to E risetLSV = PWEL − tLSD —tLSV 9ns

21 Low strobe(6) hold time —tLSH 20 ns

22 Address access time(5)tACCA = tcyc − tAD − tDSR —tACCA 42 ns

23 Access time from E rise(5)tACCE = PWEH − tDSR —tACCE 35 ns

24 DBE delay from ECLK rise(5)tDBED = tcyc/4 + delay 8tDBED 39 ns

25 DBE valid timetDBE = PWEH − tDBED —tDBE 21 ns

26 DBE hold time from ECLK fall tDBEH –310ns

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Technical Data MC68HC912DG128 — Rev 3.0

Electrical Specifications

Figure 19-10. Multiplexed Expansion Bus Timing Diagram

3. Reduced drive must be off to meet these timings.

4. Unequalled loading of pins will affect relative timing numbers.

5. This characteristic is affected by clock stretch.

Add N × tcyc where N = 0, 1, 2, or 3, depending on the number of clock stretches.

6. Without TAG enabled.

DBE

24 25

ECLK

R/W

2 3

11 12

NOTE: Measurement points shown are 20% and 70% of VDD

16 17

READ

WRITE

LSTRB

2119 20

(W/O TAG ENABLED)

5 7 22

815

ADDRESS/DATA

MULTIPLEXED

ADDRESS

DATA

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MC68HC912DG128 — Rev 3.0 Technic al Data

Electrical Specifications

Table 19-15. SPI Timing

(VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH , 200 pF load on all SPI pins)(1)

Num Function Symbol Min Max Unit

Operating Frequency

Master

Slave fop 1/256

1/256 1/2

1/2 feclk

SCK Pe riod

Master

Slave tsck 2

2256

—tcyc

tcyc

Enable Lead Time

Master

Slave tlead 1/2

1—

—tsck

tcyc

Enable Lag Time

Master

Slave tlag 1/2

1—

—tsck

tcyc

Clock (SCK) High or Low Time

Master

Slave twsck tcyc − 30

tcyc − 30 128 tcyc

—ns

Sequential Transfer Delay

Master

Slave ttd 1/2

1—

—tsck

tcyc

Data Setup Time (Inputs)

Master

Slave tsu 30

30 —

—ns

Data Hold Time (Inputs)

Master

Slave thi 0

30 —

—ns

Slave Ac ce ss Time ta— 1 tcyc

Slave MISO Dis able Time tdis — 1 tcyc

Data Valid (after SCK Edge)

Master

Slave tv—

—50

50 ns

Data Hold Time (Outputs)

Master

Slave tho 0

0—

—ns

Rise Time

Input

Output tri

tro

—

—tcyc − 30

30 ns

Fall Time

Input

Output tfi

tfo

—

—tcyc − 30

30 ns

1. All AC timing is shown with respect to 20% VDD and 70% VDD levels unless otherwise noted.

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Electrical Specifications

Technical Data MC68HC912DG128 — Rev 3.0

Electrical Specifications

A) SPI Master Timing (CPHA = 0)

B) SPI Master Timing (CPHA = 1)

Figure 19-11. SPI Timing Diagram (1 of 2)

SCK

(OUTPUT)

SCK

(OUTPUT)

MISO

(INPUT)

MOSI

(OUTPUT)

SS1

(OUTPUT)

6 7

MSB IN2

BIT 6 . . . 1

LSB IN

MSB OUT2LSB OUT

BIT 6 . . . 1

(CPOL = 0)

(CPOL = 1)

1. SS output mod e (DDS7 = 1, SSOE = 1).

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

SCK

(OUTPUT)

SCK

(OUTPUT)

MISO

(INPUT)

MOSI

(OUTPUT)

6 7

MSB IN2

BIT 6 . . . 1

LSB IN

MASTER MS B OUT2MASTER LSB OUT

BIT 6 . . . 1

12 13

PORT DATA

(CPOL = 0)

(CPOL = 1)

PORT DATA

SS1

(OUTPUT) 5

213 12 3

1. SS output mode (DDS7 = 1, SSOE = 1).

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

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MC68HC912DG128 — Rev 3.0 Technic al Data

Electrical Specifications

A) SPI Slave Timing (CPHA = 0)

B) SPI Slave Timing (CPHA = 1)

Figure 19-12. SPI Timing Diagram (2 of 2)

SCK

(INPUT)

SCK

(INPUT)

MOSI

(INPUT)

MISO

(OUTPUT)

(INPUT)

6 7

MSB IN

BIT 6 . . . 1

LSB IN

MSB OUT SLAVE LSB OUT

BIT 6 . . . 1

(CPOL = 0)

(CPOL = 1)

NOTE: Not defined but normally MSB of character just received.

SLAVE

SEE

NOTE

SPI SLAVE CPHA1

SCK

(INPUT)

SCK

(INPUT)

MOSI

(INPUT)

MISO

(OUTPUT)

6 7

MSB IN

BIT 6 . . . 1

LSB IN

MSB OUT SLAVE LSB OUT

BIT 6 . . . 1

12 13

SEE

(CPOL = 0)

(CPOL = 1)

(INPUT) 5

213 12

NOTE: Not defined but normally LSB of character just received.

SLAVE

NOTE

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Technical Data MC68HC912DG128 — Rev 3.0

Electrical Specifications

Table 19-16. CGM Characteristics

5.0 Volts +/- 10%

Characteristic Symbol Min. Typ. Max. Unit

PLL referenc e frequency, crystal oscillator range fREF 0.5 8 MHz

Bus frequency fBUS 0.004 8 MHz

VCO range fVCO 2.5 8 MHz

VCO Limp-Home frequency fVCOMIN 0.5 2.5 MHz

Lock Detector transition from Acquisition to

Tracking mode(1) ∆trk 3% 4% —

Lock Detection ∆Lock 0% 1.5% —

Un-Lock Detect ion ∆unl 0.5% 2.5% —

Lock Detector transition from Tracking to

Acquisition mode ∆unt 6% 8% —

Minimum leakage resistance on crystal oscillator

pins rleak 1MΩ

PLL Stabilization delay (2)

PLL Total Stabilization Delay(3) tstab 3ns

PLLON Acquisition mode stabilization delay.(3) tacq 1ns

PLLON tracking mode stabilization delay.(3) tal 2ns

1. AUTO bit set

2. PLL stabilization delay is highly dependent on operational requirement and external component values (e.e. crystal, XFC

filter component values|). Note (3) shows typical delay values for a typical configuration. Appropriate XFC filter values

should be chosen based on operational requirement of system.

3. fREF = 4MHz, fBUS = 8MHz (REFDV = #$00, SYNR = #$01), XFC:Cs = 33nF, Cp = 3.3nF, Rs = 2.7KΩ.

Table 19-17. Key Wake-up

Characteristic Symbol Min. Max. Unit

STOP Key Wake-Up Filter time tKWSTP 210µs

Key Wake-Up Single Pulse Time Interval tKWSP 20 µs

Table 19-18. msCAN 12 Wake-up Time from Sleep Mode

VDD = 5.0V dc ± 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted

Characteristic Symbol Min. Max. Unit

Wa ke-Up time twup 25µs

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MC68HC912DG128 — Rev 3.0 Technic al Data
Appendix: CGM Practical Aspects
 
Technical Data — MC68HC912DG128
Section 20. Appendix: CGM Pra ctical Aspects
20.1  Contents
20.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .407
20.3 A Few Hints For The CGM Crystal Oscillator Application. . . .407
20.4 Practical Aspects For The PLL Usage . . . . . . . . . . . . . . . . . .4 10
20.5 Printed Circuit Board Guidelines. . . . . . . . . . . . . . . . . . . . . . .415
20.2  Introduction
This se ctions  provides useful and practical piece s of informat ion 
conc erning the implem entation of the CGM m odul e.
20.3  A Few Hints For The CGM Crystal Osci llator Application
20.3.1  What Loading Capacitors To Choose?
First, from small-signal analysis, it is known that relatively large values 
for C1 and C2 have a positive impact on the phase margin. However, the 
higher loading they represent decreases the loop gain. Alternatively, 
small val ue s for  these  capa ci tors  will  le ad  to hi gh er  ope n loop  gai n , but 
as the frequency of oscillation approaches the parallel resonance, the 
phase margin, and conseq ue ntly the  ability to start-up correctly, will 
decrease. From this it is clear that relatively large capacitor values 
(>33pF), are reserved for low frequency crystals in the MHz range.
NOTE: Using the recommended loading capacitor CL value from the crystal 
manufacturer is a good starting point. Taking into account unavoidable 
strays, this equates to about (CL-2pF).
    
  
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Appendix: CGM Practical Aspects

Technical Data MC68HC912DG128 — Rev 3.0

Appendix: CGM Practical Aspects

Theoretically speaking, nothing precludes the use of non-identical

values for C1 and C2. As this complicate a bit the management of the

final board devi ce list, this is not recommended. However, if

asym metrical capacitors are chosen , the value of C1 should be higher

than C2 (because the reflected loading is proportional to the square of

the impedance of C2).

20.3.2 DC Bias

Due to the nature of the translated ground Colpitts oscillator a DC

voltage bias is applied to the cry stal.

Please contact the crystal manufacturer for specific DC bias conditions

and recommended capacitance value (if applicable).

20.3.3 What Is the Final Oscillation Frequency?

The exact calculation is not straightforward as it takes into account the

resonator characteristics and the loading capacitors values as well as

internal design parameters which ca n vary with Process Voltage

Temperature (PVT) conditions. Nevertheless, if L is the series

inductance, R is the series resistance, C is the series capacitance and

Cc the p aralle l capacitan ce of the c rystal, w e can the n use the following

simplified equation:

20.3.4 How Do I Control The Peak to Peak Oscillation Amplitude?

The CGM oscillator is equipped with an Amplitude Limitation Control

loop which integrat es the peak to peak ‘extal’ amplitude and in return

reduces the steady current of the transconductor device until a stable

Fosc 1

2π

------ 1

--------1

LCcC1C2

+()⋅

----------------------------------------------+⋅=

C1=C2=Cl yields to

Fosc 1

2π

------ 1

--------1

LCcCl2

⁄+()⋅

---------------------------------------+⋅=

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Appendix: CGM Practical Aspects

A Few Hints For The CGM Crystal Oscillator Application

MC68HC912DG128 — Rev 3.0 Technic al Data

Appendix: CGM Practical Aspects

quiesce nt point is reached . Contro lling this final p eak to pea k amplitud e

can be performed by t hree means:

1. Reducing the values of C1 and C2. This decreases the loading so

that the necessary gm value required to sustain oscillation can be

smaller. The consequently smaller current will be reac hed with a

larger ‘extal’ swing.

2. Using VDDPLL=VSS (i.e. shutting off the PLL). Doing so

increases the starting current by approximately 50 %. All other

parameters staying the same, a larger ‘extal’ swing will be required

to reduce this starting current to its quiescent value.

3. Also, p lacing a h igh value resistor ( >1MΩ) across the EXTAL and

XTAL pins significantly increased the oscillation amplitude.

Because this complicates the design analysis as it transforms a

pure susceptance jωC1 into a complex admittance G+jωC1,

Freescale cannot promote this application trick.

20.3.5 What Do I Do In Case The Oscillator Does Not Start-up?

1. First, verify that the application schematic respects the principle of

operation, i.e. crystal mounted between EXTAL and VSS,

Capacitor C1 between XTAL and EXTAL, Capacitor C2 between

XTAL and VSS , nothing els e. This is not the conventional MCU

applic ation sche matic of the Pier ce oscilla tor as i t can be se en on

other HC12 derivatives!

2. Re -consider th e choice of the tuni ng capac itors .

3. The oscillator circuitry is powered internally from a core VDD pad

and the return path is the VSSPLL pad. Verify on the application

PCB the correct connection of these pads (especially VSSPLL),

but also verify the waveform of the VDD voltage as it is imposed

on the pad. Sometimes external components (for instance choke

inductors), can caus e oscillations on the po wer line. This is of

course detrimental to the oscillator circuitry.

4. If possible, consider using a resonator with built-in tuning

capacitors. They may offer better performances with respect to

their discrete elements implementation.

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Appendix: CGM Practical Aspects

Technical Data MC68HC912DG128 — Rev 3.0

Appendix: CGM Practical Aspects

20.4 Practical Aspects For The PLL Usage

20.4.1 Synthesized Bus Frequency

Starting from a ceramic resonator or quartz crystal frequency FXTAL, if

‘refdv’ and ‘synr’ are the de cimal content of the REFDV an d SYNR

registers respectively, then the MCU bus frequency will simpl y be:

NOTE: It is not allowed to synthesize a bus frequency that is lower than the

crystal frequency, as the correct functioning of some internal

synchronize rs would be jeopardiz ed (e. g. the MCLK and XCLK c lock

generators).

20.4.2 Operation Under Adverse Environmental Conditions

The norm al op er ation fo r the PLL is th e so- c a lled ‘autom ati c bandwi d th

selection mode’ which is obtained by having the AUTO bit set in the

PLLCR r egister. When this mode is sel ected and as the VCO frequency

approaches its target, the charge pump curren t leve l will automatically

switch from a relatively high value of around 40 µA to a lower value of

about 3 µA. It can happen that this low level of charge pump current is

not enough to overcome leakages present at the XFC pin due to adverse

environmental conditions. These conditions are frequently encountered

for uncoated PCBs in automotive appl ications. The main symptom for

this failure is an unstable characteristic of the PLL which in fact ‘hunts’

between acquisition and tracking modes. It is then advised for the

running software to place the PLL in manual, forced acquisition mode by

clearing both the AUTO and the ACQ bits in the PLLCR register. Doing

so will maintain the high current level in the cha rge pump constantly and

will permit to sustain higher levels of leakages at the XFC pin. This latest

revision of the Clock Generator Module maintains the lock detection

FBUS FVCO

FXTAL synr 1+()⋅

refdv 1+()

------------------------------------------------==

synr 0,1,2,3...63}

{∈

refdv 0,1,2,3...7}{∈

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Appendix: CGM Practical Aspects

Practical Aspects For The PLL Usage

MC68HC912DG128 — Rev 3.0 Technic al Data

Appendix: CGM Practical Aspects

feature even in manual bandwidth control, offering then to the

application software the same flexibility for the clocking control as the

automatic mode.

20.4.3 Filter Components Selection Guide

20.4.3.1 Equations Set

These equations can be used to select a set of filter components. Two

cases are considered:

1. The ‘tracking’ mode. This situation is reached norm ally when t he

PLL operates in automatic bandwidth selection mode (AUTO=1 in

the PLLCR register).

2. The ‘acquisition’ mode. This si tuation is r eached when t he PLL

operates in manual bandwidth selection mode and forced

acquisition (AUTO=0, ACQ=0 in the PLLCR re gister).

In both equations, the power supply should be 5V. Start with the target

loop bandwid th as a function of the other para meters, but obviou sly,

nothing prevents the user from starting with the capacitor value for

example. Also, remember that the smoothing capacitor is always

assumed to be one tenth of the series capacitance value.

So with:

m: the multiplying factor for the reference frequency (i.e. (synr+1))

R: the series resistance of the low pass filter in Ω

C: the series capacitance of the low pass filter in nF

Fbus: the target bus frequency expressed in MHz

ζ: the desired dampin g factor

Fc: the desired lo op band width expressed in Hz

for the ‘tracking’ mode:

Fc210

9ζ2

⋅⋅

πRC⋅⋅

------------------------- 37.78 e

1.675 Fbus

–

10.795

-----------------------------





R⋅⋅

2πm⋅⋅

------------------------------------------------------==

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Appendix: CGM Practical Aspects

Technical Data MC68HC912DG128 — Rev 3.0

Appendix: CGM Practical Aspects

and for the ‘acquisition’ mode:

20.4.3.2 Particular Case of an 8MHz Synthesis

Assume that a desired value for the damping factor of the second order

system is close to 0.9 as this leads to a sat isfactory transient resp onse.

Then, derived from the equations above, Table 20-1 and Table 20-2

suggest sets of values corresponding to several loop bandwidth

possibilities in the case of an 8M Hz synthesis for the two cases

mentioned above.

The filter components values are chosen from standard series (e.g. E12

for resistors). The operating voltage is assumed to be 5V (although there

is only a minor difference between 3V and 5V operation). The smoothing

capacitor Cp in parallel with R0 and C0 is set to be 1/10 of the value of

C0. The refe rence frequencies ment ioned in this ta ble correspond to the

output of the fine granularity divider controlled by the REFDV register.

This means that the calculations are irrespective of the way the

reference frequency is generated (directly for the crystal oscillator or

after division). The target frequency value also has an influence on the

calculations of the filter components because the VCO gain is NOT

constant over its op erati n g ran ge .

The bandwidth limit corresponds to the so-called Gardner’s criteria. It

corresponds to the maximum value that can be chosen before the

continuous time approximatio n ceases to be justified. It is of course

advisable to stay far away from this limit.

Fc210

9ζ2

⋅⋅

πRC⋅⋅

------------------------- 415.61 e

1.675 Fbus

–

10.795

-----------------------------





R⋅⋅

2πm⋅⋅

---------------------------------------------------------==

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Appendix: CGM Practical Aspects

Practical Aspects For The PLL Usage

MC68HC912DG128 — Rev 3.0 Technic al Data

Appendix: CGM Practical Aspects

Table 20-1. Suggested 8MHz Synthesis PLL Filter Elements (Tracking Mode)

Reference [MHz] SYNR Fbus [MHz] C0

[nF] R0

[kΩ]Cp

[kΩ]

Loop

Bandwidth

[kHz]

Bandwidth

Limit [kHz]

0.614 $0C 7.98 100 4.3 10 1.1 157

0.614 $0C 7.98 4.7 20 0.47 5.3 157

0.614 $0C 7.98 1 43 0.1 11.5 157

0.614 $0C 7.98 0.33 75 0.033 20 157

0.8 $09 8.00 220 2.7 22 0.9 201

0.8 $09 8.00 10 12 1.0 4.2 201

0.8 $09 8.00 2.2 27 0.22 8.6 201

0.8 $09 8.00 0.47 56 0.047 19.2 201

1 $07 8.00 220 2.4 22 1 251

1 $07 8.00 10 11 1.0 4.7 251

1 $07 8.00 2.2 24 0.22 9.9 251

1 $07 8.00 0.47 51 0.047 21.4 251

1.6 $05 8.00 330 1.5 33 1 402

1.6 $05 8.00 10 9.1 1.0 5.9 402

1.6 $05 8.00 3.3 15 0.33 10.2 402

1.6 $05 8.00 1 27 0.1 18.6 402

2 $03 8.00 470 1.1 47 0.96 502

2 $03 8.00 22 5.1 2.2 4.4 502

2 $03 8.00 4.7 11 0.47 9.6 502

2 $03 8.00 1 24 0.1 20.8 502

2.66 $02 8.00 220 1.5 22 1.6 668

2.66 $02 8.00 22 4.7 2.2 5.1 668

2.66 $02 8.00 4.7 10 0.47 11 668

2.66 $02 8.00 1 22 0.1 24 668

4 $01 8.00 220 1.2 22 1.98 1005

4 $01 8.00 33 3 3.3 5.1 1005

4 $01 8.00 10 5.6 1.0 9.3 1005

4 $01 8.00 2.2 12 0.22 19.8 1005

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Technical Data MC68HC912DG128 — Rev 3.0

Appendix: CGM Practical Aspects

Table 20-2. Suggested 8MHz Synthesis PLL Filter Elements (Acquisition Mode)

Reference

[MHz] SYNR Fbus

[MHz] C0 [nF] R0 [kΩ]C

p [nF] Loop

Bandwidth

[kHz]

Bandwidth

Limit [kHz]

0.614 $0C 7.98 1000 0.43 100 1.2 157

0.614 $0C 7.98 47 2 4.7 5.5 157

0.614 $0C 7.98 10 4.3 1.0 12 157

0.614 $0C 7.98 3.3 7.5 0.33 21 157

0.8 $09 8.00 2200 0.27 220 0.9 201

0.8 $09 8.00 100 1.2 10 4.4 201

0.8 $09 8.00 22 2.4 2.2 9.3 201

0.8 $09 8.00 4.7 5.6 0.47 20.1 201

1 $07 8.00 2200 0.22 220 1 251

1 $07 8.00 100 1.0 10 4.8 251

1 $07 8.00 2. 2.2 2.2 10.4 251

1 $07 8.00 4.7 4.7 0.47 22.5 251

1.6 $05 8.00 3300 0.15 330 1.1 402

1.6 $05 8.00 100 0.82 10 6.2 402

1.6 $05 8.00 33 1.5 3.3 10.7 402

1.6 $05 8.00 10 2.7 1.0 19.5 402

2 $03 8.00 4700 0.1 470 1 502

2 $03 8.00 220 0.51 22 4.6 502

2 $03 8.00 47 1.0 4.7 10 502

2 $03 8.00 10 2.4 1.0 21.8 502

2.66 $02 8.00 2200 0.12 220 1.7 668

2.66 $02 8.00 220 0.43 22 5.3 668

2.66 $02 8.00 47 1.0 4.7 11.6 668

2.66 $02 8.00 10 2 1.0 25.1 668

4 $01 8.00 2200 0.1 220 2.1 1005

4 $01 8.00 330 0.27 33 5.4 1005

4 $01 8.00 100 0.51 10 9.7 1005

4 $01 8.00 22 1.0 2.2 20.8 1005

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Appendix: CGM Practical Aspects

Printed Circuit Board Guidelines

MC68HC912DG128 — Rev 3.0 Technic al Data

Appendix: CGM Practical Aspects

20.5 Printe d Cir cu it Boa rd Guideline s

Printed Circuit Boards (PCBs) are the board of choice for volume

applications. If d esigned correctly, a ve ry low noise system can b e b uilt

on a PCB with con sequ ently goo d EMI/ EMC per forma nces. If de signe d

incorrectly , PCBs can be extrem ely no isy and sensitive modules, and

the CGM could be disrupted. Some common sense rules can be used to

prevent such problems.

•Use a ‘star’ style power routing plan as opposed to a ‘daisy chain’.

Route power a nd ground from a central location to each ch ip

individually, and use the widest trace practical (the more the chip

draws cur rent, the wi der the trace ). NEVER pla ce the MCU at th e

end of a long string of serially connected chips.

•When using PCB layout soft ware, first d irect the routing of the

power supply lines as well as the CGM wires (crystal oscillator and

PLL). Layout constraints must be then reported on the other

signals a nd not on these ‘hot’ nodes. Optimizing the ‘hot’ nodes at

the end of the routing process usually gives bad results.

•Avoid notches in power traces. These notches not only add

resistance (and are not usually accounted for in simulations), but

they can also add unnecessary transmission line effects.

•Avoid ground and power loops. This has been one of the most

violated guidelines of PCB layout. Loops are excellent noise

transmitters and can be easily avoided. When using multiple layer

PCBs, the power and ground plane conc ept works well but only

when strictly adhe red to (do not compro mise the grou nd pla ne b y

cutting a hol e in i t and runnin g signa ls on t he gro und p lane la yer).

Keep the spacing around via holes to a minimum (but not so small

as to add capacitive effects).

•Be aw are of the thre e dimension al capac itive effects of multi-

layered PCBs.

•Bypass (d ecou ple ) th e p ower sup pl ies o f all chips as close to th e

chip as po ssibl e. Use one d ecoup lin g capa cit or pe r po wer supply

pair (VDD/VSS, VDDX/VSSX...). Two capacitors with a ratio o f

about 100 sometimes offer better performances over a broader

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Technical Data MC68HC912DG128 — Rev 3.0

Appendix: CGM Practical Aspects

spectrum. This is especially the case for the power supply pins

close to the E port, when the E clock and/or the calibration clock

are used.

•On the gene ral VDD power supply inpu t, a ‘T’ low pass filter LCL

can be used (e.g. 10µH-47µF-10µH). The ‘T’ is preferable to the

‘Π’ version as the exhibited impedance is more constant with

respect to the VDD cur rent . Like m any mo dul ar micro contro ller s,

HC12 devices have a power consumption which not only varies

with cloc k edges but also with the functioning modes.

•Keep high speed clock and bus trace length to a minimum. The

higher th e cloc k speed, th e shorter the trac e length. If noisy

signals are sent o ver long tracks, impedanc e adjustments sho uld

be consi dered at bo th ends of t he line ( generally , simple re sistors

suffice).

•Bus drivers like the CAN physical interface should be installed

close to their connector, with dedicated filtering on their power

supply.

•Mount components as close to the board as possible. Snip excess

lead length as clos e to the board as possible. Preferably use

Surface Mount Devices (SMDs).

•Mount discrete components as close to the chip that uses them as

possible.

•Do not cross sensitive signals ON ANY LAYER. If a sensitive

signal must be crossed by another signal, do it as many layers

away as possible and at r ight angles.

•Always keep PCBs clean. Solder flux, oils from fingerprints,

humidity and general dirt can conduct electricity. Sensitive circuits

can easily be disrupted by small amounts of leakage.

•Choose PCB coatings with care. Certain epoxies, paints, gelatins,

plastics and waxes can conduct electricity. If the manufacturer

cann ot provide th e elect r ical characteristics of the substanc e, do

not use it.

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Appendix: CGM Practical Aspects

Printed Circuit Board Guidelines

MC68HC912DG128 — Rev 3.0 Technic al Data

Appendix: CGM Practical Aspects

In addition to the above general pieces of advice, the following

guidelines should be followed for the CGM pins (but also more generally

for any sensitive analog circuitry):

•Parasitic capacitance on EXTAL is absolutely critical – prob ab ly

the most critical layout consideration. The XTAL pin is not as

sensitive. All routing from the EXTAL pin through the resonator

and the blocking cap to the actual connection to VSS must be

considered.

•For minimum capacitance there should ideally be no ground /

power plane around the EXTAL pin and associated routing.

However, practical EMC considerations obviously should be taken

into consideration for each application.

•The clock input circuitry is sensitive to noise so excellent supply

routing and decoupling is mandatory. Connect the ground point of

the oscillator circuit directly to the VSSPLL pin.

•Good isolation of PLL / Oscillator Power supply is critical. Use

1nF+ 100nF and keep tracks as low impedance as possible

•Load capacitors should be low leakage and stable across

temperature – use NPO or C0G types.

•The load cap acitors may ‘pull’ the target freq uency by a few ppm.

Crystal manufacturer specs show symmetrical values but the

series device capacitance on EXTAL and XTAL are not

symmetrical. It may be possible to adjust this by changing the

values of t he lo ad capaci to rs – start-up conditions should be

evaluated.

•Keep th e adjacent Port H / Port E a nd R ESE T signals n oise free .

Don’t connect these to external signals and / or add series filtering

– a series resistor is probably adequate.

•Any DC-blocking capacitor should be as low ESR as possible – for

the ran ge of crystals we are looking at a nything ove r 1 Ohm i s too

much.

•Mount oscillator components on MCU side of board – avoid using

vias in the oscillator circuitry.

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Appendix: CGM Practical Aspects

Technical Data MC68HC912DG128 — Rev 3.0

Appendix: CGM Practical Aspects

•Mount the PLL filter and oscillator components as close to the

MCU as possible.

•Do not allow the EXTAL and XTAL signals to interfere with the

XFC node. Keep these tracks as short as possible.

•Do not cross the CGM signals with any other signal on any level.

•Remember that the reference voltage for the XFC filter is

VDDPLL.

•As the return path for the oscilla tor circuitry is VSSPLL, it is

extremely important to CONNECT VSSPLL to VSS even if the

PLL is not to be powered. Surface mount components reduce the

susceptibili ty o f signal contaminatio n.

•Ceramic reso nators with built-in capacitors are available. This is

an interesting solution because the parasitic components involved

are min i mized due to the clo se proximity of the resonating

elements.

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MC68HC912DG128 — Rev 3.0 Technic al Data
Appendix: MC68HC912DG128A Flash
 
Technical Data — MC68HC912DG128
Section 21. Append ix: MC68HC912DG128A Flash
21.1  Contents
21.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .419
21.3 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .420
21.4 Flash EEPROM Control Block . . . . . . . . . . . . . . . . . . . . . . . .420
21.5 Flash EEPROM Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .420
21.6 Flash EEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .421
21.7 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 23
21.8 Programming the Flash EEPROM . . . . . . . . . . . . . . . . . . . . .424
21.9 Erasing the Flash EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . .425
21.10 Stop or Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .425
21.2  Introduction
The four Flash EEPROM array modules 00FEE32K, 01FEE32K, 
10FEE32K and 11FEE32K for the 68HC912DG128A serve as 
electrically erasable and programmable, non-volatile ROM emulation 
memory. The modules can be used for program code that must either 
execute at high speed or is frequently executed, such as operating 
system kernels a nd standard sub routines, or they  can be used  for static 
data which is read frequently. The Flash EEPROM module is ideal for 
program storage for sin gle-c hip appl ications allowing for field 
reprogramming.
    
  
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Appendix: MC68HC912DG128A Flash

Technical Data MC68HC912DG128 — Rev 3.0

Appendix: MC68HC912DG128A Flash

21.3 Overview

Each 32K Flash EEPROM array is arranged in a 16-bit configuration and

may be read as either bytes, aligned words or misaligned words. Access

time is one bus cycle for byte and aligned word access and two bus

cycles for misaligned word operations.

Programming is by aligned word. The Flash EEPROM module supports

bulk erase only.

Each Flash EEPROM module has hardware interlocks which protect

stored data from accidental corruption. An erase- and program-

protected 8-Kbyte block for boot routines is located at the top of each 32-

Kbyte array. Since boot programs must be available at all times, the only

useful boot block is at $E000–$FFFF location. All paged boot blocks can

be used as protected program space if desired.

21.4 Flash EEPROM Con trol Block

A 4-byte register block for each module controls the Flash EEPROM

operation. Config uration informatio n is specified and programmed

independently from the contents of the Flash EEPROM array. At reset,

the 4-byte register section starts at address $00F4 and points to the

00FEE32K register block.

21.5 Flash EEPROM Arrays

After reset, a fixed 32K Flash EEPROM array, 11FEE32K, is located

from addresses $4000 to $7FFF and from $C000 to $FFFF. The other

three 32K Flash EEPROM arrays 00FEE32K, 01FEE32K and

10FEE32K, are mapped through a 16K byte program pag e window

located from addresses $8000 to $BFFF. The page window has eight

16K byte pages. The last two pages also map the physical location of the

fixed 32K Flash EEPROM array 11FEE32K. In expanded modes, the

Flash EEPROM arrays are turned off. See Operating Modes.

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Appendix: MC68HC912DG128A Flash

Flash EEPROM Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

Appendix: MC68HC912DG128A Flash

21.6 Flash EEPROM Registers

Each 32K byte Flash EEPROM module has a set of registers. The

Each re gister page of four bytes maps t he registe r space for each Flash

module an d each pa ge is sel ect ed by the PPA GE re gi ster. See

Operatin g Mo de s.

In normal modes the LOCK bit can only be written once after reset.

LOCK — Lock Register Bit

0 = Enable write to FEEMCR register

1 = Disable write to FEEMCR register

This regi ste r cont ro l s the operation of the Flash EEPROM array.

BOOTP cannot be changed when the LOCK control bit in the

FEELCK register is set or if ENPE in the FEECTL register is set.

BOOTP — Boot Protect

The boot blo cks are located at $E0 00–$FFFF and $A000–$BFFF for

odd program pages for each Flash EEPROM module. Since boot

programs must be available at all times, the only useful boot block is

at $E000–$FFFF location. All paged boot blocks can be used as

protected program space if desired.

0 = Enable erase and program of 8K byte boot block

1 = Disable erase and program of 8K byte boot block

FEELCK — Flash EEPROM Lock Control Register $00F4

Bit 7 6 5 4 3 2 1 Bit 0

0 0 0 0 0 0 0 LOCK

RESET: 0 0 0 0 0 0 0 0

FEEMCR — Flash EEPROM Module Configuration Register $00F5

Bit 7 6 5 4 3 2 1 Bit 0

0 0 0 0 0 0 0 BOOTP

RESET: 0 0 0 0 0 0 0 1

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Appendix: MC68HC912DG128A Flash

Technical Data MC68HC912DG128 — Rev 3.0

Appendix: MC68HC912DG128A Flash

This regi ste r control s the pro gr am m i ng an d era sur e of the Fla s h

EEPROM.

FEESWAI — Flash EEPROM Stop in Wait Control

0 = Do not halt Flash EEPROM clock when the part is in wait

mode.

1 = Halt Flash EEPROM clock when the part is in wait mode.

HVEN — High-Voltage Enable

This bit enables the charge pump to supply high voltages for program

and erase operations in the array. HVEN can only be set if either PGM

or ERAS are set and the proper sequence for program or erase is

followed.

0 = Disables hi gh voltage to array and charge pump off

1 = Enables high voltage to array and charge pump on

ERAS — Erase Cont ro l

This bit config ur es the me m or y for er ase operati o n. ER AS is

interl ocke d w it h the PG M bit su ch t ha t bo th bi ts ca nn ot be eq ual to 1

or set to1 at the same time.

0 = Erase operation is not selected.

1 = Erase operation selected.

PGM — Program Control

This bit configures the memory for program operation. PGM is

interl ocked with th e ERAS bit such that bo th bits cann ot be equa l to 1

or set to1 at the same time.

0 = Program operation is not selected.

1 = Progra m operation selecte d.

FEECTL — Flash EEPROM Control Register $00F7

Bit 7 6 5 4 3 2 1 Bit 0

0 0 0 FEESWAI HVEN 0ERAS PGM

RESET: 0 0 0 0 0 0 0 0

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Appendix: MC68HC912DG128A Flash

Operation

MC68HC912DG128 — Rev 3.0 Technic al Data

Appendix: MC68HC912DG128A Flash

21.7 Operation

The Flash EEPROM can contain program and data. On reset, it can

operate as a bootstrap memory to provide the CPU with internal

initializatio n in formation dur ing the reset sequence .

21.7.1 Bootstrap Operation Single-Chip Mode

After reset, the CPU controlling the system will begin booting up by

fetching the first program address from address $FFFE.

21.7.2 Normal Operation

The Flash EEPROM allows a byte or aligned word read in one bus cycle.

Misaligned word read require an additional bus cycle. The Flash

EEPROM ar r ay re spo nd s to re ad opera ti on s onl y. W rite oper ati o ns ar e

ignored.

21.7.3 Program/Erase Operation

An unprogrammed Fl ash EEPROM bit has a lo gic st ate of one. A bit

must be programmed to change its state from one to zero. Erasing a bit

returns it to a logic one. The Flash EEPROM has a minimum

program/erase life of 100 cycles. Programming or erasing the Flash

EEPROM is accomplished by a series of control register writes.

Progra mming is restricted to aligned word at a time as determined by

internal signal SZ8 and ADDR[0]. The Flash EEPROM must first be

completely erased prior to programming final data values.

Programming and erasing of Flash locations cannot be performed by

code bei ng execu ted fr om the FLASH m em ory . W hil e the se op er at ions

must be perfor m ed i n th e or de r sh ow n, other unrel at ed o per a t ions m ay

occur between the steps. Do not exceed tFPGM maximum (40µs).

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Appendix: MC68HC912DG128A Flash

Technical Data MC68HC912DG128 — Rev 3.0

Appendix: MC68HC912DG128A Flash

21.8 Programming the Flash EEPROM

Programming the Flash EEPROM is done on a row basis. A row consists

of 64 consecu tive bytes starting from addresses $XX0 0, $XX40, $XX80

and $XXC 0. Use this step -by-step proced ure to progr am a row of Flash

memory.

1. Set the PGM bit. This configures the memory for program

operation and enables the latching of address and data for

programming.

2. Write to any Flash address with any data within the row address

range desir ed.

3. Wait for a time, tNVS (min. 10µs).

4. Set the HVEN bit.

5. Wait for a time, tPGS (min. 5µs).

6. Write to the Flash address with data to the word desired to be

programmed. If BOOTP is asserted, an attempt to program an

address in the boot block will b e ignored.

7. Wait for a time, tFPGM (min. 30µs).

8. Re peat steps 6 and 7 until all the words within the row are

programmed.

9. Clear the PGM bit.

10. Wait for a time, tNVH (min. 5µs).

11. Clear the HVEN bit.

12. After time , tRCV (min 1µs), the memory can be accessed in read

mode again.

This program sequence is repeated throughout the memory until all data

is programmed. For minimum overall programming time and least

progra m disturb effect, the sequence shou ld be part of an intelligent

operation which iterates p er row.

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Appendix: MC68HC912DG128A Flash

Erasing the Flash EEPROM

MC68HC912DG128 — Rev 3.0 Technic al Data

Appendix: MC68HC912DG128A Flash

21.9 Erasing the Flash EEPROM

The fol lowing sequen ce demonstr ates t he re commen ded p roced ure f or

erasing any of the Flash EEPROM array.

1. Set the ERAS bi t.

2. Writ e to any valid address in the Flash array. The data written and

the addr ess written are not important. The boot blo ck will be

erased only if the control bit BOOTP is negated.

3. Wait for a time, tNVS (min. 10µs).

4. Set the HVEN bit.

5. Wait for a time, tERAS (min. 8ms).

6. Clear the ERAS bit.

7. Wait for a time, tNVHL (min. 100µs).

8. Clear the HVEN bit.

9. After time, t RCV (min 1µs), the memory can be accessed in read

mode again.

21.10 Stop or Wait Mode

When stop or wait commands are exec uted , the MC U puts the Flash

EEPROM in stop or wait mode. In these modes the Flash module will

cease erasure or programming immediately.

CAUTION: It is advised not to enter stop or wait modes when program or erase

operation of the Flash array is in progress.

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Appendix: MC68HC912DG128A Flash

Technical Data MC68HC912DG128 — Rev 3.0

Appendix: MC68HC912DG128A Flash

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MC68HC912DG128 — Rev 3.0 Technic al Data
Appendix: MC68HC912DG128A EEPROM
 
Technical Data — MC68HC912DG128
Section 22. Appendix: MC68HC912DG128A EEPROM
22.1  Contents
22.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .427
22.3 EEPROM Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . .428
22.4 EEPROM Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . .430
22.5 Program/Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .436
22.6 Shadow Word Mapping  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .436
22.7 Programming EEDIVH and EEDIVL Registers. . . . . . . . . . . .437
22.2  Introduction
The 68HC912DG128A EEPROM nonvolatile memory is arranged in a 
16-bi t configur at ion. The EEPROM arr ay may be re ad  as eithe r  bytes, 
aligned words or misaligned words. Acce ss times a re on e bus cycle  for 
byte and aligned word access and two bus cycles for misaligned word 
operations. 
Programming is by byte or aligned word. Attempts to program or erase 
misaligned words will fail. Only the lower byte will be latched and 
programmed or erased. Programming and erasing of the user EEPROM 
can be done in normal modes.
Each EEPROM byte or aligned word must be erased before 
programming. The EEPROM module  supports byte, aligned word, row 
(32 bytes)  or bulk erase, all  using  the intern al charge pump . The erased 
state is $FF. The EEPROM module has hardware interlocks which 
prot ect stored data from  corruption by ac cidentally enabling the 
program/erase voltage. Programming voltage is derived from the 
internal VDD supply with an internal charge pump.
    
  
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Appendix: MC68HC912DG128A EEPROM

Technical Data MC68HC912DG128 — Rev 3.0

Appendix: MC68HC912DG128A EEPROM

22.3 EEPROM Programm er’s Model

The EEPR OM module con sists of two se parately addr essable sectio ns.

The first is an eight-byte memory mapped cont rol register block used for

control, testing and configuration of the E EPROM array. The second

section is the EEPROM array itself.

At reset, t he eight-byt e register sectio n starts at add ress $00EC and the

EEPROM array is located from addresses $0800 to $0FFF. Registers

$00EC-$00ED are rese rved.

Read/write access to the memory array section can be enabled or

disabled by the EEON control bit in the INITEE register ($0012). This

feature allows the access of memory mapped resources that have lower

priority than the EEPROM memory array. EEPROM control registers can

be accessed re gardless of the state of EEON. For in formation on re-

mapping the register block and EEPROM address space, refer to

Operatin g Mo de s.

CAUTION: It is strongly recommended to discont inue pr ogram/erase operations

during WAIT (when EESWAI=1) or STOP modes since all

program/erase activities will be terminated abruptly and cons idered

unsuccessful.

For lowe st power consumpt ion during WAIT mode, it is advised to turn

off EEPGM.

The EEPROM module contains an extra word called SHADOW word

which is loaded at reset into the EEMCR, EEDIVH and EEDIVL

registers. To program the SHADOW word, when in special modes

(SMODN=0), the NOSHW bit in EEMCR register must be cleared.

Normal programming routines are used to program the SHADOW word

which becomes a ccessible at add ress $0FC0–$0FC1 when NOSHW is

cleared. At the next reset the SHADOW word data is loaded into the

EEMCR, EEDIVH and EEDIVL registers. The SHADOW word can be

protected from being programmed or erased by setting the SHPROT bit

of EEPROT register.

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Appendix: MC68HC912DG128A EEPROM

EEPROM Programmer’s Model

MC68HC912DG128 — Rev 3.0 Technic al Data

Appendix: MC68HC912DG128A EEPROM

A steady internal self-time clock is required to provide accurate counts

to meet EEP ROM program/erase requirements. This clock is generated

via by a programmable 10-bit prescaler register. Automatic

prog ram/erase termination is also pro vided.

In ordinary situations, with crystal operating properly, the steady internal

self-time clock is derived from the input clock source (EXTALi). The

divider value is as in EEDIVH:EEDIVL. In limp-home mode, where the

oscillator has malfunctioned or is unavailable, the self-time clock is

derived from the PLL with approximately 1 MHz frequency, with a

predefined divider value of $0023. Program/erase operation is not

guaranteed in limp-home mode. The clock switching function is only

applicable for permanent loss of crystal condition, so the program/erase

will also not be guaranteed when the loss of crystal condition is

intermittent.

It is strongly recommended that the clock monitor is enabled to ensure

that the program/erase operation will be shutdown in the event of loss of

crystal with a clock monitor reset, or switch to a limp-home mode clock.

This will pr event unnecessary stress on the emulated EEPROM during

oscillator failure.

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Appendix: MC68HC912DG128A EEPROM

Technical Data MC68HC912DG128 — Rev 3.0

Appendix: MC68HC912DG128A EEPROM

22.4 EEPROM Con t rol Regi sters

EEDIV[9:0] — Prescaler divider

Loaded from SHADOW word at reset.

Read anytime. Write once in normal modes (SMODN =1) if EELAT =

0 and anytime in special modes (SMODN =0) if EELAT = 0.

The prescaler divider is required to pro duce a self -time clock with a

fixed freque ncy around 28.6 Khz for the range of oscilla tor

frequencies. The divider is set so that the oscillator frequency can be

divided by a divide f actor that can p r oduce a 35 µs +/- 2µs pulse.

CAUTION: An incorrect or uninitialized value on EEDIV can result in overstress of

EEPROM array during program/erase operati on. It is also s trong ly

recomm end not t o program EEPROM with oscillator frequencies less

than 250 Khz.

The EEDIV value is determined by the following formula:

NOTE: INT[A] denotes the round down integer value of A. Program/erase cycles

will not be activated when EEDIV = 0.

EEDIVH — EEPROM Modulus Divider $00EE

Bit 7654 321Bit 0

000000EEDIV9EEDIV8

RESET: 0 0 0 0 0 0 —(1) —(1)

1. Loaded from SHADOW word.

EEDIVL — EEPROM Modulus Divider $00EF

Bit 7654 321Bit 0

EEDIV7 EEDIV6 EEDIV5 EEDIV4 EEDIV3 EEDIV2 EEDIV1 EEDIV0

RESET: —(1) —(1) —(1) —(1) —(1) —(1) —(1) —(1)

1. Loaded from SHADOW word.

EEDIV INT EXTALi (hz) x 3 5 6–

×10 0.5+[]=

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Appendix: MC68HC912DG128A EEPROM

EEPROM Contro l Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

Appendix: MC68HC912DG128A EEPROM

Bits[7:4] are loaded at reset from the EEPROM SHADOW word.

NOTE: The bits 5 and 4 are reserved for test purposes. These locations in

SHADOW word should not be programmed otherwise some locations of

regular EEPROM array will not be more visible.

NOBDML — Background Debug Mod e Lockout Disable

0 = The BDM lockout is enabled.

1 = The BDM lockout is disabled.

Loaded from SHADOW word at reset.

Read anytime. Write anytime in special modes (SMODN=0).

NOSHW — SHADOW Word Disable

0 = The SHADOW word is enabled and accessible at address

$0FC0-$0FC1.

1 = Regula r EEPROM array at address $0FC0-$ 0FC1.

Loaded from SHADOW word at reset.

Read anytime. Write anytime in special modes (SMODN=0).

When NOSHW cleared, the regular EEPROM array bytes at address

$0FC0 and $0FC1 are not visible. Th e SHADOW wor d is accessed

instead for both read and program/erase operations. Bits[7:4] from

Table 22-1. EEDIV Selection

Osc Freq. Osc Period Divide Factor EEDIV

16 Mhz 62.5ns 560 $0230

8 Mhz 125ns 280 $0118

4 Mhz 250ns 140 $008C

2 Mhz 500ns 70 $0046

1 Mhz 1µs 35 $0023

500 Khz 2µs 18 $0012

250 Khz 4µs 9 $0009

EEMCR — EEPROM Module Configuration $00F0

Bit 7654 321Bit 0

NOBDML NOSHW RESERVED(1) 1 EESWAI PROTLCK DMY

RESET: —(2) —(2) —(2) —(2) 1100

1. Bits 4 and 5 have test functions and should not be programmed.

2. Loaded from SHADOW word.

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Appendix: MC68HC912DG128A EEPROM

Technical Data MC68HC912DG128 — Rev 3.0

Appendix: MC68HC912DG128A EEPROM

the high byte of the SHADOW word, $0FC0, are loaded to

EEMCR[7:4]. Bits[1:0] from the high byte of the SHADOW word,

$0FC0,are loaded to EEDIVH[1:0]. Bits[7:0] from the low byte of the

SHAD OW wo r d, $0FC 1 ,ar e lo aded to EEDIV L[7 : 0] . BULK

prog ram/erase on ly applies if SHADOW word is enabled.

NOTE: Bit 6 from high byte of SHADOW word should not be programmed in

order to have the full EEPROM array visible.

EESWAI — EEPROM Stops in Wait Mode

0 = The module is not affected during WAIT mode

1 = The module ceases to be clocked during WAIT mode

Read and write anytime.

NOTE: The EESWAI bit should be cleared if the WAIT mode vectors are

mapped in the EEPROM array.

PROTLCK — Blo ck Protect Write Lock

0 = Block protect bits and bulk erase protection bit can be written

1 = Block protect bits are locked

Read anytime. Write once in normal modes (SMODN = 1), set and

clear any time in special modes (SMODN = 0 ).

DMY— Dummy bit

Read and write anytime.

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Appendix: MC68HC912DG128A EEPROM

EEPROM Contro l Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

Appendix: MC68HC912DG128A EEPROM

Preven ts accidenta l writes to EEPROM. R ead anytime. W rite anyti me if

EEPGM = 0 and PROTLCK = 0.

SHPROT — SHADOW Word Protection

0 = The SHADOW word can be programmed and erased.

1 = The SHADOW word is protected from being programmed and

erased.

BPROT[5:0] — EEPROM Block Protection

0 = Associated EEPROM block ca n be programmed and erased.

1 = Associated EEPROM block is protected from being

prog rammed a nd erased.

In normal mode, writes to EETST control bits have no effect and

always read zero. The EEPROM module cannot be placed in test

mode inadvertently during no rmal operation

EEPROT — EEPROM Block Protect $00F1

Bit 7654321Bit 0

SHPROT 1 BPROT5 BPROT4 BPROT3 BPROT2 BPROT1 BPROT0

RESET: 1 1 1 1 1 1 1 1

Table 22-2. 2K byte EEPROM Block Protection

Bit Name Block Protected Block Size

BPROT5 $ 0800 to $0BFF 10 24 Bytes

BPROT4 $0C00 to $0DFF 512 Bytes

BPROT3 $0E00 to $0EFF 256 Bytes

BPROT2 $0F00 to $0F7F 128 Bytes

BPROT1 $0F80 to $0FBF 64 Bytes

BPROT0 $0FC0 to $0FFF 64 Bytes

EETST — EEPROM Test $00F2

Bit 7654321Bit 0

0 EREVTN 0 0 0 ETMSD ETMR ETMSE

RESET:00000000

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Appendix: MC68HC912DG128A EEPROM

Technical Data MC68HC912DG128 — Rev 3.0

Appendix: MC68HC912DG128A EEPROM

BULKP — Bulk Erase Protection

0 = EEPROM can be bulk erased.

1 = EEPROM is protected from being bulk or row erased.

Read anytime. Write anytime if EEPGM = 0 and PROTLCK = 0.

AUTO — Automatic shutdown of program/er ase operation.

EEPGM is cleared automatically after the program/erase cycles are

finished when AUTO is set.

0 = Automati c clear of EEPGM is disabled.

1 = Automati c clear of EEPGM is enabled.

Read anytime. Write anytime if EEPGM = 0.

BYTE — Byte and Aligned Word Erase

0 = Bulk or row erase is enab led.

1 = One byte or one aligned word erase only.

Read anytime. Write anytime if EEPGM = 0.

ROW — Row or Bulk Erase (when BYTE = 0)

0 = Erase entire EEPROM array.

1 = Erase only one 32-byte row.

Read anytime. Write anytime if EEPGM = 0.

BYTE an d ROW have no effect when ERASE = 0

EEPROG — EEPROM Control $00F3

Bit 7654321Bit 0

BULKP 0 AUTO BYTE ROW ERASE EELAT EEPGM

RESET:10000000

Table 22-3 . Erase Selectio n

BYTE ROW Block size

0 0 Bulk erase entire EEPROM array

0 1 Row erase 32 bytes

1 0 Byte or aligned word erase

1 1 Byte or aligned word erase

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Appendix: MC68HC912DG128A EEPROM

EEPROM Contro l Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

Appendix: MC68HC912DG128A EEPROM

If BYTE = 1 only the location specified by the address written to the

progra mming latches will be era s ed. The operation will be a byte or

an aligned word erase depending on the size of written data.

ERASE — Erase Cont rol

0 = EEPROM configuration for programming.

1 = EEPROM configuration for erasure.

Read anytime. Write anytime if EEPGM = 0.

Configures the EEPROM for erasure or programming.

Unless BULKP is set, erasure is by byte, aligned word, row or bulk.

EELAT — EEPROM Latch Control

0 = EEPROM set up for normal reads.

1 = EEPROM address and data bus latches set up for

prog r am m i ng or era sing.

Read anyt ime .

Write anytime except when EEPGM = 1 or EEDIV = 0.

BYTE, ROW, ERASE and EELAT bits can be written simultaneously

or in any sequence.

EEPGM — Pr og ra m and Erase Enable

0 = Disables program/erase voltage to EEPROM.

1 = Applies program/erase volt age to EEPRO M .

The EEPGM bit can be set only after EELAT has been set. When

EELAT and EEPGM are set simultaneously, EEPGM remains clear

but EELAT is set.

The BULKP, AUTO, BYTE, ROW, ERASE and EELAT b its cannot be

changed when EEPG M is set. To co mplete a progra m or erase cycle

when AUTO bit is clear, two successive writes to clear EEPGM and

EELAT bits are required before reading the programmed data. When

AUTO bit is set, EEPGM is automat ically cleared after the program or

erase cycle is over. A write to an EEPROM location has no effect

when EEPGM is set. Latched address and data cannot be modified

during program or erase.

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Appendix: MC68HC912DG128A EEPROM

Technical Data MC68HC912DG128 — Rev 3.0

Appendix: MC68HC912DG128A EEPROM

22.5 Program/ Erase Operation

A program or erase operation should follow the sequence below if AUTO

bit is clear :

1. Writ e BYTE, ROW an d ERASE to desired value, write E ELAT = 1

2. Write a byte or an aligned word to an EEPROM address

3. Write EEPGM = 1

4. Wait for programming, tPROG or erase, tERASE delay time (10ms)

5. Write EEPGM = 0

6. Write EELAT = 0

If AUTO bit is set, steps 4 and 5 can be replaced by a step to poll the

EEPGM bit until is cleared.

It is possible to program/erase more bytes or words without intermediate

EEPROM reads, by jumping from step 5 to step 2.

22.6 Shadow Word Mapping

The shadow word is mapped to location $_FC0 and $_FC1 when the

NOSHW bit in EEMCR register is zero. The value in the shadow word is

loaded to the EEMCR, EEDIVH and EEDIVL after reset. Table 22-4

shows the mapping of each bit from shadow word to the registers

Table 22- 4. Shadow word mapping

Shadow word location Register / Bit

$_FC0 bit 7 EEMCR / NOBDML

$_FC0, bit 6 EEMCR / NOSHW

$_FC0, bit 5 EEMCR / bit 5(1)

1. Reserved for testing. Must be set to one in user application.

$_FC0, bit 4 EEMCR / bit 4(1)

$_FC0, bit 3:2 not mapped(2))

2. Reserved. Must be set to one in user application for future compatibility.

$_FC0, bit 1:0 EEDIVH / bit 1:0

$_FC1, bit 7:0 EEMCR / bit 7:0

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Appendix: MC68HC912DG128A EEPROM

Programming EEDIVH and EEDIVL Registers

MC68HC912DG128 — Rev 3.0 Technic al Data

Appendix: MC68HC912DG128A EEPROM

22.7 Programming EEDIVH and EEDIVL Registers

The EEDIVH and EEDIVL registers must be correctly set according to

the oscillator frequency before any EEPROM location can be

prog rammed o r erased.

22.7.1 Normal mode

The EEDI VH and EEDIVL registers are write once in normal mode.

Upon system reset, the application program is required to write correct

divider value to EEDIVH and EEDIVL reg isters based on the oscillator

frequency. After the first write, the value in the EEDIVH and EEDIVL

registers is locked from been overwritten until the next reset. The

EEPRO M is then ready for standard progra m/erase routines.

CAUTION: Runaway code can pos sibly corrup t th e E EDIV H an d E EDIVL reg isters

if they are not initialized for the write on ce.

22.7.2 Special mode

If an existing application code with EEPROM program/erase routines is

fixed and the system is already operating at a known oscillator

frequency, it is recommended to initialize the shadow word with the

corresponding EEDIVH and EEDIVL values in special mode. The

shadow word initializes EEDIVH and EEDIVL registers upon system

reset to ensure software compatibility with existing code. Initializing the

EEDIVH and EEDIVL registers in special modes (SMODN=0) is

accomplished by the following steps.

1. Write correct divider value to EEDIVH and EEDIVL registers

based on the oscillator fr equency as per Table 22-1.

2. Remove the SHADOW word protection by clearing SHPROT bit in

EEPROT register.

3. Clear NOSHW bit in EEMCR register to make the SHADOW word

visible at $0FC0-$0FC1.

4. Write NOSHW bit in EEMCR register to make the SHADOW word

visible at $0FC0-$0FC1.

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Appendix: MC68HC912DG128A EEPROM

Technical Data MC68HC912DG128 — Rev 3.0

Appendix: MC68HC912DG128A EEPROM

5. Program bits 1 and 0 of the high byte of the SHADOW word and

bits 7 to 0 of the low byte of the SHADOW word like a regular

EEPROM location at addre ss $0FC0 and $0FC1. Do not program

other bits of the high byte of the SHADOW word (location $0FC0);

otherwise some regular EEPROM array locations will not be

visible. At the next reset, the SHADOW values are loaded into the

EEDIVH and EEDIVL registers. They do not require further

initialization as long as the oscillator frequency of the target

application is not changed.

6. Protect the SHADOW word by setting SHPROT bit in EEPROT

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MC68HC912DG128 — Rev 3.0 Technic al Data
Revisi on Histor y
 
Technical Data — MC68HC912DG128
Section 23. Revision History
This section lists the revision history of the document since the first 
release. Data for previous versions and internal drafts is unavailable.
Changes from Rev 2.0 to Rev 3.0
Section Page (in Rev 3.0) Description of change
Pinout and Signal 
Descriptions
41 Ca in Figure 3-3 changed to Cp
43 Note added about consideration of crystal selection due to EMC 
emissions
Clock Functions
157 Note added about consideration of crystal selection due to EMC 
emissions
161 Major rewrite of Limp-Home and Fast STOP Recovery modes.
179 System Clock Frequency formulas updated for clarification.
180 Figure 11-6 modified for clarification.
183 Figure 11-9 modified for clarification.
MSCAN Controller 326 First two bullets of sleep mode description updated
339 SLPRQ = 1 description updated
Electrical 
Specifications
392 Changes to maximum EEPROM erase and data retention times
395 fXTAL re moved
395 Footnote added restricting external oscillator operating frequency 
to 8MHz when using a quartz crystal
406 Table footnote removed from Table 19-16  regarding VDDPLL
    
  
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Revision Hist ory
Technical Data MC68HC912DG128 — Rev 3.0
Revisi on Histor y
Changes from Rev 1.0 to Rev 2.0
Appendix: CGM 
Practical Aspects
408 Added section on DC bias
409 Point 3 removed regarding high frequency resonators
412  In paragraph 2, C changed to C0, R changed to R0
413  In Table 20-1
In header, C changed to C0, R changed to R0
Extra column added for Cp
413  In Table 20-2
In header, C changed to C0, R changed to R0
Extra column added for Cp
417 Extra bulle ts added
Section Page (in Rev 2.0) Description of change
Clock Functions 157 Prescaled MCLK and TIMCLK signal names added to Figure 21 
for clarification
ECT 188 Prescaled clock from timer changed to Prescaled MCLK in Figure 
29 for clarification
MSI 244 SP0DR register state on reset clarified
Section Page (in Rev 3.0) Description of change
    
  
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MC68HC912DG128 — Rev 3.0 Technic al Data

Glossary

Technical Data — MC68HC912DG128

Glossary

A — See “accumulators (A and B or D).”

accumulators (A and B or D) — Two 8-bit (A and B) or one 16-bit (D) general-purpose registers

in th e CP U . Th e C P U use s the accu m ul ato rs to h ol d op er an ds an d r e sul ts of ar i thmetic

and logic operations.

acquisition mode — A mode of PLL operation with large loop bandwidth. Also see ’tracking

mode’.

address bus — The set of wires that the CPU or DMA uses to read and write memory locations.

addressing mode — The w ay that the CP U dete rmines th e oper and add ress for a n instruct ion.

The M68HC12 CPU has 15 addressing modes.

ALU — See “arithmetic logic unit (ALU).”

analogue-to-digital convert er (ATD) — The ATD module is an 8-channel, multiplexed-input

successive-approximation analog-to-digital converter.

arithmetic logic unit (ALU) — The portion of the CPU that contains the logic circuitry to perform

arithmetic, logic, and manipulation operations on operands.

asynchronous — Refers to logic circuits and operations that are not synchronized by a common

reference signal.

ATD — See “analogue-to-digital converter”.

B — See “accumulators (A and B or D).”

baud rate — The total number of bits transmitted per unit of time.

BCD — See “binary-coded decimal (BCD). ”

binary — Relating to the base 2 number system.

binary number system — The base 2 number system, having two digits, 0 and 1. Binary

arithmetic is convenient in digital circuit design because digital circuits have two

permissible v oltage levels, lo w and high. The binary digits 0 and 1 can be int erpreted to

correspond to the two digital voltage levels.

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Glossary

Technical Data MC68HC912DG128 — Rev 3.0

Glossary

binary-coded decimal (BCD) — A nota ti on tha t use s 4- bit b in ary nu m bers to repr ese nt t he 1 0

decima l digits and that retains the same positi onal structur e of a deci mal numb er. For

example,

234 (decimal) = 0010 0011 0100 (BCD)

bit — A binary digit. A bit has a value of either logic 0 or logic 1.

branch instruct ion — An instru ction that ca uses the C PU to cont inue pr ocessin g at a memo ry

location other than the next sequential address.

break module — The break module allows software to halt program execution at a

programmable point in order to enter a backgro und routine.

breakpoint — A number written into the break address registers of the break module. When a

numbe r appe ars o n the int ernal address bus th at is t he sam e a s the numb er in the brea k

address registers, the CPU executes the software interrupt instruction (SWI).

break interrupt — A software interrupt caused by the appearance on the internal address bus

of the same value that is written in the break address registers.

bus — A set of wires that transfers logic signals.

bus clock — See "CPU clock".

byte — A set of eight bits.

CAN — See "Freescale scalabl e CAN."

CCR — See “co ndition code reg ist er .”

central processor unit (CPU) — The primary functioning unit of any computer system. The

CPU controls the execution of instructions.

CGM — See “clock generator module (CGM).”

clear — To change a bit from logic 1 to logic 0; the opposite of set.

clock — A square wave signal used to synchronize events in a computer.

clock generator module (CGM) — The CGM module generates a base clock signal from which

the system clocks are derived. The CGM may include a crystal oscillator circuit and/or

phase-locked loop (PLL ) circui t.

comparator — A device that compares the magnitude of two inputs. A digital comparator defines

the equality or relative differences between two binary numbers.

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Glossary

MC68HC912DG128 — Rev 3.0 Technic al Data

Glossary

computer operating properly module (COP) — A counter module that resets the MCU if

allowed to overflow.

condition code register (CCR) — A n 8-bit regist er in the CPU that conta ins the in terr upt mask

bit and five bits that indicate the results of the instruction just executed.

control bit — One bit of a register manipulated by software to control the operation of the

module.

control unit — One o f two major u nits of the CPU. The con trol unit contains lo gic function s that

synchronize the machine and direct various operatio ns. The control unit decodes

instructions and genera tes the internal control s i gnals that perform the requested

operations. The outputs of the control unit drive the execution unit, which contains the

arithmetic logic unit (ALU), CPU registers, and bus inte rface.

COP — See "computer operating properly module (COP)."

CPU — See “central processor unit (CPU).”

CPU12 — The CPU of the MC68HC12 Family.

CPU clock — Bus clock select bits BCSP and BCSS in the clock select register (CLKSEL)

determine which clock drives SYSCLK for the main system, including the CPU and buses.

When EXTALi drives the SYSCLK, the CPU or bus clock frequency (fo) is equal to the

EXTALi frequ en cy divide d by 2.

CPU cycles — A CPU cycle is one period of the internal bus clock, normally d erived by dividing

a crystal oscillator source by two or more so the high and low times will be equal. The

length of time required to execute an instruction is measured in CPU clock cycles.

CPU registers — Memory locations that are wired directly into the CPU logic instead of being

part of the addressable memory map. The CPU always has direct access to the

information in these registers. The CPU registers in an M68HC12 are:

•A (8-bit accumulator)

•B (8-bit accumulator)

–D (16-bit accumulator f ormed by c oncatenatio n of accumulators A and B)

•IX (16- bit index register)

•IY (16- bit index register)

•SP (16-bit stac k point er)

•PC (16- bi t pr ogram counter)

•CCR (8-bit condition code register)

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Technical Data MC68HC912DG128 — Rev 3.0

Glossary

cycle time — The period of the operating frequency: tCYC =1/f

OP.

D — See “accumulators (A and B or D).”

decimal number system — Base 10 numbering system that uses the digits zero through nine.

duty cycl e — A ratio of the amount o f time the signal is on versus the time it is off. Duty cycle is

usually represented by a percentage.

ECT — See “enhanced capture timer.”

EEPROM — Electrically erasable, programmable, read-only memory. A nonvolatile type of

memor y that can be electric ally er ased and reprogrammed.

EPROM — Eras able, pr ogram mable, re ad-onl y memor y. A nonvola tile type of memor y that can

be erased by exposure to an ultraviolet light source and then reprogrammed.

enhanced capture timer (ECT) — The HC12 Enhanced Capture Timer module has the features

of the HC12 Standard Timer module enhanced by additional features in order to enlarge

the field of applications .

exception — An even t such as an inter rupt or a rese t that stops the seq uential ex ecution of the

instructions in the main program.

fetch — To copy data from a memory location into the accumulator.

firmware — Instructions and data programmed into nonvolatile memory.

free-running counter — A device that co un ts fr om zero to a prede t erm i ned nu mb er , th en r o lls

over to zero and begins counting again.

full-duplex transmission — Communication on a channel in which data can be sent and

received simultaneously.

hexadecimal — Base 16 numbering system that uses the digits 0 through 9 and the letters A

through F.

high byte — The most significant eight bits of a word.

illegal address — An address not within the memory map

illegal opcode — A nonexistent opcode.

index registers (IX and IY) — Two 16-bit registers in the CPU. In the indexed addressing

modes, the CPU uses the contents of IX or IY to determine the effective address of the

operand. IX and IY can also s erve a s a temporary data st orage locations.

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MC68HC912DG128 — Rev 3.0 Technic al Data

Glossary

input/output (I/O) — Input/output interfaces between a computer system and the external world.

A CPU reads an input to sense the level of an external signal and writes to an output to

change the leve l on an external sig na l.

instructions — Operations that a CPU can perform. Instructions are expressed by programmers

as assembly lang uage mnemonics. A CPU interprets an opco de and its associated

oper and(s ) and ins truction.

inter-IC bus (I2C) — A two-wire, b idirection al serial bus that p rovides a simple , efficien t method

of data exchange between devices.

interrupt — A temporary break in the sequential execution of a program to respond to signals

from peripheral devices b y executing a subroutine.

interrupt request — A signal from a peri ph er al to the CPU intended to cause the CP U to

execute a subroutine.

I/O — See “input/output (I/0).”

jitter — Short-term signal instability.

latch — A circuit that retains th e voltage level (logic 1 or logic 0) written to it for as long as power

is applied to the circuit.

latency — The time lag between instruction completion and data movement.

least significant bit (LSB) — The rightmost digit of a binary number.

logic 1 — A voltage level ap proximately equal to t he input power voltage (VDD).

logic 0 — A voltage level ap proximately equal to t he grou nd volta ge (VSS).

low byte — The least significant eight bits of a word.

M68HC12 — A Freescale family of 16-bit MCUs.

mark/space — The logic 1/logic 0 convention used in formatting data in serial communication.

mask — 1. A logic circuit that forces a bit or group of bits to a desired state. 2. A photomask used

in integrated circuit fabrication to transfer an image onto silicon.

MCU — Microcontroller unit. See “microcontroller.”

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Technical Data MC68HC912DG128 — Rev 3.0

Glossary

memory location — Each M68HC1 2 memory lo cation holds on e byte of data an d has a unique

address. To store information in a memory location, the CPU places the address of the

location on the address bus, the data information on the data bus, and asserts the write

signal. To read information from a memory location, the CPU places the address of the

location on the address bus and asserts the read signal. In response to the read signal,

the selected memory location places its data onto the data bus.

memory map — A pictorial representation of all memory locations in a computer system.

MI-Bus — See "Freescale interconnect bus".

microcontroller — Microcontroller unit (MCU). A complete computer system, including a CP U,

memory, a clock oscilla tor, and input/output (I/O) on a single integrated circuit.

modulo counter — A counter that can be programmed to count to any number from zero to its

maximum po ssible modulus.

most significant bit (MSB) — The leftmost digit of a binary number.

Freescale interconnect bus (MI-Bus) — The Freescale Interconnect Bus (MI Bus) is a serial

commu nic ations prot oco l whi ch supp or ts distr i bu ted rea l-time contro l efficiently and w ith

a high degree of nois e immunity.

Freescale scalable CAN (fsCAN) — The Freescale scalable controller area network is a serial

communications protocol that efficiently supports distributed real-time control with a very

high l ev el of data integrity.

msCAN — See "Freescale scalable CAN".

MSI — See "multiple serial interface".

multiple serial interface — A module consisting of multiple independent serial I/O sub-systems,

e.g. two SCI and one SPI.

multiplexer — A device tha t can select one of a numb er of inputs and p ass the logic level of that

input on to the output.

nibble — A set of four bits (half of a byte).

object code — The output from an assembler or compiler that is itself executable machine code,

or is suitable for processing to produce executable machine code.

opcode — A b i nary code that instructs the CPU to perform an op eration.

open-drain — An output that has no pullup transi stor. An external pullup device can be

connected to the power supply to provide the logic 1 output voltage.

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MC68HC912DG128 — Rev 3.0 Technic al Data

Glossary

operand — Data on which an operation is performed. Usually a statement consists of an

operator and an operand. For example, the operator may be an add instruction, and the

operand m ay be t he quantity to be added.

oscillator — A circuit that produces a constant frequency square wave that is used by the

computer as a timing and sequencing reference.

OTPROM — One-time programmable read-o nly memory. A non v olatile typ e of memory that

cannot be reprogrammed.

overflow — A quantity that is too large to be contained in one byte or one word.

page zero — The first 256 bytes of memory (addresses $0000–$00FF).

parity — An error-che cking scheme th at counts the number of l ogic 1s in each byte tr ansmitted .

In a system that uses odd parity, every byte is expected to have an odd number of logic

1s. In an even parity system, every byte should have an even number of logic 1s. In the

transmitter, a parity generator appends an extra bit to each byte to make the number of

logic 1s odd for odd parity or even for even parity. A parity checker in the receiver counts

the number of lo gic 1s in each byte . The parity checker gene rates an error signal if it finds

a byte with an incorrect number of logic 1s.

PC — See “program counter (PC).”

peripheral — A circuit not under direct CPU control.

phase-locked loop (PLL) — A clock generator circuit in which a voltage controlled oscillator

prod uces an oscillation which is synchronized to a r eference signal.

PLL — See "phase-locked loop (PLL)."

pointer — Poi nte r re gi ste r. An i nd ex register i s som eti mes called a poi n ter r eg ister b eca use i ts

contents a re used in the calcu lation of the ad dress of an operan d, and therefo re points to

the oper and.

polarity — The two opposite logic levels, logic 1 and logic 0, which correspond to two different

voltage levels, VDD and VSS.

polling — Periodically reading a status bit to monitor the con dition of a peripheral device.

port — A set of wires for communicating with off-chip devices.

prescaler — A circuit that generates an output signal related to the input signal by a fractional

scale factor such as 1/2, 1/8, 1/10 etc.

program — A set of computer instructions that cause a computer to perform a desired operation

or operati on s.

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Technical Data MC68HC912DG128 — Rev 3.0

Glossary

program counter (PC) — A 16-bit register in the CPU. The PC register holds the address of the

next instruction or operand that the CPU will use.

pull — An instruction that copies into the accumulator the contents of a s tack RAM location. The

stack RAM address is in the stack pointer.

pullup — A tr ansistor i n the outp ut of a logi c gate that connects the output to the lo gic 1 voltag e

of the power supply .

pulse-width — The amount of time a signal is on as opposed to being in its off state.

pulse-width modulation (PWM) — Controlled variation (modulation) of the pulse width of a

signal with a constant frequency.

push — A n instruct ion tha t copies th e con tents of t he accumulat or to th e stack RAM. The stack

RAM address is in the stack pointer.

PWM period — The time required for one complete cycle of a PWM waveform.

RAM — Random access memory. All RAM locations can be read or written by the CPU. The

contents of a RAM memory location remain valid until the CPU writes a different value or

until power is turned off.

RC circuit — A circuit consisting of capacitors and resistors having a defined time constant.

read — To copy the contents of a memory location to the accumulator.

reserved memory location — A memory location that is used only in special factory test modes.

Writing to a reserved location has no effect. Read ing a reserved locat ion returns an

unpr edictable value.

reset — To force a device to a known condition.

SCI — See "serial com mu nic a ti on in ter f a ce module (SC I) ."

serial — Pertaining to sequential transmission over a single line.

serial communications interface module (SCI) — A module that supports asynchronous

communication.

serial peripheral interface module (SPI) — A module that supports s ynchronous

communication.

set — To change a bit from logic 0 to logic 1; opposite of clear.

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MC68HC912DG128 — Rev 3.0 Technic al Data

Glossary

shift register — A chain of circuits that can retain the logic levels (logic 1 or logic 0) written to

them and that can shift the logic levels to the right or left through adjacent circuits in the

chain.

signed — A binary number notation that accommodates both positive and negative numbers.

The most significant bit is used to indicate whether the number is positive or negative,

normally logic 0 for positive and logic 1 for negative. The other seven bits indicate the

magnitude of the number.

software — Instructions and data that control the operation of a microcontroller.

software interrupt (SWI) — An instruction that causes an interrupt and its associated vector

fetch.

SPI — See "serial peripheral interface module (SPI)."

stack — A po rtion o f R AM reserved for st or ag e o f C PU re gi ster co nt ents and su br ou ti ne r etu rn

addresses.

stack pointer (S P) — A 16-bit register in the CPU containing the address of the next available

storage location on the stack.

start bi t — A bit that signals the beginning of an asynchronous serial transmission.

status bit — A register bit that indicates the condition of a device.

stop bit — A bit that signals the end of an asynchronous serial tra nsmiss ion.

subroutine — A sequence of instructions to be used more than once in the course of a program.

The la st instructi on in a su br ou ti ne i s a return from su br ou ti ne ( RTS) instr uctio n. At each

place in the main program where the subroutine instructions are needed, a jump or branch

to subr outine (JSR or BSR) inst ruction is u sed to call t he subrouti ne. The CPU leaves the

flow of the main program to execute the instructions in the subroutine. When the RTS

instruction is executed, the CPU returns to the main program where it left off.

synchronous — Refers to logic circuits and operatio ns that are synchronized by a co mmon

reference signal.

timer — A module used to relate events in a system to a point in time.

toggle — To change the state of an ou tput from a logic 0 to a logic 1 or from a lo gic 1 to a logic 0.

tracki ng mode — A mode of PLL operation with narrow loop bandwidth. Also see ‘acquisition

mode.’

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Technical Data MC68HC912DG128 — Rev 3.0

Glossary

two’s complement — A means of performing binary subtraction using addition techniques. The

most significant bit of a two’s complement number indicates the sign of the number (1

indicate s negative). The two’s complement negative of a number is obtained by inverting

each bit in the number and then adding 1 to the result.

unbuffered — Utilizes only one register for data; new data overwrites current data.

unimplemented memory location — A memory location that is not used. Writing to an

unimplemented location has no effect. Reading an unimplemented location returns an

unpredictable value.

variable — A value that changes during the course of program execution.

VCO — See "voltage-controlled oscillator."

vector — A memory l oca tion that con tai n s the ad dress of the begi nn in g of a sub r out in e w ritt en

to service an interrupt or reset.

voltage- controll ed os cillator (VC O) — A circuit that produces an oscillating output signal of a

frequency that is controlled by a dc voltage applied to a control input.

waveform — A graphical representation in which the amplitude of a wave is plott ed against time.

wired-OR — Connection of circuit outputs so that if any output is high, the connection point is

high.

word — A set of two bytes (16 bits).

write — The transfer of a byte of data from the CPU to a memory location.

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MC68HC912DG128/D

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