AMD RS690 Databook Technical Reference Manual Rev. 3.04 P/N: 41977_rs690_ds (c) 2007 Advanced Micro Devices, Inc Please note that in this databook, references to "DVI" and "HDMI" may refer to: (1) the function of the integrated DVI/HDMI interface described in details in section 2.2.1 and 3.7, as well as in other sections; or (2) the capability of the TMDS interface, multiplexed on the PCI-E external graphics interface, to enable DVI or HDMI through passive enabling circuitries. Any statement in this databook on any DVI or HDMI-related functionality must be understood to apply to (1), (2), or both, according to the immediate context of the reference. Advanced Micro Devices, Inc., will not provide any indemnity, pay any royalty, nor provide any license/sublicense to any: (a) Intellectual property rights relating to any of the following: (i) Macrovision for its Analog Protection System ("APS") technologies; (ii) Advanced Television Systems Committee (ATSC) standard and related technologies; or (iii) the High Definition Multimedia Interface (HDMI) standard and related technologies; or (b) Audio and/or video codecs or any industry standard technology (e.g., technology or specifications promulgated by any standards development organization, consortium, trade association, special interest group or like entity). This device is protected by U.S. patent numbers 4,631,603, 4,577,216 and 4,819,098 and other intellectual property rights. The use of Macrovision's copy protection technology in the device must be authorized by Macrovision and is intended for home and other limited pay-per-view uses only, unless otherwise authorized in writing by Macrovision. Reverse engineering or disassembly is prohibited. This device may only be sold or distributed to: (i) a Macrovision Authorized Buyer, (ii) a customer (PMA Customer) who has executed a Proprietary Materials Agreement (PMA) with Macrovision that is still in effect, (iii) a contract manufacturer approved by Macrovision to purchase this device on behalf of a Macrovision Authorized Buyer or a PMA Customer, or (iv) a distributor who has executed a Macrovision-specified distribution agreement with ATI. Trademarks AMD, the AMD Arrow logo, AMD Athlon, AMD Sempron, AMD Turion, AMD Xilleon, AMD Cool'n'Quiet, AMD PowerNow!, and combinations thereof, ATI, the ATI logo, Radeon, Avivo, 3Dc, SmartShader HD, SmoothVision HD, HyperMemory, PowerPlay, and PowerShift are trademarks of Advanced Micro Devices, Inc. HyperTransport is a licensed trademark of the HyperTransport Technology Consortium. Macrovision is a registered trademarks of Macrovision Corporation in the United States and/or other countries. Microsoft, Windows, DirectX, Direct3D, DirectDraw, and ClearType are registered trademarks and Windows Vista is a trademark of Microsoft Corporation. Macrovision is a registered trademarks of Macrovision Corporation in the United States and/or other countries. OpenGL is a registered trademark of SGI. PCI Express is a registered trademark of PCI-SIG. WinBench is a registered trademark of Ziff Davis, Inc. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Disclaimer The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel, or otherwise, to any intellectual property rights are granted by this publication. Except as set forth in AMD's Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. AMD's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD's product could create a situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice. (c) 2007 Advanced Micro Devices, Inc. All rights reserved. Table of Contents Chapter 1: Overview 1.1 Introducing the RS690 ........................................................................................................................................................1-1 1.2 RS690C ...............................................................................................................................................................................1-2 1.3 RS690 Features ...................................................................................................................................................................1-2 1.3.1 CPU HyperTransportTM Interface.........................................................................................................................1-2 1.3.2 ATI HyperMemoryTM Technology.......................................................................................................................1-2 1.3.3 PCI Express(R) Interface .......................................................................................................................................1-2 1.3.4 A-Link Express II Interface..................................................................................................................................1-2 1.3.5 2D Acceleration Features .....................................................................................................................................1-3 1.3.6 3D Acceleration Features .....................................................................................................................................1-3 1.3.7 Motion Video Acceleration Features....................................................................................................................1-4 1.3.8 Multiple Display Features ....................................................................................................................................1-4 1.3.9 DVI/HDMI (Not applicable to the RS690C)........................................................................................................1-5 1.3.10 Power Management Features ...............................................................................................................................1-6 1.3.11 PC Design Guide Compliance..............................................................................................................................1-6 1.3.12 Test Capability Features .......................................................................................................................................1-6 1.3.13 Packaging .............................................................................................................................................................1-6 1.4 Software Features................................................................................................................................................................1-6 1.5 Branding Diagrams .............................................................................................................................................................1-7 1.5.1 Branding Diagrams for ASIC Revision A11........................................................................................................1-7 1.5.2 Branding Diagrams for ASIC Revision A12 and After........................................................................................1-8 1.6 Part Number Legend ...........................................................................................................................................................1-9 1.7 Conventions and Notations ...............................................................................................................................................1-10 1.7.1 Pin Names...........................................................................................................................................................1-10 1.7.2 Pin Types ............................................................................................................................................................1-10 1.7.3 Numeric Representation .....................................................................................................................................1-10 1.7.4 Register Field...................................................................................................................................................... 1-11 1.7.5 Hyperlinks .......................................................................................................................................................... 1-11 1.7.6 Acronyms and Abbreviations ............................................................................................................................. 1-11 Chapter 2: Functional Descriptions 2.1 Host Interface ......................................................................................................................................................................2-2 2.2 DVI/HDMI (Not Applicable to the RS690C) .....................................................................................................................2-4 2.2.1 DVI/HDMI Data Transmission Order and Signal Mapping ................................................................................2-4 2.2.2 Support for HDMI Packet Types..........................................................................................................................2-7 2.3 VGA DAC Characteristics..................................................................................................................................................2-8 2.4 External Clock Chip............................................................................................................................................................2-8 Chapter 3: Pin Descriptions and Strap Options 3.1 Pin Assignment ...................................................................................................................................................................3-2 (c) 2007 Advanced Micro Devices, Inc. Proprietary 41977 AMD RS690 Databook 3.04 Table of Contents-1 3.2 Interface Block Diagram .................................................................................................................................................... 3-4 3.3 CPU HyperTransport Interface .......................................................................................................................................... 3-5 3.4 PCI Express(R) Interfaces .................................................................................................................................................... 3-5 3.4.1 1 x 16 Lane Interface for External Graphics ....................................................................................................... 3-5 3.4.2 A-Link Express II to Southbridge........................................................................................................................ 3-5 3.4.3 4 x 1 Lane Interface for General Purpose External Devices .............................................................................. 3-6 3.4.4 Miscellaneous PCI Express(R) Signals ................................................................................................................. 3-6 3.5 Clock Interface ................................................................................................................................................................... 3-6 3.6 CRT and TV Interface........................................................................................................................................................ 3-6 3.7 Integrated DVI/HDMI Interface......................................................................................................................................... 3-7 3.8 TMDS Interface Multiplexed on the PCI Express(R) Graphics Lanes (Not Applicable to the RS690C) ........................... 3-8 3.9 Power Management Pins ................................................................................................................................................... 3-9 3.10 Miscellaneous Pins........................................................................................................................................................... 3-9 3.11 Power Pins...................................................................................................................................................................... 3-10 3.12 Ground Pins.....................................................................................................................................................................3-11 3.13 Debug Port Signals..........................................................................................................................................................3-11 3.14 Strapping Options.......................................................................................................................................................... 3-12 Chapter 4: Timing Specifications 4.1 CPU HyperTransport Bus Timing...................................................................................................................................... 4-1 4.2 HyperTransport Reference Clock Timing Parameters ....................................................................................................... 4-1 4.3 PCI Express(R) Differential Clock AC Specifications......................................................................................................... 4-1 4.4 OSCIN Timing ................................................................................................................................................................... 4-1 4.5 Power Rail Power Up Sequence......................................................................................................................................... 4-3 Chapter 5: Electrical Characteristics and Physical Data 5.1 Electrical Characteristics.................................................................................................................................................... 5-1 5.1.1 Maximum and Minimum Ratings........................................................................................................................ 5-1 5.1.2 DC Characteristics ............................................................................................................................................... 5-2 5.2 RS690 Thermal Characteristics.......................................................................................................................................... 5-4 5.2.1 RS690 Thermal Limits ........................................................................................................................................ 5-4 5.2.2 Thermal Diode Characteristics ............................................................................................................................ 5-5 5.3 Package Information .......................................................................................................................................................... 5-5 5.3.1 Physical Dimensions............................................................................................................................................ 5-5 5.3.2 Pressure Specification.......................................................................................................................................... 5-7 5.3.3 Board Solder Reflow Process Recommendations ............................................................................................... 5-8 Chapter 6: Power Management and ACPI 6.1 ACPI Power Management Implementation ....................................................................................................................... 6-1 6.2 Power Management for the Graphics Controller ............................................................................................................... 6-2 6.2.1 PCI Function Power States .................................................................................................................................. 6-2 6.2.2 PCI Power Management Interface....................................................................................................................... 6-2 6.2.3 Capabilities List Data Structure in PCI Configuration Space ............................................................................. 6-2 6.2.4 Register Block Definition .................................................................................................................................... 6-3 41977 AMD RS690 Databook 3.04 Table of Contents-2 (c) 2007 Advanced Micro Devices, Inc. Proprietary 6.2.5 6.2.6 6.2.7 Capability Identifier: Cap_ID (Offset = 0)...........................................................................................................6-4 Next Item Pointer .................................................................................................................................................6-5 PMC - Power Management Capabilities (Offset = 2) ..........................................................................................6-5 Chapter 7: Testability 7.1 Test Capability Features......................................................................................................................................................7-1 7.2 Test Interface.......................................................................................................................................................................7-1 7.3 XOR Tree ............................................................................................................................................................................7-1 7.3.1 Brief Description of an XOR Tree .......................................................................................................................7-1 7.3.2 Description of the XOR Tree for the RS690 ........................................................................................................7-2 7.3.3 XOR Tree Activation ...........................................................................................................................................7-2 7.3.4 XOR Chain for the RS690....................................................................................................................................7-2 7.4 VOH/VOL Test...................................................................................................................................................................7-4 7.4.1 Brief Description of a VOH/VOL Tree................................................................................................................7-4 7.4.2 VOH/VOL Tree Activation..................................................................................................................................7-4 7.4.3 VOH/VOL Pin List...............................................................................................................................................7-5 Appendix A: Pin Listings A.1 RS690 Pin List Sorted by Ball Reference ......................................................................................................................... 1-2 A.2 RS690 Pin List Sorted by Pin Name ................................................................................................................................. 1-6 Appendix B: Revision History (c) 2007 Advanced Micro Devices, Inc. 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Proprietary List of Figures Figure 1-1: RS690-variant Branding Diagrams for ASIC Revision A11 ........................................................................................1-8 Figure 1-2: RS690 Branding Diagram for ASIC Revision A12 and After ......................................................................................1-8 Figure 1-3: RS690C Branding Diagram for ASIC Revision A12 and After ...................................................................................1-9 Figure 1-4: The RS690-Family ASIC Part Number Legend ...........................................................................................................1-9 Figure 2-1: RS690 Internal Block Diagram .....................................................................................................................................2-1 Figure 2-2: Host Interface Block Diagram ......................................................................................................................................2-2 Figure 2-3: RS690 Host Bus Interface Signals ...............................................................................................................................2-3 Figure 2-4: Data Transmission Ordering for the Integrated DVI/HDMI and TMDS Interfaces .....................................................2-4 Figure 3-1: RS690 Pin Assignment (Left) .......................................................................................................................................3-2 Figure 3-2: RS690 Pin Assignment (Right) .....................................................................................................................................3-3 Figure 3-3: RS690 Interface Block Diagram ...................................................................................................................................3-4 Figure 4-1: Power Rail Power Up Sequence for the RS690 ......................................................................................................4-3 Figure 5-1: DC Characteristics of the Integrated DVI/HDMI and the TMDS Interface .................................................................5-4 Figure 5-2: RS690 Package Outline ................................................................................................................................................5-6 Figure 5-3: RS690 Ball Arrangement ..............................................................................................................................................5-7 Figure 5-4: Stencil Opening Recommendations ..............................................................................................................................5-8 Figure 5-5: RoHS/Lead-Free Solder (SAC305/405 Tin-Silver-Copper) Reflow Profile ................................................................5-9 Figure 6-1: Linked List for Capabilities ..........................................................................................................................................6-5 Figure 7-1: An Example of a Generic XOR Tree ............................................................................................................................7-2 Figure 7-2: Sample of a Generic VOH/VOL Tree ...........................................................................................................................7-4 41977 AMD RS690 Databook 3.04 List of Figures-1 (c) 2007 Advanced Micro Devices, Inc. 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Proprietary List of Tables Table 1-1: RS690-Family ASIC Part Numbers ............................................................................................................................ 1-10 Table 1-2: Pin Type Codes ........................................................................................................................................................... 1-10 Table 1-3: Acronyms and Abbreviations ...................................................................................................................................... 1-11 Table 2-1: Single-Link Signal Mapping for DVI/HDMI ............................................................................................................... 2-5 Table 2-2: Dual-Link Signal Mapping for DVI .............................................................................................................................. 2-6 Table 2-3: Support for HDMI Packet Type .................................................................................................................................... 2-7 Table 2-4: VGA DAC Characteristics ............................................................................................................................................ 2-8 Table 3-1: CPU HyperTransport Interface ..................................................................................................................................... 3-5 Table 3-2: 1 x 16 Lane PCI Express Interface for External Graphics ............................................................................................ 3-5 Table 3-3: 1 x 4 Lane A-Link Express II Interface for Southbridge .............................................................................................. 3-5 Table 3-4: 4 x 1 Lane PCI Express(R) Interface for General Purpose External Devices ................................................................. 3-6 Table 3-5: PCI Express(R) Interface for Miscellaneous PCI Express(R) Signals .............................................................................. 3-6 Table 3-6: Clock Interface .............................................................................................................................................................. 3-6 Table 3-7: CRT and TV Interface ................................................................................................................................................... 3-6 Table 3-8: Integrated DVI/HDMI Interface .................................................................................................................................... 3-7 Table 3-9: TMDS Interface Multiplexed on the PCI Express(R) Graphics Interface ....................................................................... 3-8 Table 3-10: Power Management Pins ............................................................................................................................................. 3-9 Table 3-11: Miscellaneous Pins ...................................................................................................................................................... 3-9 Table 3-12: Power Pins ................................................................................................................................................................. 3-10 Table 3-13: Ground Pins ............................................................................................................................................................... 3-11 Table 3-14: RS690 Debug Port Signals ........................................................................................................................................ 3-11 Table 3-15: Strap Definitions for the RS690 ................................................................................................................................ 3-12 Table 3-16: Strap Definition for GPPSB_LINK_CONFIG .......................................................................................................... 3-13 Table 4-1: HTREFCLK Pad (66.66MHz) Timing Parameters ....................................................................................................... 4-1 Table 4-2: PCI Express(R) Differential Clock (GFX_CLK, SB_CLK) AC Characteristics ............................................................ 4-1 Table 4-3: Timing Requirements for the OSCIN Pad .................................................................................................................... 4-1 Table 4-4: RS690 Power Rail Power Up Sequence Requirements ................................................................................................. 4-3 Table 5-1: Maximum and Minimum Ratings ................................................................................................................................. 5-1 Table 5-2: DC Characteristics for 3.3V TTL Signals ..................................................................................................................... 5-2 Table 5-3: DC Characteristics for 1.8V TTL Signals ..................................................................................................................... 5-2 Table 5-4: DC Characteristics for the HTREFCLK Pad (66.66MHz) ............................................................................................ 5-2 Table 5-5: DC Characteristics for the OSCIN Pad (14.3181818MHz) .......................................................................................... 5-2 Table 5-6: DC Characteristics for the Integrated DVI/HDMI (Not Applicable to the RS690C) ................................................... 5-3 Table 5-7: DC Characteristics for the TMDS Interface Multiplexed on the PCI Express(R) Gfx Lanes ......................................... 5-3 Table 5-8: RS690 Thermal Limits .................................................................................................................................................. 5-4 Table 5-9: RS690 465-Pin FCBGA Package Physical Dimensions ............................................................................................... 5-6 Table 5-10: Recommended Board Solder Reflow Profile - RoHS/Lead-Free Solder .................................................................... 5-9 Table 6-1: ACPI States Supported by the RS690 ........................................................................................................................... 6-1 Table 6-2: ACPI Signal Definitions ................................................................................................................................................ 6-1 Table 6-3: Standard PCI Configuration Space Header Type 0 ....................................................................................................... 6-2 Table 6-4: PCI Status Register ........................................................................................................................................................ 6-3 Table 6-5: Capabilities Pointer (CAP_PTR) ................................................................................................................................... 6-3 Table 6-6: Power Management Register Block .............................................................................................................................. 6-3 Table 6-7: Power Management Control/Status Register (PMCSR) ............................................................................................... 6-4 Table 6-8: Capability Identifier (Cap_ID) ...................................................................................................................................... 6-4 Table 6-9: Next Item Pointer (NEXT_ITEM_PTR) ....................................................................................................................... 6-5 Table 6-10: Power Management Capabilities - PMC .................................................................................................................... 6-5 Table 7-1: Pins on the Test Interface .............................................................................................................................................. 7-1 Table 7-2: Example of an XOR Tree .............................................................................................................................................. 7-2 41977 AMD RS690 Databook 3.04 List of Tables-1 (c) 2007 Advanced Micro Devices, Inc. Proprietary Table 7-3: RS690 XOR Tree .......................................................................................................................................................... 7-3 Table 7-4: Truth Table for the VOH/VOL Tree Outputs ............................................................................................................... 7-4 Table 7-5: RS690 VOH/VOL Tree ................................................................................................................................................ 7-5 41977 AMD RS690 Databook 3.04 List of Tables-2 (c) 2007 Advanced Micro Devices, Inc. Proprietary Chapter 1 Overview 1.1 Introducing the RS690 The RS690 is a seventh generation Integrated Graphics Processor (IGP) that integrates a DirectX(R) 9.0 compliant 2D/3D graphics core and a system controller in a single chip. It supports the AMD AthlonTM 64, Athlon 64 FX, Athlon 64 X2, AMD and Sempron processors, including AM2 socket CPUs. All CPUs are supported on both high performance and value platforms. The RS690 integrates an ATI RadeonTM X700-based graphics engine, dual display, a TV encoder, an integrated DVI/HDMI interface, an integrated TMDS controller, and Northbridge functionality in a single BGA package. This high level of integration and scalability enables manufacturers to offer enthusiast level capabilities and performance while minimizing board space and system cost. The RS690 is pin-compatible with AMD's RS485, allowing existing RS485 platforms to easily migrate to the RS690. Comparing with the RS485, the RS690 provides additional features with reduced overall system power. Robust and Flexible Core Logic Features The RS690 combines graphics and system logic functions in a single chip using a 21mm-body FCBGA package, reducing overall solution area. For optimal system and graphics performance, the RS690 supports a high speed HyperTransportTM interface to the AMD processor, running at a data rate of up to 2GT/s and supporting the new generation of AM2 socket processors. The RS690 is ideally suited to 64-bit operating systems, and supports platform configurations with greater than 4GB of system memory. The rich PCI Express(R) expansion capabilities of RS690, including support for PCI Express external graphics and up to four other PCI Express peripherals (or five, when using only 8 lanes for external graphics), are complemented by the advanced I/O features of AMD's SB600 Southbridge. Best for Windows VistaTM The RS690 delivers the best Windows VistaTM experience of any integrated graphics and core logic product for the AMD platform. It incorporates an ATI RadeonTM X700-based graphics core, which provides the 3D rendering power needed to generate the Windows Vista desktop even under the most demanding circumstances. In addition, dedicated hardware acceleration is provided for key new Windows Vista features such as ClearType(R). This ATI Radeon X700-based graphics technology also enables great 3D application performance through SmartShaderTM HD, SmoothVisionTM HD, and 3DcTM technologies. Leading Multimedia Capabilities The RS690 incorporates the innovative ATI AvivoTM* display architecture, providing users with visual quality which is second to none. Advanced scaling and color correction capabilities, along with increased precision through the entire display pipeline, ensure an optimal image on CRT monitors, LCD panels, and any other display devices. A new TV encoder, based on designs used in ATI's XilleonTM products, provides unequalled quality, and fully integrated DVI/HDMI and HDCP support allows compatibility with even the most modern high definition televisions without the additional cost of external components. *Note: ATI AvivoTM is a technology platform that includes a broad set of capabilities offered by certain ATI Radeon products. Full enablement of some ATI AvivoTM capabilities may require complementary products. Low Power Consumption and Industry Leading Power Management The RS690 is manufactured using a power efficient 80nm technology, and it supports a whole range of industry standards and all new proprietary power management features. It provides comprehensive support for the ACPI specification and AMD power management features such as AMD PowerNow!TM. The RS690 family also includes variants with support for dedicated local display cache memory, which further reduces system power consumption. (c) 2007 Advanced Micro Devices, Inc. Proprietary 41977 AMD RS690 Databook 3.04 1-1 RS690C Software Compatibility The graphics driver for the RS690 is fully compatible with all other ATI Radeon class graphics controllers from AMD. A single driver can support multiple graphics configurations across AMD's product lines, including the ATI Radeon family and the AMD chipset family. In addition, this driver compatibility allows the RS690 to benefit immediately from AMD's software optimization and from the advanced Windows(R) XP and Windows Vista support available in the ATI Radeon family drivers. 1.2 RS690C The RS690C is a special variant of the RS690 that supports neither a DVI/HDMI interface nor a TMDS interface that enables DVI/HDMI. Beyond the difference, all other information in this document applies to both the RS690 and RS690C, unless otherwise specified. 1.3 RS690 Features 1.3.1 CPU HyperTransportTM Interface 1.3.2 * Supports the mobile and desktop Athlon 64/Athlon 64 FX/Athlon X2/AMD Sempron processors, including AM2 socket CPUs. * * Supports 200, 400, 600, 800, and 1000MHz HyperTransport (HT) interface speeds. Supports LDTSTP interface, CPU throttling, and stutter mode. ATI HyperMemoryTM Technology * Supports ATI HyperMemoryTM* technology. * Note: The amount of HyperMemory available includes both dedicated and shared memory and is determined by various factors. For details, please refer to the product advisory numbered PA_IGPGenC5, available on AMD's OEM Resource Center or from you AMD CSS representative. 1.3.3 PCI Express(R) Interface * * * * * 1.3.4 Compliant with the PCI Express (PCI-E) 1.1a Specification. Highly flexible PCI-E implementation to suit a variety of platform needs. Supports a x16 graphics interface. A single-port, x16 graphics interface, configurable to any of the following modes of support: * An external graphics device utilizing all 16 lanes. * A TMDS interface, enabling DVI/HDMI (see section 1.3.9, "DVI/HDMI (Not applicable to the RS690C)" below for details). * A single x1, x2, x4, or x8 general purpose PCI-E link. A four-port, x4 PCI Express general purpose interface, configurable to one of the following modes of support: * Four x1 links. * Two x2 links. * One x2 and two x1 links. * One x4 link. A-Link Express II Interface * One x4 A-Link Express II interface (PCI Express 1.1 compliant) for connection to an AMD Southbridge, providing more bandwidth than the older A-Link Express interface. 41977 AMD RS690 Databook 3.04 1-2 (c) 2007 Advanced Micro Devices, Inc. Proprietary RS690 Features 1.3.5 2D Acceleration Features * * * * * Hardware acceleration of Bitblt, Line Draw, Polygon / Rectangle Fill, Bit Masking, Monochrome Expansion, Panning/Scrolling, Scissoring, and full ROP support (including ROP3). Optimized handling of fonts and text using AMD proprietary techniques. Hardware acceleration for ClearType font rendering. Game acceleration including support for Microsoft's DirectDraw(R): Double Buffering, Virtual Sprites, Transparent Blit, and Masked Blit. * Supports a maximum resolution of 2048x1536 @ 32bpp for a maximum pixel clock speed of 400MHz (driver-limited). * Acceleration in 1/8/15/16/32 bpp modes: * * * * 1.3.6 Highly-optimized 128-bit engine, capable of processing multiple pixels per clock. * ClearType mode for 1bpp * Pseudocolor mode for 8bpp * ARGB1555 and RGB565 modes for 16bpp * ARGB8888 mode for 32bpp Significant increase in the High-End Graphics WinBench(R) score due to capability for C18 color expansion. Setup of 2D polygons and lines. Support for GDI extensions in Windows XP and Windows Vista: Alpha BLT, Transparent BLT, Gradient Fill. Hardware cursor (up to 64x64x32bpp), with alpha channel for direct support of Windows XP and Windows Vista alpha cursor. 3D Acceleration Features * * * * * Multi-texturing via one texture blending unit per pixel pipes, allowing up to 512 texel reads per pixel in a single pass. * * * Complete 3D primitive support: points, lines, triangles, lists, strips and quadrilaterals and BLTs with Z compare. * * * * * * * * * * 8-bit stencil buffer. 3D texture support, including projective 3D textures. Comprehensive support for bump mapping: emboss, dot-product, and environment bump maps. Improved precision in anisotropic filtering and bilinear filtering. Supports a maximum resolution of 2048x1536 @ 32bpp for a maximum pixel clock speed of 400MHz (driver-limited). Improved texture compositing. Hidden surface removal using 16, 24, or 32-bit Z-buffering (maximum Z-buffer depth is 24 bits when stencil buffer enabled) and Early Z hardware. Bilinear and trilinear texture filtering. Full support of Direct3D texture lighting. Dithering support in 16bpp for near 24bpp quality in less memory. Extensive 3D mode support. Anti-aliasing using multi-sampling algorithm with support for 2, 4, and 6 samples. Optimized for full performance in true color triple buffered 32bpp acceleration modes. New generation rendering engine provides top 3D performance. Support for OpenGL format for Indirect Vertices in Vertex Walker. Full DirectX 9.0 support (Vertex Shader version 2.0 and Pixel Shader version 2.0): * Full precision floating point pixel pipeline. (c) 2007 Advanced Micro Devices, Inc. Proprietary 41977 AMD RS690 Databook 3.04 1-3 RS690 Features 1.3.7 Support for up to 4 MRTs (Multiple-Render-Targets). * Support for writing all texture formats from render pipe in floating points (including cube mapes and 3D textures). * Support for up to 512bpp formats (4 color case). * Advanced setup engine, capable of processing 1 polygon (lit and textured) per cycle. Motion Video Acceleration Features * * * * * * 1.3.8 * Enhanced MPEG-2 hardware decode acceleration (SD contents only), including support for: * Integrated general purpose iDCT engine for MPEG2 and DV decode acceleration. * Integrated MPEG motion compensation engine for decode acceleration. * Parallel operation of the iDCT and MC and high processing rates with minimal software overhead. Supports Microsoft DirectX Video Acceleration (DirectX VA) 2.0 (for SD contents only). Provides dramatically reduced CPU utilization without incurring the cost of a full MPEG-2 decoder. MPEG-4 simple profile support. Supports top quality DVD with low CPU usage. Hardware-based adaptive de-interlacing filter and scaler provide high quality full-screen and full-speed video playback. Minimizes the aliasing artifacts along edges usually caused by a conventional deinterlacer/scaler. Multiple Display Features General * [Not applicable to the RS690C] Dual independent displays. Possible configurations include: * CRT and DVI/HDMI * TV (component, composite, or S-Video) and DVI/HDMI * DVI and DVI* * DVI and HDMI* * Note: The options require implementation of the TMDS interface that is multiplexed on the PCI-E external graphics interface; see section 1.3.9, "DVI/HDMI (Not applicable to the RS690C)," on page 1-5. * [Not applicable to the RS690C] Resolution, refresh rates, and display data can be completely independent for the two display paths. * * Each display controller supports true 30bpp throughout the display pipeline. * * * * * * * Supports both interlaced and non-interlaced displays. * Each display path supports VGA and accelerated modes, video overlay, hardware cursor, hardware icon, and palette gamma correction. Support for display modes up to 2880 pixels/line per display. Full ratiometric expansion ability is supported for source desktop modes up to 1920 pixels/line. HD TV support (with underscan) for display modes of 1920 or less pixels/line. SD TV support (with underscan) for display modes of 1024 or less pixels/line. Maximum DAC frequency of 400MHz. Supports 8, 16, 32 & 64-bpp depths for the main graphics layer: * For 32-bpp depth, supports xRGB 8:8:8:8, xRGB 2:10:10:10, sCrYCb 8:8:8:8, and xCrYCb 2:10:10:10 data formats. * For 64-bpp depth, supports xRGB 16:16:16:16 data format. Independent gamma, color conversion and correction controls for main graphics layer. 41977 AMD RS690 Databook 3.04 1-4 (c) 2007 Advanced Micro Devices, Inc. Proprietary RS690 Features * * * * * Supports display resolutions beyond 2560x1600. * * Virtual desktop support. * * [Not applicable to the RS690C] Integrated HD Audio Controller for HDMI audio data. Support for DDC1 and DDC2B+ for plug and play monitors. 8-bit alpha blending of graphics and video overlay. Hardware cursor up to 64x64 pixels in 2bpp, full color AND/XOR mix, and full color 8-bit alpha blend. Hardware icon up to 128x128 pixels in 2bpp, with two colors, transparent, and inverse transparent. AND/XOR mixing. Supports 2x2 icon magnification. Support for flat panel displays via VGA, DVI (not applicable to the RS690C), or HDMI (not applicable to the RS690C). Support for stereoscopic monitors. TV Out * An integrated TV encoder from AMD's Xilleon products, with an on-chip DAC (shared with the CRT analog output) (Note: Simultaneous output for TV and CRT is not supported). * 10-bit DAC with 10-tap filter producing scaled, flicker removed, artifact suppressed display on a PAL or NTSC TV with composite, S-Video, component, and RGB output. * With the proper BIOS implementation, supports different TV standards including NTSC, NTSC-J, PAL-M, PAL-CN, PAL-B, PAL-G, PAL-D, PAL-H, PAL-I, PAL-K, and PAL-N. * * * * * * * Supports Macrovision 7.1 copy protection standard (required by DVD players). * CGMS copy management support in VBI through Line-20 and/or Extended Data Service (Line-21 Field 2) for NTSC, and through Wide Screen Signaling data (WSS) for PAL. Supports a maximum resolution of 1024x768. Supports the following formats of YPbPr component output: 480i, 480p, 576i, 576p, 720p, and 1080i. Internal adaptive flicker filtering available on both display paths for interlaced TV outputs. Supports fully-programmable 2D, adaptive comb filter for composite output. TV-out power management support. Line 21 Closed Caption and Extended Data Service support for encoding in Vertical Blanking Interval (VBI) of TV signal. SURROUNDVIEW * 1.3.9 RS690's SURROUNDVIEWTM feature allows support for up to three independent monitors for systems equipped with an additional ATI discrete graphics card (requires special BIOS and display driver support). DVI/HDMI (Not applicable to the RS690C) * * Integrated DVI or HDMI interface: single-link support only for HDMI, 30-bit dual-link support for DVI. Also supports a TMDS interface, enabling DVI or HDMI*, which is multiplexed on the PCI-E external graphics interface (only available if no external graphics card, or only a x8 one, is attached to the PCI-E external graphics interface). * * 1650 Mbps/channel with 165MHz pixel clock rate per link. * HDMI basic audio support at 32, 44.1, and 48 kHz. Supports two-channel uncompressed audio and multi-channel audio compressed to two channels like 5.1 AC3 and DTS. HD Audio device compatible with Microsoft's HD audio drivers. * HDCP support on data stream for single-link transmission, with on-chip key storage (available only on either one of the integrated DVI/HDMI interface or the TMDS interface (multiplexed on the PCI-E graphics lanes) at any time).** Supports industry standard EVA-861B video modes including 480p, 720p, and 1080i. For a full list of currently supported modes, contact your AMD CSS representative. Notes: * CEC is not supported. (c) 2007 Advanced Micro Devices, Inc. Proprietary 41977 AMD RS690 Databook 3.04 1-5 Software Features To be qualified. ** HDCP content protection is only available to licensed buyers of the technology and can only be enabled when connected to an HDCP-capable receiver. The TMDS interface multiplexed on the PCI-E graphics lanes cannot enable HDMI when the integrated DVI/HDMI interface is supporting HDMI, and vice versa. 1.3.10 Power Management Features * * Fully supports ACPI states S1, S3, S4, and S5. * Hardware controlled intelligent clock gating enables clocks only to active functional blocks, and is completely transparent to software. * * * Support for AMD Cool'n'QuietTM technology via FID/VID change. * Support dynamic lane reduction for the PCI-E interfaces, adjusting lane width according to required bandwidth. The chip power management support logic supports four device power states defined for the OnNow Architecture-- On, Standby, Suspend, and Off. Each power state can be achieved by software control bits. Support for AMD PowerNow!TM technology. Clocks to every major functional block are controlled by a unique dynamic clock switching technique that is completely transparent to the software. By turning off the clock to the block that is idle or not used at that point, the power consumption is significantly reduced during normal operation. 1.3.11 PC Design Guide Compliance The RS690 complies with all relevant Windows Logo Program (WLP) requirements from Microsoft for WHQL certification. 1.3.12 Test Capability Features The RS690 has a variety of test modes and capabilities that provide a very high fault coverage and low DPM (Defect Per Million) ratio: * * * * * Full scan implementation on the digital core logic through ATPG (Automatic Test Pattern Generation) vectors. * * Improved access to the analog modules to allow full evaluation and characterization. Dedicated test logic for the on-chip custom memory macros to provide complete coverage on these modules. A JTAG test mode to allow board level testing of neighboring devices. An EXOR tree test mode on all the digital I/O's to allow for proper soldering verification at the board level. A VOH/VOL test mode on all digital I/O's to allow for proper verification of output high and output low values at the board level. Improved IDDQ mode support to allow chip evaluation through current leakage measurements. These test modes can be accessed through the settings on the instruction register of the JTAG circuitry. 1.3.13 Packaging * * 1.4 Single chip solution in 80nm, 1.2V low power CMOS technology. 465-FCBGA package, 21mmx21mm. Software Features * * * * Supports Microsoft Windows XP and Windows Vista operating systems. BIOS ability to read EDID 1.1, 1.2, and 1.3. Ability to selectively enable and disable several devices including CRT, LCD, TV, and DFP. Register-compatible with VGA standards, BIOS-compatible with VESA VBE2.0. 41977 AMD RS690 Databook 3.04 1-6 (c) 2007 Advanced Micro Devices, Inc. Proprietary Branding Diagrams * * * * Supports corporate manageability requirements such as DMI. ACPI support. Full Write Combining support for maximum performance of the CPU. Full-featured, yet simple Windows utilities: * Calibration utility for WYSIWYG color * Independent brightness control of desktop and overlay * End user diagnostics * Drivers meet Microsoft's rigorous WHQL criteria and are suitable for systems with the "Designed for Windows" logos. * * * * * * * * Comprehensive OS and API support. Hot-key support (Windows ACPI 1.0b or AMD Event Handler Utility where appropriate). Extensive power management support. Rotation mode support in software. Dual CRTC, simultaneous view, extended desktop support (Windows XP and Windows Vista) DirectX 9.0 support. Switchable overlay support. H.264 playback support. 1.5 Branding Diagrams 1.5.1 Branding Diagrams for ASIC Revision A11 Artwork o (c) 2007 Advanced Micro Devices, Inc. Proprietary RS690 215RQA6AVA11FG Part Number (for ASIC revision A11) GGGGG Wafer Foundry's Lot Number YYWWXXV Date and Other Codes* TAIWAN Country of Origin AMD Code Name * YY - Assembly Start Year WW - Assembly Start Week XX - Assembly Location V - Substrate Vendor Code 41977 AMD RS690 Databook 3.04 1-7 Branding Diagrams Artwork RS690C 215CQA6AVA11FG Part Number (for ASIC revision A11) GGGGG Wafer Foundry's Lot Number YYWWXXV Date and Other Codes* TAIWAN Country of Origin AMD Code Name * YY - Assembly Start Year WW - Assembly Start Week XX - Assembly Location V - Substrate Vendor Code o Figure 1-1 RS690-variant Branding Diagrams for ASIC Revision A11 1.5.2 Branding Diagrams for ASIC Revision A12 and After Note: The branding diagrams below do not necessarily contain the latest ASCI revision numbers for the IGPs. Unless specified otherwise, no information in this databook is specific to the ASIC revision numbers given in the diagrams. AMD Logo CHIPSET 215RQA6AVA12FG GGGGGG YYWWXXV COO AMD Product Type Part Number (for ASIC revision A12) Wafer Foundry's Lot Number Date and Other Codes* Country of Origin * YY - Assembly Start Year WW - Assembly Start Week XX - Assembly Location V - Substrate Vendor Code o "o" indicates pin A1. Figure 1-2 RS690 Branding Diagram for ASIC Revision A12 and After 41977 AMD RS690 Databook 3.04 1-8 (c) 2007 Advanced Micro Devices, Inc. Proprietary Part Number Legend AMD Logo CHIPSET 215CQA6AVA12FG GGGGGG YYWWXXV COO AMD Product Type Part Number (for ASIC revision A12) Wafer Foundry's Lot Number Date and Other Codes* Country of Origin * YY - Assembly Start Year WW - Assembly Start Week XX - Assembly Location V - Substrate Vendor Code o "o" indicates pin A1. Figure 1-3 RS690C Branding Diagram for ASIC Revision A12 and After 1.6 Part Number Legend Foundry Code N - UMC Fab 8F M - IBM C - TSMC Fab 3 S - TSMC Fab 4 F - TSMC Fab 5 G - TSMC Fab 6 K - TSMC Fab 12 L - TSMC Fab14 W - TSMC WSMC Q - TSMC WSMC (8B) T - TSMC Wafer Tech V - UMC Fab 12A Marketing Brand Name RQA6 - RS690 CQA6 - RS690C MQA6 - RS690M LQA6 - RS 690MC TQA6 - RS690T NQA6 - RX690 215 RQA6 Product Type 215 - Desktop 216 - Mobile A Substrate Revision V A12 ASIC Revision Flip Chip Blank - No F - Yes F G Package BOM K - High Temp G - Lead Free Figure 1-4 The RS690-Family ASIC Part Number Legend (c) 2007 Advanced Micro Devices, Inc. Proprietary 41977 AMD RS690 Databook 3.04 1-9 Conventions and Notations Table 1-1 RS690-Family ASIC Part Numbers Code Name Part Number RS690 1.7 215RQA6AVA12FG RS690C 215CQA6AVA12FG RS690M 216MQA6AVA12FG RS690MC 216LQA6AVA12FG RS690T 216TQA6AVA12FG RX690 215NQA6AVA12FG Conventions and Notations The following conventions are used throughout this manual. 1.7.1 Pin Names Pins are identified by their pin names or ball references. Multiplexed pins assume alternate "functional names" when they perform their alternate functions, and these "functional names" are given in Chapter 3, "Pin Descriptions and Strap Options." All active-low signals are identified by the suffix `#' in their names (e.g., LDTSTOP#). 1.7.2 Pin Types The pins are assigned different codes according to their operational characteristics. These codes are listed in Table 1-2. Table 1-2 Pin Type Codes Code I 1.7.3 Pin Type Digital Input O Digital Output OD Open Drain I/O Bi-Directional Digital Input or Output M Multifunctional Pwr Power Gnd Ground A-O Analog Output A-I Analog Input A-I/O Analog Bi-Directional Input/Output A-Pwr Analog Power A-Gnd Analog Ground Other Pin types not included in any of the categories above Numeric Representation Hexadecimal numbers are appended with "h" (Intel assembly-style notation) whenever there is a risk of ambiguity. Other numbers are in decimal. Pins of identical functions but different trailing integers (e.g., "CPU_D0, CPU_D1,... CPU_D7") are referred to collectively by specifying their integers in square brackets and with colons (i.e., "CPU_D[7:0]"). A similar short-hand notation is used to indicate bit occupation in a register. For example, NB_COMMAND[15:10] refers to the bit positions 10 through 15 of the NB_COMMAND register. 41977 AMD RS690 Databook 3.04 1-10 (c) 2007 Advanced Micro Devices, Inc. Proprietary Conventions and Notations 1.7.4 Register Field A field of a register is referred to by the format of [Register Name].[Register.Field]. For example, "NB_MC_CNTL.DISABLE_BYPASS" is the "DISABLE_BYPASS" field of the register "NB_MC_CNTL." 1.7.5 Hyperlinks Phrases or sentences in blue italic font are hyperlinks to other parts of the manual. Users of the PDF version of this manual can click on the links to go directly to the referenced sections, tables, or figures. 1.7.6 Acronyms and Abbreviations The following is a list of the acronyms and abbreviations used in this manual. Table 1-3 Acronyms and Abbreviations Acronym ACPI A-Link-E II Full Expression Advanced Configuration and Power Interface A-Link Express II interface between the IGP and the Southbridge. BGA Ball Grid Array BIOS Basic Input Output System. Initialization code stored in a ROM or Flash RAM used to start up a system or expansion card. BIST Built In Self Test. BLT Blit bpp bits per pixel CEC Consumer Electronic Control CPIS Common Panel Interface Specification CRT Cathode Ray Tube CSP Chip Scale Package DAC Digital to Analog Converter DBI Dynamic Bus Inversion DDC Display Data Channel. A VESA standard for communicating between a computer system and attached display devices. DDR Double Data Rate DFP Digital Flat Panel. Monitor connection standard from VESA. DPM Defects per Million DTV Digital TV DVD Digital Video Disc DVI Digital Video Interface. Monitor connection standard from the DDWG (Digital Display Work Group). DVS EPROM Digital Video Stream Erasable Programmable Read Only Memory FIFO First In, First Out FPDI Flat Panel Display Interface GDI Graphics Device Interface GND Ground GPIO General Purpose Input/Output GTL+ Gunning Transceiver Logic HDCP High-Bandwidth Digital Content Protection HDMI High Definition Multimedia Interface HDTV HPD High Definition TV. The 1920x1080 and the 1280x720 modes defined by ATSC. Hot Plug Detect iDCT inverse Discrete Cosine Transform IDDQ Direct Drain Quiescent Current IGP Integrated Graphics Processor. A single device that integrates a graphics processor and a system controller. (c) 2007 Advanced Micro Devices, Inc. Proprietary 41977 AMD RS690 Databook 3.04 1-11 Conventions and Notations Table 1-3 Acronyms and Abbreviations (Continued) Acronym JTAG MB Full Expression Joint Test Access Group. An IEEE standard. Mega Byte MPEG Motion Pictures Experts Group. Refers to compressed video image streams in either MPEG-1 or MPEG-2 formats. NTSC National Television Standards Committee. The standard definition TV system used in North America and other areas. PAL Phase Alternate Line. The standard definition TV system used in Europe and other areas. PCI Peripheral Component Interface PCI-E PCMCIA PCI Express Personal Computer Memory Card International Association. It is also the name of a standard for PC peripherals promoted by the Association. PLL Phase Locked Loop POST Power On Self Test PD Pull-down Resistor PU Pull-up Resistor ROP SDRAM TMDS UMA UV UXGA VBI Raster Operation Synchronous Dynamic RAM Transition Minimized Differential Signaling Unified Memory Architecture Chrominance (also CrCb). Corresponds to the color of a pixel. Ultra Extended Graphics Array Vertical Blank Interval VESA Video Electronics Standards Association VGA Video Graphics Adapter VRM Voltage Regulation Module 41977 AMD RS690 Databook 3.04 1-12 (c) 2007 Advanced Micro Devices, Inc. Proprietary Chapter 2 Functional Descriptions This chapter describes the functional operation of the major interfaces of the RS690 system logic chip. Figure 2-1, "RS690 Internal Block Diagram," illustrates the RS690 internal blocks and interfaces. CPU Interface CPU HyperTransport Unit A-Link-E II Interface (1 x 4 Lanes) (1 x 16 Lanes) SB PCI-E Gfx Interface External Graphics Root Complex Memory Controller (4 x 1 Lanes) PCI-E GPP Interface Expansion Slots or On-board Devices BIF Register Interface iDCT Setup Engine 2D Engine 3D Engine TMDS, enabling DVI/HDMI (Multiplexed on PCI-E Gfx Lanes)* Overlay TV-Out CRT Display 1& 2 MUX Integrated DVI/HDMI* * Not applicable to the RS690C. Figure 2-1 RS690 Internal Block Diagram (c) 2007 Advanced Micro Devices, Inc. Proprietary 41977 AMD RS690 Databook 3.04 2-1 Host Interface 2.1 Host Interface The RS690 is optimized to interface with the Athlon 64/Athlon 64 FX/Athlon X2/AMD Sempron processors, including AM2 socket CPUs. This section presents an overview of the HyperTransport interface. For a detailed description of the interface, please refer to the HyperTransport I/O Link Specification from the HyperTransport Consortium. Figure 2-2, "Host Interface Block Diagram," illustrates the basic blocks of the host bus interface of the RS690. HT Interface to CPU (PHY) Configuration Registers LTA LRA Protocol/Transaction Layer SCH Root Complex Data Link Layer Memory Controller Figure 2-2 Host Interface Block Diagram The HyperTransport (HT) Interface, formerly known as the LDT (Lightning Data Transport) interface, is a high speed, packet-based link implemented on two unidirectional buses. It is a point-to-point interface where data can flow both upstream and downstream at the same time. The commands, addresses, and data travel in packets on the HyperTransport link. Lengths of packets are in multiples of four bytes. The HT link consists of three parts: the physical layer (PHY), the data link layer, and the protocol/transaction layer. The PHY is the physical interface between the RS690 and the CPU. The data link layer includes the initialization and configuration sequences, periodic redundancy checks, connect/disconnect sequences, and information packet flow controls. The protocol layer is responsible for maintaining strict ordering rules defined by the HT protocol. The RS690 HyperTransport bus interface consists of 17 unidirectional differential data/control pairs and two differential clock pairs in each of the upstream and downstream direction. On power up, the HT link is 8 bits wide and runs at a default speed of 200MT/s. After negotiation, carried out by the HW and SW together, the link width can be brought up to 16 bits and the interface can run up to 2GT/s. The interface is illustrated in Figure 2-3, "RS690 Host Bus Interface Signals," on page 2-3. The signal name and direction for each signal is shown with respect to the processor. Please note that the signal names may be different from those used in the pin listing of the RS690. Detailed descriptions of the signals are given in section 3.3, "CPU HyperTransport Interface' on page 3-5. 41977 AMD RS690 Databook 3.04 2-2 (c) 2007 Advanced Micro Devices, Inc. Proprietary Host Interface HT_TXCALN HT_TXCLKP 2 HT_TXCLKN 2 HT_TXCTLP HT_TXCTLN RS690 VDD_HT HT_RXCALN HT_RXCALP HT_TXCADP 16 HT_TXCADN 16 HT_RXCLKP 2 HT_RXCLKN 2 AMD CPU HT_TXCALP HT_RXCTLP HT_RXCTLN HT_RXCADP 16 HT_RXCADN 16 Figure 2-3 RS690 Host Bus Interface Signals (c) 2007 Advanced Micro Devices, Inc. Proprietary 41977 AMD RS690 Databook 3.04 2-3 DVI/HDMI (Not Applicable to the RS690C) 2.2 DVI/HDMI (Not Applicable to the RS690C) 2.2.1 DVI/HDMI Data Transmission Order and Signal Mapping The RS690 contains an integrated DVI/HDMI interface and a TMDS interface (multiplexed on the PCI-E graphics lanes), both supporting clock frequencies of up to 165 MHz for each signal link. Figure 2-4 below shows the transmission ordering of the signals on both interfaces in single-link mode. TXCP TXCM TX0P TX0M TB0 TB1 TG0 TG1 Depending upon state PLL_SYNC and CTL1 Various control and ofaudio (for HDMI only) signals TX2P TX2M TB4 TB5 TB6 TB7 TB8 TB9 TG2 TG3 TG4 TG5 TG6 TG7 TG8 TG9 Depending encoded Green Pixel channel pixel data Encodedupon Green Channel Data TR0 Depending upon state of CTL2 and CTL3 only) signals Various control and audio (for HDMI TB3 DependingBlue upon encoded channel Encoded ChannelBlue Pixel Datapixel data Depending upon state HSYNC(for andHDMI VSYNConly) signals Various control andofaudio TX1P TX1M TB2 TR1 TR2 TR3 TR4 TR5 TR6 TR7 TR8 TR9 Depending upon Red channel pixel data Encoded Red encoded Channel Pixel Data Figure 2-4 Data Transmission Ordering for the Integrated DVI/HDMI and TMDS Interfaces For dual-link mode, which is for DVI only, the same transmission order applies to data channels on the second link, with the first link transmitting data for even pixels and the second link for odd pixels. See Table 2-2, "Dual-Link Signal Mapping for DVI," on page 2-6 for details. The signal mapping for the transmission is shown in Table 2-1, "Single-Link Signal Mapping for DVI/HDMI," on page 2-5, and Table 2-2, "Dual-Link Signal Mapping for DVI," on page 2-6. 41977 AMD RS690 Databook 3.04 2-4 (c) 2007 Advanced Micro Devices, Inc. Proprietary DVI/HDMI (Not Applicable to the RS690C) Table 2-1 Single-Link Signal Mapping for DVI/HDMI DVI/HDMI Functional Name Data Phase Signal TX0M/P Phase 1 B0 TX1M/P TX2M/P Phase 2 B1 Phase 3 B2 Phase 4 B3 Phase 5 B4 Phase 6 B5 Phase 7 B6 Phase 8 B7 Phase 9 B8 Phase 10 B9 Phase 1 G0 Phase 2 G1 Phase 3 G2 Phase 4 G3 Phase 5 G4 Phase 6 G5 Phase 7 G6 Phase 8 G7 Phase 9 G8 Phase 10 G9 Phase 1 R0 Phase 2 R1 Phase 3 R2 Phase 4 R3 Phase 5 R4 Phase 6 R5 Phase 7 R6 Phase 8 R7 Phase 9 R8 Phase 10 R9 Note: H/VSYNC are transmitted on TX0M/P(Blue) channel during blank. (c) 2007 Advanced Micro Devices, Inc. Proprietary 41977 AMD RS690 Databook 3.04 2-5 DVI/HDMI (Not Applicable to the RS690C) Table 2-2 Dual-Link Signal Mapping for DVI Link 1 DVI Functional Name TX0M/P TX1M/P TX2M/P Data Phase Link 2 Signal DVI Functional Name TX3M/P Data Phase Signal Phase 1 EVEN_B0 Phase 1 ODD_B0 Phase 2 EVEN_B1 Phase 2 ODD_B1 Phase 3 EVEN_B2 Phase 3 ODD_B2 Phase 4 EVEN_B3 Phase 4 ODD_B3 Phase 5 EVEN_B4 Phase 5 ODD_B4 Phase 6 EVEN_B5 Phase 6 ODD_B5 Phase 7 EVEN_B6 Phase 7 ODD_B6 Phase 8 EVEN_B7 Phase 8 ODD_B7 Phase 9 EVEN_B8 Phase 9 ODD_B8 Phase 10 EVEN_B9 Phase 10 ODD_B9 Phase 1 EVEN_G0 Phase 1 ODD_G0 Phase 2 EVEN_G1 Phase 2 ODD_G1 Phase 3 EVEN_G2 Phase 3 ODD_G2 Phase 4 EVEN_G3 Phase 4 ODD_G3 Phase 5 EVEN_G4 Phase 5 ODD_G4 Phase 6 EVEN_G5 Phase 6 ODD_G5 Phase 7 EVEN_G6 Phase 7 ODD_G6 Phase 8 EVEN_G7 Phase 8 ODD_G7 Phase 9 EVEN_G8 Phase 9 ODD_G8 Phase 10 EVEN_G9 Phase 10 ODD_G9 Phase 1 EVEN_R0 Phase 1 ODD_R0 Phase 2 EVEN_R1 Phase 2 ODD_R1 Phase 3 EVEN_R2 Phase 3 ODD_R2 Phase 4 EVEN_R3 Phase 4 ODD_R3 Phase 5 EVEN_R4 Phase 5 ODD_R4 Phase 6 EVEN_R5 Phase 6 ODD_R5 Phase 7 EVEN_R6 Phase 7 ODD_R6 Phase 8 EVEN_R7 Phase 8 ODD_R7 Phase 9 EVEN_R8 Phase 9 ODD_R8 Phase 10 EVEN_R9 Phase 10 ODD_R9 TX4M/P TX5M/P Notes: - H/VSYNC are transmitted on TX0M/P(Blue) channel during blank. - For DVI dual-link mode, the first active data pixel is defined as pixel#0 (an even pixel), as opposed to the DVI specifications. 41977 AMD RS690 Databook 3.04 2-6 (c) 2007 Advanced Micro Devices, Inc. Proprietary DVI/HDMI (Not Applicable to the RS690C) 2.2.2 Support for HDMI Packet Types Table 2-3 Support for HDMI Packet Type Packet Value Packet Type 0x00 Null 0x01 Audio Clock Regeneration 0x02 Audio Sample Supported Source or Not Comment Yes Sent when required to meet Inserted by hardware if no packets in horizontal active on line 2 (can be disabled maximum time between data island specification. by software). Yes Inserted by hardware or video driver. Contents from register bits or combination of register bits and hardware control. Inserted in horizontal blank. -- Yes Audio samples come from HD audio DMA. Channel status from HD audio and video registers. Inserted in horizontal blank whenever audio FIFO contains data. -- No Sending and contents controlled by video driver. Inserted (on even frames only in interlaced mode) when requested by software or whenever AVMUTE status changes. Inserted in horizontal active on line selected by software. -- -- Audio content protection information. 0x03 General Control 0x04 ACP Packet Yes* 0x05 ISRC1 Packet Yes Controlled by video driver. Inserted in horizontal active on line selected For transmitting UPC or ISRC codes. by software. 0x06 ISRC2 Packet Yes Software controlled. Inserted in horizontal active on line selected Implement if ISRC1 is used. by software. 0x07 Reserved N/A N/A N/A InfoFrame Packet Type HDMI ID EIA-861B ID 0x80 0x00 Vendor-Specific Yes* 0x81 0x01 AVI Yes 0x82 0x02 Source Product Descriptor Yes* -- -- Controlled by video driver. For colorimetry, repetition count, Inserted in horizontal active on line selected video format, picture formatting. by software. -- -- 0x83 0x03 Audio Yes Inserted in horizontal active on line selected by software. For channel counts, sampling Contents from registers written by video frequency, etc. and HD audio drivers. Sent only when HD audio enables audio (video driver can also disable). 0x84 0x04 MPEG Source Yes Software controlled. Inserted in horizontal active on line selected For bit rate, field repeat, frame type by software. * Note: These packet types are supported using generic packet types. A maximum of two of them can be supported simultaneously. (c) 2007 Advanced Micro Devices, Inc. Proprietary 41977 AMD RS690 Databook 3.04 2-7 VGA DAC Characteristics 2.3 VGA DAC Characteristics Table 2-4 VGA DAC Characteristics Parameter Resolution Min Typ Max Notes 10 bits - - 1 Maximum PS/2 setting Output Voltage - 0.7V - 1, 10 Maximum PS/2 setting Output Current - 18.7mA - 1, 10 +8% / -3% - +10% 2, 3 -2% - +2% 1, 4 Full Scale Error DAC to DAC Correlation Differential Linearity -2 LSB - +2 LSB 1, 5 Integral Linearity -2 LSB - +2 LSB 1, 5 Rise Time (10% to 90%) 0.58ns - 1.7ns 1, 6 Full Scale Settling Time - TBA - 1, 7, 8 Glitch Energy - TBA - 1, 8 Monotonicity - - - 9 Notes: 1 Tested over the operating temperature range at nominal supply voltage, with an Iref of -1.50mA (Iref is the level of the current flowing out of the RSET resistor). 2 Tested over the operating temperature range at reduced supply voltage, with an Iref of -1.50mA (Iref is the level of the current flowing out of the RSET resistor). 3 Full scale error from the value predicted by the design equations. 4 About the mid-point of the distribution of the three DACs measured at full scale deflection. 5 Linearity measured from the best fit line through the DAC characteristics. Monotonicity guaranteed. 6 Load = 37.5 + 20pF with Iref = -1.50 mA (Iref is the current flowing out of the RSET resistor). 7 Measured from the end of the overshoot to the point where the amplitude of the video ringing is down to +/-5% of the final steady state value. 8 This parameter is sampled, not 100% tested. 9 Monotonicity is guaranteed. 10 Levels are 7.8% higher with setup pedestal enabled. 2.4 External Clock Chip On the RS690 platform, an external clock chip provides the reference clock to the CPU (for generating the CPU internal clocks) and a reference clock to the RS690 (for generating the HyperTransport, PCI Express, and A-Link Express II clocks). For more information about supported clock chips, please consult your AMD CSS representative. 41977 AMD RS690 Databook 3.04 2-8 (c) 2007 Advanced Micro Devices, Inc. Proprietary Chapter 3 Pin Descriptions and Strap Options This chapter gives the pin descriptions and the strap options for the RS690. To jump to a topic of interest, use the following list of hyperlinked cross references: "Pin Assignment" on page 3-2 "Interface Block Diagram" on page 3-4 "CPU HyperTransport Interface" on page 3-5 "PCI Express(R) Interfaces" on page 3-5: "1 x 16 Lane Interface for External Graphics" on page 3-5 "A-Link Express II to Southbridge" on page 3-5 "4 x 1 Lane Interface for General Purpose External Devices" on page 3-6 "Miscellaneous PCI Express(R) Signals" on page 3-6 "Clock Interface" on page 3-6 "CRT and TV Interface" on page 3-6 "Integrated DVI/HDMI Interface" on page 3-7 "TMDS Interface Multiplexed on the PCI Express(R) Graphics Lanes (Not Applicable to the RS690C)" on page 3-8 "Power Management Pins" on page 3-9 "Miscellaneous Pins" on page 3-9 "Power Pins" on page 3-10 "Ground Pins" on page 3-11 "Debug Port Signals" on page 3-11 "Strapping Options" on page 3-12 (c) 2007 Advanced Micro Devices, Inc. Proprietary 41977 AMD RS690 Databook 3.04 3-1 Pin Assignment 3.1 Pin Assignment The figures below only represent the relative ball positions. For the actual physical layout of the balls, please refer to Figure 5-3, "RS690 Ball Arrangement," on page 5- 7. 1 2 3 4 5 6 7 8 9 10 11 12 13 A VSSA I2C_CLK STRP_DATA VDD_CORE DACHSYNC DACSDA VDD_CORE DFT_GPIO5 VDD_CORE PLLVDD18 PLLVDD12 LVDDR18D TXOUT_L1N B VDDA_12 BMREQ# DDC_DATA I2C_DATA ALLOW_LDTSTOP DACSCL VSS DFT_GPIO4 VDD_CORE PLLVSS OSCIN LVDDR18D TXOUT_L1P C VDDA_12 TVCLKIN TESTMODE VSS LDTSTOP# DACVSYNC DFT_GPIO3 DFT_GPIO2 VDD_CORE SYSRESET# POWERGOOD LVDDR33 LVDDR33 D VDDA_12 VDDA_12 VDDA_12 VSS DFT_GPIO0 DFT_GPIO1 VDD_CORE VDDR3 LVSSR E GFX_CLKN VDDA_12 VDDA_12 VDDA_12 VDD_PLL VSS VDDR3 GPIO3 F VSSA GFX_CLKP VSSA VDDA_12 VDD_PLL VSS_PLL VSS GPIO4 G SB_CLKP SB_CLKN VSSA GFX_RX0N VDDA_12 VSS_PLL VSS GPIO2 H VSSA GFX_TX0N VSSA VDD_CORE VSS J GFX_TX0P VSSA VSSA VDD_CORE VSS K GFX_TX1N GFX_TX1P GFX_TX2P GFX_RX0P VSSA GFX_RX2P GFX_RX2N VSSA GFX_RX1N GFX_RX1P L GFX_TX3P GFX_TX3N GFX_TX2N GFX_RX4P GFX_RX4N VSSA GFX_RX3N GFX_RX3P VDDA_12 VDD_CORE VSS M VDDA_12_PKG VSSA VSSA GFX_RX6P GFX_RX6N VSSA GFX_RX5N GFX_RX5P VDDA_12 VSS VDD_CORE VSS N GFX_TX4N GFX_TX4P VSSA VDD_CORE VSS VDD_CORE P GFX_TX5N GFX_TX5P GFX_TX6P GFX_RX8P GFX_RX8N VSSA GFX_RX7N GFX_RX7P VSSA VSS VDD_CORE VSS R GFX_TX7P GFX_TX7N GFX_TX6N GFX_RX9P GFX_RX9N VSSA GFX_RX10P GFX_RX10N VSSA VDD_CORE VSS VDD_CORE VSSA GFX_RX11P GFX_RX11N VSSA VDDA_12 VDD_CORE VDD_CORE T VSSA GFX_TX8P U GFX_TX8N VSSA VSSA V GFX_TX9N GFX_TX9P GFX_TX10P W GFX_TX11P GFX_TX11N GFX_TX10N GFX_RX12P GFX_RX12N Y VSSA GFX_TX12P VSSA GFX_RX13P GFX_RX13N AA GFX_TX12N GFX_TX13P VSSA VSSA VDDA_12 GFX_RX14P VSSA VSSA GFX_RX14N SB_RX2P SB_RX2N GPP_RX2P VSSA VSSA VSSA GPP_RX2N GPP_RX3N SB_RX3P SB_RX1N GPP_RX3P VDD_CORE AB GFX_TX14P GFX_TX13N VDDA_12 VDDA_12 GFX_RX15N GFX_RX15P SB_RX3N SB_RX1P AC GFX_TX14N VSSA VDDA_12 VSSA VSSA VSSA VSSA SB_TX1P VSSA VSSA VDDA_12_PKG VDDR DEBUG2 AD VSSA VDDA_12 VSSA GPP_TX2P GPP_TX3P GPP_TX3N SB_TX3P SB_TX2P SB_TX1N SB_TX0N PCE_CALRP VDDR DEBUG0 AE VDDA_12 VDDA_12 GFX_TX15P GFX_TX15N GPP_TX2N VSSA SB_TX3N SB_TX2N SB_TX0P VSSA PCE_CALRN VDDR DEBUG1 1 2 3 4 5 6 7 8 9 10 11 12 13 CPU Interface A-Link Express II interface Clock Interface CRT and TV Interface External graphics Interface Integrated DVI/HDMI Interface General Purpose External Device Interface Power Management Interface Powers Grounds Others Figure 3-1 RS690 Pin Assignment (Left) 41977 AMD RS690 Databook 3.04 3-2 (c) 2007 Advanced Micro Devices, Inc. Proprietary Pin Assignment 14 15 16 17 18 19 20 21 22 23 24 25 LVSSR TXOUT_U0P LVSSR TXOUT_U2N TXOUT_U3P VDD_CORE AVDDDI AVDDQ AVSSQ VSS HT_RXCALP VSS A TXOUT_L0P TXOUT_L0N TXOUT_U0N TXOUT_U2P TXOUT_U3N VDD_CORE AVSSDI RSET AVDD HTREFCLK HTPVDD HTPVSS B TMDS_HPD LVSSR LVSSR TXOUT_U1P TXOUT_U1N LVSSR Y C AVDD HTTSTCLK HT_RXCALN HT_TXCALP C LPVDD TXCLK_LN TXOUT_L3P COMP VDD_CORE VDD_HT_PKG VSS HT_TXCALN VSS D LPVSS TXCLK_LP TXOUT_L3N RED HT_TXCAD1P HT_TXCAD0P HT_TXCAD0N E LVSSR LVSSR VSS GREEN TXOUT_L2N TXCLK_UN AVSSN BLUE TXOUT_L2P TXCLK_UP AVSSN VDD_18 VDD_18 VDD_CORE HT_TXCAD8P HT_TXCAD8N HT_TXCAD1N HT_TXCAD2N HT_TXCAD2P F VDD_CORE HT_TXCAD10N HT_TXCAD10P VSS VSS HT_TXCAD3P G VSS HT_TXCAD3N VSS H HT_TXCAD9P HT_TXCAD9N VSS HT_TXCAD4P HT_TXCLK0P HT_TXCLK0N J HT_TXCAD4N HT_TXCAD5N HT_TXCAD5P K VSS VDD_CORE VDD_CORE HT_TXCAD11P HT_TXCAD11N VSS HT_TXCLK1P HT_TXCLK1N VSS VSS HT_TXCAD6P L VDD_CORE VSS VSS HT_TXCAD12P HT_TXCAD12N VSS HT_TXCAD13N HT_TXCAD13P VSS HT_TXCAD6N VSS M N VSS VDD_CORE HT_TXCTLP HT_TXCAD7P HT_TXCAD7N VDD_CORE VSS VDD_CORE HT_TXCAD14P HT_TXCAD14N VSS HT_TXCAD15P HT_TXCAD15N HT_TXCTLN HT_RXCTLP HT_RXCTLN P VSS VDD_CORE VSS HT_RXCAD15N HT_RXCAD15P VSS HT_RXCAD14P HT_RXCAD14N VSS VSS HT_RXCAD7N R VSS HT_RXCAD7P VSS T VDD_CORE VDD_CORE HT_RXCAD12P HT_RXCAD12N VSS HT_RXCAD13N HT_RXCAD13P HT_RXCAD5N HT_RXCAD6N HT_RXCAD6P U HT_RXCAD5P HT_RXCAD4P HT_RXCAD4N V HT_RXCAD11N HT_RXCLK1P HT_RXCLK1N VSS VSS HT_RXCLK0N W VSSA VSSA SB_RX0P SB_RX0N VDD_HT HT_RXCAD11P VSSA VDD_HT HT_RXCAD8N VDD_HT HT_RXCAD8P HT_RXCAD9N VDD_HT HT_RXCAD9P VDD_HT VDD_HT VSSA NC NC THERMALDIODE_ P THERMALDIODE_ N VSS VSS GPP_TX0P VSS 14 VDD_HT VSS VSS HT_RXCLK0P VSS Y HT_RXCAD2N HT_RXCAD3N HT_RXCAD3P AA HT_RXCAD10N HT_RXCAD2P HT_RXCAD1P HT_RXCAD1N AB HT_RXCAD10P VSS VSS HT_RXCAD0P HT_RXCAD0N AC GPP_RX1P VDD_HT VDD_HT VDD_HT VDD_HT VSS AD GPP_RX1N DEBUG15 VSS VDD_HT VDD_HT VDD_HT AE 21 22 23 24 25 VSS DEBUG9 VDD_HT GPP_TX0N GPP_RX0P DEBUG13 DEBUG10 GPP_TX1P DEBUG6 GPP_RX0N DEBUG14 VSS GPP_TX1N 15 16 17 18 19 20 CPU Interface A-Link Express interface Clock Interface CRT and TV Interface External graphics Interface Integrated DVI/HDMI Interface General Purpose External Device Interface Power Management Interface Powers Grounds Others Figure 3-2 RS690 Pin Assignment (Right) (c) 2007 Advanced Micro Devices, Inc. Proprietary 41977 AMD RS690 Databook 3.04 3-3 Interface Block Diagram 3.2 Interface Block Diagram The figure below shows the different interfaces on the RS690. Interface names in blue are hyperlinks to the corresponding sections in this chapter. HT_RXCAD[15:0]P, HT_RXCAD[15:0]N HT_RXCLK[1:0]P, HT_RXCLK[1:0]N HT_RXCTLP, HT_RXCTLN HT_TXCAD[15:0]P, HT_TXCAD[15:0]N HT_TXCLK[1:0]P, HT_TXCLK[1:0]N HT_TXCTLP, HT_TXCTLN HT_RXCALP, HT_RXCALN HT_TXCALP, HT_TXCALN TXOUT_U0N, TXOUT_U0P TXOUT_U1N, TXOUT_U1P TXOUT_U2N, TXOUT_U2P TXCLK_UN, TXCLK_UP TXOUT_L0N, TXOUT_L0P TXOUT_L1N, TXOUT_L1P TXOUT_L2N, TXOUT_L2P TXCLK_LN, TXCLK_LP SB_TX[3:0]P, SB_TX[3:0]N SB_RX[3:0]P, SB_RX[3:0]N SB_CLKP, SB_CLKN SYSRESET# POWERGOOD LDTSTOP# HyperTransport Interface Integrated DVI/HDMI Interface A-Link Express II Interface Power Management Interface PCI-E External Graphics or TMDS [RS690 only] Interface GFX_TX[15:0]P, GFX_TX[15:0]N GFX_RX[15:0]P, GFX_RX[15:0]N GFX_CLKP, GFX_CLKN PCI-E Interface for General Purpose External Devices GPP_TX[3:0]P, GPP_TX[3:0]N GPP_RX[3:0]P, GFX_RX[3:0]N Misc. PCI-E Signals PCE_CALRP PCE_CALRN RED GREEN BLUE DACVSYNC DACHSYNC DACSCL DACSDA C Y COMP RSET CRT and TV-out Interface ALLOW_LDTSTOP BMREQ# DDC_DATA STRP_DATA TVCLKIN OSCIN Clock Interface I2C_CLK I2C_DATA HTREFCLK HTTSTCLK Misc. Signals DFT_GPIO[5:0] GPIO[4:2] TESTMODE THERMALDIDOE_N, THERMALDIODE_P TMDS_HPD VDD_HT_PKG VDDA_12_PKG AVDD AVDDDI AVDDQ HTPVDD LPVDD LVDDR33 LVDDR18D PLLVDD18 PLLVDD12 VDD_18 Power AVSSN AVSSQ AVSSDI HTPVSS LPVSS LVSSR PLLVSS VSS VSSA VSS_PLL VDDA_12 VDD_CORE VDD_HT VDDR VDDR3 VDD_PLL Grounds Figure 3-3 RS690 Interface Block Diagram 41977 AMD RS690 Databook 3.04 3-4 (c) 2007 Advanced Micro Devices, Inc. Proprietary CPU HyperTransport Interface 3.3 CPU HyperTransport Interface Table 3-1 CPU HyperTransport Interface Pin Name 3.4 3.4.1 Type Power Domain Ground Domain Functional Description HT_RXCAD[15:0]P, HT_RXCAD[15:0]N I VDDHT VSS Receiver Command, Address, and Data Differential Pairs HT_RXCLK[1:0]P, HT_RXCLK[1:0]N I VDDHT VSS Receiver Clock Signal Differential Pair. Forwarded clock signal. Each byte of RXCAD uses a different clock signal. Data is transferred on each clock edge. HT_RXCTLP, HT_RXCTLN I VDDHT VSS Receiver Control Differential Pair. For distinguishing control packets from data packets. HT_TXCAD[15:0]P, HT_TXCAD[15:0]N O VDDHT VSS Transmitter Command, Address, and Data Differential Pairs HT_TXCLK[1:0]P, HT_TXCLK[1:0]N O VDDHT VSS Transmitter Clock Signal Differential Pair. Each byte of TXCAD uses a different clock signal. Data is transferred on each clock edge. HT_TXCTLP, HT_TXCTLN O VDDHT VSS Transmitter Control Differential Pair. Forwarded clock signal. For distinguishing control packets from data packets. HT_RXCALN Other VDDHT VSS Receiver Calibration Resistor to VDD_HT power rail. HT_RXCALP Other VDDHT VSS Receiver Calibration Resistor to Ground HT_TXCALP Other VDDHT VSS Transmitter Calibration Resistor to HTTX_CALN HT_TXCALN Other VDDHT VSS Transmitter Calibration Resistor to HTTX_CALP PCI Express(R) Interfaces 1 x 16 Lane Interface for External Graphics Table 3-2 1 x 16 Lane PCI Express Interface for External Graphics Pin Name 3.4.2 Type Power Domain Ground Domain Integrated Termination Functional Description GFX_TX[15:0]P, GFX_TX[15:0]N O VDD_PCIE VSS_PCIE 50 between complements Transmit Data Differential Pairs. Connect to external connector for an external graphics card on the motherboard (if implemented). GFX_RX[15:0]P, GFX_RX[15:0]N I VDD_PCIE VSS_PCIE 50 between complements Receive Data Differential Pairs. Connect to external connector for an external graphics card on the motherboard (if implemented). GFX_REFCLKP, GFX_REFCLKN I VDD_PCIE VSS_PCIE 50 between complements Clock Differential Pairs. Connect to external clock generator when an external graphics card is implemented. A-Link Express II to Southbridge Table 3-3 1 x 4 Lane A-Link Express II Interface for Southbridge Power Domain Ground Domain Integrated Termination Functional Description Pin Name Type SB_TX[3:0]P, SB_TX[3:0]N O VDD_PCIE VSS_PCIE 50 between Transmit Data Differential Pairs. Connect to the corresponding complements Receive Data Differential pairs on the Southbridge. SB_RX[3:0]P, SB_RX[3:0]N I VDD_PCIE VSS_PCIE 50 between Receive Data Differential Pairs. Connect to the corresponding complements Transmit Data Differential pairs on the Southbridge. SB_CLKP, SB_CLKN I VDD_PCIE VSS_PCIE 50 between Clock Differential Pair. Connect to an external clock generator on complements the motherboard. (c) 2007 Advanced Micro Devices, Inc. Proprietary 41977 AMD RS690 Databook 3.04 3-5 Clock Interface 3.4.3 4 x 1 Lane Interface for General Purpose External Devices Table 3-4 4 x 1 Lane PCI Express(R) Interface for General Purpose External Devices Pin Name 3.4.4 Power Domain Type Ground Domain Integrated Termination Functional Description GPP_TX[3:0]P, GPP_TX[3:0]N O VDD_PCIE VSS_PCIE 50 between Transmit Data Differential Pairs. Connect to external connectors on complements the motherboard for add-in card or ExpressCard support. GPP_RX[3:0]P, GPP_RX[3:0]N I VDD_PCIE VSS_PCIE 50 between Receive Data Differential Pairs. Connect to external connectors on complements the motherboard for add-in card or ExpressCard support. Miscellaneous PCI Express(R) Signals Table 3-5 PCI Express(R) Interface for Miscellaneous PCI Express(R) Signals 3.5 Power Domain Ground Domain Pin Name Type Functional Description PCE_CALRN Other VDD_PCIE VSS_PCIE RX Impedance Calibration. Connect to VDD_PCIE on the motherboard with an external resistor of an appropriate value. PCE_CALRP Other VDD_PCIE VSS_PCIE TX Impedance Calibration. Connect to GND on the motherboard with an external resistor of an appropriate value. Clock Interface Table 3-6 Clock Interface Type Power Domain TVCLKIN I VDDR3 VSS - Input pin for reference clock for external TV-out support (3.3V signaling). HTREFCLK I HTPVDD HTPVSS - HyperTransport 66MHz reference clock from external clock source HTTSTCLK I HTPVDD HTPVSS - HyperTransport Bus Test Clock. Drives test clock in test mode. Connect to ground in functional mode. GFX_REFCLKP, GFX_REFCLKN I VDDPCIE VSSAPCIE SB_CLKP, SB_CLKN I VDDPCIE VSSAPCIE OSCIN I Pin Name 3.6 VDDR3 Ground Integrated Domain Termination Functional Description VSS 50 between complements Clock Differential Pairs for external graphics. Connect to external clock generator when an external graphics card is implemented. Clock Differential Pair for the Southbridge and general purpose PCI 50 between Express(R) (PCI-E) devices. Connect to an external clock generator on complements the motherboard. Disabled 14.3181818MHz Reference clock input from the External Clock chip (3.3 volt signaling). CRT and TV Interface Table 3-7 CRT and TV Interface Pin Name RED Type A-O Power Ground Integrated Domain Domain Termination Functional Description AVDD AVSSN - Red for CRT monitor output, or Pr for component video TV output GREEN A-O AVDD AVSSN - Green for CRT monitor output, or Y for component video TV output BLUE A-O AVDD AVSSN - Blue for CRT monitor output, or Pb for component video TV output Y A-O AVDD AVSSN - SVID luminance output for TV out, or Y for component video TV output C A-O AVDD AVSSN - SVID chrominance output for TV out, or Pr for component video TV output COMP A-O AVDD AVSSN - Composite video TV output, or Pb for component video TV output 41977 AMD RS690 Databook 3.04 3-6 (c) 2007 Advanced Micro Devices, Inc. Proprietary Integrated DVI/HDMI Interface Table 3-7 CRT and TV Interface Power Ground Integrated Domain Domain Termination Functional Description Pin Name Type DACHSYNC A-O VDDR3 VSS 50k programmable: Display Horizontal Sync PU/PD/none DACVSYNC A-O VDDR3 VSS 50k programmable: Display Vertical Sync PU/PD/none Other N/A AVSSQ DACSDA I/O VDDR3 VSS 50k programmable: I2C Data for display (to video monitor) PU/PD/none DACSCL I/O VDDR3 VSS 50k programmable: I2C Clock for display (to video monitor) PU/PD/none RSET 3.7 (Continued) DAC internal reference to set full scale DAC current through 1% resistor to AVSS - Integrated DVI/HDMI Interface Note: The RS690C does not contain an integrated DVI/HDMI interface. The following pins should be treated as reserved for the RS690C. Table 3-8 Integrated DVI/HDMI Interface Pin Name DVI/HDMI Functional Name Type Power Domain TXOUT_L0N TX0M O LVDDR33 LVDDR18D VSSLT None DVI/HDMI data channel 0 (-) TXOUT_L0P TX0P O LVDDR33 LVDDR18D VSSLT None DVI/HDMI data channel 0 (+) TXOUT_L1N TX1M O LVDDR33 LVDDR18D VSSLT None DVI/HDMI data channel 1 (-) TXOUT_L1P TX1P O LVDDR33 LVDDR18D VSSLT None DVI/HDMI data channel 1 (+) TXOUT_L2N TX2M O LVDDR33 LVDDR18D VSSLT None DVI/HDMI data channel 2 (-) TXOUT_L2P TX2P O LVDDR33 LVDDR18D VSSLT None DVI/HDMI data channel 2 (+) TXOUT_L3N TX3M O LVDDR33 LVDDR18D VSSLT None DVI data channel 3 (-). The channel is only used in DVI dual-link mode and is not used for HDMI support. TXOUT_L3P TX3P O LVDDR33 LVDDR18D VSSLT None DVI data channel 3 (+). The channel is only used in DVI dual-link mode and is not used for HDMI support. TXOUT_U0N TX4M O LVDDR33 LVDDR18D VSSLT None DVI data channel 4 (-). The channel is only used in DVI dual-link mode and is not used for HDMI support. TXOUT_U0P TX4P O LVDDR33 LVDDR18D VSSLT None DVI data channel 4 (+) The channel is only used in DVI dual-link mode and is not used for HDMI support. TXOUT_U1N TX5M O LVDDR33 LVDDR18D VSSLT None DVI data channel 5 (-). The channel is only used in DVI dual-link mode and is not used for HDMI support. TXOUT_U1P TX5P O LVDDR33 LVDDR18D VSSLT None DVI data channel 5 (+). The channel is only used in DVI dual-link mode and is not used for HDMI support. (c) 2007 Advanced Micro Devices, Inc. Proprietary Ground Integrated Domain Termination Functional Description 41977 AMD RS690 Databook 3.04 3-7 TMDS Interface Multiplexed on the PCI Express(R) Graphics Lanes (Not Applicable to the RS690C) Table 3-8 Integrated DVI/HDMI Interface (Continued) 3.8 Pin Name DVI/HDMI Functional Name Type Power Domain TXOUT_U2N - O LVDDR33 LVDDR18D VSSLT None Unused TXOUT_U2P - O LVDDR33 LVDDR18D VSSLT None Unused TXOUT_U3N - O LVDDR33 LVDDR18D VSSLT None Unused TXOUT_U3P - O LVDDR33 LVDDR18D VSSLT None Unused TXCLK_LN TXCM O LVDDR33 LVDDR18D VSSLT None DVI/HDMI clock channel (-) TXCLK_LP TXCP O LVDDR33 LVDDR18D VSSLT None DVI/HDMI clock channel (+) TXCLK_UN - O LVDDR33 LVDDR18D VSSLT None Unused TXCLK_UP - O LVDDR33 LVDDR18D VSSLT None Unused Ground Integrated Domain Termination Functional Description TMDS Interface Multiplexed on the PCI Express(R) Graphics Lanes (Not Applicable to the RS690C) The RS690 supports a dual-link TMDS interface, enabling DVI/HDMI, which is multiplexed on the PCI-E external graphics lanes. The TMDS interface is available only if no external graphics card, or only a x8 one, is attached to the PCI-E graphics interface. HDMI is enabled only through the single-link mode. The interface cannot enable HDMI when the integrated DVI/HDMI interface is supporting HDMI, and vice versa. Table 3-9, "TMDS Interface Multiplexed on the PCI Express(R) Graphics Interface," shows the multiplexing relationships between the PCI-E external graphics signals and the TMDS signals. Table 3-9 TMDS Interface Multiplexed on the PCI Express(R) Graphics Interface Pin Name Ball Reference TMDS Function GFX_TX0P J1 TX2P - 1st Link Red+ GFX_TX0N H2 TX2M - 1st Link Red- GFX_TX1P K2 TX1P - 1st Link Green+ GFX_TX1N K1 TX1M - 1st Link Green- GFX_TX2P K3 TX0P - 1st Link Blue+ GFX_TX2N L3 TX0M- 1st Link Blue - GFX_TX3P L1 TXCP - Clock+ GFX_TX3N L2 TXCM - Clock- GFX_TX4P N2 TX5P- 2nd Link Red+ GFX_TX4N N1 TX5M - 2nd Link Red- GFX_TX5P P2 TX4P- 2nd Link Green+ GFX_TX5N P1 TX4M - 2nd Link Green- GFX_TX6P P3 TX3P - 2nd Link Blue+ GFX_TX6N R3 TX3M - 2nd Link Blue- 41977 AMD RS690 Databook 3.04 3-8 (c) 2007 Advanced Micro Devices, Inc. Proprietary Power Management Pins 3.9 Power Management Pins Table 3-10 Power Management Pins Pin Name Type Power Domain Ground Domain LDTSTOP# I VDDR3 VSS OD VDDR3 VSS Output going to the Southbridge to allow LDTSTOP assertions: 1 = LDTSTOP# can be asserted 0 = LDTSTOP# has to be de-asserted ALLOW_LDTSTOP 3.10 Functional Description HyperTransport Stop. Input from the Southbridge to enable and disable the HyperTransport link during system state transitions. For systems requiring power management. Single-ended. SYSRESET# I VDDR3 VSS Global Hardware Reset. This signal comes from the Southbridge. POWERGOOD I VDDR3 VSS Input from the motherboard signifying that the power to the RS690 is up and ready. Signal high means all power planes are valid. It is not observed internally until it has been high for more than 6 consecutive REFCLK cycles. The rising edge of this signal is deglitched. The nominal input high voltage is 3.3V. Miscellaneous Pins Table 3-11 Miscellaneous Pins Pin Name Type Power Ground Integrated Domain Domain Termination Functional Description BMREQ# O VDDR3 VSS - This output signal to the Southbridge indicates that there is a DMA request from a PCI Express Bus device. The signal is not used on the RS690 platforms and should be left unconnected. DEBUG[15:13, 10:9, 6, 2:0] I/O VDDR VSS - Debug port signals. See section 3.13, "Debug Port Signals," on page 3- 11 for details. DFT_GPIO[5:0] I/O VDD_18 VSS - GPIO for DFT purpose. General Purpose I/O. These pins can also be used as outputs to the voltage regulator for pulse-width modulation of various voltages on the motherboard. If not used for pulse-width-modulation, GPIO3 50k programmable: can also be used as a "hot plug" panel detection input pin that PU/PD/none monitors if the voltage is greater than 2.0V on the hot-plugging line from a digital display. GPIO[4:2] I/O VDDR3 VSS I2C_CLK I/O VDDR3 VSS 50k I2C interface clock signal. Can also be used simultaneously as programmable: DDC interface clock . It can also be used as GPIO. PU/PD/none I2C_DATA I/O VDDR3 VSS 50k programmable: I2C interface data signal. It can also be used as GPIO. PU/PD/none DDC_DATA I/O VDDR3 VSS 50k Pin for additional DDC data channel for displays. It makes use of programmable: I2C_CLK to create an I2C interface. Can also be used as GPIO. PU/PD/none - - - NC - No connect. These pins should be left unconnected to anything. I2C interface data signal for external EEPROM based strap 50k programmable: loading. Can also be used as GPIO, or as output to the voltage PU/PD/none regulator for pulse-width modulation of RS690's core voltage. STRP_DATA I/O VDDR3 VSS TESTMODE I VDDR3 VSS - When high, puts the RS690 in test mode and disables the RS690 from operating normally. A-O - - - Diode connections to external SMBus microcontroller for monitoring IC thermal characteristics. THERMALDIODE_P, THERMALDIODE_N TMDS_HPD I/O VDDR3 (c) 2007 Advanced Micro Devices, Inc. Proprietary VSS TMDS Hot Plug Detect. It monitors the hot-plug line for panel detection. It is a 3.3V CMOS compatible input. When not used for 50k programmable: hot plug detection, it can also be used as output to the voltage PU/PD/none regulator for pulse-width modulation of various voltages on the motherboard. 41977 AMD RS690 Databook 3.04 3-9 Power Pins Table 3-11 Miscellaneous Pins (Continued) Pin Name VDD_HT_PKG Other VDDA_12_PKG 3.11 Power Ground Integrated Domain Domain Termination Functional Description Type Other VDD_HT VDDA_12 VSS VSS - The pin is for connecting a calibration resistor to the VDD_HT power plane. The VDD_HT_PKG pin is connected to the VDD_HT power pins via package routing, so that a calibration resistor for the VDD_HT power plane can be connected to the RS690 through the VDD_HT_PKG pin, and the VDD_HT power plane does not have to be extended physically for the purpose. - The pins are for connecting calibration resistors to the VDDA_12 power plane. VDDA_12_PKG pins are connected to the VDDA_12 power pins via package routing, so that the calibration resistors for the VDDA_12 power plane can be connected to the RS690 through the VDDA_12_PKG pins, and the VDDA_12 power plane does not have to be extended physically for the purpose. Power Pins Table 3-12 Power Pins Pin Name AVDD Voltage Pin Count Ball Reference Comments 2.5V or 3.3V 2 B22, C22 Dedicated power for the DAC. Effort should be made at the board level to provide as clean a power as possible to this pin to avoid noise injection, which can affect display quality. Adequate decoupling should be provided between this pin and AVSS. AVDDQ 1.8V 1 A21 DAC Bandgap Reference Voltage AVDDDI 1.8V 1 A20 Dedicated digital power for the DAC VDD_CORE 1.2V 32 A19, A4, A7, A9, B19, B9, Core power C9, D20, D9, G20, H11, J11, J19, L11, L13, L15, L17, M12, M14, N11, N13, N15, P12, P14, P17, R11, R13, R15, U11, U12, U14, U15 VDD_18 1.8V 2 J14, J15 VDDA_12 1.2 V 20 AB3, AB4, AC3, AD2, AE1, PCI-E interface main I/O power AE2, B1, C1, D1, D2, D3, E2, E3, E6, F4, G7, L9, M9, U7, W7 VDDR Core transform power for GPIOs and power for DFT_GPIOs 1.8 3 AC12, AD12, AE12 VDD_HT 1.2V 15 AA17, AB17, AB19, AC18, I/O power for HyperTransport interface AC19, AC20, AD21, AD22, AD23, AD24, AE23, AE24, AE25, W17, Y17 VDDR3 3.3V 2 D11, E11 I/O power for the following I/O pads: POWERGOOD, SYSRESET# VDD_PLL 1.2V 2 E7, F7 PCI-E interface PLL power LPVDD 1.8V 1 D14 Power for integrated DVI/HDMI PLL macro. LVDDR18D 1.8V 2 A12, B12 1.8V integrated DVI/HDMI Digital Power LVDDR33 3.3V 2 C12, C13 3.3V integrated DVI/HDMI Analog Power PLLVDD18 1.8V 1 A10 1.8V power for system PLLs PLLVDD12 1.2V 1 A11 1.2V power for system PLLs HTPVDD 1.8V 1 B24 Power for HyperTransport interface PLL Total Power Pin Count 41977 AMD RS690 Databook 3.04 3-10 IO power for debug interface (1.8V) 88 (c) 2007 Advanced Micro Devices, Inc. Proprietary Ground Pins 3.12 Ground Pins Table 3-13 Ground Pins Pin Name Ball Reference Comments AVSSN 2 G17, H17 Dedicated analog ground for the DAC AVSSQ 1 A22 Dedicated ground for the Band Gap Reference. Effort should be made at the board level to provide as clean a ground as possible to this pin to avoid noise injection, which can affect display quality. Adequate decoupling should be provided between this pin and AVDD. AVSSDI 1 B20 Dedicated digital ground for the DAC (1.8V) LPVSS 1 E14 PLL macro ground pin LVSSR 8 A14, A16, C15, C16, C19, D12, F14, F15 ground pin VSS 59 A23, A25, AC14, AC15, AC16, Common ground AC22, AC23, AD25, AE14, AE18, AE22, B7, C4, D23, D25, D4, E9, F11, F17, G11, G23, G24, H12, H23, H25, J12, J22, L12, L14, L20, L23, L24, M11, M13, M15, M17, M20, M23, M25, N12, N14, P11, P13, P15, P20, R12, R14, R17, R20, R23, R24, T23, T25, U20, W23, W24, Y22, Y23, Y25 VSSA 48 PCI Express interface ground A1, AA3, AC10, AC2, AC4, AC5, AC6, AC7, AC9, AD1, AD3, AE10, AE6, F1, F3, G3, G6, H1, H3, J2, J3, J6, L6, M2, M3, M6, N3, P6, P9, R6, R9, T1, T3, U2, U3, U6, V11, V12, V14, V15, W6, Y1, Y11, Y12, Y14, Y15, Y3, Y9 VSS_PLL 2 F9. G9 Ground pin for PCI-E interface PLL PLLVSS 1 B10 Ground pin for graphics core PLL 1 B25 Ground pin for HyperTransport interface PLL HTPVSS Total Ground Pin Count 3.13 Pin Count 124 Debug Port Signals In order to fully support debugging of customer platforms, it is mandatory that customer designs allow access to the signals listed in Table 3-14, "RS690 Debug Port Signals" below. Signals in the table should be brought out to test points on the motherboard. Table 3-14 RS690 Debug Port Signals Pin Name Ball Ref Debug Port Name DEBUG0 AD13 Debug0 DEBUG1 AE13 Debug1 DEBUG2 AC13 Debug2 DEBUG6 AE15 Debug6 DEBUG9 AC17 Debug9 DEBUG10 AD18 Debug10 DEBUG13 AD17 Debug13 DEBUG14 AE17 Debug14 (c) 2007 Advanced Micro Devices, Inc. Proprietary 41977 AMD RS690 Databook 3.04 3-11 Strapping Options Table 3-14 RS690 Debug Port Signals Pin Name Ball Ref Debug Port Name DEBUG15 AE21 Debug15 DFT_GPIO2 C8 Debug [programmable*] DFT_GPIO3 C7 Debug [programmable*] DFT_GPIO4 B8 Debug [programmable*] DFT_GPIO5 A8 Debug [programmable*] *Note: The port is programmable into any of Debug0 to Debug15. 3.14 Strapping Options The RS690 provides strapping options to define specific operating parameters. The strap values are latched into internal registers after the assertion of the POWERGOOD signal to the RS690. Table 3-15, "Strap Definitions for the RS690," shows the definitions of all the strap functions. These straps are set by one of the following four methods: * * * * Allowing the internal pull-up resistors to set all strap values to "1" automatically. Attaching pull-down resistors to specific strap pins listed in Table 3-15 to set their values to "0". Downloading the strap values from an I2C serial EEPROM (for debug purpose only; contact your AMD CSS representative for details). Setting through an external debug port, if implemented (contact your AMD CSS representative for details). All of the straps below are defined active low. They are pulled up internally by default, so that no external pull-ups are required to select "1"s for those straps. To select "0"s, the strap pins must be pulled down to VSS through resistors. During reset, the strap pins are undriven, allowing either an internal pull-up to pull a pin to "1" or an external pull-down to pull a pin to "0." The values on the strap pins are then latched into the device and used as operational parameters. However, for debug purposes, those latched values may be overridden through an external debug strap port or by a bit-stream downloaded from a serial EEPROM. Table 3-15 Strap Definitions for the RS690 Strap Function Strap Pin Description RESERVED DFT_GPIO5 This is a reserved strap and no strap resistor should be connected to it. GPPSB_LINK_CONFIG DFT_GPIO[4:2] Southbridge and General Purpose Link Configuration. See Table 3-16 below for details. LOAD_ROM_STRAPS# DFT_GPIO1 Selects loading of strap values from EEPROM 0: I2C master can load strap values from EEPROM if connected, or use default values if not connected 1: Use default values (Default) RESERVED DFT_GPIO0 This is a reserved strap and no strap resistor should be connected to it. 41977 AMD RS690 Databook 3.04 3-12 (c) 2007 Advanced Micro Devices, Inc. Proprietary Strapping Options Table 3-16 Strap Definition for GPPSB_LINK_CONFIG Strap Pin Value DFT_GPIO4 DFT_GPIO3 Link Width DFT_GPIO2 SB GPP1 GPP2 GPP3 GPP4 Use register field STRAP_BIF_LINK_CONFIG_GPPSB of register StrapsOutputMux_7 (NBMISCIND: 0x67 bit[7:4]) to define link configuration (Default). Configuration - 1 1 1 1 1 0 4 0 0 0 0 A 1 0 1 4 4 0 0 0 B 1 0 0 4 2 2 0 0 C 0 1 1 4 2 1 1 0 D 0 1 0 4 1 1 1 1 E Others Use register field STRAP_BIF_LINK_CONFIG_GPPSB of register StrapsOutputMux_7 (NBMISCIND: 0x67 bit[7:4]) to define link configuration. - Note: The three strap pins are internally pulled up so that if left unconnected on the motherboard, the RS690 will use register field STRAP_BIF_LINK_CONFIG_GPPSB of register StrapsOutputMux_7 (NBMISCIND: 0x67 bit[7:4]) to define the link configuration. The power on default value of this register corresponds to Configuration E. If the pin straps are used, the GPPSB configuration will then be determined according to this table and cannot be changed after the system has been powered up. (c) 2007 Advanced Micro Devices, Inc. Proprietary 41977 AMD RS690 Databook 3.04 3-13 Strapping Options This page intentionally left blank. 41977 AMD RS690 Databook 3.04 3-14 (c) 2007 Advanced Micro Devices, Inc. Proprietary Chapter 4 Timing Specifications 4.1 CPU HyperTransport Bus Timing For HyperTransport bus timing information, please refer to CPU specifications. 4.2 HyperTransport Reference Clock Timing Parameters Table 4-1 HTREFCLK Pad (66.66MHz) Timing Parameters 4.3 Symbol Parameter Min Typ Max Unit TIP FIP Comment REFCLK Period - 15 - ns REFCLK Frequency - 66.66 - MHz TIH REFCLK High Time 2 - - ns - TIL REFCLK Low Time 2 - - ns - TIR REFCLK Rise Time - - 1.5 ns - TIF REFCLK Fall Time - - 1.5 ns - TIJCC REFCLK Cycle-to-Cycle Jitter Requirement - - 300 ps - TIJLT REFCLK Long Term Jitter Requirement (1s after scope trigger) - - 1 ns - Time intervals measured at 50% VDDCK threshold point FIP is the reciprocal of TIP. PCI Express(R) Differential Clock AC Specifications Table 4-2 PCI Express(R) Differential Clock (GFX_CLK, SB_CLK) AC Characteristics Parameter Minimum Absolute Minimum Differential Clock Period Unit 9.872 - ns Rise Time 175 700 ps Fall time 175 700 ps - 20 % Cycle-to-Cycle Jitter - 125 ps Duty Cycle 45 55 % Rise/Fall Matching 4.4 Maximum OSCIN Timing Table 4-3 Timing Requirements for the OSCIN Pad Symbol TIP Parameter REFCLK Period Min Typical Max Unit Note 0.037 - 1.1 s 1 2 FIP REFCLK Frequency 0.9 - 27 MHz TIR REFCLK Rise Time - - 1.5 ns TIF REFCLK Fall Time - - 1.5 ns (c) 2007 Advanced Micro Devices, Inc. Proprietary 41977 AMD RS690 Databook 3.04 4-1 OSCIN Timing Table 4-3 Timing Requirements for the OSCIN Pad (Continued) Symbol Min Typical Max Unit TIJCC REFCLK Cycle-to-Cycle Jitter Requirement Parameter - - 300 ps FRQD Frequency Tolerance - 30 - ppm Note 3 Notes: 1 Time intervals measured at 50% threshold point. 2 FIP is the reciprocal of TIP. 3 FRQD is the tolerance of the frequency input for proper generation of the expected PLL frequencies. 41977 AMD RS690 Databook 3.04 4-2 (c) 2007 Advanced Micro Devices, Inc. Proprietary Power Rail Power Up Sequence 4.5 Power Rail Power Up Sequence 3.3V Rails (VDDR3, LVDDR33, AVDD) T11 1.8V Display and PLL Rails (PLLVDD18, LVDDR18D, LPVDD, AVDDDI, AVDDQ, HTPVDD, VDD_18) 1.8V Debug IO Rails (VDDR) T12 T13 1.2V PLL Rails (PLLVDD12) T14 1.2V VDD_CORE Figure 4-1 Power Rail Power Up Sequence for the RS690 Table 4-4 RS690 Power Rail Power Up Sequence Requirements Symbol Parameter Voltage Difference During Ramping Minimum (V) Maximum (V) T11 3.3V rails ramp high relative to 1.8V display and PLL rails 0 2.1 T12 1.8V debug IO rail ramps high relative to VDD_CORE (1.2V) 0 No restrictions T13 1.8V display and PLL rails ramp high relative to 1.2V PLL rails 0 No restrictions T14 1.2V PLL rails ramp high relative to VDD_CORE (1.2V) 0 No restrictions Notes: 1. Power rails in the same group may require separate power sources. Please refer to the RS690/RS485-series IGP Motherboard Design Guide for details. 2. There are no specific requirements for the following 1.2V rails: VDD_HT, VDDA_12, and VDD_PLL. 3. For power down, the rails should either be turned off simultaneously or in the reversed order of the above power up sequence. Variations in speeds of decay due to different capacitor discharge rates can be safely ignored. Figure 4-1 above only shows the power up sequence for the power rails that the RS690 connects to. For a power up sequence for the whole RS690 platform, please refer to the RS690/RS485-Series IGP Motherboard Design Guide. (c) 2007 Advanced Micro Devices, Inc. Proprietary 41977 AMD RS690 Databook 3.04 4-3 Power Rail Power Up Sequence This page is left blank intentionally. 41977 AMD RS690 Databook 3.04 4-4 (c) 2007 Advanced Micro Devices, Inc. Proprietary Chapter 5 Electrical Characteristics and Physical Data 5.1 Electrical Characteristics 5.1.1 Maximum and Minimum Ratings Table 5-1 Maximum and Minimum Ratings Pin Minimum VDD_CORE Typical Maximum Unit Comments 1.2 1.26 V ASIC core power VDD_18 1.71 1.8 1.89 V Core transform power for GPIOs and power for DFT_GPIOs VDD_HT 1.14 1.2 1.26 V I/O power for HyperTransportTM interface VDDR3 3.135 3.3 3.465 V 3.3 Volt I/O power VDDA_12 1.14 1.2 1.26 V PCI Express Interface main I/O power AVDDDI 1.71 1.8 1.89 V Digital power for DAC AVDDQ 1.71 1.8 1.89 V Band gap reference voltage for DAC AVDD 3.135 3.3 3.465 V I/O power for DAC LPVDD 1.71 1.8 1.89 V Power forintegrated DVI/HDMI PLL macro LVDDR18D 1.71 1.8 1.89 V 1.8V power LVDDR33 3.135 3.3 3.465 V 3.3V power PLVDD12 1.14 1.2 1.26 V 1.2V power for system PLLs PLVDD18 1.71 1.8 1.89 V 1.8V power for system PLLs HTPVDD 1.71 1.8 1.89 V Power for HyperTransport interface PLL Note: Numbers in this table are to be qualified. (c) 2007 Advanced Micro Devices, Inc. Proprietary 41977 AMD RS690 Databook 3.04 5-1 Electrical Characteristics 5.1.2 DC Characteristics Table 5-2 DC Characteristics for 3.3V TTL Signals Pins Symbol ALLOW_LDTSTOP BMREQ# DACVSYNC DACSCL*, DACSDA DACHSYNC DDC_DATA GPIO[4:2] LDTSTOP# OSCIN I2C_DATA, I2C_CLK* POWERGOOD STRP_DATA SYSRESET# TESTMODE TMDS_HPD SUS_STAT# Description Minimum Maximum Unit VILdc DC voltage at PAD pin that will produce a stable low at the Y pin of macro - 0.6 V VIHdc DC voltage at PAD pin that will produce a stable high at the Y pin of macro 1.4 - V VOL Output low voltage - 0.35 V VOH Output high voltage 2.6 - V IOL Output low current at V=0.1V 2.3* - mA IOH Output high current at V=VDDR-0.1V 2.2* - mA Notes: Input pins. Output parameters in the table do not apply. Output pins. Input parameters in the table do not apply. * DACSCL and I2C_CLK have different values for IOL and IOH: DACSCL: IOL=14mA, IOH=5.8mA I2C_CLK: IOL=9.5mA, IOH=3.2mA Other numbers in this tables are applicable to the two signals. Table 5-3 DC Characteristics for 1.8V TTL Signals Pins Symbol DFT_GPIO[5:0] Description Minimum Maximum Unit VILdc DC voltage at PAD pin that will produce a stable low at the Y pin of macro - 0.69* V VIHdc DC voltage at PAD pin that will produce a stable high at the Y pin of macro 0.81* - V V VOL Output low voltage - 0.59 VOH Output high voltage 1.16 - V IOL Output low current at V=0.1V 1.52 - mA IOH Output high current at V=VDDR-0.1V 1.79 - mA * Note: Measured with edge rate of 1s at PAD pin. Table 5-4 DC Characteristics for the HTREFCLK Pad (66.66MHz) Symbol Description Minimum Typical Maximum Comments VIL Input Low Voltage - 0V 0.2V - VIH Input High Voltage 1.4V 1.8V - - - - 2.1V - VIMAX Maximum Input Voltage Table 5-5 DC Characteristics for the OSCIN Pad (14.3181818MHz) Symbol VIL VIH VIMAX Description Minimum Typical Maximum Comments Input Low Voltage - 0V 0.6V - Input High Voltage 2.5V 2.6V - - - - 3.3V - Maximum Input Voltage 41977 AMD RS690 Databook 3.04 5-2 (c) 2007 Advanced Micro Devices, Inc. Proprietary Electrical Characteristics Table 5-6 DC Characteristics for the Integrated DVI/HDMI (Not Applicable to the RS690C) Symbol Parameter Min Typical Max Unit -0.5 - 4.0 V Note VCM Common-mode Voltage on Signal Pair VH Single-ended High Level Output Voltage AVCC - 10 - AVCC + 10 mV 1 VL Single-ended Low Level Output Voltage AVCC - 600 - AVCC - 400 mV 1 400 - 600 mV - - 15%*2VSW - VSW Single-ended Output Swing VOS Differential Output Overshoot (Ringing) Differential Output Undershoot (Ringing) - - 25%*2VSW - IDDLP VUS Average Supply Current at LPVDD - 20.0 - mA 2 IDDLV Average Supply Current at LVDDR18 and LVDDR33 - 100.0 - mA 2 IPDLP Power Down Current at LPVDD - 10.0 - A 3 IPDLV Power Down Current at LVDDR18 and LVDDR33 - 10.0 - A 3 Notes: 1 AVCC stands for the termination supply voltage of the receiver, which is 3.3V +/- 5%. 2 Measured under typical conditions, at minimum differential clock frequency and maximum DVI/HDMI PLL VOC frequency. 3 Measured under typical conditions, based on typical leakage values. 4 Figure 5-1 below illustrates some of the DC Characteristics of the DVI/HDMI interface. Table 5-7 DC Characteristics for the TMDS Interface Multiplexed on the PCI Express(R) Gfx Lanes Symbol Parameter Minimum Typical Maximum Unit Note VCM Common-mode Voltage on Signal Pair -0.5 - 4.0 V VH Single-ended High Level Output Voltage AVCC - 10 - AVCC + 10 mV 1 VL Single-ended Low Level Output Voltage AVCC - 600 - AVCC - 400 mV 1 400 - 600 mV VSW Single-ended Output Swing VOS Differential Output Overshoot (Ringing) - - 15%*2VSW - VUS Differential Output Undershoot (Ringing) - - 25%*2VSW - Notes: 1 AVCC stands for the termination supply voltage of the receiver, which is 3.3V +/- 5%. 2 Figure 5-1 below illustrates some of the DC characteristics of the TMDS interface. (c) 2007 Advanced Micro Devices, Inc. Proprietary 41977 AMD RS690 Databook 3.04 5-3 RS690 Thermal Characteristics Single-ended W aveforms VHmax VHmin VSW VLmax VLmin VOS Differential W aveform VUS 2VSW VUS VOS Figure 5-1 DC Characteristics of the Integrated DVI/HDMI and the TMDS Interface 5.2 RS690 Thermal Characteristics This section describes some key thermal parameters of the RS690. For a detailed discussion on these parameters and other thermal design descriptions including package level thermal data and analysis, please consult the Thermal Design and Analysis Guidelines for the RS690 Product Family. 5.2.1 RS690 Thermal Limits Table 5-8 RS690 Thermal Limits Parameter Minimum Nominal Maximum Operating Case Temperature 0 -- 95 C 1 Absolute Rated Junction Temperature -- -- 125 C 2 Storage Temperature -40 -- 60 41977 AMD RS690 Databook 3.04 5-4 Unit Note C (c) 2007 Advanced Micro Devices, Inc. Proprietary Package Information Table 5-8 RS690 Thermal Limits (Continued) Parameter Minimum Nominal Maximum Unit 4 5 Ambient Temperature 0 -- 45 C Thermal Design Power -- 8 -- W Note Notes: 1 - The maximum operating case temperature is the die top-center temperature measured via a thermocouple based on the methodology given in the document Thermal Design and Analysis Guidelines for the RS690 Product Family (Chapter 10). This is the temperature at which the functionality of the chip is qualified. 2 - The maximum absolute rated junction temperature is the junction temperature at which the device can operate without causing damage to the ASIC. 3 - The ambient temperature is defined as the temperature of the local intake air at the inlet to the thermal management device. The maximum ambient temperature is dependent on the heat sink design, and the value given here is based on AMD's own heat sink solution for the RS690. Refer to Chapter 7 in Thermal Design and Analysis Guidelines for the RS690 Product Family for heatsink and thermal design guidelines. Refer to Chapter 5 for details of ambient conditions. 4 The Thermal Design Power (TDP) is defined as the worst-case power dissipation while running currently available applications at nominal voltages and at the maximum operating temperature. The TDP is intended only as a design reference. It is not an absolute maximum power under all conditions. The value shown here is a preliminary estimate only. 5.2.2 Thermal Diode Characteristics The RS690 has an on-die thermal diode, with its positive and negative terminals connected to the THERMALDIODE_P and THERMALDIODE_N pins respectively. Combined with a thermal sensor circuit, the diode temperature, and hence the ASIC temperature, can be derived from a differential voltage reading (V). The equation relating T to V is given below: x K x T x ln ( N ) V = -------------------------------------------q where: V = Difference of two base-to-emitter voltage readings, one using current = I and the other using current = N x I N = Ratio of the two thermal diode currents (=10 when using an ADI thermal sensor, e.g. ADM 1020, 1030) = Ideality factor of the diode K = Boltzman's Constant T = Temperature in Kelvin q = Electron charge The series resistance of the thermal diode (RT) must be taken into account as it introduces an error in the reading (for every 1.0 W, approximately 0.8oC is added to the reading). The sensor circuit should be calibrated to offset the RT induced, plus any other known fixed error. Measured values of diode ideality factor and series resistance for the diode circuit are defined in the Thermal Design and Analysis Guidelines for the RS690 Product Family. 5.3 Package Information 5.3.1 Physical Dimensions Figure 5-2 and Table 5-9 describe the physical dimensions of the RS690 package. Figure 5-3 shows the detailed ball arrangement for the RS690. (c) 2007 Advanced Micro Devices, Inc. Proprietary 41977 AMD RS690 Databook 3.04 5-5 Package Information 210210046508001_3-REV B Figure 5-2 RS690 Package Outline Table 5-9 RS690 465-Pin FCBGA Package Physical Dimensions Ref. Minimum(mm) Typical(mm) Maximum(mm) c 0.96 1.06 1.16 A 2.18 2.33 2.48 A1 0.30 0.40 0.50 A2 0.84 0.87 0.90 b 0.40 0.50 0.60 D1 20.80 21.00 21.20 D2 - 7.33 - E1 20.80 21.00 21.20 E2 - 6.93 - F1 - 19.20 - F2 - 19.20 - e1 - 0.80* - ddd - - 0.15 * Note: Only minimum pitch shown. 41977 AMD RS690 Databook 3.04 5-6 (c) 2007 Advanced Micro Devices, Inc. Proprietary Package Information Figure 5-3 RS690 Ball Arrangement 5.3.2 Pressure Specification To avoid damages to the ASIC (die or solder ball joint cracks) caused by improper mechanical assembly of the cooling device, follow the recommendations below: * It is recommended that the maximum pressure which is evenly applied across the contact area between the thermal management device and the die does not exceed 40 PSI. Note that a contact pressure of 30-40 PSI is adequate to secure the thermal management device and achieve the lowest thermal contact resistance with a temperature drop across the thermal interface material of no more than 3C. Also, the surface flatness of the metal spreader should be 0.001 inch/1 inch. * Pre-test the assembly fixture with a strain gauge to make sure that the flexing of the final assembled board and the pressure applying around the ASIC package will not exceed 600 micron strain under any circumstances. * Ensure that any distortion (bow or twist) of the board after SMT and cooling device assembly is within industry guidelines (IPC/EIA J-STD-001). For measurement method, refer to the industry approved technique described in the manual IPC-TM-650, section 2.4.22. (c) 2007 Advanced Micro Devices, Inc. Proprietary 41977 AMD RS690 Databook 3.04 5-7 Package Information 5.3.3 Board Solder Reflow Process Recommendations 5.3.3.1 Stencil Opening Size for Solderball Pads on PCB It is recommended that the stencil aperture for solderballs be kept at the same size as the land pads' except for the nine pads at each corner of the ASIC package, for which a maximum size of 400m is recommended (see Figure 5-4 below). This recommendation is based on AMD's sample land pattern design for the RS690, which is available from your AMD CSS representative. 400 m maximum for the nine corner balls' openings 400 m maximum for the nine corner balls' openings Stencil apperture for solderballs to be kept at the same size as the land pads', except for the corner balls. 400 m maximum for the nine corner balls' openings 400 m maximum for the nine corner balls' openings Figure 5-4 Stencil Opening Recommendations 5.3.3.2 Reflow Profile A reference reflow profile is given below. Please note the following when using RoHS/lead-free solder (SAC105/305/405 Tin-Silver-Cu): * The final reflow temperature profile will depend on the type of solder paste and chemistry of flux used in the SMT process. Modifications to the reference reflow profile may be required in order to accommodate the requirements of the other components in the application. * An oven with 10 heating zones or above is recommended. 41977 AMD RS690 Databook 3.04 5-8 (c) 2007 Advanced Micro Devices, Inc. Proprietary Package Information * To ensure that the reflow profile meets the target specification on both sides of the board, a different profile and oven recipe for the first and second reflow may be required. * Mechanical stiffening can be used to minimize board warpage during reflow. * * It is suggested to decrease temperature cooling rate to minimize board warpage. This reflow profile applies only to RoHS/lead-free (high temperature) soldering process and it should not be used for Eutectic solder packages. Damage may result if this condition is violated. Maximum 3 reflows are allowed on the same part. * Table 5-10 Recommended Board Solder Reflow Profile - RoHS/Lead-Free Solder Profiling Stage Temperature Process Range Overall Preheat Room temp to 220C 2 mins to 4 mins Soaking Time 130C to 170C Typical 60 - 80 seconds Liquidus 220C Typical 60 - 80 seconds Ramp Rate Ramp up and Cooling <2C / second Peak Max. 245C 235C +/-5C Temperature at peak within 5C 240C to 245C 10 - 30 seconds o Solder/Part Surface Temp. ( C ) Peak Temp. (235 oC+/-5% typ., 245 oC max.) 250 220 deg.C <2.0oC / Sec. 200 170 oC 150 Soaking Zone 130 oC 100 50 Soldering Zone 60 - 120 sec. max 60 - 80 sec. typical 45 - 90 sec. Max. 60 - 80 sec. typical <2.0o.C / Sec. Pre-heating Zone 2 min to 4 min Max. Heating Time Figure 5-5 RoHS/Lead-Free Solder (SAC305/405 Tin-Silver-Copper) Reflow Profile (c) 2007 Advanced Micro Devices, Inc. Proprietary 41977 AMD RS690 Databook 3.04 5-9 Package Information This page is left blank intentionally. 41977 AMD RS690 Databook 3.04 5-10 (c) 2007 Advanced Micro Devices, Inc. Proprietary Chapter 6 Power Management and ACPI 6.1 ACPI Power Management Implementation This chapter describes the support for ACPI power management provided by the RS690. The RS690 supports ACPI Revision 1.0b. The hardware, system BIOS, video BIOS, and drivers of the RS690 have all the logic required for meeting the power management specifications of PC2001, OnNow, and the Windows Logo Program and Device Requirements version 2.1. Table 6-1, "ACPI States Supported by the RS690," describes the ACPI states supported by the RS690. Table 6-2, "ACPI Signal Definitions," describes the signals used in the ACPI power management scheme of the RS690. Table 6-1 ACPI States Supported by the RS690 ACPI State Description Graphics States: D0 Full on, display active. D1 Display Off. RS690 power on. Configuration registers, state, and main memory contents retained. D3 Hot Similar to D1, with additional power saving and the graphics PLLs shut off. D3 Cold RS690 power off. Processor States: S0/C0: Working State Working State. The processor is executing instructions. S0/C1: Halt CPU Halt state. No instructions are executed. This state has the lowest latency on resume and contributes minimum power savings. S0/C2: Stop Grant Caches Snoopable Stop Grant or Cache Snoopable CPU state. This state offers more power savings but has a higher latency on resume than the C1 state. S0/C3: Stop Grant Caches Not Snoopable Stop Grant or Cache not Snoopable Sleep state. The CPU's caches maintain state but ignore any snoops. This state offers more power savings but has a higher latency on resume than the C1 and C2 states. System States: S1: Standby Powered On Suspend System is in Standby mode. This state has low wakeup latency on resume. OEM support of this state is optional. S3: Standby Suspend to RAM System is off but context is saved to RAM. OEM support of this state is optional. System memory is put into self-refresh. S4: Hibernate Suspend to Disk System is off but context is saved to disk. When the system transitions to the working state, the OS is resumed without a system re-boot. S5: Soft Off System is off. OS re-boots when the system transitions to the working state. G3: Mechanical Off Occurs when system power (AC or battery) is not present or is unable to keep the system in one of the other states. Note: Also supported are additional processor power states that are not part of the ACPI specification, e.g. C1E (C1 Enhanced) and C3 pop-up. Please refer to the SB600 Databook and the RS690 Register Programming Requirements for more information. Table 6-2 ACPI Signal Definitions Signal Name Description Source ALLOW_LDTSTOP Output to the Southbridge to allow LDTSTOP# assertion. Northbridge LDTSTOP# HyperTransportTM Technology Stop: Enables and disables links during system state transitions. Southbridge POWERON# Power on Power switch RESET# Global Reset Southbridge (c) 2007 Advanced Micro Devices, Inc. Proprietary 41977 AMD RS690 Databook 3.04 6-1 Power Management for the Graphics Controller 6.2 Power Management for the Graphics Controller The RS690 supports power management for the embedded graphics device as specified by the PCI Bus Power Management Interface Specification version 1.0, according to which the integrated graphics core of the RS690 qualifies as a device embedding a single function in the power management system. 6.2.1 PCI Function Power States There are up to four power states defined for each PCI function associated with each PCI device in the system. These power states are D0, D1, D2 and D3. D0 (on) consumes the most power while D3 (off) consumes the least. D1 and D2 enable levels of power savings in between those of D0 and D3. The concepts of these power states are universal for all functions in the system. When transitioned to a given power management state, the intended functional behavior is dependent upon the type (or class) of the function. 6.2.2 PCI Power Management Interface The four basic power management operations are: * * * * Capabilities Reporting Power Status Reporting Setting Power State System Wakeup All four of these capabilities are required for each power management function with the exception of wakeup event generation. This section describes the format of the registers in the PCI Configuration Space that are used by these power management operations. The Status and Capabilities Pointer (CAP_PTR) fields have been highlighted to indicate where the PCI Power Management features appear in the standard Configuration Space Header. Table 6-3 Standard PCI Configuration Space Header Type 0 Register Fields (32bits) MSB Device ID Offset LSB Vendor ID 00h (LSB) Status (with Bit 4 set to 1) Command 04h Class Code Revision ID 08h BIST Header Type Latency Timer Cache Line Size Base Address Registers 0Ch 10h 14h 18h 1Ch 20h 24h CardBus CIS Pointer 28h Subsystem ID Subsystem Vendor ID Expansion ROM Base Address 30h Reserved CAP_PTR Reserved Max_Lat 6.2.3 2Ch 34h 38h Min_Gnt Interrupt Pin Interrupt Line 3Ch Capabilities List Data Structure in PCI Configuration Space The Capabilities bit in the PCI Status register (offset = 06h) indicates whether or not the subject function implements a linked list of extended capabilities. Specifically, if bit 4 is set, the CAP_PTR register is implemented to give offset to the first item in the Capabilities link list. 41977 AMD RS690 Databook 3.04 6-2 (c) 2007 Advanced Micro Devices, Inc. Proprietary Power Management for the Graphics Controller Table 6-4 PCI Status Register Bits Read/ Write Default Value Description 15:05 -- -- Refer to PCI Local Bus Specification, Revision 2.2 04 1b Read Only This bit indicates whether this function implements a list of extended capabilities such as PCI power management. When set, this bit indicates the presence of Capabilities. A value of 0 implies that this function does not implement Capabilities. 03:00 0h Read Only Reserved The location of the Capabilities Pointer (CAP_PTR) depends on the PCI header type. See PCI specification Revision 2.2 for specification of CAP_PTR offsets. Table 6-5 Capabilities Pointer (CAP_PTR) Bits 07:00 Read/ Write Default Value 50h Read Only Description The CAP_PTR provides an offset in the PCI Configuration Space of the function to access the location of the first item in the Capabilities linked list. The CAP_PTR offset is DWORD aligned, so that the two least significant bits are always zeros. The graphics core implements extended capabilities of the AGP and Power Management. It needs to provide the standardized register interface. The first entry in the chain of descriptors has to be the PMI descriptor, as this functionality will be supported even if the RS690 operates as a PCI device. The Capabilities Identifier for Power Management is 01h. 6.2.4 Register Block Definition This section describes the PCI Power Management Interface registers. These registers are implemented inside the Host Interface (HI) as part of the configuration space of the device (RS690). Table 6-6 Power Management Register Block Register Fields Offset Capabilities ID 00h Next Item Pointer 01h Power Management Capabilities (PMC) 02h Power Management Control/Status Register (PMCSR) 04h Reserved 06h The first 16 bits (Capabilities ID [offset = 0] and Next Item Pointer [offset = 1]) are used for the linked list infrastructure. The next 32 bits (PMC [offset = 2] and PMCSR registers [offset = 4]) are required for compliance with this specification. As with all PCI configuration registers, these registers may be accessed as bytes, 16-bit words, or 32-bit DWORDs. All of the write operations to the reserved registers must be treated as no-ops. This implies that the access must be completed normally on the bus and the data should be discarded. Read accesses to the reserved or the unimplemented registers must be completed normally and a data value of 0000h should be returned. (c) 2007 Advanced Micro Devices, Inc. Proprietary 41977 AMD RS690 Databook 3.04 6-3 Power Management for the Graphics Controller Table 6-7 Power Management Control/Status Register (PMCSR) Field Name Bits Power State 1:0 Default (Reset) 00b Description This field describes the power state of the graphics core. States Power State 15:2 00h Function 00 = D0 Normal operation, no power savings enabled 01 = D1 Sleeping state 1: Display is off Host access to DRAM is allowed 10 = D2 Sleeping state 2 Display is off. All engines are off. Graphics core does not respond to host accesses to the frame buffer. 11 = D3 Everything, except Host Interface, is turned off. These Read Only bits will return the clock status of each clock tree, generated inside the clock block. The offset for each register is listed as an offset from the beginning of the linked list item that is determined either from the CAP_PTR (if Power Management is the first item in the list) or the NEXT_ITEM_PTR of the previous item in the list. 6.2.5 Capability Identifier: Cap_ID (Offset = 0) The Capability Identifier, when read by system software as 01h, indicates that the data structure currently being pointed to is the PCI Power Management data structure. Each function of a PCI device may have only one item in its capability list with Cap_ID set to 01h. Table 6-8 Capability Identifier (Cap_ID) Bits 7:0 Default Value 01h Read/ Write Read Only Description This field, when set to 01h, identifies the linked list item as being the PCI Power Management registers Figure 6-1, `Linked List for Capabilities," shows the implementation of the capabilities list. The CAP_PTR gives the location of the first item in the list. PCI Power Management registers have been stated as example in this list (although the capabilities can be in any order). * * * The first byte of each entry is required to be the ID of that capability. The PCI Power Management capability has an ID of 01h. The next byte is a pointer giving an absolute offset in the functions PCI Configuration Space to the next item in the list and must be DWORD aligned. If there are no more entries in the list, the NEXT_ITEM_PTR must be set to 0 to indicate an end of the linked list. Each capability can then have registers following the NEXT_ITEM_PTR. The definition of these registers (including layout, size, and bit definitions) is specific to each capability. The PCI Power Management Register Block is defined in Figure 6-1, `Linked List for Capabilities," below. 41977 AMD RS690 Databook 3.04 6-4 (c) 2007 Advanced Micro Devices, Inc. Proprietary Power Management for the Graphics Controller PCI Configuration Header Offset 34h Cap_Ptr = 50h 8 bits Offset 50h 5Ch 02 AGP Capability Offset 5Ch 00h 01 PM Registers Figure 6-1 Linked List for Capabilities 6.2.6 Next Item Pointer The Next Item Pointer register describes the location of the next item in the capability list of the function. The value given is an offset in the PCI Configuration Space of that function. This register must be set to 00h if the function does not implement any other capabilities defined by the PCI Specifications for inclusion in the capabilities list, or if power management is the last item in the list. Table 6-9 Next Item Pointer (NEXT_ITEM_PTR) 7:0 6.2.7 Read/ Write Default Value Bits 80h Read Only Description This field provides an offset in the PCI Configuration Space of the function pointing to the location of next item in the capability list of the function. For Power Management of the RS690, this pointer is set to 80h and it points to the next capability pointer of the MSI structure. PMC - Power Management Capabilities (Offset = 2) The Power Management Capabilities register is a 16-bit Read Only register that provides information on the capabilities of the function related to power management. The information in this register is generally static and is known at design time. Table 6-10 Power Management Capabilities - PMC Bits Default Value Read/ Write Description 15:11 00111b Read Only This 5-bit field indicates the power states in which the function may assert PME#. A value of 0b for any bit indicates that the function is not capable of asserting the PME# signal while in that power state. bit(11) XXXX1b - PME# can be asserted from D0. bit(12) XXX1Xb - PME# can be asserted from D1. bit(13) XX1XXb - PME# can be asserted from D2. bit(14) X0XXXb - PME# cannot be asserted from D3hot. bit(15) 0XXXXb - PME# cannot be asserted from D3cold. 10 1b Read Only RS690 supports D2. (c) 2007 Advanced Micro Devices, Inc. Proprietary 41977 AMD RS690 Databook 3.04 6-5 Power Management for the Graphics Controller Table 6-10 Power Management Capabilities - PMC Bits Default Value Read/ Write (Continued) Description 9 1b Read Only RS690 supports D1. 8:6 000b Read Only Reserved 5 1b Read Only The Device Specific Initialization bit indicates whether special initialization of this function is required (beyond the standard PCI configuration header) before the generic class device driver is able to use it. The RS690 requires device specific initialization after Reset; this field must therefore return a value 1 to the system. 4 0b Read Only Reserved 3 0b Read Only Reserved 2:0 001b Read Only A value of 001b indicates that this function complies with Revision 1.0 of the PCI Power Management Interface Specification. 41977 AMD RS690 Databook 3.04 6-6 (c) 2007 Advanced Micro Devices, Inc. Proprietary Chapter 7 Testability 7.1 Test Capability Features The RS690 has integrated test modes and capabilities. These test features cover both the ASIC and board level testing. The ASIC tests provide a very high fault coverage and low DPM (Defect Per Million) ratio of the part. The board level tests modes can be used for motherboard manufacturing and debug purposes. The following are the test modes of the RS690: * Full scan implementation on the digital core logic that provides about 99% fault coverage through ATPG (Automatic Test Pattern Generation Vectors). * Dedicated test logic for the on-chip custom memory macros to provide complete coverage on these modules. * Improved access to the analog modules and PLLs in the RS690 to allow full evaluation and characterization of these modules. * A JTAG test mode (which is not entirely compliant to the IEEE 1149.1 standard) to allow board level testing of neighboring devices. * An XOR TREE test mode on all the digital I/Os to allow for proper soldering verification at the board level. * A VOH/VOL test mode on all digital I/Os to allow for proper verification of output high and output low voltages at the board level. These test modes can be accessed through the settings on the instruction register of the JTAG circuitry. 7.2 Test Interface Table 7-1 Pins on the Test Interface Pin Name TESTMODE Ball number Type C3 I Description IEEE 1149.1 test port reset DDC_DATA B3 I TMS: Test Mode Select (IEEE 1149.1 test mode select) I2C_DATA B4 I TDI: Test Mode Data In (IEEE 1149.1 data in) I2C_CLK A2 I TCLK: Test Mode Clock (IEEE 1149.1 clock) TMDS_HPD C14 O TDO: Test Mode Data Out (IEEE 1149.1 data out) POWERGOOD C11 I I/O Reset OSCIN B11 I I/O Test Clock 7.3 XOR Tree 7.3.1 Brief Description of an XOR Tree An example of a generic XOR tree is shown in the Figure 7-1 below. (c) 2007 Advanced Micro Devices, Inc. Proprietary 41977 AMD RS690 Databook 3.04 7-1 XOR Tree XOR Start Signal 1 2 A 3 4 5 6 Figure 7-1 An Example of a Generic XOR Tree Pin A is assigned to the output direction, and pins 1 through 6 are assigned to the input direction. It can be seen that after all pins 1 to 6 are assigned to logic 0 or 1, a logic change in any one of these pins will toggle the output pin A. The following is the truth table for the XOR tree shown in Figure 7-1 The XOR start signal is assumed to be logic 1. Table 7-2 Example of an XOR Tree 7.3.2 Test Vector number Input Pin 1 Input Pin 2 Input Pin 3 Input Pin 4 Input Pin 5 Input Pin 6 Output Pin A 1 0 0 0 0 0 0 1 2 1 0 0 0 0 0 0 3 1 1 0 0 0 0 1 4 1 1 1 0 0 0 0 5 1 1 1 1 0 0 1 6 1 1 1 1 1 0 0 7 1 1 1 1 1 1 1 Description of the XOR Tree for the RS690 The XOR start signal is applied at the TDI pin of the JTAG circuitry and the output of the XOR tree is obtained at the TDO pin. Refer to Section 7.3.4 for the list of the signals included on the XOR tree. There is no specific connection order to the signals on the tree. A toggle of any of these balls in the XOR tree will cause the output to toggle. 7.3.3 XOR Tree Activation The RS690 chip enters the XOR tree test mode by means of the JTAG. First, the 8-bit instruction register of the JTAG is loaded with the XOR instruction ("00001000"). This instruction assigns the input direction to all the pins except pin TDO, which is assigned the output direction to serve as the output of the XOR tree. After loading, the JTAG is taken to the Run-Test state for completion of the XOR tree initialization. Note: 10MHz clock frequency is recommended for the XOR TREE test mode. 7.3.4 XOR Chain for the RS690 When the XOR tree is activated, any pin on the XOR tree must be either pulled down or pulled up to the I/O voltage of the pin. Only pins that are not on the XOR tree can be left floating. When differential signal pairs are listed as single entries on the XOR tree, opposite input values should be applied to the two signals in each pair (e.g., for entry no. 13 on the tree, when "1" is applied to HT_RXCAD15P, "0" should be applied to HT_RXCAD15N). 41977 AMD RS690 Databook 3.04 7-2 (c) 2007 Advanced Micro Devices, Inc. Proprietary XOR Tree Table 7-3 RS690 XOR Tree No. Pin Name Ball Ref. No. Pin Name Ball Ref. 1 GPIO2 G12 36 SB_RX3N/P AB11/AA11 2 GPIO4 F12 37 SB_RX2N/P W12/W11 3 GPIO3 E12 38 SB_RX1N/P AA12/AB12 4 DACVSYNC C6 39 SB_RX0N/P W15/W14 5 DACHSYNC A5 40 GFX_RX15N/P AB6/AB7 6 DACSCL B6 41 GFX_RX14N/P W9/V9 7 DFT_GPIO0 D6 42 GFX_RX13N/P Y5/Y4 8 DFT_GPIO1 D7 43 GFX_RX12N/P W5/W4 9 DFT_GPIO2 C8 44 GFX_RX11N/P U5/U4 10 DFT_GPIO3 C7 45 GFX_RX10N/P R8/R7 11 DFT_GPIO4 B8 46 GFX_RX9N/P R5/R4 12 DFT_GPIO5 A8 47 GFX_RX8N/P P5/P4 13 HT_RXCAD15N/P R18/R19 48 GFX_RX7N/P P7/P8 14 HT_RXCAD14N/P R22/R21 49 GFX_RX6N/P M5/M4 15 HT_RXCAD13N/P U21/U22 50 GFX_RX5N/P M7/M8 16 HT_RXCAD12N/P U19/U18 51 GFX_RX4N/P L5/L4 17 HT_RXCAD11N/P W20/W19 52 GFX_RX3N/P L7/L8 18 HT_RXCAD10N/P AB22/AC21 53 GFX_RX2N/P J5/J4 19 HT_RXCAD9N/P AA20/AB20 54 GFX_RX1N/P J7/J8 20 HT_RXCAD8N/P Y19/AA19 55 GFX_RX0N/P G4/G5 21 HT_RXCAD7N/P R25/T24 56 NC/NC AD17/AE17 22 HT_RXCAD6N/P U24/U25 57 NC AE21 23 HT_RXCAD5N/P U23/V23 58 NC AD18 24 HT_RXCAD4N/P V25/V24 59 NC AC17 25 HT_RXCAD3N/P AA24/AA25 60 NC AE15 26 HT_RXCAD2N/P AA23/AB23 61 NC AC13 27 HT_RXCAD1N/P AB25/AB24 62 NC AE13 28 HT_RXCAD0N/P AC25/AC24 63 NC AD13 29 HT_RXCTLN/P P25/P24 30 HT_RXCLK1N/P W22/W21 31 HT_RXCLK0N/P W25/Y24 32 GPP_RX3N/P AA9/AB9 33 GPP_RX2N/P AA7/Y7 34 GPP_RX1N/P AE20/AD20 35 GPP_RX0N/P AE16/AD16 (c) 2007 Advanced Micro Devices, Inc. Proprietary 41977 AMD RS690 Databook 3.04 7-3 VOH/VOL Test 7.4 VOH/VOL Test 7.4.1 Brief Description of a VOH/VOL Tree The VOH/VOL logic gives signal output on I/Os when test patterns are applied through the TEST_ODD and TEST_EVEN inputs. Sample of a generic VOH/VOL tree is shown in the Figure 7-2 below. TEST_ODD TEST_EVEN VOH/VOL mode 1 2 3 4 5 6 Figure 7-2 Sample of a Generic VOH/VOL Tree The following is the truth table for the above VOH/VOL tree. Table 7-4 Truth Table for the VOH/VOL Tree Outputs Test Vector Number TEST_ODD TEST_EVEN Input Input Output Pin 1 Output Pin 2 Output Pin 3 Output Pin 4 Output Pin 5 Output Pin 6 1 0 0 0 0 0 0 0 0 2 0 1 0 1 0 1 0 1 3 1 0 1 0 1 0 1 0 4 1 1 1 1 1 1 1 1 Refer to Table 7.4.3, "VOH/VOL Pin List," on page 7-5 for the list of pins that are on the VOH/VOL tree. 7.4.2 VOH/VOL Tree Activation To activate the VOH/VOL tree and run a VOH/VOL test, perform the sequence below: 1. Supply a clock at any speed (same or faster than test pattern data rate) to the OSCIN pin as the I/O test clock source. 2. Set POWERGOOD to 0. 3. Set TESTMODE to 1. 4. Set DACSDA to 0. 41977 AMD RS690 Databook 3.04 7-4 (c) 2007 Advanced Micro Devices, Inc. Proprietary VOH/VOL Test 5. Load JTAG instruction register with the instruction 0110 0011. 6. Load JTAG instruction register with the instruction 0010 0111. 7. Set POWERGOOD to 1. 8. Load JTAG instruction register with the instruction 1001 1001. 9. Run test by loading JTAG data register with data 0000 0000 0000 00xy, where bit x is the input value for TEST_ODD and bit y that for TEST_EVEN (see Table 7-4 above). 10. To end test, load JTAG instruction register with the instruction 0101 1101. 7.4.3 VOH/VOL Pin List Table 7-5 below shows the RS690 VOH/VOL tree. There is no specific order of connection. Under the Control column, an "ODD" or "EVEN" indicates that the logical output of the pin is same as the "TEST_ODD" or "TEST_EVEN" input respectively. When a differential pair appear in the table as a single entry, the output of the positive ("P") pin is indicated in the Control column (see last paragraph for explanations), and the output of the negative pin ("N") will be of the opposite value. E.g., for entry no. 1 on the tree, when TEST_EVEN is 1, HT_TXCAD15P will give a value of 1 and HT_TXCAD15N will give a value of 0. Table 7-5 RS690 VOH/VOL Tree No. Pin Name Ball Ref. Control No. Pin Name Ball Ref. Control 1 HT_TXCAD15P/N P21/P22 EVEN 21 GPIO2 G12 EVEN 2 HT_TXCAD14P/N P18/P19 ODD 22 GPIO4 F12 ODD 3 HT_TXCAD13P/N M22/M21 EVEN 23 GPIO3 E12 EVEN 4 HT_TXCAD12P/N M18/M19 ODD 24 DFT_GPIO5 A8 ODD 5 HT_TXCAD11P/N L18/L19 EVEN 25 DFT_GPIO4 B8 EVEN 6 HT_TXCAD10P/N G22/G21 ODD 26 DFT_GPIO3 C7 ODD 7 HT_TXCAD9P/N J20/J21 EVEN 27 DFT_GPIO2 C8 EVEN 8 HT_TXCAD8P/N F21/F22 ODD 28 DFT_GPIO1 D7 ODD 9 HT_TXCTLP/N N23/P23 EVEN 29 DFT_GPIO0 D6 EVEN 10 HT_TXCAD7P/N N24/N25 ODD 30 SB_TX3P/N AD7/AE7 ODD 11 HT_TXCAD6P/N L25/M24 EVEN 31 SB_TX2P/N AD8/AE8 EVEN 12 HT_TXCAD5P/N K25/K24 ODD 32 SB_TX1P/N AC8/AD9 ODD 13 HT_TXCAD4P/N J23/K23 EVEN 33 SB_TX0P/N AE9/AD10 EVEN 14 HT_TXCAD3P/N G25/H24 ODD 34 GPP_TX3P/N AD5/AD6 ODD 15 HT_TXCAD2P/N F25/F24 EVEN 35 GPP_TX2P/N AD4/AE5 EVEN 16 HT_TXCAD1P/N E23/F23 ODD 36 GPP_TX1P/N AD19/AE19 ODD 17 HT_TXCAD0P/N E24/E25 EVEN 37 GPP_TX0P/N AD14/AD15 EVEN 18 DACSCL B6 ODD 38 GFX_TX15P/N AE3/AE4 ODD 19 DACVSYNC C6 EVEN 39 GFX_TX14P/N AB1/AC1 EVEN 20 DACHSYNC A5 ODD 40 GFX_TX13P/N AA2/AB2 ODD (c) 2007 Advanced Micro Devices, Inc. Proprietary 41977 AMD RS690 Databook 3.04 7-5 VOH/VOL Test No. Pin Name Ball Ref. Control 41 GFX_TX12P/N Y2/AA1 EVEN 42 GFX_TX11P/N W1/W2 ODD 43 GFX_TX10P/N V3/W3 EVEN 44 GFX_TX9P/N V2/V1 ODD 45 GFX_TX8P/N T2/U1 EVEN 46 GFX_TX7P/N R1/R2 ODD 47 GFX_TX6P/N P3/R3 EVEN 48 GFX_TX5P/N P2/P1 ODD 49 GFX_TX4P/N N2/N1 EVEN 50 GFX_TX3P/N L1/L2 ODD 51 GFX_TX2P/N K3/L3 EVEN 52 GFX_TX1P/N K2/K1 ODD 53 GFX_TX0P/N J1/H2 EVEN 54 NC AE17 EVEN 55 NC AD17 ODD 56 NC AE21 EVEN 57 NC AD18 ODD 58 NC AC17 EVEN 59 NC AE15 ODD 60 NC AC13 ODD 61 NC AE13 ODD 62 NC AD13 ODD 41977 AMD RS690 Databook 3.04 7-6 (c) 2007 Advanced Micro Devices, Inc. Proprietary Appendix A Pin Listings This appendix contains pin listings for the RS690 sorted in different ways. To go to the listing of interest, use the linked cross-references below: "RS690 Pin List Sorted by Ball Reference" on page A-2 "RS690 Pin List Sorted by Pin Name" on page A-6 (c) 2007 Advanced Micro Devices, Inc. Proprietary 41977 AMD RS690 Databook 3.04 A-1 A.1 RS690 Pin List Sorted by Ball Reference Table A-1 RS690 Pin List Sorted by Ball Reference Ball Ref. Pin Name A1 VSSA A10 PLLVDD18 A11 PLLVDD12 A12 LVDDR18D A13 TXOUT_L1N A14 LVSSR A15 TXOUT_U0P A16 LVSSR A17 TXOUT_U2N A18 TXOUT_U3P A19 VDD_CORE A2 I2C_CLK A20 AVDDDI A21 AVDDQ A22 AVSSQ A23 VSS A24 HT_RXCALP A25 VSS A3 STRP_DATA A4 VDD_CORE A5 DACHSYNC A6 DACSDA A7 VDD_CORE A8 DFT_GPIO5 A9 VDD_CORE AA1 GFX_TX12N AA11 SB_RX3P AA12 SB_RX1N AA14 NC AA15 THERMALDIODE_P AA17 VDD_HT AA19 HT_RXCAD8P AA2 GFX_TX13P AA20 HT_RXCAD9N AA23 HT_RXCAD2N AA24 HT_RXCAD3N AA25 HT_RXCAD3P AA3 VSSA AA7 GPP_RX2N AA9 GPP_RX3N AB1 GFX_TX14P AB11 SB_RX3N AB12 SB_RX1P AB14 NC 41977 AMD RS690 Databook 3.04 A-2 Ball Ref. Pin Name Ball Ref. Pin Name AB15 THERMALDIODE_N AD14 GPP_TX0P AB17 VDD_HT AD15 GPP_TX0N AB19 VDD_HT AD16 GPP_RX0P AB2 GFX_TX13N AD17 DEBUG13 AB20 HT_RXCAD9P AD18 DEBUG10 AB22 HT_RXCAD10N AD19 GPP_TX1P AB23 HT_RXCAD2P AD2 VDDA_12 AB24 HT_RXCAD1P AD20 GPP_RX1P AB25 HT_RXCAD1N AD21 VDD_HT AB3 VDDA_12 AD22 VDD_HT AB4 VDDA_12 AD23 VDD_HT AB6 GFX_RX15N AD24 VDD_HT AB7 GFX_RX15P AD25 VSS AB9 GPP_RX3P AD3 VSSA AC1 GFX_TX14N AD4 GPP_TX2P AC10 VSSA AD5 GPP_TX3P AC11 VDDA_12_PKG AD6 GPP_TX3N AC12 VDDR AD7 SB_TX3P AC13 DEBUG2 AD8 SB_TX2P AC14 VSS AD9 SB_TX1N AC15 VSS AE1 VDDA_12 AC16 VSS AE10 VSSA AC17 DEBUG9 AE11 PCE_CALRN AC18 VDD_HT AE12 VDDR AC19 VDD_HT AE13 DEBUG1 AC2 VSSA AE14 VSS AC20 VDD_HT AE15 DEBUG6 AC21 HT_RXCAD10P AE16 GPP_RX0N AC22 VSS AE17 DEBUG14 AC23 VSS AE18 VSS AC24 HT_RXCAD0P AE19 GPP_TX1N AC25 HT_RXCAD0N AE2 VDDA_12 AC3 VDDA_12 AE20 GPP_RX1N AC4 VSSA AE21 DEBUG15 AC5 VSSA AE22 VSS AC6 VSSA AE23 VDD_HT AC7 VSSA AE24 VDD_HT AC8 SB_TX1P AE25 VDD_HT AC9 VSSA AE3 GFX_TX15P AD1 VSSA AE4 GFX_TX15N AD10 SB_TX0N AE5 GPP_TX2N AD11 PCE_CALRP AE6 VSSA AD12 VDDR AE7 SB_TX3N AD13 DEBUG0 AE8 SB_TX2N (c) 2007 Advanced Micro Devices, Inc. Proprietary Ball Ref. Pin Name Ball Ref. Pin Name Ball Ref. Pin Name AE9 SB_TX0P B1 VDDA_12 C5 LDTSTOP# F21 HT_TXCAD8P C6 DACVSYNC F22 HT_TXCAD8N B10 B11 PLLVSS C7 DFT_GPIO3 F23 HT_TXCAD1N OSCIN C8 DFT_GPIO2 F24 HT_TXCAD2N B12 LVDDR18D B13 TXOUT_L1P C9 VDD_CORE F25 HT_TXCAD2P D1 VDDA_12 F3 VSSA B14 B15 TXOUT_L0P D11 VDDR3 F4 VDDA_12 TXOUT_L0N D12 LVSSR F7 VDD_PLL B16 TXOUT_U0N D14 LPVDD F9 VSS_PLL B17 TXOUT_U2P D15 TXCLK_LN G1 SB_CLKP B18 TXOUT_U3N D17 TXOUT_L3P G11 VSS B19 VDD_CORE D19 COMP G12 GPIO2 B2 BMREQ# D2 VDDA_12 G14 TXOUT_L2N B20 AVSSDI D20 VDD_CORE G15 TXCLK_UN B21 RSET D22 VDD_HT_PKG G17 AVSSN B22 AVDD D23 VSS G19 BLUE B23 HTREFCLK D24 HT_TXCALN G2 SB_CLKN B24 HTPVDD D25 VSS G20 VDD_CORE B25 HTPVSS D3 VDDA_12 G21 HT_TXCAD10N B3 DDC_DATA D4 VSS G22 HT_TXCAD10P B4 I2C_DATA D6 DFT_GPIO0 G23 VSS B5 ALLOW_LDTSTOP D7 DFT_GPIO1 G24 VSS B6 DACSCL D9 VDD_CORE G25 HT_TXCAD3P B7 VSS E1 GFX_CLKN G3 VSSA B8 DFT_GPIO4 E11 VDDR3 G4 GFX_RX0N B9 VDD_CORE E12 GPIO3 G5 GFX_RX0P C1 VDDA_12 E14 LPVSS G6 VSSA C10 SYSRESET# E15 TXCLK_LP G7 VDDA_12 C11 POWERGOOD E17 TXOUT_L3N G9 VSS_PLL C12 LVDDR33 E19 RED H1 VSSA C13 LVDDR33 E2 VDDA_12 H11 VDD_CORE C14 TMDS_HPD E23 HT_TXCAD1P H12 VSS C15 LVSSR E24 HT_TXCAD0P H14 TXOUT_L2P C16 LVSSR E25 HT_TXCAD0N H15 TXCLK_UP C17 TXOUT_U1P E3 VDDA_12 H17 AVSSN C18 TXOUT_U1N E6 VDDA_12 H2 GFX_TX0N C19 LVSSR E7 VDD_PLL H23 VSS C2 TVCLKIN E9 VSS H24 HT_TXCAD3N C20 Y F1 VSSA H25 VSS C21 C F11 VSS H3 VSSA C22 AVDD F12 GPIO4 J1 GFX_TX0P C23 HTTSTCLK F14 LVSSR J11 VDD_CORE C24 HT_RXCALN F15 LVSSR J12 VSS C25 HT_TXCALP F17 VSS J14 VDD_18 C3 TESTMODE F19 GREEN J15 VDD_18 C4 VSS F2 GFX_CLKP J19 VDD_CORE (c) 2007 Advanced Micro Devices, Inc. Proprietary 41977 AMD RS690 Databook 3.04 A-3 Ball Ref. Pin Name Ball Ref. Pin Name Ball Ref. Pin Name J2 VSSA M15 VSS P5 GFX_RX8N J20 HT_TXCAD9P M17 VSS P6 VSSA J21 HT_TXCAD9N M18 HT_TXCAD12P P7 GFX_RX7N J22 VSS M19 HT_TXCAD12N P8 GFX_RX7P J23 HT_TXCAD4P M2 VSSA P9 VSSA J24 HT_TXCLK0P M20 VSS R1 GFX_TX7P J25 HT_TXCLK0N M21 HT_TXCAD13N R11 VDD_CORE J3 VSSA M22 HT_TXCAD13P R12 VSS J4 GFX_RX2P M23 VSS R13 VDD_CORE J5 GFX_RX2N M24 HT_TXCAD6N R14 VSS J6 VSSA M25 VSS R15 VDD_CORE J7 GFX_RX1N M3 VSSA R17 VSS J8 GFX_RX1P M4 GFX_RX6P R18 HT_RXCAD15N K1 GFX_TX1N M5 GFX_RX6N R19 HT_RXCAD15P K2 GFX_TX1P M6 VSSA R2 GFX_TX7N K23 HT_TXCAD4N M7 GFX_RX5N R20 VSS K24 HT_TXCAD5N M8 GFX_RX5P R21 HT_RXCAD14P K25 HT_TXCAD5P M9 VDDA_12 R22 HT_RXCAD14N K3 GFX_TX2P N1 GFX_TX4N R23 VSS L1 GFX_TX3P N11 VDD_CORE R24 VSS L11 VDD_CORE N12 VSS R25 HT_RXCAD7N L12 VSS N13 VDD_CORE R3 GFX_TX6N L13 VDD_CORE N14 VSS R4 GFX_RX9P L14 VSS N15 VDD_CORE R5 GFX_RX9N L15 VDD_CORE N2 GFX_TX4P R6 VSSA L17 VDD_CORE N23 HT_TXCTLP R7 GFX_RX10P L18 HT_TXCAD11P N24 HT_TXCAD7P R8 GFX_RX10N L19 HT_TXCAD11N N25 HT_TXCAD7N R9 VSSA L2 GFX_TX3N N3 VSSA T1 VSSA L20 VSS P1 GFX_TX5N T2 GFX_TX8P L21 HT_TXCLK1P P11 VSS T23 VSS L22 HT_TXCLK1N P12 VDD_CORE T24 HT_RXCAD7P L23 VSS P13 VSS T25 VSS L24 VSS P14 VDD_CORE T3 VSSA L25 HT_TXCAD6P P15 VSS U1 GFX_TX8N L3 GFX_TX2N P17 VDD_CORE U11 VDD_CORE L4 GFX_RX4P P18 HT_TXCAD14P U12 VDD_CORE L5 GFX_RX4N P19 HT_TXCAD14N U14 VDD_CORE L6 VSSA P2 GFX_TX5P U15 VDD_CORE L7 GFX_RX3N P20 VSS U18 HT_RXCAD12P L8 GFX_RX3P P21 HT_TXCAD15P U19 HT_RXCAD12N L9 VDDA_12 P22 HT_TXCAD15N U2 VSSA M1 VDDA_12_PKG P23 HT_TXCTLN U20 VSS M11 VSS P24 HT_RXCTLP U21 HT_RXCAD13N M12 VDD_CORE P25 HT_RXCTLN U22 HT_RXCAD13P M13 VSS P3 GFX_TX6P U23 HT_RXCAD5N M14 VDD_CORE P4 GFX_RX8P U24 HT_RXCAD6N 41977 AMD RS690 Databook 3.04 A-4 (c) 2007 Advanced Micro Devices, Inc. Proprietary Ball Ref. Pin Name Ball Ref. Pin Name U25 HT_RXCAD6P Y23 VSS U3 VSSA Y24 HT_RXCLK0P U4 GFX_RX11P Y25 VSS U5 GFX_RX11N Y3 VSSA U6 VSSA Y4 GFX_RX13P U7 VDDA_12 Y5 GFX_RX13N V1 GFX_TX9N Y7 GPP_RX2P V11 VSSA Y9 VSSA V12 VSSA V14 VSSA V15 VSSA V2 GFX_TX9P V23 HT_RXCAD5P V24 HT_RXCAD4P V25 HT_RXCAD4N V3 GFX_TX10P V9 GFX_RX14P W1 GFX_TX11P W11 SB_RX2P W12 SB_RX2N W14 SB_RX0P W15 SB_RX0N W17 VDD_HT W19 HT_RXCAD11P W2 GFX_TX11N W20 HT_RXCAD11N W21 HT_RXCLK1P W22 HT_RXCLK1N W23 VSS W24 VSS W25 HT_RXCLK0N W3 GFX_TX10N W4 GFX_RX12P W5 GFX_RX12N W6 VSSA W7 VDDA_12 W9 GFX_RX14N Y1 VSSA Y11 VSSA Y12 VSSA Y14 VSSA Y15 VSSA Y17 VDD_HT Y19 HT_RXCAD8N Y2 GFX_TX12P Y22 VSS (c) 2007 Advanced Micro Devices, Inc. Proprietary 41977 AMD RS690 Databook 3.04 A-5 A.2 RS690 Pin List Sorted by Pin Name Table A-2 RS690 Pin List Sorted by Pin Name Pin Name Ball Ref. Pin Name Ball Ref. Pin Name Ball Ref. ALLOW_LDTSTOP B5 GFX_RX13P Y4 GFX_TX4P N2 AVDD B22 GFX_RX14N W9 GFX_TX5N P1 AVDD C22 GFX_RX14P V9 GFX_TX5P P2 AVDDDI A20 GFX_RX15N AB6 GFX_TX6N R3 AVDDQ A21 GFX_RX15P AB7 GFX_TX6P P3 AVSSDI B20 GFX_RX1N J7 GFX_TX7N R2 AVSSN G17 GFX_RX1P J8 GFX_TX7P R1 AVSSN H17 GFX_RX2N J5 GFX_TX8N U1 AVSSQ A22 GFX_RX2P J4 GFX_TX8P T2 BLUE G19 GFX_RX3N L7 GFX_TX9N V1 BMREQ# B2 GFX_RX3P L8 GFX_TX9P V2 C C21 GFX_RX4N L5 GPIO2 G12 COMP D19 GFX_RX4P L4 GPIO3 E12 DACHSYNC A5 GFX_RX5N M7 GPIO4 F12 DACSCL B6 GFX_RX5P M8 GPP_RX0N AE16 DACSDA A6 GFX_RX6N M5 GPP_RX0P AD16 DACVSYNC C6 GFX_RX6P M4 GPP_RX1N AE20 DDC_DATA B3 GFX_RX7N P7 GPP_RX1P AD20 DEBUG0 AD13 GFX_RX7P P8 GPP_RX2N AA7 DEBUG1 AE13 GFX_RX8N P5 GPP_RX2P Y7 DEBUG10 AD18 GFX_RX8P P4 GPP_RX3N AA9 DEBUG13 AD17 GFX_RX9N R5 GPP_RX3P AB9 DEBUG14 AE17 GFX_RX9P R4 GPP_TX0N AD15 DEBUG15 AE21 GFX_TX0N H2 GPP_TX0P AD14 DEBUG2 AC13 GFX_TX0P J1 GPP_TX1N AE19 DEBUG6 AE15 GFX_TX10N W3 GPP_TX1P AD19 DEBUG9 AC17 GFX_TX10P V3 GPP_TX2N AE5 DFT_GPIO0 D6 GFX_TX11N W2 GPP_TX2P AD4 DFT_GPIO1 D7 GFX_TX11P W1 GPP_TX3N AD6 DFT_GPIO2 C8 GFX_TX12N AA1 GPP_TX3P AD5 DFT_GPIO3 C7 GFX_TX12P Y2 GREEN F19 DFT_GPIO4 B8 GFX_TX13N AB2 HT_RXCAD0N AC25 DFT_GPIO5 A8 GFX_TX13P AA2 HT_RXCAD0P AC24 GFX_CLKN E1 GFX_TX14N AC1 HT_RXCAD10N AB22 GFX_CLKP F2 GFX_TX14P AB1 HT_RXCAD10P AC21 GFX_RX0N G4 GFX_TX15N AE4 HT_RXCAD11N W20 GFX_RX0P G5 GFX_TX15P AE3 HT_RXCAD11P W19 GFX_RX10N R8 GFX_TX1N K1 HT_RXCAD12N U19 GFX_RX10P R7 GFX_TX1P K2 HT_RXCAD12P U18 GFX_RX11N U5 GFX_TX2N L3 HT_RXCAD13N U21 GFX_RX11P U4 GFX_TX2P K3 HT_RXCAD13P U22 GFX_RX12N W5 GFX_TX3N L2 HT_RXCAD14N R22 GFX_RX12P W4 GFX_TX3P L1 HT_RXCAD14P R21 Y5 GFX_TX4N N1 HT_RXCAD15N R18 GFX_RX13N 41977 AMD RS690 Databook 3.04 A-6 (c) 2007 Advanced Micro Devices, Inc. Proprietary Ball Ref. Pin Name Ball Ref. Pin Name Ball Ref. HT_RXCAD15P R19 HT_RXCAD1N AB25 HT_TXCAD3P G25 PCE_CALRP AD11 HT_TXCAD4N K23 PLLVDD12 A11 HT_RXCAD1P AB24 HT_RXCAD2N AA23 HT_TXCAD4P J23 PLLVDD18 A10 HT_TXCAD5N K24 PLLVSS B10 HT_RXCAD2P AB23 HT_RXCAD3N AA24 HT_TXCAD5P K25 POWERGOOD C11 HT_TXCAD6N M24 RED E19 HT_RXCAD3P AA25 HT_RXCAD4N V25 HT_TXCAD6P L25 RSET B21 HT_TXCAD7N N25 SB_CLKN G2 HT_RXCAD4P V24 HT_RXCAD5N U23 HT_TXCAD7P N24 SB_CLKP G1 HT_TXCAD8N F22 SB_RX0N W15 HT_RXCAD5P HT_RXCAD6N V23 HT_TXCAD8P F21 SB_RX0P W14 U24 HT_TXCAD9N J21 SB_RX1N AA12 HT_RXCAD6P U25 HT_RXCAD7N R25 HT_TXCAD9P J20 SB_RX1P AB12 HT_TXCALN D24 SB_RX2N W12 HT_RXCAD7P HT_RXCAD8N T24 HT_TXCALP C25 SB_RX2P W11 Y19 HT_TXCLK0N J25 SB_RX3N AB11 HT_RXCAD8P AA19 HT_TXCLK0P J24 SB_RX3P AA11 HT_RXCAD9N AA20 HT_TXCLK1N L22 SB_TX0N AD10 HT_RXCAD9P AB20 HT_TXCLK1P L21 SB_TX0P AE9 HT_RXCALN C24 HT_TXCTLN P23 SB_TX1N AD9 HT_RXCALP A24 HT_TXCTLP N23 SB_TX1P AC8 HT_RXCLK0N W25 HTPVDD B24 SB_TX2N AE8 HT_RXCLK0P Y24 HTPVSS B25 SB_TX2P AD8 HT_RXCLK1N W22 HTREFCLK B23 SB_TX3N AE7 HT_RXCLK1P W21 HTTSTCLK C23 SB_TX3P AD7 HT_RXCTLN P25 I2C_CLK A2 STRP_DATA A3 HT_RXCTLP P24 I2C_DATA B4 SYSRESET# C10 HT_TXCAD0N E25 LDTSTOP# C5 TESTMODE C3 HT_TXCAD0P E24 LPVDD D14 THERMALDIODE_N AB15 HT_TXCAD10N G21 LPVSS E14 THERMALDIODE_P AA15 HT_TXCAD10P G22 LVDDR18D A12 TMDS_HPD C14 HT_TXCAD11N L19 LVDDR18D B12 TVCLKIN C2 HT_TXCAD11P L18 LVDDR33 C12 TXCLK_LN D15 HT_TXCAD12N M19 LVDDR33 C13 TXCLK_LP E15 HT_TXCAD12P M18 LVSSR A14 TXCLK_UN G15 HT_TXCAD13N M21 LVSSR A16 TXCLK_UP H15 HT_TXCAD13P M22 LVSSR C15 TXOUT_L0N B15 HT_TXCAD14N P19 LVSSR C16 TXOUT_L0P B14 HT_TXCAD14P P18 LVSSR C19 TXOUT_L1N A13 HT_TXCAD15N P22 LVSSR D12 TXOUT_L1P B13 HT_TXCAD15P P21 LVSSR F14 TXOUT_L2N G14 HT_TXCAD1N F23 LVSSR F15 TXOUT_L2P H14 HT_TXCAD1P E23 NC AA14 TXOUT_L3N E17 HT_TXCAD2N F24 NC AB14 TXOUT_L3P D17 HT_TXCAD2P F25 OSCIN B11 TXOUT_U0N B16 HT_TXCAD3N H24 PCE_CALRN AE11 TXOUT_U0P A15 Pin Name (c) 2007 Advanced Micro Devices, Inc. Proprietary 41977 AMD RS690 Databook 3.04 A-7 Pin Name Ball Ref. Pin Name Ball Ref. Pin Name Ball Ref. TXOUT_U1N C18 VDD_HT AD22 VSS AE18 TXOUT_U1P C17 VDD_HT AD23 VSS AE22 TXOUT_U2N A17 VDD_HT AD24 VSS B7 TXOUT_U2P B17 VDD_HT AE23 VSS C4 TXOUT_U3N B18 VDD_HT AE24 VSS D23 TXOUT_U3P A18 VDD_HT AE25 VSS D25 VDD_18 J14 VDD_HT W17 VSS D4 VDD_18 J15 VDD_HT Y17 VSS E9 VDD_CORE A19 VDD_HT_PKG D22 VSS F11 VDD_CORE A4 VDD_PLL E7 VSS F17 VDD_CORE A7 VDD_PLL F7 VSS G11 VDD_CORE A9 VDDA_12 AB3 VSS G23 VDD_CORE B19 VDDA_12 AB4 VSS G24 VDD_CORE B9 VDDA_12 AC3 VSS H12 VDD_CORE C9 VDDA_12 AD2 VSS H23 VDD_CORE D20 VDDA_12 AE1 VSS H25 VDD_CORE D9 VDDA_12 AE2 VSS J12 VDD_CORE G20 VDDA_12 B1 VSS J22 VDD_CORE H11 VDDA_12 C1 VSS L12 VDD_CORE J11 VDDA_12 D1 VSS L14 VDD_CORE J19 VDDA_12 D2 VSS L20 VDD_CORE L11 VDDA_12 D3 VSS L23 VDD_CORE L13 VDDA_12 E2 VSS L24 VDD_CORE L15 VDDA_12 E3 VSS M11 VDD_CORE L17 VDDA_12 E6 VSS M13 VDD_CORE M12 VDDA_12 F4 VSS M15 VDD_CORE M14 VDDA_12 G7 VSS M17 VDD_CORE N11 VDDA_12 L9 VSS M20 VDD_CORE N13 VDDA_12 M9 VSS M23 VDD_CORE N15 VDDA_12 U7 VSS M25 VDD_CORE P12 VDDA_12 W7 VSS N12 VDD_CORE P14 VDDA_12_PKG AC11 VSS N14 VDD_CORE P17 VDDA_12_PKG M1 VSS P11 VDD_CORE R11 VDDR AC12 VSS P13 VDD_CORE R13 VDDR AD12 VSS P15 VDD_CORE R15 VDDR AE12 VSS P20 VDD_CORE U11 VDDR3 D11 VSS R12 VDD_CORE U12 VDDR3 E11 VSS R14 VDD_CORE U14 VSS A23 VSS R17 VDD_CORE U15 VSS A25 VSS R20 VDD_HT AA17 VSS AC14 VSS R23 VDD_HT AB17 VSS AC15 VSS R24 VDD_HT AB19 VSS AC16 VSS T23 VDD_HT AC18 VSS AC22 VSS T25 VDD_HT AC19 VSS AC23 VSS U20 VDD_HT AC20 VSS AD25 VSS W23 VDD_HT AD21 VSS AE14 VSS W24 41977 AMD RS690 Databook 3.04 A-8 (c) 2007 Advanced Micro Devices, Inc. Proprietary Pin Name Ball Ref. Pin Name Ball Ref. Pin Name Ball Ref. VSS Y22 VSSA F3 VSSA U2 VSS Y23 VSSA G3 VSSA U3 VSS Y25 VSSA G6 VSSA U6 VSS_PLL F9 VSSA H1 VSSA V11 VSS_PLL G9 VSSA H3 VSSA V12 VSSA A1 VSSA J2 VSSA V14 VSSA AA3 VSSA J3 VSSA V15 VSSA AC10 VSSA J6 VSSA W6 VSSA AC2 VSSA L6 VSSA Y1 VSSA AC4 VSSA M2 VSSA Y11 VSSA AC5 VSSA M3 VSSA Y12 VSSA AC6 VSSA M6 VSSA Y14 VSSA AC7 VSSA N3 VSSA Y15 VSSA AC9 VSSA P6 VSSA Y3 VSSA AD1 VSSA P9 VSSA Y9 VSSA AD3 VSSA R6 Y C20 VSSA AE10 VSSA R9 VSSA AE6 VSSA T1 VSSA F1 VSSA T3 (c) 2007 Advanced Micro Devices, Inc. Proprietary 41977 AMD RS690 Databook 3.04 A-9 This page is left blank intentionally. 41977 AMD RS690 Databook 3.04 A-10 (c) 2007 Advanced Micro Devices, Inc. Proprietary Appendix B Revision History Rev. 0.2 (May 2006) * Preliminary release (Rev. 0.1 has not been released publicly). Rev0.3 (Aug 2006) * * * * * * * * * * * * * * * * * Added references to the RS690C. Added legal disclaimers concerning DVI and HDMI references in this book. Changed the ways in which the integrated DVI/HDMI and the TMDS interface (multiplexed on the PCI-E graphics lanes) are being referred to. Updated Section 1.3.9, "DVI/HDMI (Not applicable to the RS690C)": Clarified limitation of HDCP support. Updated Section 1.6, "Branding Diagram": Added branding diagrams. Updated Section 2.2, "DVI/HDMI (Not Applicable to the RS690C)": Corrected data ordering of DVI/HDMI; the section now applies to both the integrate DVI/HDMI interface and the TMDS interface (multiplexed on the PCI-E graphics lanes). Updated Table 3-10, "Power Management Pins": Corrected nominal voltage of POWERGOOD to 3.3V. Updated Table 3-19, "TMDS Interface Multiplexed on the PCI-E Graphics Interface": Corrected mapping relationships between and PCI-E and TMDS signals. Updated Section 3.10, "Miscellaneous Pins": Added description for pulse-width modulation function of the following pins: STRP_DATA, GPIO[4:2], and TMDS_HPD; added description for DDC_DATA; corrected I/O type for GPIOs. Updated Table 3-15, "Strap Definitions for the RS690": Added descriptions for two Reserved straps. Added Section 4.1, "CPU HyperTransport Bus Timing": Referred designers to AMD specifications. Updated Section 4.4, "OSCIN Timing": Removed high and low time requirements. Updated Section 4.5, "Power Rail Power Up Sequence": Added power rail power up sequence. Added Table 5-6, "DC Characteristics for the Integrated DVI/HDMI (Not Applicable to the RS690C)." Added Table 5-7, "DC Characteristics for the TMDS Interface Multiplexed on the PCI Express(R) Gfx Lanes." Updated Section 5.2, "RS690 Thermal Characteristics." Updated Section 5.3.3.1, "Stencil Opening Size for Solderball Pads on PCB": Changed stencil opening recommendations. Rev 0.4 (Aug 2006) * Revised Table 3-23, "Power Pins": Corrected ball references for VDD_PLL pins; corrected voltage level for LVDDR33. Rev 0.5 (Sep 2006) * * * * * Revised Section 1.3.6, "3D Acceleration Features": Corrected maximum resolution supported to 2048x1536@32bpp for a maximum pixel clock speed of 400MHz. . Revised Section 1.3.9, "DVI/HDMI (Not applicable to the RS690C)": Updated HDMI basic audio support statement. Updated Table 3-10, "Power Management Pins": Corrected I/O type for ALLOW_LDTSTOP to "OD." Updated Table 3-11, "Miscellaneous Pins": Corrected I/O type for TMDS_HPD to "I/O." Revised Section 4.5, "Power Rail Power Up Sequence": Removed 1.2V PCI-E and HT rails from the sequence. (c) 2007 Advanced Micro Devices, Inc. Proprietary 41977 AMD RS690 Databook 3.04 B-1 Rev 0.6 (Oct 2006) * Updated Table 5-4, "DC Characteristics for the HTREFCLK Pad (66.66MHz)": Revised VIH minimum to 1.4V. Rev 3.00 (Jan 2007) * * * * * * * * * Raised revision number to 3.00, following the AMD scheme. Revised H.264 support statement and moved it to Section 1.3. Added Section 1.3.2, "ATI HyperMemoryTM Technology." Updated Section 1.3.8, "Multiple Display Features": Corrected TV modes supported. Added Section 1.5.2, "Branding Diagrams for ASIC Revision A12 and After." Updated Section 2.2, "DVI/HDMI (Not Applicable to the RS690C)": Reorganized the section into two subsections. Updated Table 5-2, "DC Characteristics for 3.3V TTL Signals": Corrected IOL and IOH values for DACSCL and I2C_CLK. Updated Section 5.3.2, "Pressure Specification": Revised statement on the maximum pressure to be applied for securing the thermal management device. Updated Table 3-23, "Power Pins" and Table 5-1, "Maximum and Minimum Ratings": Clarified description for VDD_18, which also powers the DFT_GPIOs. Rev 3.01 (Feb 2007) * * * * * Updated Section 1.3.9, "DVI/HDMI (Not applicable to the RS690C)": Qualified that HDCP support is for single-link transmission only; revised audio support statement. Updated Table 3-2, "1 x 16 Lane PCI Express Interface for External Graphics": Corrected pin type of GFX_REFCLKP/N to input only. Updated Table 3-3, "1 x 4 Lane A-Link Express II Interface for Southbridge": Corrected pin type of SB_CLKP/N to input only. Updated Table 3-11, "Miscellaneous Pins": Updated description for BMREQ#. Updated Table 5-8, "RS690 Thermal Limits": Revised Operating Case Temperature to 0C minimum and 95C maximum. Rev 3.02 (April 2007) * * Added legal note on Macrovision in Section 1.3.8, "Multiple Display Features." Added Table 5-3, "DC Characteristics for 1.8V TTL Signals." Rev 3.03 (April 2007) * Updated legal notes on Macrovision and moved them to the legal notice page at the beginning of the book. Rev 3.04 (Sep 2007) * * * * Updated branding diagrams for ASIC revision A12 (Section 1.5.2, "Branding Diagrams for ASIC Revision A12 and After"). Added support for DirectX VA 2.0 (SD contents only) (Section 1.3.7, "Motion Video Acceleration Features"). Updated the solder reflow profile (Section 5.3.3.2, "Reflow Profile"). Corrected A13 to TXOUT_L1N in Table A-1, "RS690 Pin List Sorted by Ball Reference." 41977 AMD RS690 Databook 3.04 B-2 (c) 2007 Advanced Micro Devices, Inc. Proprietary