ie e)ay Weta ene) DATA SIA 74LVC10A = = | Triple 3-input NAND gate Product specification Philips Semiconductors 1998 Apr 28 PHILIPSPhilips Semiconductors Product specification Da Triple 3-input NAND gate 74LVC1OA FEATURES Wide supply voltage range of 1.2 V to 3.6 V In accordance with JEDEC standard no. 8-1A. Inputs accept voltages up to 5.5 V CMOS low power consumption @ Direct interface with TTL levels Output capability: standard icc category: SSI QUICK REFERENCE DATA GND = 0-V; Tamp = 25C; tf = & <2.5 ns DESCRIPTION The 74LVC10A is a high performance, low power, low voitage, Si gate CMOS device and superior to rnost advanced CMOS compatible TTL famities. The 74LVC10A provides the 3-input NAND function. SYMBOL PARAMETER CONDITIONS TYPICAL tenL/tpLy nA Propagation delay nB, nC tonY C= 80 pF; Veco =3.3 V 3.9 Cy Input capacitance 5.0 Cpep Power dissipation capacitance per gate V, = GND to Voc! 26 NOTE: 1. Cpp is used to determine the dynamic power dissipation (Pp in uW) Pp = Cpp x Vec x fj + (CL Voc? x fo) where: f, = input frequency in MHz; C, = output load capacity in pF; fo = output frequency in MHz; Voc = supply voltage in V; S (CL x Voc? x fp) = sum of the outputs. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 14-Pin Plastic SO 40C to +85C T4LVCIOA D 74UNC10A D SOT108-1 14-Pin Plastic SSOP Type II 40C to +85C 741NC10A DB 74LVC10A DB SOT337-1 14-Pin Plastic TSSOP Type | ~OS to +86C 74LVC1I0A PW 74LVC10APW DH SOT402-1 PIN CONFIGURATION LOGIC SYMBOL val if 2 | zal 3 | La xe ay{_ 6 | enol 7 | LJ Ha%e | 3c 10; 3B | 9] 3a | 8] sv SV06416 PIN DESCRIPTION $V00417 PIN NUMBER SYMBOL NAME AND FUNCTION 1,3,9 1A-3A Data inputs 2,4, 10 1B - 3B Data inputs 7 GND Ground (0 V) 12, 6, 8 1-3Y Data outputs 43, 5, 11 10 ~3C Data inputs 14 Voc Positive supply voltage 1998 Apr 28 853-1973 19308Philips Semiconductors Product specification Triple 3-input NAND gate 74LVCIOA LOGIC SYMBOL (IEEE/IEC) FUNCTION TABLE 1 z INPUTS OUTPUTS 13 12 nA nB ac ny 3 L L L H 5 L L H H 8 L H L H 1 i L H H H H L L H Sv00418 H L H H H H L H LOGIC DIAGRAM (ONE GATE) H H 4 L NOTES: H = HIGH voltage tevel A L = LOW voltage level B Y c $vo0419 RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER CONDITIONS UNIT MIN MAX Vec DC supply voitage (for max. speed performance) 2.7 3.6 Vv Voc DC supply voltage (for low-voltage applications) 1.2 3.6 v Vy DC input voltage range 0 5.5 Vv Tamb Operating free-air temperature range -40 +85 . , Voc = 1.2 to 2.7V 0 20 th, & Input rise and fall times Voc = 2.7 to 3.6V 0 10 ns/V ABSOLUTE MAXIMUM RATINGS! In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = OV). SYMBOL PARAMETER CONDITIONS RATING UNIT Voc DC supply voltage 0.5 to +6.5 Vv lx DC input diode current Vi <0 ~50 mA vi DC input voltage Note 2 ~0.5 to +6.5 Vv lox DC output diede current Vo >Voc or Vo < 0 +50 mA V DC output voltage; output HIGH or LOW Note 2 ~0.5 to Veco 40.5 V vo DC input voltage; output 3-State Note 2 -0.5 to 6.5 fo DC output source or sink current Vo =0to Voc +60 mA leno: loc =| DC Voc or GND current +100 mA Tstg Storage temperature range -65 to +150 C Power dissipation per package Pror ~ plastic mini-pack (SO) above +70C derate linearly with 8 mW/K 500 mW ~ plastic shrink mini-pack (SSOP and TSSOP) above +60C derate linearly with 5.5 mW/K 500 NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1998 Apr 28Philips Semiconductors Product specification Triple 3-input NAND gate 74LVC10A DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions. Voltages are referenced to GND (ground = OV). Limits SYMBOL PARAMETER TEST CONDITIONS Temp = -40C to +B86C =| UNIT MIN TYP | MAX Veco = 1.2V Vv, Vin | HIGH tevel Input voltage ge ce V Vec = 2.7 to 3.6V 2.0 Vv LOW level Input volta Veo = 12V aM y evel Input vo! i. P ge Voc = 2.7 to 3.6V 0.8 Veco =2.7V; Vi= Vin or Vit: lo =12mA Voc 0.5 Veo = 3.0V; Vy = Vi or Vip; lo = 100; Voo~6.2] V. Vou _ | HIGH level output voltage ce 15 Min OF Vins to = 100u4 ge ce Vv Voo = 3.0V; V) = Viz or Vip. lg = -12mA Veco ~ 0.6 Voc = 3.0V; V1 = Vin of Vit. Iq = -24mA Voc ~ 1.0 Vec = 2.7V; Vy = Vin or Vie; Ip = 12MA 0.40 Vat LOW tevel output voltage Veco = 3.0V; V) = Vin or Vis Io = 100uA 0.20 v Voc = 3.0V; V) = Vin oF Vit. lo = 24mA 0.55 h Input leakage current Voc = 3.6V; V, = 5.5V or GND +0.1 +5 pA lec Quiescent supply. current Voc = 3.6V; V| = Veo or GND; Ip = 0 0.1 10 pA Alec put pi quiescent supply current per |). _ 2 7V to 3.6V; Vi = Voc -0.6V Ig = 0 5 | 500 | pA NOTE: 1. All typical values are at Voc = 3.3V and Tamp = 25C. AC CHARACTERISTICS GND =O V;t,=t < 2.5 ns; C, = 50 pF LIMITS SYMBOL PARAMETER WAVEFORM Voc = 3.3V 10.3V Voc =2.7V UNIT MIN Typi MAX MIN MAX fpr! Propagation delay tel nA, nB, nC to nY Figures 1,2 15 3.9 5.7 15 6.7 ns NOTE: 1. These typical values are at Voc = 3.3V and Tamp = 25C. AC WAVEFORMS TEST CIRCUIT VMm=15VatVec = 2.7V Vu = 0.5 Voge at Voc < 2.7 V Vee St 8 Vee Vor and Voy are the typical output voltage drop that occur with the O- Open output joad. o-- GND 5002 Vp---- vy Vo na, nB, nC GENERATOR DUT INPUT F GNO RT T uF 5002 Ay OUTPUT SWITCH POSITION Vor TEST $y Vee vy _ teLHAPHE Open <2.7V Voc Figure 1. Input (nA, nB, nC) to output (nY) bpaev oy propagation delays. _ : $vo0903 1998 Apr 28 Figure 2. Load circuitry for switching times.Philips Semiconductors Triple 3-input NAND gate Product specification 74LVCIOA $014: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 pin 1 index BRRUUEH detail X o 2.5 Smm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mae Ar | Az | As | bp | | DM |] EM] e@ | He | L | ip | a v w y | 2M) 6 om [as [95/148 [ozs | 088 [0% [078 | 20 | sar] 92 [sos] 29 | 82 [oz | oaslor | 2] rove | 0060 [98% [2082 | oor [BBTELE TMH B35 [O72 [cso] 2244 [ ones | 200 [SET on: | oor [occu] game] Note +, Plastic or metal protrusions of 0.145 mm maximum per side are not included. SOT108-1 076E06S MS-012AB =} worse 1998 Apr 28Philips Semiconductors Product specification Triple 3-input NAND gate 74LVC10A SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 q i q met i] a 0 2.5 5mm Laden abd lmartonied scale DIMENSIONS (mm are the original dimensions) unt | A] As | Ap | As | bp |e | OM] eM) | He | LP up] @ |] v | wf y | 2] oe 0.21 | 4:80 0.38 | 0.20] 64 | 54 73 103 | 09 14 | 8 mm | 20 | 905 | 1.65 | 925 | 0.25} oo9 | 60 | 52 | 98 | 76 | 1751 oes] o7 | %2 | O18] OT | Og | oe Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC EIAJ PROJECTION SOT337-1 MO-150AB =} 96-01-18 1998 Apr 28 6Philips Semiconductors Product specification Triple 3-input NAND gate 74LVC1I0A TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 _ ASST 14 8 | t [oi | foes pin f inden | : | | | OC | Ll TP p- | _-p>| ole) G0 2.5 Smm | EN Sa Se es SO SS BO Oe | scale DIMENSIONS (mm are the original dimensions) A max.| At | Az | As | Bp e | pM) | BQ! e He L Lp | @ v w y zM] 6 UNIT 0.15 | 0.95 0.30 | 02 | 51 | 45 6.6 075 | 0.4 a72| 8 mm 11101 gos | 080 | 21 o19] 01 | 49 | 43 | 98] oo | 19 Toso] o3 | &2 | 9197 O71 | ong] 92 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25.mm maxdmum per side are not included. OUTLINE REFERENCES EUROPEAN VERSION IEC JEDEC FIA PROJECTION soT402-1 MO-153 E60 eros ISSUE DATE 4998 Apr 28 7Philips Semiconductors Product specification Triple 3-input NAND gate 74LVC10A Data sheet status Data sheet Product Definition [11 status status Objective Development This data sheet contains the design target or goal specifications for product development. specification Specification may change in any manner without notice. Preliminary Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. specification Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make specification changes at any time without notice in order to improve design and supply the best possible product. {1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System. (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and-cperation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indernnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the rightto make. changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors Copyright Philips Electronics North America Corporation 1998 811 East Arques Avenue All rights reserved. Printed in U.S.A. P.O. Box 3409 Sunnyvale, California 94088-3409 print code Date of release: 07-98 Telephone 800-234-7381 Document order number: 9397-750-04482 Lett make Philips Semiconductors