© Semiconductor Components Industries, LLC, 1995
January, 2019 − Rev. 40
1Publication Order Number:
TL431/D
TL431A, B Series,
NCV431A, B Series,
SCV431A
Programmable
Precision References
The TL431A, B integrated circuits are three−terminal
programmable shunt regulator diodes. These monolithic IC voltage
references operate as a low temperature coefficient zener which is
programmable from Vref to 36 V with two external resistors. These
devices exhibit a wide operating current range of 1.0 mA to 100 mA
with a typical dynamic impedance of 0.22 W. The characteristics of
these references make them excellent replacements for zener diodes in
many applications such as digital voltmeters, power supplies, and op
amp circuitry. The 2.5 V reference makes it convenient to obtain a
stable reference from 5.0 V logic supplies, and since the TL431A, B
operates as a shunt regulator, it can be used as either a positive or
negative voltage reference.
Features
•Programmable Output Voltage to 36 V
•Voltage Reference Tolerance: ±0.4%, Typ @ 25°C (TL431B)
•Low Dynamic Output Impedance, 0.22 W Typical
•Sink Current Capability of 1.0 mA to 100 mA
•Equivalent Full−Range Temperature Coefficient of 50 ppm/°C Typical
•Temperature Compensated for Operation over Full Rated Operating
Temperature Range
•Low Output Noise Voltage
•NCV/SCV Prefixes for Automotive and Other Applications
Requiring Unique Site and Control Change Requirements;
AEC−Q100 Qualified and PPAP Capable
•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant (Top View)
3
1Reference
N/C
N/C
N/C
2
4
8
7
6
5N/C
Anode
N/C
Cathode
Anode Anode
PDIP−8
P SUFFIX
CASE 626
SOIC−8
D SUFFIX
CASE 751
(Top View)
3
1Reference
N/C
2
4
8
7
6
5N/C
Cathode
Micro8E
DM SUFFIX
CASE 846A
8
1
8
1
This is an internally modified SOIC−8 package. Pins 2, 3, 6 and
7 are electrically common to the die attach flag. This internal
lead frame modification increases power dissipation capability
when appropriately mounted on a printed circuit board. This
modified package conforms to all external dimensions of the
standard SOIC−8 package.
See detailed ordering and shipping information on page 13 of
this data sheet.
ORDERING INFORMATION
See general marking information in the device marking
section on page 14 of this data sheet.
DEVICE MARKING INFORMATION
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TO−92
LP SUFFIX
CASE 29−11
123
12
BENT LEAD
TAPE & REEL
AMMO PACK
STRAIGHT LEAD
BULK PACK
3
TO−92
LPRA, LPRE, LPRM,
LPRP SUFFIX
CASE 29−11
Pin 1. Reference
2. Anode
3. Cathode
TL431A, B Series, NCV431A, B Series, SCV431A
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2
1.0 k
Cathode
(K)
2.5 Vref
Anode (A)
Reference
(R)
4.0 k
150
Figure 1. Symbol
10 k
20 pF
800
Cathode (K)
3.28 k
Anode (A)
-
+
Anode
(A)
800
Reference
(R)
2.4 k 7.2 k
20 pF
800
Cathode
(K)
Reference
(R)
This device contains 12 active transistors.
Figure 2. Representative Block Diagram
Figure 3. Representative Schematic Diagram
Component values are nominal
MAXIMUM RATINGS (Full operating ambient temperature range applies, unless otherwise noted.)
Rating Symbol Value Unit
Cathode to Anode Voltage VKA 37 V
Cathode Current Range, Continuous IK−100 to +150 mA
Reference Input Current Range, Continuous Iref −0.05 to +10 mA
Operating Junction Temperature TJ150 °C
Operating Ambient Temperature Range TA°C
TL431I, TL431AI, TL431BI −40 to +85
TL431C, TL431AC, TL431BC 0 to +70
NCV431AI, NCV431B, TL431BV, SCV431AI −40 to +125
Storage Temperature Range Tstg −65 to +150 °C
Total Power Dissipation @ TA = 25°C PDW
Derate above 25°C Ambient Temperature
D, LP Suffix Plastic Package 0.70
P Suffix Plastic Package 1.10
DM Suffix Plastic Package 0.52
Total Power Dissipation @ TC = 25°C PDW
Derate above 25°C Case Temperature
D, LP Suffix Plastic Package 1.5
P Suffix Plastic Package 3.0
ESD Rating (Note 1)
Human Body Model per JEDEC JESD22−A114F
Machine Model per JEDEC JESD22−A115C
Charged Device Model per JEDEC JESD22−C101E
HBM
MM
CDM
>2000
>200
>500
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device contains latch−up protection and exceeds ±100 mA per JEDEC standard JESD78.
RECOMMENDED OPERATING CONDITIONS
Condition Symbol Min Max Unit
Cathode to Anode Voltage VKA Vref 36 V
Cathode Current IK1.0 100 mA
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
TL431A, B Series, NCV431A, B Series, SCV431A
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3
THERMAL CHARACTERISTICS
Characteristic Symbol
D, LP Suffix
Package
P Suffix
Package
DM Suffix
Package Unit
Thermal Resistance, Junction−to−Ambient RqJA 178 114 240 °C/W
Thermal Resistance, Junction−to−Case RqJC 83 41 −°C/W
ELECTRICAL CHARACTERISTICS (TA = 25°C, unless otherwise noted.)
Characteristic Symbol
TL431I TL431C
Unit
Min Typ Max Min Typ Max
Reference Input Voltage (Figure 1)
VKA = Vref, IK = 10 mA
TA = 25°C
TA = Tlow to Thigh (Note 2)
Vref
2.44
2.41
2.495
−
2.55
2.58
2.44
2.423
2.495
−
2.55
2.567
V
Reference Input Voltage Deviation Over
Temperature Range (Figure 1, Notes 3, 4)
VKA= Vref, IK = 10 mA
DVref −7.0 30 −3.0 17 mV
Ratio of Change in Reference Input Voltage to Change
in Cathode to Anode Voltage
IK = 10 mA (Figure 2),
DVKA = 10 V to Vref
DVKA = 36 V to 10 V
DVref
DVKA
−
−
−1.4
−1.0
−2.7
−2.0
−
−
−1.4
−1.0
−2.7
−2.0
mV/V
Reference Input Current (Figure 2)
IK = 10 mA, R1 = 10 k, R2 = ∞
TA = 25°C
TA = Tlow to Thigh (Note 2)
Iref
−
−
1.8
−
4.0
6.5
−
−
1.8
−
4.0
5.2
mA
Reference Input Current Deviation Over
Temperature Range (Figure 2, Note 3)
IK = 10 mA, R1 = 10 k, R2 = ∞
DIref −0.8 2.5 −0.4 1.2 mA
Minimum Cathode Current For Regulation
VKA = Vref (Figure 1)
Imin −0.5 1.0 −0.5 1.0 mA
Off−State Cathode Current (Figure 3)
VKA = 36 V, Vref = 0 V
Ioff −20 1000 −20 1000 nA
Dynamic Impedance (Figure 1, Note 5)
VKA = Vref, DIK = 1.0 mA to 100 mA, f ≤ 1.0 kHz
|ZKA|−0.22 0.5 −0.22 0.5 W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Tlow =−40°C for TL431AIP TL431AILP, TL431IP, TL431ILP, TL431BID, TL431BIP, TL431BILP, TL431AIDM, TL431IDM, TL431BIDM;
=0°C for TL431ACP, TL431ACLP, TL431CP, TL431CLP, TL431CD, TL431ACD, TL431BCD, TL431BCP, TL431BCLP, TL431CDM,
TL431ACDM, TL431BCDM
Thigh = +85°C for TL431AIP, TL431AILP, TL431IP, TL431ILP, TL431BID, TL431BIP, TL431BILP, TL431IDM, TL431AIDM, TL431BIDM
= +70°C for TL431ACP, TL431ACLP, TL431CP, TL431ACD, TL431BCD, TL431BCP, TL431BCLP, TL431CDM, TL431ACDM,
TL431BCDM
3. Guaranteed by design.
4. The deviation parameter DVref is defined as the difference between the maximum and minimum values obtained over the full operating
ambient temperature range that applies.
DVref = Vref max
-Vref min
DTA = T2 - T1
T2
Ambient Temperature
T1
Vref min
Vref max
The average temperature coefficient of the reference input voltage, aVref is defined as: Vref
ppm
_C+ǒDVref
Vref @25_CǓX10
6
DTA+
DVref x10
6
DTA(Vref @25_C)
aVref can be positive or negative depending on whether Vref Min or Vref Max occurs at the lower ambient temperature. (Refer to Figure 6.)
Example : DVref +8.0 mV and slope is positive,
Vref @25_C+2.495 V, DTA+70_CaVref +0.008 x 106
70 (2.495) +45.8 ppmń_C
5. The dynamic impedance ZKA is defined as: |ZKA|+
DVKA
DIK
. When the device is programmed with two external resistors, R1 and R2,
(refer to Figure 2) the total dynamic impedance of the circuit is defined as: |ZKAȀ|[|ZKA|ǒ1)R1
R2 Ǔ
TL431A, B Series, NCV431A, B Series, SCV431A
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4
ELECTRICAL CHARACTERISTICS (TA = 25°C, unless otherwise noted.)
Characteristic Symbol
TL431AI /
NCV431AI/
SCV431AI TL431AC
TL431BC / TL431BI /
TL431BV /
NCV431BV
Unit
Min Typ Max Min Typ Max Min Typ Max
Reference Input Voltage (Figure 1)
VKA = Vref, IK = 10 mA
TA = 25°C
TA = Tlow to Thigh (Note 6)
Vref
2.47
2.44
2.495
−
2.52
2.55
2.47
2.453
2.495
−
2.52
2.537
2.485
2.475
2.495
2.495
2.505
2.515
V
Reference Input Voltage Deviation Over
Temperature Range (Figure 1, Notes 7, 8)
VKA= Vref, IK = 10 mA
DVref −7.0 30 −3.0 17 −3.0 17 mV
Ratio of Change in Reference Input Voltage to
Change in Cathode to Anode Voltage
IK = 10 mA (Figure 2),
DVKA = 10 V to Vref
DVKA = 36 V to 10 V
DVref
DVKA
−
−
−1.4
−1.0
−2.7
−2.0
−
−
−1.4
−1.0
−2.7
−2.0
−
−
−1.4
−1.0
−2.7
−2.0
mV/V
Reference Input Current (Figure 2)
IK = 10 mA, R1 = 10 k, R2 = ∞
TA = 25°C
TA = Tlow to Thigh (Note 6)
Iref
−
−
1.8
−
4.0
6.5
−
−
1.8
−
4.0
5.2
−
−
1.1
−
2.0
4.0
mA
Reference Input Current Deviation Over
Temperature Range (Figure 2, Note 7)
IK = 10 mA, R1 = 10 k, R2 = ∞
DIref −0.8 2.5 −0.4 1.2 −0.8 2.5 mA
Minimum Cathode Current For Regulation
VKA = Vref (Figure 1)
Imin −0.5 1.0 −0.5 1.0 −0.5 1.0 mA
Off−State Cathode Current (Figure 3)
VKA = 36 V, Vref = 0 V
Ioff −20 1000 −20 1000 −0.23 500 nA
Dynamic Impedance (Figure 1, Note 9)
VKA = Vref, DIK = 1.0 mA to 100 mA
f ≤ 1.0 kHz
|ZKA|−0.22 0.5 −0.22 0.5 −0.14 0.3 W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Tlow =−40°C for TL431AIP TL431AILP, TL431IP, TL431ILP, TL431BID, TL431BIP, TL431BILP, TL431BV, TL431AIDM, TL431IDM,
TL431BIDM, NCV431AIDMR2G, NCV431AIDR2G, NCV431BVDR2G, SCV431AIDMR2G
=0°C for TL431ACP, TL431ACLP, TL431CP, TL431CLP, TL431CD, TL431ACD, TL431BCD, TL431BCP, TL431BCLP, TL431CDM,
TL431ACDM, TL431BCDM, SCV431AIDMR2G
Thigh = +85°C for TL431AIP, TL431AILP, TL431IP, TL431ILP, TL431BID, TL431BIP, TL431BILP, TL431IDM, TL431AIDM, TL431BIDM
= +70°C for TL431ACP, TL431ACLP, TL431CP, TL431ACD, TL431BCD, TL431BCP, TL431BCLP, TL431CDM, TL431ACDM,
TL431BCDM
= +125°C TL431BV, NCV431AIDMR2G, NCV431AIDR2G, NCV431BVDMR2G, NCV431BVDR2G, SCV431AIDMR2G
7. Guaranteed by design.
8. The deviation parameter DVref is defined as the difference between the maximum and minimum values obtained over the full operating
ambient temperature range that applies.
DVref = Vref max
-Vref min
DTA = T2 - T1
T2
Ambient Temperature
T1
Vref min
Vref max
The average temperature coefficient of the reference input voltage, aVref is defined as: Vref
ppm
_C+ǒDVref
Vref @25_CǓX10
6
DTA+
DVref x10
6
DTA(Vref @25_C)
aVref can be positive or negative depending on whether Vref Min or Vref Max occurs at the lower ambient temperature. (Refer to Figure 6.)
Example : DVref +8.0 mV and slope is positive,
Vref @25_C+2.495 V, DTA+70_CaVref +0.008 x 106
70 (2.495) +45.8 ppmń_C
9. The dynamic impedance ZKA is defined as |ZKA|+
DVKA
DIK
When the device is programmed with two external resistors, R1 and R2, (refer
to Figure 2) the total dynamic impedance of the circuit is defined as: |ZKAȀ|[|ZKA|ǒ1)R1
R2 Ǔ
10.NCV431AIDMR2G, NCV431AIDR2G, NCV431BVDMR2G, NCV431BVDR2G, SCV431AIDMR2G Tlow = −40°C, Thigh = +125°C.
NCV prefix is for automotive and other applications requiring unique site and control change requirements.
TL431A, B Series, NCV431A, B Series, SCV431A
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5
IK
Vref
VKA
Input
Figure 1. Test Circuit for VKA = Vref
Input
IK
R2
Iref
Vref
VKA
R1
Figure 2. Test Circuit for VKA > Vref
VKA +Vrefǒ1 )R1
R2Ǔ)IrefSR1
Ioff
Input VKA
Figure 3. Test Circuit for Ioff
-1.0
IMin
200
400
VKA, CATHODE VOLTAGE (V)
-200 0
0
1.0 2.0 3.0
800
600
-2.0 -1.0 0
-100 1.0 2.0 3.0
150
50
VKA, CATHODE VOLTAGE (V)
0
-50
Figure 4. Cathode Current versus
Cathode Voltage
Figure 5. Cathode Current versus
Cathode Voltage
Input
100
VKA = Vref
TA = 25°C
IK
VKA
IK, CATHODE CURRENT (mA)
IK, CATHODE CURRENT ( A)μ
125
TA, AMBIENT TEMPERATURE (°C)
3.0
10050 75-55
0
2.5
0.5
2.0
1.0
250-25
1.5
2600
2580
2560
2540
2520
2500
2480
2460
VKA = Vref
IK = 10 mA
TA, AMBIENT TEMPERATURE (°C)
VKA
IK
-55
Input
Vref
75 100 125
2440
050
Figure 6. Reference Input Voltage versus
Ambient Temperature
Figure 7. Reference Input Current versus
Ambient Temperature
2420
2400 25-25
Input
IK
IK = 10 mA
Iref
10k
VKA
ref
V , REFERENCE INPUT VOLTAGE (mV)
Iref, REFERENCE INPUT CURRENT ( A)μ
Vref Max = 2550 mV
Vref Typ = 2495 mV
Vref Min = 2440 mV
VKA = Vref
TA = 25°C
Input VKA
IK
TL431A, B Series, NCV431A, B Series, SCV431A
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6
√
NOISE VOLTAGE (nV/ Hz)
-55
f, FREQUENCY (MHz)
100
10
1.0
100 k 10 M1.0 M1.0 k 10 k
0.1 75-25 0 25 50 100 125
TA, AMBIENT TEMPERATURE (°C)
0.200
0.220
0.240
0.300
0.320
0.260
0.280
IK
50 -
1.0 k
+
Output
GND Output
GND
IK
50 -
1.0k
+
VKA = Vref
D IK = 1.0 mA to 100 mA
f ≤ 1.0 kHz
TA = 25°C
D IK = 1.0 mA to 100 mA
|ZKA Ω|, DYNAMIC IMPEDANCE ( )
|ZKA Ω|, DYNAMIC IMPEDANCE ( )
f, FREQUENCY (Hz)
40
10 10 k1.0 k100
0
20
100 k
60
f, FREQUENCY (MHz)
100 k
0
10 M1.0 M
-10
10
20
30
60
50
40
1.0 k 10 k
VKA = Vref
IK = 10 mA
TA = 25°C
IK
OutputInput
80
, OPEN LOOP VOLTAGE GAIN (dB)
230
GND
Output
IK
9.0 mF
8.25k
15k
IK = 10 mA
TA = 25°C
-55
0.01
100
10
1.0
0.1
TA, AMBIENT TEMPERATURE (5C)
75-25 0 25 50 100 125
40
1.0 k
VKA, CATHODE VOLTAGE (V)
30100
-32
-8.0
-16
20
0
-24 R2 Vref
R1 IK
Input VKA
Input Ioff
VKA = 36 V
Vref = 0 V VKA
Vref, REFERENCE INPUT VOLTAGE (mV)Δ
Ioff, OFF-STATE CATHODE CURRENT (nA)
IK = 10 mA
TA = 25°C
Figure 8. Change in Reference Input
Voltage versus Cathode Voltage
Figure 9. Off−State Cathode Current
versus Ambient Temperature
Figure 10. Dynamic Impedance
versus Frequency
Figure 11. Dynamic Impedance
versus Ambient Temperature
Figure 12. Open−Loop Voltage Gain
versus Frequency
Figure 13. Spectral Noise Density
VOL
A
TL431A, B Series, NCV431A, B Series, SCV431A
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7
Input
Output
t, TIME (ms)
Pulse
Generator
f = 100 kHz
0 8.04.0 20
0
16
2.0
3.0
12
0
1.0
5.0
Figure 14. Pulse Response Figure 15. Stability Boundary Conditions
50
220 Output
GND
Input
Monitor
TA = 25°C
VOLTAGE SWING (V)
TA = 25°C
C
A
B
CL, LOAD CAPACITANCE
120
80
100
60
0
IK, CATHODE CURRENT (mA)
140
1.0 nF 100 mF1.0 mF 10 mF
Stable Stable
40
20
10 nF 100 nF
A
B
D
Unstable
Area
Programmed
VKA(V)
A
B
C
D
Vref
5.0
10
15
Figure 16. Test Circuit For Curve A
of Stability Boundary Conditions
Figure 17. Test Circuit For Curves B, C, And D
of Stability Boundary Conditions
V+
IK
150
IK
V+
150
CL
10 k
CL
Figure 18. Shunt Regulator Figure 19. High Current Shunt Regulator
V+ Vout
R1
V+ Vout
R1
R2
R2
Vout +ǒ1)R1
R2ǓVref Vout +ǒ1)R1
R2ǓVref
TYPICAL APPLICATIONS
TL431A, B Series, NCV431A, B Series, SCV431A
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8
Figure 20. Output Control for a
Three−Terminal Fixed Regulator
Figure 21. Series Pass Regulator
V+ Vout
R1
R2
Out
In
MC7805
V+ Vout
R2
Common
R1
Vout +ǒ1)R1
R2ǓVref
Vout(min) +Vref )5.0V
Vout +ǒ1)R1
R2ǓVref
Vout(min) +Vref
Vin(min) +Vout )Vbe
Figure 22. Constant Current Source Figure 23. Constant Current Sink
V+
RCL Iout
V+
RS
ISink +Vref
RS
Iout +Vref
RCL
Isink
Figure 24. TRIAC Crowbar Figure 25. SRC Crowbar
Vout
V+
R2
V+ Vout
R1
R2
R1
Vout(trip) +ǒ1)R1
R2ǓVref
Vout(trip) +ǒ1)R1
R2ǓVref
TL431A, B Series, NCV431A, B Series, SCV431A
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Figure 26. Voltage Monitor Figure 27. Single−Supply Comparator with
Temperature−Compensated Threshold
Vth = Vref
V+
Vout
Vin
R1 R3
V+ Vout
R2 R4
l
L.E.D. indicator is `on' when V+ is between the
upper and lower limits.
LowerLimit +ǒ1)R1
R2ǓVref
UpperLimit +ǒ1)R3
R4ǓVref
Vin Vout
< Vref V+
> Vref ≈2.0 V
Figure 28. Linear Ohmmeter Figure 29. Simple 400 mW Phono Amplifier
*Thermalloy
*THM 6024
*Heatsink on
*LP Package
*
Tl = 330 to 8.0 W
8.0 W
+
-
LM11
2.0 mA
25 V
25 V
-5.0 V
Vout
Range
V
1.0 MW
V
100 kW
V
V
1.0 kW
RX
5.0 M
1%
500 k
1%
50 k
1%
5.0 k
1%
47 k
Tone
0.05 mF
470 mF
Volume
1N5305
1.0 mF
TI
360 k
330
56 k 10 k 25 k
38 V
+
10 kW
10 k
Calibrate
Rx+VoutD W
V Range
TL431A, B Series, NCV431A, B Series, SCV431A
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Figure 30. High Efficiency Step−Down Switching Converter
150 mH @ 2.0 A
1N5823
0.01mF
+
470 mF
51 k
0.1 mF
+2200 mF
4.7 k
Vin = 10 V to 20 V TIP115
MPSA20
1.0 k
4.7 k
4.7 k
102.2 k
100 k
Vout = 5.0 V
Iout = 1.0 A
Test Conditions Results
Line Regulation Vin = 10 V to 20 V, Io = 1.0 A 53 mV (1.1%)
Load Regulation Vin = 15 V, Io = 0 A to 1.0 A 25 mV (0.5%)
Output Ripple Vin = 10 V, Io = 1.0 A 50 mVpp P.A.R.D.
Output Ripple Vin = 20 V, Io = 1.0 A 100 mVpp P.A.R.D.
Efficiency Vin = 15 V, Io = 1.0 A 82%
TL431A, B Series, NCV431A, B Series, SCV431A
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APPLICATIONS INFORMATION
The TL431 is a programmable precision reference which
is used in a variety of ways. It serves as a reference voltage
in circuits where a non−standard reference voltage is
needed. Other uses include feedback control for driving an
optocoupler in power supplies, voltage monitor, constant
current source, constant current sink and series pass
regulator. In each of these applications, it is critical to
maintain stability of the device at various operating currents
and load capacitances. In some cases the circuit designer can
estimate the stabilization capacitance from the stability
boundary conditions curve provided in Figure 15. However,
these typical curves only provide stability information at
specific cathode voltages and at a specific load condition.
Additional information is needed to determine the
capacitance needed to optimize phase margin or allow for
process variation.
A simplified model of the TL431 is shown in Figure 31.
When tested for stability boundaries, the load resistance is
150 W. The model reference input consists of an input
transistor and a dc emitter resistance connected to the device
anode. A dependent current source, Gm, develops a current
whose amplitude is determined by the difference between
the 1.78 V internal reference voltage source and the input
transistor emitter voltage. A portion of Gm flows through
compensation capacitance, CP2. The voltage across CP2
drives the output dependent current source, Go, which is
connected across the device cathode and anode.
Model component values are:
Vref = 1.78 V
Gm = 0.3 + 2.7 exp (−IC/26 mA)
where IC is the device cathode current and Gm is in mhos
Go = 1.25 (Vcp2) mmhos.
Resistor and capacitor typical values are shown on the
model. Process tolerances are ±20% for resistors, ±10% for
capacitors, and ±40% for transconductances.
An examination of the device model reveals the location
of circuit poles and zeroes:
P1 +1
2pRGM CP1 +1
2p* 1.0 M * 20 pF +7.96 kHz
P2 +1
2pRP2CP2 +1
2p* 10 M * 0.265 pF +60 kHz
Z1 +1
2pRZ1CP1 +1
2p*15.9k*20pF+500 kHz
In addition, there is an external circuit pole defined by the
load:
PL+1
2pRLCL
Also, the transfer dc voltage gain of the TL431 is:
G+GMRGMGoRL
Example 1:
I
C
+10 mA, RL+230 W,C
L+0. Define the transfer gain.
The DC gain is:
G+GMRGMGoRL+
(2.138)(1.0 M)(1.25 m)(230) +615 +56 dB
Loop gain +G8.25 k
8.25 k )15 k +218 +47 dB
The resulting transfer function Bode plot is shown in
Figure 32. The asymptotic plot may be expressed as the
following equation:
Av +615 ǒ1)jf
500 kHzǓ
ǒ1)jf
8.0 kHzǓǒ1)jf
60 kHzǓ
The Bode plot shows a unity gain crossover frequency of
approximately 600 kHz. The phase margin, calculated from
the equation, would be 55.9 degrees. This model matches the
Open−Loop Bode Plot of Figure 12. The total loop would
have a unity gain frequency of about 300 kHz with a phase
margin of about 44 degrees.
TL431A, B Series, NCV431A, B Series, SCV431A
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12
Figure 31. Simplified TL431 Device Model
+
RL
VCC
-
CL
15 k
9.0 mF
Input
8.25 k
3
Cathode
500 k
Vref
1.78 V
Rref
16
GM
Anode 2
RGM
1.0 M
Ref
1
Go
1.0 mmho
CP2
0.265 pF
RP2
10 M
RZ1
15.9 k
CP1
20 pF
f, FREQUENCY (Hz)
102
101
-20
30
20
60
0
Av, OPEN-LOOP VOLTAGE GAIN (dB)
Figure 32. Example 1 Circuit Open Loop Gain Plot
TL431 OPEN-LOOP VOLTAGE GAIN VERSUS FREQUENCY
40
104
103107
105106
10
-10
50
Example 2.
IC = 7.5 mA, RL = 2.2 kW, CL = 0.01 mF. Cathode tied to
reference input pin. An examination of the data sheet
stability boundary curve (Figure 15) shows that this value of
load capacitance and cathode current is on the boundary.
Define the transfer gain.
The DC gain is:
G+GMRGMGoRL+
(2.323)(1.0 M)(1.25 m)(2200) +6389 +76 dB
The resulting open loop Bode plot is shown in Figure 33.
The asymptotic plot may be expressed as the following
equation:
Av +615 ǒ1)jf
500 kHzǓ
ǒ1)jf
8.0 kHzǓǒ1)jf
60 kHzǓǒ1)jf
7.2 kHzǓ
Note that the transfer function now has an extra pole
formed by the load capacitance and load resistance.
Note that the crossover frequency in this case is about
250 kHz, having a phase margin of about −46 degrees.
Therefore, instability of this circuit is likely.
f, FREQUENCY (Hz)
102
101
-20
40
20
80
0
Av, OPEN-LOOP GAIN (dB)
Figure 33. Example 2 Circuit Open Loop Gain Plot
TL431 OPEN-LOOP BODE PLOT WITH LOAD CAP
60
104
103106
105
With three poles, this system is unstable. The only hope
for stabilizing this circuit is to add a zero. However, that can
only be done by adding a series resistance to the output
capacitance, which will reduce its effectiveness as a noise
filter. Therefore, practically, in reference voltage
applications, the best solution appears to be to use a smaller
value of capacitance in low noise applications or a very
large value to provide noise filtering and a dominant pole
rolloff of the system.
TL431A, B Series, NCV431A, B Series, SCV431A
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13
ORDERING INFORMATION
Device
Marking
Code Operating Temperature Range Package Code Shipping Information†Tolerance
TL431ACDG AC
0°C to 70°C
SOIC−8
(Pb−Free)
98 Units / Rail
1.0%
TL431BCDG BC 0.4%
TL431CDG C 2.2%
TL431ACDR2G AC
2500 / Tape & Reel
1.0%
TL431BCDR2G BC 0.4%
TL431CDR2G C 2.2%
TL431ACDMR2G TAC
Micro8
(Pb−Free) 4000 / Tape & Reel
1.0%
TL431BCDMR2G TBC 0.4%
TL431CDMR2G T−C 2.2%
TL431ACPG ACP
PDIP−8
(Pb−Free) 50 Units / Rail
1.0%
TL431BCPG BCP 0.4%
TL431CPG CP 2.2%
TL431ACLPG ACLP
TO−92
(Pb−Free)
2000 Units / Bag
1.0%
TL431BCLPG BCLP 0.4%
TL431CLPG CLP 2.2%
TL431ACLPRAG ACLP
2000 / Tape & Reel
1.0%
TL431BCLPRAG BCLP 0.4%
TL431CLPRAG CLP 2.2%
TL431ACLPREG ACLP 1.0%
TL431BCLPREG BCLP 0.4%
TL431CLPREG CLP 2.2%
TL431ACLPRPG ACLP 2000 / Tape & Ammo Box 1.0%
TL431BCLPRMG BCLP
2000 / Fan−Fold
0.4%
TL431CLPRMG CLP 2.2%
TL431CLPRPG CLP
TL431AIDG AI
−40°C to 85°C
SOIC−8
(Pb−Free)
98 Units / Rail
1.0%
TL431BIDG BI 0.4%
TL431IDG I 2.2%
TL431AIDR2G AI
2500s / Tape & Reel
1.0%
TL431BIDR2G BI 0.4%
TL431IDR2G I 2.2%
TL431AIDMR2G TAI
Micro8
(Pb−Free) 4000 / Tape & Reel
1.0%
TL431BIDMR2G TBI 0.4%
TL431IDMR2G T−I 2.2%
TL431AIPG AIP
PDIP−8
(Pb−Free) 50 Units / Rail
1.0%
TL431BIPG BIP 0.4%
TL431IPG IP 2.2%
TL431AILPG AILP
TO−92
(Pb−Free)
2000 Units / Bag
1.0%
TL431BILPG BILP 0.4%
TL431ILPG ILP 2.2%
TL431AILPRAG AILP
2000 / Tape & Reel
1.0%
TL431BILPRAG BILP 0.4%
SC431ILPRAG ILP 2.2%
TL431ILPRAG ILP
TL431AILPRMG AILP 2000 / Tape & Ammo Box 1.0%
TL431AILPRPG
TL431ILPRPG ILP 2.2%
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV/SCV Prefixes for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified
and PPAP Capable.
TL431A, B Series, NCV431A, B Series, SCV431A
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14
ORDERING INFORMATION
Device ToleranceShipping Information†
Package CodeOperating Temperature Range
Marking
Code
TL431BVDG BV
−40°C to 125°C
SOIC−8
(Pb−Free)
98 Units / Rail
0.4%
TL431BVDR2G 2500 / Tape & Reel
TL431BVDMR2G TBV Micro8
(Pb−Free) 4000 / Tape & Reel
TL431BVLPG BVLP TO−92
(Pb−Free)
2000 Units / Bag
TL431BVLPRAG 2000 / Tape & Reel
TL431BVPG BVP PDIP−8
(Pb−Free) 50 Units / Rail 0.4%
NCV431AIDMR2G* RAN Micro8
(Pb−Free) 4000 / Tape & Reel
1%
SCV431AIDMR2G* RAP
NCV431AIDR2G* AV SOIC−8
(Pb−Free) 2500 / Tape & Reel
NCV431BVDMR2G* NVB Micro8
(Pb−Free) 4000 / Tape & Reel
0.4%
NCV431BVDR2G* BV SOIC−8
(Pb−Free) 2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV/SCV Prefixes for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified
and PPAP Capable.
SOIC−8
D SUFFIX
CASE 751
MARKING DIAGRAMS
Micro8
CASE 846A
TO−92 (TO−226)
CASE 29
PDIP−8
CASE 626
TL431xxx
AWL
YYWWG
1
8
TL431
xxxx
ALYW G
G
xxxx = See Specific Marking Code
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
xxx
AYWG
G
1
8
431xx
ALYW
G
1
8
TL431
ALYWx
G
1
8
(Exception for the TL431CD
and TL431ID only)
TL431A, B Series, NCV431A, B Series, SCV431A
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15
PACKAGE DIMENSIONS
TO−92 (TO−226)
CASE 29−11
ISSUE AN
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. CONTOUR OF PACKAGE BEYOND DIMENSION R
IS UNCONTROLLED.
4. LEAD DIMENSION IS UNCONTROLLED IN P AND
BEYOND DIMENSION K MINIMUM.
R
A
P
J
L
B
K
G
H
SECTION X−X
C
V
D
N
N
XX
SEATING
PLANE DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.175 0.205 4.45 5.20
B0.170 0.210 4.32 5.33
C0.125 0.165 3.18 4.19
D0.016 0.021 0.407 0.533
G0.045 0.055 1.15 1.39
H0.095 0.105 2.42 2.66
J0.015 0.020 0.39 0.50
K0.500 --- 12.70 ---
L0.250 --- 6.35 ---
N0.080 0.105 2.04 2.66
P--- 0.100 --- 2.54
R0.115 --- 2.93 ---
V0.135 --- 3.43 ---
1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. CONTOUR OF PACKAGE BEYOND
DIMENSION R IS UNCONTROLLED.
4. LEAD DIMENSION IS UNCONTROLLED IN P
AND BEYOND DIMENSION K MINIMUM.
RA
P
J
B
K
G
SECTION X−X
C
V
D
N
XX
SEATING
PLANE DIM MIN MAX
MILLIMETERS
A4.45 5.20
B4.32 5.33
C3.18 4.19
D0.40 0.54
G2.40 2.80
J0.39 0.50
K12.70 ---
N2.04 2.66
P1.50 4.00
R2.93 ---
V3.43 ---
1
T
BENT LEAD
TAPE & REEL
AMMO PACK
STRAIGHT LEAD
BULK PACK
TL431A, B Series, NCV431A, B Series, SCV431A
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16
PACKAGE DIMENSIONS
PDIP−8
CASE 626−05
ISSUE P
14
58
b2
NOTE 8
D
b
L
A1
A
eB
E
A
TOP VIEW
C
SEATING
PLANE
0.010 CA
SIDE VIEW
END VIEW
END VIEW
WITH LEADS CONSTRAINED
DIM MIN MAX
INCHES
A−−−− 0.210
A1 0.015 −−−−
b0.014 0.022
C0.008 0.014
D0.355 0.400
D1 0.005 −−−−
e0.100 BSC
E0.300 0.325
M−−−− 10
−−− 5.33
0.38 −−−
0.35 0.56
0.20 0.36
9.02 10.16
0.13 −−−
2.54 BSC
7.62 8.26
−−− 10
MIN MAX
MILLIMETERS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK-
AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
E1 0.240 0.280 6.10 7.11
b2
eB −−−− 0.430 −−− 10.92
0.060 TYP 1.52 TYP
E1
M
8X
c
D1
B
A2 0.115 0.195 2.92 4.95
L0.115 0.150 2.92 3.81
°°
H
NOTE 5
e
e/2 A2
NOTE 3
MBMNOTE 6
M
TL431A, B Series, NCV431A, B Series, SCV431A
www.onsemi.com
17
PACKAGE DIMENSIONS
Micro8t
CASE 846A−02
ISSUE J
S
B
M
0.08 (0.003) A S
T
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. 846A-01 OBSOLETE, NEW STANDARD 846A-02.
b
e
PIN 1 ID
8 PL
0.038 (0.0015)
−T−
SEATING
PLANE
A
A1 cL
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
DIM
A
MIN NOM MAX MIN
MILLIMETERS
−− −− 1.10 −−
INCHES
A1 0.05 0.08 0.15 0.002
b0.25 0.33 0.40 0.010
c0.13 0.18 0.23 0.005
D2.90 3.00 3.10 0.114
E2.90 3.00 3.10 0.114
e0.65 BSC
L0.40 0.55 0.70 0.016
−− 0.043
0.003 0.006
0.013 0.016
0.007 0.009
0.118 0.122
0.118 0.122
0.026 BSC
0.021 0.028
NOM MAX
4.75 4.90 5.05 0.187 0.193 0.199
HE
HE
DD
E
8X 0.48
0.65
PITCH
5.25
8X
0.80
DIMENSION: MILLIMETERS
RECOMMENDED
TL431A, B Series, NCV431A, B Series, SCV431A
www.onsemi.com
18
PACKAGE DIMENSIONS
SOIC−8
D SUFFIX
CASE 751−07
ISSUE AK
SEATING
PLANE
1
4
58
N
J
X 45 _
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
BS
D
H
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
−X−
−Y−
G
M
Y
M
0.25 (0.010)
−Z−
Y
M
0.25 (0.010) ZSXS
M
____
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
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Micro8 is a trademark of International Rectifier.
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