1. General description
The HEF4069UB-Q100 is a general-purpose hex inverter. Each inverter has a single
stage.
It operates over a recommended VDD power supply r ange of 3 V to 15 V referenced to V SS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Complies with JEDEC standard JESD 13-B
3. Applications
Oscillator
4. Ordering information
HEF4069UB-Q100
Hex inverter
Rev. 2 — 9 September 2014 Product data sheet
Table 1. Ordering information
All types operate from
40
C to +125
C.
Type number Package
Name Description Version
HEF4069UBT-Q100 SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
HEF4069UBTT-Q100 TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
HEF4069UB_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 9 September 2014 2 of 16
NXP Semiconductors HEF4069UB-Q100
Hex inverter
5. Functional diagram
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 1. Functional diagram Fig 2. Schematic diagram (one inv e r ter)
001aag152
1
1A 1Y
2
3
2A 2Y
4
5
3A 3Y
6
9
4A 4Y
8
11
5A 5Y
10
13
6A 6Y
12
001aag154
VDD
VSS
YA
Fig 3. Pin configuratio n
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Table 2. Pin description
Symbol Pin Description
1A to 6A 1, 3, 5, 9, 11, 13 input
1Y to 6Y 2, 4, 6, 8, 10, 12 output
VSS 7 ground (0 V)
VDD 14 supply voltage
HEF4069UB_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 9 September 2014 3 of 16
NXP Semiconductors HEF4069UB-Q100
Hex inverter
7. Limiting values
[1] For SO14 packages: above Tamb = 70 C, Ptot derates linearly with 8 mW/K.
[2] For TSSOP14 packages: above Tamb = 60 C, Ptot derates linearly with 5.5 mW/K.
8. Recommended operating conditions
Table 3. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDD supply voltage 0.5 +18 V
IIK input clamping current VI<0.5 V or VI>V
DD + 0.5 V - 10 mA
VIinput voltage 0.5 VDD + 0.5 V
IOK output clamping current VO<0.5 V or VO>V
DD + 0.5 V - 10 mA
II/O input/output current - 10 mA
IDD supply current - 50 mA
Tstg storage temperature 65 +150 C
Tamb ambient temperature 40 +125 C
Ptot total power dissipation Tamb = 40 C to +125 C
SO14 [1] -500mW
TSSOP14 [2] -500mW
P power dissipation per output - 100 mW
Table 4. Recommended operating con ditions
Symbol Parameter Conditions Min Typ Max Unit
VDD supply voltage 3 - 15 V
VIinput voltage 0 - VDD V
Tamb ambient temperature in free air 40 - +125 C
HEF4069UB_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 9 September 2014 4 of 16
NXP Semiconductors HEF4069UB-Q100
Hex inverter
9. Static characteristics
Table 5. Static characteristics
VSS = 0 V; VI=V
SS or VDD; unless otherwise specified.
Symbol Parameter Conditions VDD Tamb = 40 C Tamb = +25 C Tamb = +8 5 C Tamb = +125 CUnit
Min Max Min Max Min Max Min Max
VIH HIGH-level
input voltage IO<1A5V4-4-4-4-V
10V8-8-8-8-V
15 V 12.5 - 12.5 - 12.5 - 12.5 - V
VIL LOW-level
input voltage IO<1A5V -1-1-1-1V
10V-2-2-2-2V
15 V - 2.5 - 2.5 - 2.5 - 2.5 V
VOH HIGH-level
output voltage IO<1A 5 V 4.95 - 4.95 - 4.95 - 4.95 - V
10 V 9.95 - 9.95 - 9.95 - 9.95 - V
15 V 14.95 - 14.95 - 14.95 - 14.95 - V
VOL LOW-level
output voltage IO<1A 5 V - 0.05 - 0.05 - 0.05 - 0.05 V
10 V - 0.05 - 0.05 - 0.05 - 0.05 V
15 V - 0.05 - 0.05 - 0.05 - 0.05 V
IOH HIGH-level
output current VO = 2.5 V 5 V - 1.7 - 1.4 - 1.1 - 1.1 mA
VO = 4.6 V 5 V - 0.64 - 0.5 - 0.36 - 0.36 mA
VO = 9.5 V 10 V - 1.6 - 1.3 - 0.9 - 0.9 mA
VO = 13.5 V 15 V - 4.2 - 3.4 - 2.4 - 2.4 mA
IOL LOW-level
output current VO = 0.4 V 5 V 0.64 - 0.5 - 0.36 - 0.36 - mA
VO = 0.5 V 10 V 1.6 - 1.3 - 0.9 - 0.9 - mA
VO = 1.5 V 15 V 4.2 - 3.4 - 2.4 - 2.4 - mA
IIinput leakage
current 15 V - 0.1 - 0.1 - 1.0 - 1.0 A
IDD supply current all valid input
combinations;
IO=0A
5 V - 0.25 - 0.25 - 7.5 - 7.5 A
10 V - 0.5 - 0.5 - 15.0 - 15.0 A
15 V - 1.0 - 1.0 - 30.0 - 30.0 A
CIinput
capacitance digital inputs - - - 7.5 - - - - pF
HEF4069UB_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 9 September 2014 5 of 16
NXP Semiconductors HEF4069UB-Q100
Hex inverter
10. Dynamic characteristics
[1] The typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (CL in pF).
Table 6. Dynamic characteristics
Tamb = 25
C; for wavefo rms see Figure 4; for test circuit see Figure 5.
Symbol Parameter Conditions VDD Extrapolation formula[1] Min Typ Max Unit
tPHL HIGH to LOW
propagation delay nA to nY 5 V 18 ns + (0.55 ns/pF)CL-4590ns
10 V 9 ns + (0.23 ns/pF)CL-2040ns
15 V 7 ns + (0.16 ns/pF)CL-1525ns
tPLH LOW to HIGH
propagation delay nA to nY 5 V 13 ns + (0.55 ns/pF)CL-4080ns
10 V 9 ns + (0.23 ns/pF)CL-2040ns
15 V 7 ns + (0.16 ns/pF)CL-1530ns
tTHL HIGH to LOW output
transition time output nY 5 V 10 ns + (1.00 ns/pF)CL- 60 120 ns
10 V 9 ns + (0.42 ns/pF)CL-3060ns
15 V 6 ns + (0.28 ns/pF)CL-2040ns
tTLH LOW to HIGH output
transition time output nY 5 V 10 ns + (1.00 ns/pF)CL- 60 120 ns
10 V 9 ns + (0.42 ns/pF)CL-3060ns
15 V 6 ns + (0.28 ns/pF)CL-2040ns
Table 7. Dynamic power dissipation
VSS = 0 V; tr = tf
20 ns; Tamb = 25
C.
Symbol Parameter VDD Typical formula Where
PDdynamic power dissipation 5 V PD = 600 fi + (fo CL) VDD2 (W) fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
(fo CL) = sum of the outputs;
VDD = supply voltage in V.
10 V PD = 4000 fi + (fo CL) VDD2 (W)
15 V PD = 22000 fi + (fo CL) VDD2 (W)
HEF4069UB_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 9 September 2014 6 of 16
NXP Semiconductors HEF4069UB-Q100
Hex inverter
11. Waveforms
Measurement points: VM = 0.5VDD.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 4. Propagation dela y a nd tran s ition times
001aag185
t
PLH
t
PHL
t
TLH
90 %
10 %
t
THL
t
r
t
f
90 %
10 %
V
M
V
M
input
output
0 V
V
I
V
OH
V
OL
Definitions for test circuit:
CL= load capacitance including jig and probe capacitance;
RT= termination resistance should be equal to the output impedance Zo of the pulse generator;
For test data, refer to Table 8.
Fig 5. Test circuit for measuring switching times
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Table 8. Test data
Supply voltage Input Load
VDD VItr, tfCL
5 V to 15 V VSS or VDD 20 ns 50 pF
HEF4069UB_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 9 September 2014 7 of 16
NXP Semiconductors HEF4069UB-Q100
Hex inverter
11.1 Transfer characteristics
a. VDD = 5 V; IO = 0 A b. VDD = 10 V; IO = 0 A
c. VDD = 15 V; IO = 0 A
(1) VO = output voltage.
(2) ID = drain current.
Fig 6. Typical transfer characteristics
VI (V)
0 5.02.5
001aag159
2.5
5.0
VO
(V) ID
(μA)
0
250
500
0
(2) (2)(1)
VI (V)
0105
001aag160
5
10
VO
(V) ID
(mA)
0
5
10
0
(2) (2)(1)
VI (V)
02010
001aag161
10
20
VO
(V) ID
(mA)
0
10
20
0
(2) (2)(1)
HEF4069UB_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 9 September 2014 8 of 16
NXP Semiconductors HEF4069UB-Q100
Hex inverter
12. Application information
Some examples of applications for the HEF4069UB-Q100.
Figure 7 shows an astable relaxation oscillator using two HEF4069UB-Q100 inverters and
2 BAW62 diodes. The oscillation frequency is mainly determined by R1 C1, provided
R1 << R2 and R2 C2 << R1 C1.
The function of R2 is to minimize the influence of the forward volt age across the protection
diodes on the frequency; C2 is a stray (parasitic) capacitance.
The period Tpis given by Tp=T
1+T
2,
where:
VST = the signal threshold level of the inverter.
The period is fairly independe nt of VDD, VST and temperature. The duty factor , however , is
influenced by VST.
T1R1C1InVDD VST
+
VST
--------------------------=
Fig 7. Astable relaxation oscillator
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HEF4069UB_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 9 September 2014 9 of 16
NXP Semiconductors HEF4069UB-Q100
Hex inverter
Figure 8 shows a crystal oscillator for frequencies up to 10 MHz using two
HEF4069UB-Q100 inverters. The second inverter amplifies the oscillator output voltage to
a level sufficient to drive other Local Oxidation CMOS (LOCMOS) circuits.
Figure 9 and Figure 10 show vo ltage gain and supply current. Figure 11 shows the test
set-up and an example of an analog amplifier using one HEF4069UB-Q100.
The output inverter is used to amplify the oscillator output voltage to a level sufficient to drive other LOCMOS circuits.
Fig 8. Crystal osci ll ator
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Fig 9. Typical voltage gain as a function of
supply voltage Fig 10. Typical supply current as a function of
supply voltage
VDD (V)
015105
001aag156
25
50 typ
75
gain
(VO/VI)
0
001aag157
VDD (V)
015105
10
5
15
20
IDD
(mA)
0
typ
Fig 11. Test set-up
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HEF4069UB_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 9 September 2014 10 of 16
NXP Semiconductors HEF4069UB-Q100
Hex inverter
Figure 12 shows typical forward transconductance and Figure 13 show s the test set-up.
(1) Average +2; where: ‘’ is the standard deviation.
(2) Average.
(3) Average 2; where: ‘’ is the standard deviation.
at VO is constant.
fi.= 1 kHz
Fig 12. Typical for ward transconductance as a
function of supply voltage at Tamb = 25 CFig 13. Test set-up
001aag164
VDD (V)
015105
5.0
2.5
7.5
10
gfs
(mA/V)
0
(1)
(2)
(3)
001aag163
VDD
VSS
input output 100 μF
Rbias = 560 kΩ
0.47 μF
Io
ViA
gfs dIo
dVi
--------
=
HEF4069UB_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 9 September 2014 11 of 16
NXP Semiconductors HEF4069UB-Q100
Hex inverter
13. Package outline
Fig 14. Package outline SOT108-1 (SO14)
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HEF4069UB_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 9 September 2014 12 of 16
NXP Semiconductors HEF4069UB-Q100
Hex inverter
Fig 15. Package outline SOT402-1 (TSSOP14)
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HEF4069UB_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 9 September 2014 13 of 16
NXP Semiconductors HEF4069UB-Q100
Hex inverter
14. Abbreviations
15. Revision history
Table 9. Abbreviations
Acronym Description
HBM Human Body Model
ESD ElectroStatic Discharge
MM Machine Model
MIL Military
Table 10. Revision history
Document ID Release date Data sheet status Change notice Supersedes
HEF4069UB_Q100 v.2 20140909 Product data sheet - HEF4069UB_Q100 v.1
Modifications: •Section 2: ESD protection: MIL-STD-833 changed to MIL-STD883
HEF4069UB_Q100 v.1 20130228 Product data sheet - -
HEF4069UB_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 9 September 2014 14 of 16
NXP Semiconductors HEF4069UB-Q100
Hex inverter
16. Legal information
16.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conf lict with the short data sheet, the
full data sheet shall pre vail.
Product specificatio n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyon d those described in the
Product data sheet.
16.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregat e and cumulative liabil ity towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descripti ons, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless ot herwise agreed in writing, t he product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications an d ther efo re su ch inclusi on a nd/or use is at the cu stome r's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associate d with t heir
applications and products.
NXP Semiconductors does not accept any liabil ity related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the appl ication or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and pro ducts using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress rating s only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby exp ressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the obj ective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specificat ion.
Product [short] dat a sheet Production This document contains the product specification.
HEF4069UB_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 9 September 2014 15 of 16
NXP Semiconductors HEF4069UB-Q100
Hex inverter
No offer to sell or license — Nothing in this document may be interpret ed or
construed as an of fer to sell product s that is op en for accept ance or the grant ,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) versio n of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
16.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors HEF4069UB-Q100
Hex inverter
© NXP Semiconductors N.V. 2014. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 9 September 2014
Document identifier: HEF40 69UB_Q100
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
18. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 1
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
8 Recommended operating conditions. . . . . . . . 3
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
11.1 Transfer characteristics . . . . . . . . . . . . . . . . . . 7
12 Application information. . . . . . . . . . . . . . . . . . . 8
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 13
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13
16 Legal information . . . . . . . . . . . . . . . . . . . . . . . 14
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
17 Contact information. . . . . . . . . . . . . . . . . . . . . 15
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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