5962-9096503MTC(MSC) - MICROSEMI

REVISIONS

LTR DESCRIPTION DATE (YR-MO-DA) APPROVED

A Add device type 02; editorial changes throughout. Redrawn. 93-06-23 M. A. Frye

B Update boilerplate. Add device types 03 and 04. Add case outline M.

Editorial changes throughout.

94-06-30 M. A. Frye

C Add 05 device. Removed some parameters from table IIB. Updated

boilerplate. ksr

98-04-06 Raymond Monnin

D Added equation to footnote 2/, made corrections to table IB. Changed

sample size in paragraph 4.4.1. Removed (Dose Rate Induced latchup

testing) and (Dose Rate Upset testing) paragraphs. Updated

boilerplate. ksr

98-07-10 Raymond Monnin

E Change 1.3 Maximum junction temperature from 175C to 150C.

Added footnote 2/ to Figure 2 for the T and M case outlines. Add die

information per Appendix A. ksr

98-09-21 Raymond Monnin

F Correct bond pad symbol on figure A-1, pad #45 I/O vs GND. Updated

boilerplate. ksr

04-03-08 Raymond Monnin

G Added additional information to footnote 2 on figure 2 Terminal

connections, for case outlines T and M. Added note 3 to figure A-1

A1020B and RH1020 Bond Pad Locations and Functions. ksr

05-05-13 Raymond Monnin

H Added device types 06-09 in section 1.2.2. Added vendor CAGE

1RU44. Added updated RHA requirements in section 1.5 for device

types 06-09. Added Case outline N. Updated SEP limits in Table IB.

Updated boilerplate paragraphs required by the MIL-PRF-38535

requirements. – lhl

11-11-07 Charles F. Saffle

REV

SHEET

REV H H H H H H H H H H H H

SHEET 15 16 17 18 19 20 21 22 23 24 25 26

REV STATUS REV H H H H H H H H H H H H H H

OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14

PMIC N/A PREPARED BY

Tim H. Noh DLA LAND AND MARITIME

COLUMBUS, OHIO 4321 8-3990

http://www.landandmaritime.dla.mil

STANDARD

MICROCIRCUIT

DRAWING

CHECKED BY

Kenneth Rice

THIS DRAWING IS

AVAILABLE

FOR USE BY ALL

APPROVED BY

Tim H. Noh

MICROCIRCUIT, MEMORY, DIGITAL,

CMOS, FIELD PROGRAMMABLE GATE

ARRAY, 2,000 GATES, MONOLITHIC

SILICON

DEPARTMENTS

AND AGENCIES OF THE

DEPARTMENT OF DEFENSE

DRAWING APPROVAL DATE

92-06-23

AMSC N/A

REVISION LEVEL

H

SIZE

A

CAGE CODE

67268

5962-90965

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1. SCOPE

1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and

M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part

or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN.

1.2 PIN. The PIN is as shown in the following example:

5962 - 90965 01 Q X C

| | | | | |

Federal RHA Device Device Case Lead

stock class designator type class outline finish

designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5)

\ / (see 1.2.3)

\/

Drawing number

1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are

marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A

specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.

1.2.2 Device type(s). The device type(s) identify the circuit function as follows:

Device type Generic number Circuit function Bin speed

01 1020A 2000 gate, field programmable gate array 186 ns

02 1020A-1 2000 gate, field programmable gate array 158 ns

03 1020B 2000 gate, field programmable gate array 168.2 ns

04 1020B-1 2000 gate, field programmable gate array 142.9 ns

05 RH1020 2000 gate, field programmable gate array (radiation hardened) 168.2 ns

06 197A805 (RH1020B) 2000 gate, field programmable gate array (radiation hardened) 168.2 ns

07 197A805 (RH1020B) 2000 gate, field programmable gate array (radiation hardened) 168.2 ns

08 197A805 (RH1020B) 2000 gate, field programmable gate array (radiation hardened) 168.2 ns

09 197A805 (RH1020B) 2000 gate, field programmable gate array (radiation hardened) 168.2 ns

1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level

as follows:

Device class Device requirements documentation

M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN

class level B microcircuits in accordance with MIL-PRF-38535, appendix A

Q or V Certification and qualification to MIL-PRF-38535

1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:

Outline letter Descriptive designator Terminals Package style

X CQCC2 - J44 44 J-lead chip carrier

Y CQCC2 - J68 68 J-lead chip carrier

Z CQCC2 - J84 84 J-lead chip carrier

U CMGA15 - P85 84 Pin grid array 1/

T CQCC1 - F84 84 Unformed lead chip carrier

M See figure 1 84 Unformed lead chip carrier

N See figure 1 84 Unformed lead chip carrier

1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix

A for device class M.

1/ Actual number of pins is 85 including one index or orientation pin (C3).

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1.3 Absolute maximum ratings. 2/

DC supply voltage range (VDD) ---------------------------------------------- 0.5 V dc to +7.0 V dc

Input voltage range (VI) -------------------------------------------------------- - 0.5 V dc to VDD + 0.5 V dc

Output voltage range (VO) ---------------------------------------------------- - 0.5 V dc to VDD + 0.5 V dc

I/O source sink current (IIO) --------------------------------------------------- ± 20 mA

Storage temperature range (TSTG) ------------------------------------------ - 65C to +150C

Lead temperature

(soldering, 10 seconds), (device 05) --------------------------------- 300C

Lead temperature

(soldering, 5 seconds), (devices 06 – 09) -------------------------- 250ºC

Thermal resistance, junction-to-case (θJC)

Case outline X, Y, Z, U, T ----------------------------------------------------- See MIL-STD-1835

Case outline M (device types 03-04) --------------------------------------- 10ºC/W 3/

Case outline M and N (device types 05-07) ------------------------------ 3C/W 3/

Case outline N (device types 08-09) --------------------------------------- 2.5C/W 3/

Maximum junction temperature (TJ) --------------------------------------- +150C

1.4 Recommended operating conditions. 4/

Supply voltage (VDD) ------------------------------------------------------------ +4.5 V dc to +5.5 V dc

Case operating temperature range (TC) ---------------------------------- -55C to +125C

1.5 Radiation features.

Maximum total dose available:

Device type 05 (dose rate = 50 – 300 rads (Si)/s) ------------------ 300K rads (Si) 5/

Device type 06-09 (dose rate = 27 rads (Si)/s) ---------------------- 100K rads (Si) 6/

Single event phenomenon (SEP):

Device type 05:

No SEL occurs at an effective LET (see 4.4.4.2) ---------------- ≤ 84 MeV/(mg/cm2)

Device types 06-09:

No SEL occurs at an effective LET (see 4.4.4.2) ---------------- ≤ 120 MeV/(mg/cm2)

Device types 05:

No SEU occurs at an effective LET (see 4.4.4.2) (C-Latch) -- ≤ 13 MeV/(mg/cm2)

No SEU occurs at an effective LET (see 4.4.4.2) (1 MHz clock) ≤ 18.8 MeV/(mg/cm2)

Device types 06-09:

No SEU occurs at an effective LET (see 4.4.4.2) (C-Latch) -- ≤ 3.6 MeV/(mg/cm2)

No SEU occurs at an effective LET (see 4.4.4.2) (1 MHz clock) ≤ 120 MeV/(mg/cm2)

Device types 05:

No SEDR occurs at effective LET (see 4.4.4.2) ------------------ ≤ 40 MeV/(mg/cm2)

Device types 06-09:

No SEDR occurs at effective LET (see 4.4.4.2) ------------------ ≤ 115 MeV/(mg/cm2)

1.6 Digital logic testing for device classes Q and V.

Fault coverage measurement of manufacturing logic tests

(MIL-STD-883, method 5012) --------------------------------------------- 100 percent 7/

2/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the

maximum levels may degrade performance and affect reliability.

3/ When a thermal resistance for this case is specified in MIL-STD-1835 that value shall supersede the value indicated herein.

4/ Power shall be applied to the device only in the following sequences to prevent damage due to excessive currents.

a. Power- up sequence: GND, VDD, Inputs.

b. Power-down: Inputs, VDD, GND.

5/ For device 05, device electrical characteristics are verified for post irradiation levels at 25C per MIL-STD-883, method 1019,

condition A and post 168 hours, 100C, biased anneal.

6/ For device types 06-09, total dose irradiation test performed according to MIL-STD-883, method 1019, condition B.

7/ 100 percent test coverage of blank programmable logic devices.

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2. APPLICABLE DOCUMENTS

2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part

of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the

solicitation or contract.

DEPARTMENT OF DEFENSE SPECIFICATION

MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.

DEPARTMENT OF DEFENSE STANDARDS

MIL-STD-883 - Test Method Standard Microcircuits.

MIL-STD-1835 - Interface Standard For Microcircuit Case Outlines.

DEPARTMENT OF DEFENSE HANDBOOKS

MIL-HDBK-103 - List of Standard Microcircuit Drawings.

MIL-HDBK-780 - Standard Microcircuit Drawings.

(Copies of these documents are available online at https://assist.daps.dla.mil/quicksearch/ or from the Standardization

Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)

2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein.

Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation.

ASTM INTERNATIONAL (ASTM)

ASTM Standard F1192 - Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by

Heavy Ion Irradiation of Semiconductor Devices.

(Applications for copies of ASTM publications should be addressed to: ASTM International, PO Box C700, 100 Barr Harbor

Drive, West Conshohocken, PA 19428-2959; http://www.astm.org.)

JEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC)

JEDEC Standard No. 78 - IC Latch-Up Test.

(Copies of this document are available online at www.jedec.org/ or from JEDEC – Solid State Technology Association, 3103

North 10th Street, Suite 240-S, Arlington, VA 22201).

(Non-Government standards and other publications are normally available from the organizations that prepare or distribute the

documents. These documents also may be available in or through libraries or other informational services.)

2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text

of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless

a specific exemption has been obtained.

3. REQUIREMENTS

3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with

MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The

modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for

device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified

herein.

3.1.1 Microcircuit die. For the requirements of microcircuit die, see appendix A to this document.

3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified

in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.

3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1.

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3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.

3.2.3 Truth table(s).

3.2.3.1 Unprogrammed devices. The truth table or test vectors for unprogrammed devices for contracts involving no altered

item drawing is not part of this drawing. When required in screening (see 4.2 herein) or quality conformance inspection group A,

B, C, D, or E (see 4.4 herein), the devices shall be programmed by the manufacturer prior to test. A minimum of 50 percent of

the total number of logic modules shall be utilized or at least 25 percent of the total logic modules shall be utilized for any altered

item drawing pattern.

3.2.3.2 Programmed devices. The truth table or test vectors for programmed devices shall be as specified by an attached

altered item drawing.

3.2.4 Switching waveform and test circuit. The switching waveform and test circuit shall be as specified on figure 3.

3.2.5 Radiation exposure circuit. The radiation exposure circuit shall be specified on figure 4.

3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the

electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the

full case operating temperature range.

3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical

tests for each subgroup are defined in table IA.

3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be

marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer

has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be

marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be

in accordance with MIL-PRF-38535, appendix A.

3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in

MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.

3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535

listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of

compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see

6.6.2 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of

supply for this drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-

PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.

3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for

device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.

3.8 Notification of change for device class M. For device class M, notification to DLA Land and Maritime-VA of change of

product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing.

3.9 Verification and review for device class M. For device class M, DLA Land and Maritime, DLA Land and Maritime's agent,

and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore

documentation shall be made available onshore at the option of the reviewer.

3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in

microcircuit group number 42 (see MIL-PRF-38535, appendix A).

3.11 Processing options. Since the device is capable of being programmed by either the manufacturer or the user to result in

a wide variety of configurations; two processing options are provided for selection in the contract.

3.11.1 Unprogrammed device delivered to the user. All testing shall be verified through group A testing as defined in 3.2.3.1

and table IIA. It is recommended that users perform subgroups 7 and 9 after programming to verify the specific program

configuration.

3.11.2 Manufacturer-programmed device delivered to the user. All testing requirements and quality assurance provisions

herein, including the requirements of the altered item drawing, shall be satisfied by the manufacturer prior to delivery.

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Table IA. Electrical performance characteristics.

Test Symbol Conditions

-55ºC ≤ TC ≤ +125ºC

4.5 V ≤ VDD ≤ 5.5 V 1/

unless otherwise specified

Group A

subgroups

Device

type

Limits Unit

Min Max

Output low voltage VOL test one output at a time,

VDD = 4.5 V, IOL = 4.0 mA

1, 2, 3 All 0.4

V

Output high voltage VOH test one output at a time,

VDD = 4.5 V, IOH = -3.2 mA

1, 2, 3 All 3.7

Input low voltage VIL 1, 2, 3 01-04 0.8

05-09 -0.3 0.8

Input high voltage VIH 1, 2, 3 01-04 2.0

05-09 2.2 VDD+

0.3

Standby supply current IDD outputs unloaded,

VDD = 5.5 V,

VIN = VDD or GND

1, 2, 3 All 25 mA

Input leakage current IIL V

DD = 5.5 V,

VIN = VDD or GND

1, 2, 3 All -10 10

µA

Output leakage current IOZ V

DD = 5.5 V,

VOUT = VDD or GND

1, 2, 3 All -10 10

Output short circuit

Current

IOS 2/ VOUT = VDD 1, 2, 3 01, 02 20 140

mA

05-09 0 160

VOUT = GND 1, 2, 3 01, 02 -100 -10

05-09 -100 0

I/O terminal capacitance

CI/O See 4.4.1c, f = 1.0 Mhz, VOUT = 0 V 4 All 20 pF

Functional tests FT 3/ VDD = 4.5 V , See 4.4.1e and f 7, 8A, 8B All

Binning circuit delay tPBLH,

tPBHL

See figure 3, VIL = 0 V,

VIH = 3.0 V, VDD = 4.5 V,

VOUT = 1.5 V

4/

9, 10, 11 01

02

03

04

05-09

186

158

168.2

142.9

168.2

ns

Notes:

1/ All tests shall be performed under the worst case condition unless otherwise specified. Device type 05 supplied to this

drawing will meet levels M, D, P, L, R, and F, of irradiation. However, this device type is only tested at the "F" level.

Devices types 06-09 supplied to this drawing will meet levels M, D, P, L, and R, of irradiation. However, device types

06-09 are tested at the "R" level. Pre and post irradiation values are identical unless otherwise specified in

Table IA. When performing post irradiation electrical measurements for any RHA level, TA = +25°C.

2/ VDD = 4.5 V for minimum limits and VDD = 5.5 V for maximum limits. Test one output at a time,

duration of short circuit condition shall not exceed one second. This test for devices 01, 02, 05-09 only.

3/ Devices are functionally tested using a serial scan test method. Data is shifted into the SDI pin and the DCLK pin is

used as a clock. The data is used to drive the inputs of the internal logic and I/O modules, allowing a complete

functional test to be performed. The outputs of the module can be read by shifting out the output response or by

monitoring the PRA and PRB pins. These tests form a part of the manufacturer's test tape and shall be maintained by

the approved source(s) of supply and shall be made available upon request by the preparing or acquiring activity

4/ Binning circuit delay is defined as the input-to-output delay of a special path called the "binning circuit". The binning

circuit shall be programmed into all devices prior to screening. The binning circuit consists of one input buffer plus 16

combinatorial logic modules plus one output buffer. The logic modules are configured as non-inverting buffers and are

connected through programmed antifuses with typical capacitive loading. The input to the binning circuit is pin number

two; the output is pin number 63.

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TABLE IB. SEP test limits. 1/ 2/ 3/

Symbol

Characteristics

Upset Mode

Conditions

Bias

VDD =

Device

Type

Effective

LET no

upset

(MeV-

cm2/mg)

Saturated

X-section

SEL

Single event

latchup

All

TA= 125C

5.5 V 05 <84

N/A

06-09 <120

SEU

Single event

upset

C-Latch

TA = 25C

4.5 V 05 <13 3/ 1.5 x 10-6

cm2/bit

06-09 <3.6 3/ 4.0 x 10-6

cm2/bit

1 MHz Clock

4/

TA = +25C

5.0 V 05 < 18.8

2.5 x 10-7

cm2/device

06-09 < 120 None

Observed

SEDR

5/

Single event

dielectric

(antifuse)

rupture

All

TA=125C

5.5 V 05 <40

N/A

06-09 <115

Notes:

1/ Table IB applies to device types 05-09 only

2/ Verification test per TRB approved test plan.

3/ Threshold LET at 1% saturated X-section is 13 (device type 05) or 3.6 (device types 06-09), and at 10%,

saturated X-section is 25 (device type 05) or 22 (device types 06-09).

4/ Clock upset causes upset in the clocked flip-flops, its rate is proportional to the clock frequency and can be

computed using the following equation:

f x (3x10-8 upset/device-day)

1 MHz

Where f is the clock frequency of interest and 3 x 10-8 (upset/device-day) is the computed rate from the SEU testing data.

5/ Tested at worst case where ions have perpendicular incidence.

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Case outline M

Inches mm Inches mm Inches mm Inches mm

.002 .050 .020 2.67 .120 3.05 .935 23.75

.004 .100 .025 3.05 .130 3.30 .975 24.77

.006 .150 .030 3.30 .160 4.06 1.590 40.39

.008 .200 .035 4.06 .500 12.70 1.620 41.15

.012 .300 .040 12.70 .640 16.26

.014 .360 .105 16.26 .660 16.76

NOTES:

1. Dimensions are in inches.

2. The US government preferred system of measurement is the metric SI system. However, this item was

originally designed using inch-pound units of measurement. In the event of conflict between the metric

and inch-pound units, the inch-pound units shall take precedence.

3. For detail A: Includes lead attach dogleg height and lid height, whichever is greater.

FIGURE 1. Case outline.

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Case outline N

NOTES: 1. Dimensions are in inches.

2. The US government preferred system of measurement is the metric SI system. However, this item was

originally designed using inch-pound units of measurement. In the event of conflict between the metric and

inch-pound units, the inch-pound units shall take precedence.

FIGURE 1. Case outline - Continued.

Symbol Dimension (unit : inch)

Min. Max.

A1 0.030 0.040

A2 0.065 0.085

A3 0.102

b 0.008 0.012

c 0.004 0.008

D/E 1.635

D1/E1 1.560 1.600

D2/E2 0.640 0.660

D3/E3 0.498 (LID) 0.502 (LID)

e 0.0200 0.030

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Device types

01-02 1/

Case outlines

X

Y Case outlines X

Y

Terminal number

Terminal symbol Terminal number Terminal symbol

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

I/O

VDD

I/O

GND

I/O

VDD

I/O

VPP

I/O

GND

I/O

VDD

I/O

GND

CLK or I/O

MODE

I/O

VDD

I/O

GND

I/O

VDD

I/O

VPP

I/O

GND

I/O

35

36

37

38 1/

39 1/

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58 1/

59 1/

60

61

62

63

64

65

66

67

68

VDD

SDI or I/O

DCLK or I/O

PRA or I/O

PRB or I/O

I/O

GND

I/O

- - -

I/O

VDD

I/O

GND

I/O

CLK or I/O

I/O

MODE

VDD

SDI or I/O

DCLK or I/O

PRA or I/O

PRB or I/O

I/O

GND

I/O

1/ PRA and PRB are inverting signals for device types 01 and 02, and non-inverting signals for device types 03, 04, and

05. PRA and PRB are used only for device testing or debugging. In normal operation, all device types exhibit

identical logic on these pins.

FIGURE 2. Terminal connections.

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Device types

01-02 1/ Device types 01-02 1/

Case outline

Z Case outline Z

Terminal number

Terminal symbol Terminal number Terminal symbol

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

I/O

VDD

I/O

NC

I/O

GND

I/O

VDD

I/O

VPP

I/O

GND

I/O

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74 1/

75 1/

76

77

78

79

80

81

82

83

84

I/O

VDD

I/O

GND

I/O

CLK or I/O

I/O

MODE

VDD

I/O

SDI or I/O

DCLK or I/O

PRA or I/O

PRB or I/O

I/O

GND

I/O

1/ PRA and PRB are inverting signals for device types 01 and 02, and non-inverting

signals for device types 03, 04, and 05. PRA and PRB are used only for device testing

or debugging. In normal operation, all device types exhibit identical logic on

these pins.

FIGURE 2. Terminal connections - Continued.

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Device types

01-04 1/ Device types 01-04 1/

Case outline

U Case outline U

Terminal number

Terminal symbol Terminal number Terminal symbol

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11 1/

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10 1/

B11

C1

C2

C3

C5

C6

C7

C10

C11

D1

D2

D10

D11

E1

E2

E3

E9

E10

E11

F1

F2

F3

I/O

PRA or I/O

I/O

NC

I/O

VDD

I/O

GND

I/O

PRB or I/O

SDI or I/O

I/O

Keying pin

I/O

DCLK or I/O

I/O

GND

VDD

MODE

VDD

I/O

F9

F10

F11

G1

G2

G3

G9

G10

G11

H1

H2

H10

H11

J1

J2

J5

J6

J7

J10

J11

K1

K2

K3

K4

K5

K6

K7

K8

K9

K10

K11

L1

L2

L3

L4

L5

L6

L7

L8

L9

L10

L11

CLK or I/O

GND

I/O

VDD

I/O

GND

I/O

VPP

I/O

GND

I/O

VDD

I/O

1/ PRA and PRB are inverting signals for device types 01 and 02, and non-inverting signals for device types 03, 04,

and 05. PRA and PRB are used only for device testing or debugging. In normal operation, all device types

exhibit identical logic on these pins.

FIGURE 2. Terminal connections - Continued.

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Device types

01-09 1/ Device types 01-09 1/

Case outlines

T, M, N Case outlines T, M, N

Terminal number

Terminal symbol Terminal number Terminal symbol

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

NC

I/O

GND

I/O

VDD

I/O

VPP

I/O

GND

I/O

VDD

I/O

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61 2/

62 2/

63 1/

64 1/

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

I/O

GND

I/O

CLK/I/O

I/O

MODE

VDD

I/O

SDI/I/O

DCLK/I/O

PRA/I/O

PRB/I/O

I/O

GND

I/O

VDD

I/O

NC = No internal connection

1/ PRA and PRB are inverting signals for device types 01 and 02, and non-inverting signals for device types 03,

04, 05- 09. PRA and PRB are used only for device testing or debugging. In normal operation, all device types

exhibit identical logic on these pins.

2/ For device types 05-09 only. The special function pins 61(SDI_I/O) and 62 (DCLK_I/O) have shown anomalous

operation when configured as outputs. Designers should ensure that these pins are unused as I/Os or, if

necessary, they can be used as inputs only. Please contact vendor for complete details on product

advisory and the availability of devices devoid of this anomaly.

FIGURE 2. Terminal connections - Continued.

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FIGURE 3. Switching waveforms and test circuit.

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Total dose ionization test circuits

Note: Resistors are 1kΩ resistors.

FIGURE 4. Radiation exposure circuit.

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4. VERIFICATION

4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with

MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan

shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in

accordance with MIL-PRF-38535, appendix A.

4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted

on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in

accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.

4.2.1 Additional criteria for device class M.

a. Delete the sequence specified as initial (pre burn-in) electrical parameters through interim (post burn-in)

electrical parameters of method 5004 and substitute lines 1 through 6 of table IIA herein.

b. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made

available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases,

and power dissipation, as applicable, in accordance with the intent specified in method 1015.

(1) Dynamic burn-in for device class M (method 1015 of MIL-STD-883, test condition D; for circuit, see 4.2.1b

herein).

c. Interim and final electrical test parameters shall be as specified in table IIA herein.

4.2.2 Additional criteria for device classes Q and V.

a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the

device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained

under document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance

with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit

shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified

in method 1015 of MIL-STD-883.

b. Interim and final electrical test parameters shall be as specified in table IIA herein.

c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in appendix

B of MIL-PRF-38535.

d. Additional screening for device types 07, 09 shall include:

(1) 100% X-ray per MIL-STD-883, method 2012

(2) Increased burn-in (240 hours) dynamic burn-in

(3) interim room temperature electrical test

(4) 144 hours static burn-in with tightened class V PDA

4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in

accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups

A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).

4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with

MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for

device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed

for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections

(see 4.4.1 through 4.4.4).

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4.4.1 Group A inspection.

a. Tests shall be as specified in table IIA herein.

b. Subgroups 5 and 6 of table IA of method 5005 of MIL-STD-883 shall be omitted.

c. Subgroup 4 (CI and CO measurements) shall be measured only for initial qualification and after any process or

design changes which may affect input or output capacitance. A sample size of 5 devices with no failures, and all

input and output terminals shall be required.

d. O/V (latch-up) tests shall be measured only for initial qualification and after any design or process changes which

may affect the performance of the device. For device class M, procedures and circuits shall be maintained under

document revision level control by the manufacturer and shall be made available to the preparing activity or acquiring

activity upon request. For device classes Q and V, the procedures and circuits shall be under the control of the

device manufacturer's TRB in accordance with MIL-PRF-38535 and shall be made available to the preparing activity

or acquiring activity upon request. Testing shall be on all pins, on five devices with zero failures. Latch-up test shall

be considered destructive. Information contained in JEDEC Standard EIA/JESD78 may be used for reference.

e. Programmed device (see 3.2.3.2) - For device class M, subgroups 7, 8A, and 8B tests shall consist of verifying the

functionality of the device. For device classes Q and V, subgroups 7, 8A, and 8B shall include verifying the

functionality of the device. These tests shall have been fault graded in accordance with MIL-STD-883, method 5012

(see 1.6 herein).

f. Unprogrammed devices shall be tested for programmability and dc and ac performance compliance to the

requirements of group A, subgroups 1 and 7.

(1) A sample shall be selected from each wafer lot to satisfy programmability requirements. Eight devices shall

be submitted to programming (see 3.2.3.1). If any device fails to program, the lot shall be rejected. At the

manufacturer's option, the sample may be increased to 18 total devices with no more than two total device

failures allowable.

(2) These eight devices shall also be submitted to the requirements of the specified tests of group A, subgroups 1

and 7. If any device fails, the lot shall be rejected. At the manufacturer's option, the sample may be increased

to 18 total devices with no more than two total device failures allowable.

(3a) Eight devices from the programmability sample shall be submitted to the requirements of group A, subgroups

9 for binning circuit delay only. If any device fails, the lot shall be rejected. At the manufacturer's option, the

sample may be increased to 18 total devices with no more than two total device failures allowable.

(3b) If the binning circuit is tested on 100 percent of the products, then the above requirement is met.

4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.

4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883:

a. Test condition D. The test circuit shall be maintained by the manufacturer under document revision level control and

shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs,

outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005.

b. TA = +125°C, minimum.

c. Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.

4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,

or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The

test circuit shall be maintained under document revision level control by the device manufacturer's TRB, in accordance with MIL-

PRF-38535, and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the

inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-

STD-883.

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4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein.

4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured

(see 3.5 herein).

a. End-point electrical parameters shall be as specified in table IIA herein.

b. For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as

specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to

radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All device

classes must meet the postirradiation end-point electrical parameter limits as defined in table I at TA = +25C 5C,

after exposure, to the subgroups specified in table IIA herein.

4.4.4.1 Total dose irradiation testing. For device type 05, total dose irradiation testing shall be performed in accordance with

MIL-STD-883 method 1019 condition A, see 1.5 herein. For device types 06-09, total dose irradiation testing shall be performed

in accordance with MIL-STD-883 method 1019 condition B, see 1.5 herein.

4.4.4.1.1 Accelerated aging test. Accelerated aging tests shall be performed on all devices requiring a RHA level greater

than 5k rads(Si). The post-anneal end-point electrical parameter limits shall be as specified in table IA herein and shall be the

pre-irradiation end-point electrical parameter limit at +25ºC ± 5ºC. Testing shall be performed at initial qualification and after any

design or process changes which may affect the RHA response of the device.

4.4.4.2 Single event phenomena (SEP). When specified in the purchase order or contract, SEP testing shall be performed on

class V devices. SEP testing shall be performed on the Standard Evaluation Circuit (SEC) or alternate SEP test vehicle as

approved by the qualifying activity at initial qualification and after any design or process changes which may affect the upset or

latchup characteristics. Test four devices with zero failures. ASTM F1192 may be used as a guideline when performing SEP

testing. The test conditions for SEP are as follows:

a. The ion beam angle of incidence shall be between normal to the die surface and 60º to the normal, inclusive

(i.e. 0º≤ angle ≤ 60º). No shadowing of the ion beam due to fixturing or package related effects is allowed.

b. The fluence shall be ≥ 100 errors or ≥ 107 ions/cm2.

c. The flux shall be between 102 and 105 ions/cm2. The cross-section shall be verified to be flux independent by

measuring the cross-section at two flux rates which differ by at least an order of magnitude.

d. The particle range shall be > 20 microns in silicon.

e. The upset test temperature shall be +25ºC. The latchup test temperature shall be at the maximum rated operating

temperature ±10ºC.

f. Bias conditions shall be defined by the manufacturer for latchup measurements.

g. For SEP test limits, see table IB herein.

h. Supply current and voltage(s) as well as SEU, SEL and faults are monitored and recorded in-situ.

4.5 Delta measurements for device class V. Delta measurements, as specified in table IIA, shall be made and recorded

before and after the required burn-in screens and steady-state life tests to determine delta compliance. The electrical

parameters to be measured, with associated delta limits are listed in table IIB. The device manufacturer may, at his option,

either perform delta measurements or within 24 hours after burn-in perform final electrical parameter tests, subgroups 1, 7,

and 9.

4.6 Programming procedures. The programming procedures shall be as specified by the device manufacturer and shall be

made available upon request.

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TABLE IIA. Electrical test requirements. 1/ 2/ 3/ 4/ 5/ 6/ 7/

Line

no.

Test requirements

Subgroups

(in accordance with

MIL-STD-883,

TM 5005, table I)

Subgroups

(in accordance with

MIL-PRF-38535, table III)

Device

class M

Device

class Q

Device

class V

1 Interim electrical

parameters (see 4.2)

1, 7, 9 1, 7, 9

2 Static burn-in I and II

(method 1015)

Not

required

Not

required

Required

3 Same as line 1

1*, 7* 6/

4 Dynamic burn-in

(method 1015)

Required Required Required

5 Same as line 1 1*, 7* 6/

6 Final electrical

parameters

1*, 2, 3, 7*, 8A,

8B, 9, 10, 11

1*, 2, 3, 7*, 8A,

8B, 9, 10, 11

1*, 2, 3, 7*, 8A,

8B, 9, 10, 11

7 Group A test

requirements

1, 2, 3, 4**, 7,

8A, 8B, 9, 10, 11

1, 2, 3, 4**, 7,

8A, 8B, 9, 10, 11

1, 2, 3, 4**, 7,

8A, 8B, 9, 10, 11

8 Group C end-point

electrical parameters

2, 3, 7,

8A, 8B

2, 3, 7,

8A, 8B

1, 2, 3, 7, 8A,

8B, 9, 10, 11 6/

9 Group D end-point

electrical parameters

2, 3, 8A, 8B

10 Group E end-point

electrical parameters

(see 4.4)

1, 7, 9

1/ Blank spaces indicate tests are not applicable.

2/ Any or all subgroups may be combined when using high-speed testers.

3/ Subgroups 7, 8A, and 8B functional tests shall verify the functionality for unprogrammed devices or that the altered

item drawing pattern exists for programmed devices.

4/ * indicates PDA applies to subgroup 1 and 7.

5/ ** see 4.4.1c.

6/ Delta limit (see table IIB) shall be required where specified, and the delta values shall be computed with reference

to the previous interim electrical parameters (see line 1).

7/ See 4.4.1d.

TABLE IIB. Delta limits at +25C.

Test 1/ Device types

All

IDD ±1.0 mA 2/

IOZ ±2.0 μA 2/

tPBLH, tPBHL ±10 ns

1/ The parameters shall be recorded before and after the required

burn-in and life test to determine the delta.

2/ If device is tested at or below 35 µA, then no deltas are required.

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5. PACKAGING

5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes

Q and V or MIL-PRF-38535, appendix A for device class M.

6. NOTES

6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications

(original equipment), design applications, and logistics purposes.

6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor

prepared specification or drawing.

6.1.2 Substitutability. Device class Q devices will replace device class M devices.

6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for

the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.

6.3 Record of users. Military and industrial users should inform DLA Land and Maritime-VA when a system application

requires configuration control and which SMD's are applicable to that system. DLA Land and Maritime-VA will maintain a record

of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering

microelectronic devices (FSC 5962) should contact DLA Land and Maritime-VA, telephone (614) 692-0544.

6.4 Comments. Comments on this drawing should be directed to DLA Land and Maritime-VA, Columbus, Ohio 43218-3990,

or telephone (614) 692-0540.

6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in MIL-PRF-

38535 and MIL-HDBK-1331.

6.5.1 Timing limits. The table of timing values shows either a minimum or a maximum limit for each parameter. Input

requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the

system must supply at least that much time (even though most devices do not require it). On the other hand, responses from

the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never

provides data later than that time.

6.5.2 Waveforms.

Waveform

symbol

Input

Output

MUST BE VALID

WILL BE VALID

CHANGE FROM

H TO L

WILL CHANGE

FROM H TO L

CHANGE FROM

L TO H

WILL CHANGE

FROM L TO H

DON'T CARE

ANY CHANGE

PERMITTED

CHANGING

STATE UNKNOWN

HIGH IMPEDANCE

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6.6 Sources of supply.

6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.

The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DLA Land and Maritime-VA and

have agreed to this drawing.

6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103.

The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been

submitted to and accepted by DLA Land and Maritime-VA.

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Appendix A

Appendix A forms a part of SMD 5962-90965

A.1 Scope

A.1.1 Scope. This appendix establishes minimum requirements for microcircuit die to be supplied under the Qualified

Manufacturers List (QML) Program. QML microcircuit die meeting the requirements of MIL-PRF-38535 and the manufacturers

approved QML plan for use in monolithic microcircuits, multichip modules (MCMs), hybrids, electronic modules, or devices using

chip and wire designs in accordance with MIL-PRF-38534 are specified herein. Two product assurance classes consisting of

military high reliability (device class Q) and space application (device Class V) are reflected in the Part or Identification Number

(PIN). When available a choice of Radiation Hardiness Assurance (RHA) levels are reflected in the PIN.

A.1.2 PIN. The PIN is as shown in the following example:

5962 F 90965 03 Q 9 A

| | | | | |

Federal RHA Device Device Die Die

stock class designator type class Code details

designator (A.1.2.1) (see A.1.2.2) (see A.1.2.3) (see A.1.2.4) (see A.1.2.5)

\_____________________/

V

Drawing number

A.1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and

are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.

A.1.2.2 Device type(s). The device type(s) shall identify the circuit function as follows:

Device type Generic number Circuit function Bin speed

03 1020B 2000 gate, field programmable gate array 168.2 ns

05 RH1020 2000 gate, field programmable gate array 168.2 ns

A.1.2.3 Device class designator. The device class designator shall be a single letter identifying the product assurance level as

follows:

Device class Device requirements documentation

Q or V Certification and qualification to MIL-PRF-38535

A.1.2.4 Die code. The die code designator shall be a number 9 for all devices supplied as die only with no case outline.

A.1.2.5 Die details. The die details designation shall be a unique letter which designates the die’s physical dimensions,

bonding pad location(s) and related electrical function(s), interface materials, and other assembly related information, for each

product and variant supplied to this appendix.

A.1.2.5.1 Die physical dimensions.

Device type Die size Die thickness Die Detail Figure Number

03 254 mils X 267 mils 15±1 mils A A-1

05 254 mils X 267 mils 25±1 mils B A-1

A.1.2.5.2 Die bonding pad locations and electrical functions.

Device type Die Detail Figure Number

03 A A-1

05 B A-1

A.1.2.5.3 Interface materials.

Device type Top metalization Backside metalization Die Detail Figure Number

03 Ti-cap+Al/Cu/Si,9-12kA None (backgrind) A A-1

05 TiW+Al/Cu,9-12kA None (backgrind) B A-1

A.1.2.5.4 Assembly related information.

Device type Glassivation Die Detail Figure Number

03 Ox/Nitride A A-1

05 Ox/Nitride/Polyimide B A-1

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Appendix A

Appendix A forms a part of SMD 5962-90965

A.1.3 Absolute maximum ratings.

See paragraph 1.3 within the body of this drawing for details.

A.1.4 Recommended operating conditions.

See paragraph 1.4 within the body of this drawing for details.

A.2 APPLICABLE DOCUMENTS.

A.2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a

part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in

the solicitation or contract.

DEPARTMENT OF DEFENSE SPECIFICATION

MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.

DEPARTMENT OF DEFENSE STANDARD

MIL-STD-883 - Test Method Standard Microcircuits.

DEPARTMENT OF DEFENSE HANDBOOK

MIL-HDBK-103 - List of Standard Microcircuit Drawings (SMD's).

(Copies of these documents are available online at https://assist.daps.dla.mil/quicksearch/ or from the Standardization

Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)

A.2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text

of this drawing shall take precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a

specific exemption has been obtained.

A.3 REQUIREMENTS.

A.3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-

38535 and as specified herein or as modified in the device manufacturer’s Quality Management (QM) plan. The Modification in

the QM plan shall not effect the form, fit or function as described herein.

A.3.2 Design, construction and physical dimensions. The design, construction and physical dimensions shall be as specified

in MIL-PRF-38535 and the manufacturer’s QM plan, for device classes Q and V and herein.

A.3.2.1 Die physical dimensions. The die physical dimensions shall be specified in A.1.2.5.1 and on figure A-1.

A.3.2.2 Die bonding pad locations and electrical functions. The die bonding pad locations and electrical functions shall be as

specified in A.1.2.5.2 and figure A-1.

A.3.2.3 Interface materials. The interface materials for the die shall be as specified in A.1.2.5.3 and on figure A-1.

A.3.2.4 Assembly related information. The assembly related information shall be as specified in A.1.2.5.4 and figure A-1.

A.3.2.5 Truth table(s). Where technically applicable, (for die) the truth table(s) shall be as defined within paragraph 3.2.3 of

the body of this document.

A.3.2.6 Radiation exposure circuit. The radiation exposure circuit will be as specified on figure 4 as shown within the body of

this document.

A.3.3 Electrical performance characteristics and post-irradiation parameter limits. Unless otherwise specified herein, the

electrical performance characteristics and post-irradiation parameter limits are as specified in table IA of the body of this

document.

STANDARD

MICROCIRCUIT DRAWING

SIZE

A

5962-90965

DLA LAND AND MARITIME

COLUMBUS, OHIO 43218-3990

REVISION LEVEL

H

SHEET

24

DSCC FORM 2234

APR 97

Appendix A

Appendix A forms a part of SMD 5962-90965

A.3.4 Electrical test requirements. The wafer probe test requirements shall include functional and parametric testing

sufficient to make the packaged die capable of meeting the electrical performance requirements in table IA.

A.3.5 Marking. As a minimum, each unique lot of die, loaded in single or multiple stack of carriers, for shipment to a

customer, shall be identified with the wafer lot number, the certification mark, the manufacturer’s identification and the PIN listed

in A.1.2 herein. The certification mark shall be “QML” or “Q” as required by MIL-PRF-38535.

A.3.6 Certification of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-

38535 listed manufacturer in order to supply to the requirements of this drawing (see A.6.4 herein). The certificate of

compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this appendix shall

affirm that the manufacturer’s product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and the

requirements herein.

A.3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535

shall be provided with each lot of microcircuit die delivered to this drawing.

A.3.8 Processing options. Since the device is capable of being programmed by either the manufacturer or the user to result in

a wide variety of configurations; two processing options are provided for selection in the contract, using an altered item drawing.

A.3.8.1 Unprogrammed die delivered to the user. All testing shall be verified through wafer probe test as defined in A.4.2.

A.3.8.2 Manufacturer-programmed die delivered to the user. The programming integrity test shall be performed during

programming. It is recommended that users perform subgroups 7 and 9 after programming to verify the specific program

configuration.

A.4 VERIFICATION

A.4.1 Sampling and inspection. For device classes Q and V, die sampling and inspection procedures shall be in accordance

with MIL-PRF-38535 or as modified in the device manufacturer’s Quality Management (QM) plan. The modification in the QM

plan shall not affect the form, fit, or function as described herein.

A.4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and as defined in the

manufacturer’s QM plan. As a minimum it shall consist of:

a) Wafer lot acceptance for Class V product using the criteria within MIL-STD-883 method 5007.

b) 100% wafer probe (see paragraph A.3.4)

c) 100% internal visual inspection to the applicable class Q or V criteria defined within MIL-STD-883 method 2010 or the

alternate procedures allowed within MIL-STD-883 method 5004.

A.4.3 Conformance inspection.

A.4.3.1 Group E inspection. Group E inspection is required only for parts intended to be identified as radiation assured (see

A.3.5 herein). RHA levels for device classes Q and V shall be as specified in MIL-PRF-38535. End point electrical testing of

packaged die shall be as specified in table IIA herein. Group E tests and conditions are as specified within paragraphs 4.4.4,

4.4.4.1, 4.4.4.1.1, and 4.4.4.2 herein.

A.5 DIE CARRIER

A.5.1 Die carrier requirements. The requirements for the die carrier shall be accordance with the manufacturer’s QM plan or

as specified in the purchase order by the acquiring activity. The die carrier shall provide adequate physical, mechanical and

electrostatic protection.

A.6 NOTES

A.6.1 Intended use. Microcircuit die conforming to this drawing are intended for use in microcircuits built in accordance with

MIL-PRF-38535 or MIL-PRF-38534 for government microcircuit application (original equipment), design applications and

logistics purposes.

A.6.2 Comments. Comments on this appendix should be directed to DLA Land and Maritime-VA, Columbus, Ohio, 43218-

3990 or telephone (614)-692-0540.

A.6.3 Abbreviations, symbols and definitions. The abbreviations, symbols, and definitions used herein are defined within

MIL-PRF-38535 and MIL-HDBK-1331.

A.6.4 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.

The vendors listed within QML-38535 have submitted a certificate of compliance (see A.3.6 herein) to DLA Land and Maritime-

VA and have agreed to this drawing.

STANDARD

MICROCIRCUIT DRAWING

SIZE

A

5962-90965

DLA LAND AND MARITIME

COLUMBUS, OHIO 43218-3990

REVISION LEVEL

H

SHEET

25

DSCC FORM 2234

APR 97

Appendix A

Appendix A forms a part of SMD 5962-90965

Pad#

Name

X-Coord Y-Coord Pad# Name

X

-Coord

Y-Coord

1

I/O

-2922 2964 45 I/O 2920

-1745

2

I/O

-2922 2259 46 I/O 2920

-1489

3

I/O

-2922 2003 47 I/O 2920

-1248

4

I/O

-2922 1747 48 I/O 2920

-1082

5

I/O

-2922 1491 49 GND 2920

-839

6

I/O

-2922 1251 50 GND 2920

-521

7

GND

-2922 992 51 I/O 2920

-278

8

GND

-2922 674 52 I/O 2920

-112

9

I/O

-2922 431 53 I/O, CLK 2920

55

10

I/O

-2922 265 54 I/O 2920

297

11

I/O

-2922 98 55 MODE 2920

463

12

I/O

-2922 -68 56 VCC 2920

706

13

I/O

-2922 -253 57 VCC 2920

1024

14

VCC

-2922 -495 58 I/O 2920

1267

15

VCC

-2922 -814 59 I/O 2920

1433

16

I/O

-2922 -1056 60 I/O 2920

1674

17

I/O

-2922 -1223 61 I/O, SDI 2920

1930

18

I/O

-2922 -1489 62 I/O, DCLK 2920

2186

19

I/O

-2922 -1745 63 I/O, PRA 2920

2442

20

I/O

-2922 -2001 64 GND 2921

2964

21

I/O

-2922 -2257 65 I/O, PRB 2041

3087

22

VPP, VCC

-2788 -2987 66 I/O 1830

3087

23

I/O

-1912 -3085 67 I/O 1603

3087

24

I/O

-1685 -3085 68 I/O 1372

3087

25

I/O

-1459 -3085 69 I/O 1146

3087

26

I/O

-1233 -3085 70 I/O 979

3087

27

I/O

-997 -3085 71 I/O 813

3087

28

I/O

-830 -3085 72 GND 570

3087

29

GND

-588 -3085 73 I/O 328

3087

30

I/O

-345 -3085 74 I/O 161

3087

31

I/O

-179 -3085 75 I/O -5

3087

32

I/O

--13 -3085 76 I/O -172

3087

33

I/O

154 -3085 77 I/O -338

3087

34

I/O

320 -3085 78 VCC -580

3087

35

VCC

578 -3085 79 I/O -823

3087

36

I/O

820 -3085 80 I/O -989

3087

37

I/O

987 -3085 81 I/O -1233

3087

38

I/O

1222 -3085 82 I/O -1459

3087

39

I/O

1449 -3085 83 I/O -1685

3087

40

I/O

1680 -3085 84 I/O -1912

3087

41

I/O

1907 -3085

42

I/O

2920 -2962

43

I/O

2920 -2257

44

I/O

2920 -2001

NOTES:

1. The center of X-Y coordinate is at the center of the die.

2. All dimensions are in µm.

3. For device type 05 only. The special function pins 61(SDI_I/O) and 62 (DCLK_I/O) have shown anomalous

operation when configured as outputs. Designers should ensure that these pins are unused as I/Os or, if

necessary, they can be used as inputs only. Please contact vendor for complete details on product advisory

and the availability of devices devoid of this anomaly.

Figure A-1. A1020B and RH1020 Bond Pad Locations and Functions.

STANDARD

MICROCIRCUIT DRAWING

SIZE

A

5962-90965

DLA LAND AND MARITIME

COLUMBUS, OHIO 43218-3990

REVISION LEVEL

H

SHEET

26

DSCC FORM 2234

APR 97

Appendix A

Appendix A forms a part of SMD 5962-90965

Figure A-1. A1020B and RH1020 Bond Pad Locations and Functions - Continued.

STANDARDIZED MILITARY DRAWING SOURCE APPROVAL BULLETIN

DATE: 11-11-07

Approved sources of supply for SMD 5962-90965 are listed below for immediate acquisition information only and

shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be

revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a

certificate of compliance has been submitted to and accepted by DLA Land and Maritime-VA. This information

bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. DLA Land and Maritime

maintains an online database of all current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/.

Standard

microcircuit drawing

PIN 1/

Vendor

CAGE

number

Vendor

similar

PIN 2/

5962-9096501MXA 3/ A1020A-JQ44B

5962-9096501MYA 3/ A1020A-JQ68B

5962-9096501MZA 3/ A1020A-JQ84B

5962-9096501MUC 3/

3/

A1020A-PG84B

TPC1020AMGB84B

5962-9096501MTC 3/

3/

A1020A-CQ84B

TPC1020AMHT84B

5962-9096501MMC 3/ TPC1020AMHFG84B

5962-9096502MXA 3/ A1020A-1-JQ44B

5962-9096502MYA 3/ A1020A-1-JQ68B

5962-9096502MZA 3/ A1020A-1-JQ84B

5962-9096502MUC 3/

3/

A1020A-1-PG84B

TPC1020AMGB84B-1

5962-9096502MTC 3/

3/

A1020A-1-CQ84B

TPC1020AMHT84B-1

5962-9096502MMC 3/ TPC1020AMHFG84B-1

5962-9096503MUA 0J4Z0 A1020B-PG84B

5962-9096503MUC 0J4Z0 A1020B-PG84B

5962-9096503MTA 0J4Z0 A1020B-CQ84B

5962-9096503MTC 0J4Z0 A1020B-CQ84B

5962-9096503MMC 3/ A1020B-CQ84B

5962-9096503Q9A 3/ A1020B-DIE

5962-9096504MUA 0J4Z0 A1020B-1PG84B

See notes at end of table.

Page 1 of 2

STANDARDIZED MILITARY DRAWING SOURCE APPROVAL BULLETIN – continued.

DATE: 11-11-07

Standard

microcircuit drawing

PIN 1/

Vendor

CAGE

number

Vendor

similar

PIN 2/

5962-9096504MUC 0J4Z0 A1020B-1PG84B

5962-9096504MTA 0J4Z0 A1020B-1CQ84B

5962-9096504MTC 0J4Z0 A1020B-1CQ84B

5962-9096504MMC 3/ A1020B-1CQ84B

5962F9096505QTC 3/ RH1020-CQ84V

5962F9096505Q9B 3/ RH1020-DIE

5962R9096506QTC 1RU44 197A805-25

5962R9096506VTC 1RU44 197A805-21

5962R9096507QTC 1RU44 197A805-24

5962R9096508QNC 1RU44 197A805-35

5962R9096508VNC 1RU44 197A805-31

5962R9096509QNC 1RU44 197A805-34

1/ The lead finish shown for each PIN representing a hermetic package

is the most readily available from the manufacturer listed for that

part. If the desired lead finish is not listed contact the vendor to

determine its availability.

2/ Caution. Do not use this number for item acquisition. Items acquired

to this number may not satisfy the performance requirements

of this drawing.

3/ Not available from an approved source.

Vendor CAGE Vendor name

number and address

0J4Z0 Microsemi

2061 Stierlin Court.

Mountain View, CA 94043

1RU44 BAE Systems

9300 Wellington Road

Manassas, VA 20110-4122

The information contained herein is disseminated for convenience only and the

Government assumes no liability whatsoever for any inaccuracies in the

information bulletin.

Page 2 of 2