CY2544/CY2548, CY2546
Quad PLL Programmable Clock Generator
with Spread Spectrum
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 001-12563 Rev. *G Revised December 21, 2010
Quad PLL Prog rammable Clock G enerator
Features
■Four fully integrated phase locked loops (PLLs)
■Input frequency range
❐External crystal: 8 to 48 MHz for CY2544 and CY2546
❐External reference: 8 to 166 MHz clock
■Reference clock input voltage range
❐2.5V, 3.0V, and 3.3V for CY2548
❐1.8V for CY2544 and CY2546
■Wide operating output frequency range
❐3 to 166 MHz
■Programmable spread spectrum with center and down
spread option and Lexmark and Linear modulation profiles
■VDD supply voltage options:
❐2.5V, 3.0V, and 3.3V for CY2544 and CY2548
❐1.8V for CY2546
■Selectable output clock voltages:
❐2.5V, 3.0V, and 3.3V for CY2544 and CY2548
❐1.8V for CY2546
■Frequency select feature with option to select eight different
frequencies over nine clock outputs
■Power down, output enable, and SS ON/OFF controls
■Low jitter, high accuracy outputs
■Ability to synthesize nonstandard frequencies with
Fractional-N capability
■Up to nine clock outputs with programmable drive strength
■Glitch free outputs while frequency switching
■24-pin QFN package
■Commercial and Industrial temperature ranges
Benefits
■Multiple high performance PLLs allow synthesis of unrelated
frequencies
■Nonvolatile programming for personalization of PLL
frequencies, spread spectrum characteristics, drive strength,
crystal load capacitance, and output frequencies
■Application specific programmable EMI reduction using
spread spectrum for clocks
■Programmable PLLs for system frequency margin tests
■Meets critical timing requirements in complex system
designs
■Suitability for PC, consumer, portable, and networking
applications
■Capable of Zero PPM frequency synthesis error
■Uninterrupted system operation during clock frequency
switch
■Application compatibility in standard and low power systems
OSC PLL1
PLL2
PLL3
(SS)
PLL4
(SS)
Output
Dividers
and
Drive
Strength
Control
CLK1
CLK9
CLK8
CLK7
CLK6
CLK5
CLK4
CLK3
CLK2
CLKIN
FS 2
FS 1
FS 0
SSON
XOUT
XIN/
EXCLKIN
PD#/OE
Bank
1
Bank
3
Bank
2
MUX
and
Control
Logic
Crossbar
Switch
Logic Block Diagram
[+] Feedback
CY2544/CY2548, CY2546
Document #: 001-12563 Rev. *G Page 2 of 16
Contents
General Description ......................................................... 5
Four Configurable PLLs .............................................. 5
Input Reference Clocks ............................................... 5
Multiple Power Supplies .............................................. 5
Output Bank Settings ..................................................5
Output Source Selection ............................................. 5
Spread Spectrum Control ............................................ 5
Frequency Select ........................................................ 6
Glitch-Free Frequency Switch ..................................... 6
PD#/OE Mode .............................................................6
Output Drive Strength ..................................................6
Generic Configuration and Custom Frequency ........... 6
Absolute Maximum Conditions .......................................7
Recommended Operating Conditions ............................ 7
DC Electrical Specifications ............................................8
AC Electrical Specifications ............................................9
Recommended Crystal Specification for SMD Package 9
Test and Measurement Setup ........................................ 10
Voltage and Timing Definitions ..................................... 10
Recommended Crystal Specification for
Thru-Hole Package ......................................................... 10
Ordering Information ...................................................... 11
Possible Configurations ............................................. 11
Ordering Code Definition ........................................... 12
Package Drawing and Dimensions ............................... 13
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 16
Worldwide Sales and Design Support ....................... 16
Products .................................................................... 16
PSoC Solutions ......................................................... 16
[+] Feedback
CY2544/CY2548, CY2546
Document #: 001-12563 Rev. *G Page 3 of 16
Table 1. Device Selection Guide
Figure 1. Pin Diagram – CY2544/CY2548 24 LD QFN
Device Crystal Input EXCKLKIN Input CLKIN Input VDD VDD_CLK_BX
CY2544 Yes 1.8 V LVCMOS 2.5 V, 3.0 V, 3.3 V LVCMOS 2.5 V, 3.0 V, 3.3 V 2.5 V, 3.0 V, 3.3 V
CY2546 Yes 1.8 V LVCMOS 1.8 V LVCMOS 1.8 V 1.8 V
CY2548 No 2.5 V, 3.0 V, 3.3 V LVCMOS 2.5 V, 3.0 V, 3.3 V LVCMOS 2.5 V, 3.0 V, 3.3 V 2.5 V, 3.0 V, 3.3 V
CLKIN
CLK1
PD#OE
CY2544
24 23 22 21 20 19
18
17
16
15
14
13
1
2
3
4
5
6
7 8 9 10 11 12
GND
GND
VDD_CLK_B1
NC
CLK2
OE/FS1
CLK3/FS0
CLK4/FS2
CLK5
GND
CLK6
VDD_CLK_B
2
CLK7/SSON
VDD_CLK_B
3
CLK8
GND
CLK9
VDD
XOUT
XIN/
EXCLKIN
GND
24LD QFN
CLKIN
CLK1
PD#OE
CY2548
24 23 22 21 20 19
18
17
16
15
14
13
1
2
3
4
5
6
7 8 9 10 11 12
GND
GND
VDD_CLK_B1
NC
CLK2
OE/FS1
CLK3/FS0
CLK4/FS2
CLK5
GND
CLK6
VDD_CLK_B
2
CLK7/SSON
VDD_CLK_B
3
CLK8
GND
CLK9
VDD
DNU
EXCLKIN
GND
24LD QFN
Table 2. Pin Definition – CY2544/CY2548 (VDD = 2.5 V, 3.0 V or 3.3 V Supply)
Pin Number Name IO Description
1 GND Power Power supply ground
2 CLK1 Output Programmable clock output. Output voltage depends on VDD_CLK_B1 voltage
3 VDD_CLK_B1 Power Power supply for bank1, (CLK1, CLK2, CLK3) Outputs: 2.5 V/3.0 V/3.3 V
4 PD#/OE Input Multifunction programmable pin. Output enable or power-down mode
5NC NCNo Connect
6 CLK2 Output Programmable Clock Output. Output voltage depends on VDD_CLK_B1
voltage
7 GND Power Power supply ground
8CLK3/FS0 Output/input Multifunction programmable pin. Programmable clock output clock or
frequency select pin. Output voltage of CLK3 depends on VDD_CLK_B1 voltage
9OE/FS1 Input Multifunction programmable pin. Output enable or frequency select pin
10 CLK4/FS2 Output/input Multifunction programmable pin. Programmable clock output or frequency
select input pin. Output voltage of CLK4 depends on VDD_CLK_B2 voltage
11 CLK5 Output Programmable clock output. Output voltage depends on VDD_CLK_B2
voltage
12 GND Power Power supply ground
13 CLK6 Output Programmable clock output. Output voltage depends on VDD_CLK_B2
voltage
14 VDD_CLK_B2 Power Power supply for bank2, (CLK4, CLK5, CLK6) Outputs. 2.5 V/3.0 V/3.3 V
15 CLK7/SSON Output/input Multifunction programmable pin. Programmable clock output or spread
spectrum ON/OFF control input pin. Output voltage of CLK7 depends on Bank3
voltage
16 VDD_CLK_B3 Power Power supply for bank3, (CLK7, CLK8, CLK9) Outputs. 2.5 V/3.0 V/3.3 V
[+] Feedback
CY2544/CY2548, CY2546
Document #: 001-12563 Rev. *G Page 4 of 16
Figure 2. Pin Diagram – CY2546 24 LD QFN
17 CLK8 Output Programmable output clock. Output voltage depends on Bank3 voltage
18 GND Power Power supply ground
19 GND Power Power supply ground
20 CLK9 Output Programmable clock output. Output voltage depends on VDD_CLK_B3
voltage
21 CLKIN Input 2.5 V/3.0 V/3.3 V reference clock input. The signal level of CLKIN input must
track VDD power supply on pin 22.
22 VDD Power Power supply. 2.5 V/3.0 V/3.3 V
23 XOUT Output Crystal output for CY2544
DNU Output Do not use this pin for CY2548
24 XIN/EXCLKIN Input Crystal input or 1.8 V external clock input for CY2544
EXCLKIN Input 2.5 V/3.0 V/3.3 V external clock input for CY2548
Table 2. Pin Definition – CY2544/CY2548 (VDD = 2.5 V, 3.0 V or 3.3 V Supply) (continued)
Pin Number Name IO Description
CLKIN
CLK1
PD#OE
CY2546
24 23 22 21 20 19
18
17
16
15
14
13
1
2
3
4
5
6
7 8 9 10 11 12
GND
GND
VDD_CLK_B1
VDD
CLK2
OE/FS1
CLK3/FS0
CLK4/FS2
CLK5
GND
CLK6
VDD_CLK_B
2
CLK7/SSON
VDD_CLK_B
3
CLK8
GND
CLK9
VDD
XOUT
XIN/
EXCLKIN
GND
24LD QFN
Table 3. Pin Definition – CY2546 (VDD = 1.8 V Supply)
Pin Number Name IO Description
1GNDPower
Power supply ground
2 CLK1 Output Programmable clock output. Output voltage depends on VDD_CLK_B1
voltage
3 VDD_CLK_B1 Power Power supply for bank1, (CLK1, CLK2, CLK3) Outputs. 1.8V
4 PD#/OE Input Multifunction programmable pin. Output enable or power down mode
5VDD Power Power supply. 1.8 V
6 CLK2 Output Programmable clock output. Output voltage depends on VDD_CLK_B1
voltage
7 GND Power Power supply ground
8CLK3/FS0 Output/Input Multifunction programmable pin. Programmable clock output or frequency
select input pin. Output voltage of CLK3 depends on VDD_CLK_B1 voltage
9OE/FS1 Input Multifunction programmable pin. Output enable or frequency select pin
10 CLK4/FS2 Output/Input Multifunction programmable pin. Programmable clock output or frequency
select input pin. Output voltage of CLK4 depends on VDD_CLK_B2 voltage
11 CLK5 Output Programmable clock output. Output voltage depends on VDD_CLK_B2
voltage
[+] Feedback
CY2544/CY2548, CY2546
Document #: 001-12563 Rev. *G Page 5 of 16
General Description
Four Configurable PLLs
The CY2544, CY2548 and CY2546 have four programmable
PLLs that can be used to generate output frequencies ranging
from 3 to 166 MHz. The advantage of having four PLLs is that a
single device generates up to four independent frequencies from
a single crystal.
Input Reference Clocks
The input to the CY2544, CY2548 and CY2546 can be either a
crystal or a clock signal. The input frequency range for crystal
(XIN) is 8 MHz to 48 MHz and that for external reference clock
(EXCLKIN) is 8 MHz to 166 MHz. The voltage range for the
reference clock input of CY2548 is 2.5 V/3.0 V/3.3 V while that
for CY2544 and CY2546 is 1.8 V. This gives user an option for
this device to be compatible for different input clock voltage
levels in the system.
There is provision for a secondary reference clock input, CLKIN
with applied frequency range of 8 MHz to 166 MHz. When CLKIN
signal at pin 21 is used as a reference input to the PLL, a valid
signal at EXCLKIN (as specified in the AC and DC Electrical
Specification table) must be present for the devices to operate
properly.
Multiple Power Supplies
These devices are designed to operate at internal supply voltage
of 1.8 V. In the case of the high voltage part (CY2544/CY2548),
an internal regulator is used to generate 1.8 V from the 2.5 V/3.0
V/3.3 V VDD supply voltage at pin 22. For the low voltage part
(CY2546), this internal regulator is bypassed and 1.8 V at VDD
pin 22 is directly used.
Output Bank Settings
There are nine clock outputs grouped in three output driver
banks. The Bank 1, Bank 2, and Bank 3 correspond to (CLK1,
CLK2, CLK3), (CLK4, CLK5, CLK6), and (CLK7, CLK8, CLK9)
respectively. Separate power supplies are used for each of these
banks and they can be any of 2.5 V, 3.0 V, or 3.3 V for
CY2544/CY2548 and 1.8 V for CY2546 giving user multiple
choice of output clock voltage levels.
Output Source Selection
These devices have programmable input sources for each of its
nine clock outputs (CLK1–9). There are six available clock
sources for these outputs. These clock sources are:
XIN/EXCLKIN, CLKIN, PLL1, PLL2, PLL3, or PLL4. Output clock
source selection is done using four out of six crossbar switch.
Thus, any one of these six available clock sources can be
arbitrarily selected for the clock outputs. This gives user a
flexibility to have up to four independent clock outputs.
Spread Spectrum Control
Two of the four PLLs (PLL3 and PLL4) have spread spectrum
capability for EMI reduction in the system. The device uses a
Cypress proprietary PLL and spread spectrum clock (SSC)
technology to synthesize and modulate the frequency of the PLL.
The spread spectrum feature can be turned on or off using a
multifunction control pin (CLK7/SSON). It can be programmed to
either center spread range from ±0.125% to ±2.50% or down
spread range from –0.25% to –5.0% with Lexmark or Linear
profile.
12 GND Power Power supply ground
13 CLK6 Output Programmable clock output. Output voltage depends on VDD_CLK_B2
voltage
14 VDD_CLK_B2 Power Power supply for bank2, (CLK4, CLK5, CLK6) Outputs. 1.8 V
15 CLK7/SSON Output/input Multifunction programmable pin. Programmable clock output or spread
spectrum ON/OFF control input pin. Output voltage of CLK7 depends on
VDD_CLK_B3 voltage
16 VDD_CLK_B3 Power Power supply for bank3, (CLK7, CLK8, CLK9) Outputs. 1.8 V
17 CLK8 Output Programmable clock output. Output voltage depends on VDD_CLK_B3
voltage
18 GND Power Power supply ground
19 GND Power Power supply ground
20 CLK9 Output Programmable clock output. Output voltage depends on VDD_CLK_B3
voltage
21 CLKIN Input External 1.8 V low voltage reference clock input
22 VDD Power Power supply. 1.8 V
23 XOUT Output Crystal output
24 XIN/EXCLKIN Input Crystal input or 1.8 V external clock input
Table 3. Pin Definition – CY2546 (VDD = 1.8 V Supply) (continued)
Pin Number Name IO Description
[+] Feedback
CY2544/CY2548, CY2546
Document #: 001-12563 Rev. *G Page 6 of 16
Frequency Select
There are three multifunction frequency select pins (FS0, FS1
and FS2) that provide an option to select eight different sets of
frequencies among each of the four PLLs. Each output has
programmable output divider options.
Glitch-Free Frequency Switch
When the frequency select pin (FS) is used to switch frequency,
the outputs are glitch-free provided frequency is switched using
output dividers. This feature enables uninterrupted system
operation while clock frequency is being switched.
PD#/OE Mode
PD#/OE (Pin 4) can be programmed to operate as either power
down (PD#) or output enable (OE) mode. PD# is a low-true input.
If activated it shuts off the entire chip, resulting in minimum power
consumption for the device. Setting this signal high brings the
device in the operational mode with default register settings.
When this pin is programmed as Output Enable (OE), clock
outputs can be enabled or disabled using OE (pin 4). Individual
clock outputs can be programmed to be sensitive to this OE pin.
Output Drive Strength
The DC drive strength of the individual clock output can be
programmed for different values. Table 4 shows the typical rise
and fall times for different drive strength settings.
Generic Configuration and Custom Frequency
There is a generic set of output frequencies available from the
factory that can be used for the device evaluation purposes. The
devices, CY2544, CY2548 and CY2546 can be custom
programmed to any desired frequencies and listed features. For
customer specific programming, please contact local Cypress
Field application engineer (FAE) or sales representative.
Table 4. Output Drive Strength
Output Drive Strength Rise/Fall Time (ns)
(Typical Value)
Low 6.8
Mid Low 3.4
Mid High 2.0
High 1.0
Table 4. Output Drive Strength
Output Drive Strength Rise/Fall Time (ns)
(Typical Value)
[+] Feedback
CY2544/CY2548, CY2546
Document #: 001-12563 Rev. *G Page 7 of 16
Absolute Maximum Conditions
Parameter Description Condition Min Max Unit
VDD Supply voltage for CY2544/CY2548 –0.5 4.5 V
VDD Supply voltage for CY2546 –0.5 2.6 V
VDD_CLK_BX Output bank supply voltage –0.5 4.5 V
VIN Input voltage for CY2544/CY2548 Relative to VSS –0.5 VDD+0.5 V
VIN Input voltage for CY2546 Relative to VSS –0.5 2.2 V
TSTemperature, storage Non runctional –65 +150 °C
ESDHBM ESD protection (Human body model) JEDEC EIA/JESD22-A114-E 2000 – Volts
UL-94 Flammability rating V-0 at 1/8 in. – 10 ppm
MSL Moisture sensitivity level 3
Recommended Operating Conditions
Parameter Description Min Typ Max Unit
VDD VDD Operating voltage for CY2544/CY2548 2.25 – 3.60 V
VDD VDD Operating voltage for CY2546 1.65 1.8 1.95 V
VDD_CLK_BX Output driver voltage for Bank 1, 2 and 3 1.65 – 3.60 V
TAC Commercial ambient temperature 0–+70°C
TAI Industrial ambient temperature –40 -- +85 °C
CLOAD Maximum load capacitance ––15pF
tPU Power up time for all VDD to reach minimum specified
voltage (power ramps must be monotonic)
0.05 – 500 ms
[+] Feedback
CY2544/CY2548, CY2546
Document #: 001-12563 Rev. *G Page 8 of 16
DC Electrical Specifications
Parameter Description Conditions Min Typ Max Unit
VOL Output low voltage IOL = 2 mA, drive strength = [00] – – 0.4 V
IOL = 3 mA, drive strength = [01]
IOL = 7 mA, drive strength = [10]
IOL = 12 mA, drive strength = [11]
VOH Output high voltage IOH = –2 mA, drive strength = [00] VDD_CLK_BX
– 0.4
––V
IOH = –3 mA, drive strength = [01]
IOH = –7 mA, drive strength = [10]
IOH = –12 mA, drive strength = [11]
VIL1 Input low voltage of PD#/OE, FS0, FS1,
FS2 and SSON
–––0.2 × V
DD V
VIL2 Input low voltage of CLKIN for
CY2544/CY2548
–––0.1 × V
DD V
VIL3 Input low voltage of EXCLKIN for CY2544 – – – 0.15 V
VIL4 Input low voltage of EXCLKIN for CY2548 – – – 0.1 × VDD V
VIL5 Input low voltage of CLKIN, EXCLKIN for
CY2546
–––0.1 × V
DD V
VIH1 Input high voltage of PD#/OE, FS0, FS1,
FS2 and SSON
– 0.8 × VDD ––V
VIH2 Input high voltage of CLKIN for
CY2544/CY2548
– 0.9 × VDD ––V
VIH3 Input high voltage of EXCLKIN for
CY2544
– 1.6 – 2.2 V
VIH4 Input high voltage of EXCLKIN for
CY2548
– 0.9 × VDD ––V
VIH5 Input high voltage of CLKIN, EXCLKIN for
CY2546
– 0.9 × VDD ––V
IIL1 Input low current of PD#/OE and FS1 VIL = 0V – – 10 µA
IIH1 Input high current of PD#/OE and FS1 VIH = VDD ––10µA
IIL2 Input low current of SSON, FS0, and FS2 VIL = 0V (Internal pull dn = 160k typ) – – 10 µA
IIH2 Input high current of SSON, FS0, and FS2 VIH = VDD (Internal pull dn = 160k
typ)
14 – 36 µA
RDN Pull down resistor of SSON, FS0, FS2 and
clocks (CLK1-CLK9) in off-state
Clock outputs in off-state by setting
PD# = Low
100 160 250 k
IDD[1,2] Supply current for CY2546 PD# = High, No load –20–mA
Supply current for CY2544/CY2548 PD# = High, No load –22–mA
IDDS[1] Standby current PD# = Low –3–µA
CIN[1] Input capacitance SSON, CLKIN, PD#/OE, FS0, FS1,
and FS2 pins
––7pF
Notes
1. Guaranteed by design but not 100% tested.
2. Configuration dependent.
[+] Feedback
CY2544/CY2548, CY2546
Document #: 001-12563 Rev. *G Page 9 of 16
AC Electrical Specifications
Parameter Description Conditions Min Typ Max Unit
FIN (crystal) Crystal frequency, XIN –8–48 MHz
FIN (clock) Input clock frequency (CLKIN or EXCLKIN) –8–166 MHz
FCLK Output clock frequency –3–166 MHz
DC1 Output duty cycle, All clocks except ref out Duty cycle is defined in Figure 4; t1/t2,
measured at 50% of VDD_CLK_BX
45 50 55 %
DC2 Ref Out clock duty cycle Ref In Min 45%, Max 55% 40 – 60 %
TRF1[3] Output rise/fall Time Measured from 20% to 80% of
VDD_CLK_BX, as shown in Figure 5,
CLOAD = 15 pF, Drive strength [00]
–6.8–ns
TRF2[3] Output rise/fall time Measured from 20% to 80% of
VDD_CLK_BX, as shown in Figure 5,
CLOAD = 15 pF, Drive strength [01]
–3.4–ns
TRF3[3] Output rise/fall time Measured from 20% to 80% of
VDD_CLK_BX, as shown in Figure 5,
CLOAD = 15 pF, Drive strength [10]
–2.0–ns
TRF4[3] Output rise/fall time Measured from 20% to 80% of
VDD_CLK_BX, as shown in Figure 5,
CLOAD = 15 pF, Drive strength [11]
–1.0–ns
TCCJ[3,4] Cycle-to-cycle Jitter (peak) Configuration dependent. See Tab l e 5 –150– ps
TLOCK[3] PLL lock time Measured from 90% of the applied power
supply level
–13ms
Table 5. Configuration Example for C-C Jitter
Ref. Freq.
(MHz)
CLK1 Output CLK2 Output CLK3 Output CLK4 Output CLK5 Output
Freq.
(MHz)
C-C Jitter
Typ (ps)
Freq.
(MHz)
C-C Jitter
Typ (ps)
Freq.
(MHz)
C-C Jitter
Typ (ps)
Freq.
(MHz)
C-C Jitter
Typ (ps)
Freq.
(MHz)
C-C Jitter
Typ (ps)
14.3181 8.0 134 166 103 48 92 74.25 81 Not Used
19.2 74.25 99 166 94 8 91 27 110 48 75
27 48 67 27 109 166 103 74.25 97 Not Used
48 48 93 27 123 166 137 166 138 8 103
Recommended Crystal Specification for SMD Package
Parameter Description Range 1 Range 2 Range 3 Unit
FIN Crystal frequency 8 – 14 14 – 28 28 – 48 MHz
R1 Maximum motional resistance (ESR) 135 50 30
CL Parallel load capacitance (see Note 3 below) 8 – 18 8 – 14 8 – 12 pF
DL(max) Maximum crystal drive level 300 300 300 µW
Notes
3. Guaranteed by design but not 100% tested
4. Configuration dependent
[+] Feedback
CY2544/CY2548, CY2546
Document #: 001-12563 Rev. *G Page 10 of 16
Test and Measurement Setup
Figure 3. Test and Measurement Setup
Voltage and Timing Definitions
Figure 4. Duty Cycle Definition
Figure 5. Rise Time = TRF
, Fall Time = TRF
Note
5. CY2544, CY2548 and CY2546 have internal crystal load capacitance (CL) adjustment feature.
Recommended Crystal Specification for Thru-Hole Package
Parameter[5] Description Range 1 Range 2 Range 3 Unit
FIN Crystal frequency 8 – 14 14 – 24 24 – 32 MHz
R1 Maximum motional resistance (ESR) 90 50 30
CL Parallel load capacitance (see Note 3 below) 8 – 18 8 – 12 8 – 12 pF
DL(max) Maximum crystal drive level 1000 1000 1000 µW
0.1 F
VDD Outputs
CLOAD
GND
DUT
Clock
Output
V
DD_CLK_B
X
50% of V
DD_CLK_BX
0V
t
1
t
2
Clock
Output
TRF
TRF
V
DD_CLK_BX
80% of V
DD_CLK_BX
20% of V
DD_CLK_BX
0V
[+] Feedback
CY2544/CY2548, CY2546
Document #: 001-12563 Rev. *G Page 11 of 16
Ordering Information
Part Number Type[6] Package Supply Voltage Operating Range
Pb-free
CY2544C Field Programmable 24-pin QFN 2.5 V, 3.0 V or 3.3 V Commercial, 0 °C to 70 °C
CY2544CT Field Programmable 24-pin QFN -tape and reel 2.5 V, 3.0V or 3.3 V Commercial, 0 °C to 70 °C
CY2548C Field Programmable 24-pin QFN 2.5 V, 3.0V or 3.3 V Commercial, 0 °C to 70 °C
CY2548CT Field Programmable 24-pin QFN -tape and reel 2.5 V, 3.0V or 3.3 V Commercial, 0 °C to 70 °C
CY2546C Field Programmable 24-pin QFN 1.8 V Commercial, 0 °C to 70 °C
CY2546CT Field Programmable 24-pin QFN -tape and reel 1.8 V Commercial, 0 °C to 70 °C
CY2544I Field Programmable 24-pin QFN 2.5 V, 3.0 V or 3.3 V Industrial, -40 °C to +85 °C
CY2544IT Field Programmable 24-pin QFN -tape and reel 2.5 V, 3.0 V or 3.3 V Industrial, -40 °C to +85 °C
CY2548I Field Programmable 24-pin QFN 2.5 V, 3.0 V or 3.3 V Industrial, -40 °C to +85 °C
CY2548IT Field Programmable 24-pin QFN -tape and reel 2.5 V, 3.0 V or 3.3 V Industrial, -40 °C to +85 °C
CY2546I Field Programmable 24-pin QFN 1.8 V Industrial, -40 °C to +85 °C
CY2546IT Field Programmable 24-pin QFN -tape and reel 1.8 V Industrial, -40 °C to +85 °C
Programmer
CY3675-CLKMAKER1 Programming kit
CY3675-QFN24A Socket adapter board, for programming CY2544 and CY2548[7]
Some product offerings are factory programmed customer specific devices with customized part numbers.
The Possible Configurations table shows the available device types, but not complete part numbers. Contact your local Cypress FAE
of Sales Representative for more information.
Possible Configurations
Part Number[8] Type[6] Package Supply Voltage Operating Range
Pb-free
CY2544Cxxx Factory Programmed 24-pin QFN 2.5 V, 3.0 V or 3.3 V Commercial, 0 °C to 70 °C
CY2544CxxxT Factory Programmed 24-pin QFN -tape and reel 2.5 V, 3.0 V or 3.3 V Commercial, 0 °C to 70 °C
CY2548Cxxx Factory Programmed 24-pin QFN 2.5 V, 3.0 V or 3.3 V Commercial, 0 °C to 70 °C
CY2548CxxxT Factory Programmed 24-pin QFN -tape and reel 2.5 V, 3.0 V or 3.3 V Commercial, 0 °C to 70 °C
CY2546Cxxx Factory Programmed 24-pin QFN 1.8 V Commercial, 0 °C to 70 °C
CY2546CxxxT Factory Programmed 24-pin QFN -tape and reel 1.8 V Commercial, 0 °C to 70 °C
CY2544Ixxx Factory Programmed 24-pin QFN 2.5 V, 3.0 V or 3.3 V Industrial, -40 °C to +85 °C
CY2544IxxxT Factory Programmed 24-pin QFN -tape and reel 2.5 V, 3.0 V or 3.3 V Industrial, -40 °C to +85 °C
CY2548Ixxx Factory Programmed 24-pin QFN 2.5 V, 3.0 V or 3.3 V Industrial, -40 °C to +85 °C
CY2548IxxxT Factory Programmed 24-pin QFN -tape and reel 2.5 V, 3.0 V or 3.3 V Industrial, -40 °C to +85 °C
CY2546Ixxx Factory Programmed 24-pin QFN 1.8 V Industrial, -40 °C to +85 °C
CY2546IxxxT Factory Programmed 24-pin QFN -tape and reel 1.8 V Industrial, -40 °C to +85 °C
Notes
6. Field Programmable devices are shipped unprogrammed, and must be programmed before being installed on a board. Factory Programmed devices are shipped fully
configured and ready to install on a board.
7. The CY3675-QFN24A cannot be used to program the CY2546.
8. “xxx” is a variable that denotes a specific device configuration. For more details, contact your local Cypress FAE or Cypress Sales Representative.
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CY2544/CY2548, CY2546
Document #: 001-12563 Rev. *G Page 14 of 16
Acronyms Document Conventions
Units of Measure
Acronym Description
DL drive level
DNU do not use
DUT device under test
EMI electromagnetic interference
ESD electrostatic discharge
FAE field application engineer
FS frequency select
JEDEC EIA joint electron devices
engineering council electronic
industries alliance
LVCMOS low voltage complemetary
metal oxide semiconductor
OE output enable
OSC oscillator
PD power down
PLL phase locked loop
PPM parts per million
SS spread spectrum
SSC spread spectrum clock
SSON spread spectrum on
Symbol Unit of Measure
°C degrees Celsius
fF femtofarads
mA milliampere
MHz megahertz
smicroseconds
ms millisecond
Wmicrowatts
ns nanoseconds
pF picofarads
ppm parts per million
ps picoseconds
Vvolts
ohms
Wwatts
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CY2544/CY2548, CY2546
Document #: 001-12563 Rev. *G Page 15 of 16
Document History Page
Document Title: CY2544/CY2548 CY2546 Quad PLL Programmable Clock Generator with Spread Spectrum
Document Number: 001-12563
Revision ECN Orig. of
Change
Submission
Date
Description of Change
** 690257 RGL See ECN New Datasheet
*A 790516 RGL See ECN Separated the Pin Configuration drawing into two to show the difference
between CY2544 and CY2546 pinouts.
Changed the IDD from 22 mA maximum to 25 mA typical
Changed IILSR Internal pull down from 100K to 160K
Changed IIHSR Internal pull down from 100K to 160K and changed the
maximum value from 10 A to 25 A
Changed IILPDOE to No Internal pull up and changed the maximum value from
10 A to 1 A
Changed IIHPDOE to no Internal pull up
*B 1508943 RGL/AESA See ECN Changed the IILSR maximum value to 10 uA
Changed the IILPDOE and IIHPDOE values to a minimum of 1 A to a maximum
of 10A
Removed Preliminary from Title page
Changed the IIHPD from 1 uA to 10 uA
Changed the IILSR from 1 uA to 10 uA
Added new IDDS value = 3uA
Added new C-C Jitter typical values, Deleted Long term Jitter values
Deleted generic part numbers from Ordering Information
Added new device and specification for high ref input voltage part, CY2548
Changed I2C Tsu specification from 100ns to 250 ns
Changed ESD spec from MIL-STD to JEDEC
Combined VDD operating condition spec for CY2545 to a single VDD spec
In DC spec.: FS1 pin has no pull down resistor
Added device selection table 1
Removed C0 from crystal spec
*C 2748211 TSAI 08/10/09 Posting to external web.
*D 2764011 CXQ 09/15/09 Fixed typo in Ordering Information table – changed CY2548Cxxx and
CY2548CxxxT to CY2548Ixxx and CY2548IxxxT for industrial temp parts.
*E 2899758 KVM 03/26/10 Updated Ordering information table.
Updated package diagram
Updated copyright section.
*F 2969587 KVM 07/09/2010 Minor change: Matched spec title on the first page to document history page.
Added "WITH SPREAD SPECTRUM" in first page title.
*G 3115710 BASH 12/21/2010 Added Ordering Code Definition, Acronyms and Units of Measure table.
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Document #: 001-12563 Rev. *G Revised December 21, 2010 Page 16 of 16
All products and company names mentioned in this document may be the trademarks of their respective holders.
CY2544/CY2548, CY2546
© Cypress Semiconductor Corporation, 2007-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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