© 2004 Fairchild Semiconductor Corporation DS005994 www.fairchildsemi.com
October 1987
Revised January 2004
CD4514BC • CD4515BC 4-Bit Latched/4-to-16 Li ne Decoders
CD4514BC CD4515BC
4-Bit Latched/4-to-16 Line Decoders
General Description
The CD45 14BC and C D4515BC a re 4-to-16 line decode rs
with latched inputs impleme nted with complemen tary MOS
(CMOS) circuits constructed with N- and P-channel
enhancement mode transistors. These circuits are prima-
rily used in decoding applications where low power dissipa-
tion and/or high noise immunity is required.
The CD45 14B C ( outp ut a cti ve h igh op ti on ) pr ese nts a lo gi -
cal “1” at the selected output, whereas the CD4515BC pre-
sents a l og ical 0” at the sele cted o utpu t. The in put l atch es
are R–S type flip-flops, wh ich hold the last input data pre-
sented prior to the strobe transition from “1” to “0”. This
input dat a is deco ded and t he co rre spo ndin g ou tpu t is acti -
vated. An output inhibit line is also available.
Features
Wide supply voltage rang e: 3.0V to 15V
High noise immunity: 0.45 VDD (typ.)
Low power TTL: fan out of 2
compatibility: driving 74L
Low quiescent power dissipation:
0.025 µW/package @ 5.0 VDC
Single supply operation
Input impedance = 1012 typically
Plug-in replacement for MC14514, MC14515
Ordering Code:
Note 1: Devices al so av ailable in Tape and Re el. Specify by appending suffix le t te r X to the ordering code.
Connection Diagram
Top View
Order Number Package Number Package Diagram
CD4514BCWM M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
CD4514 BCN N24A 24-Lead Pla sti c Dual-In-Line Pa ckag e (P DIP ), JED EC MS-0 11, 0.600" Wide
CD4515BCWM
(Note 1) M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
CD4515 BCN N24A 24-Lead Pla sti c Dual-In-Line Pa ckag e (P DIP ), JED EC MS-0 11, 0.600" Wide
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CD4514BC CD4515BC
Truth Table
Decode Truth Table (Strobe = 1)
X = Dont Care
Logic Diagram
Data Inputs Selected Output
Inhibit D C B A CD4514 = Logic 1
CD4515 = Logic 0
0 0 0 0 0 S0
0 0 0 0 1 S1
0 0 0 1 0 S2
0 0 0 1 1 S3
0 0 1 0 0 S4
0 0 1 0 1 S5
0 0 1 1 0 S6
0 0 1 1 1 S7
0 1 0 0 0 S8
0 1 0 0 1 S9
0 1 0 1 0 S10
0 1 0 1 1 S11
0 1 1 0 0 S12
0 1 1 0 1 S13
0 1 1 1 0 S14
0 1 1 1 1 S15
1 X X X X All Outputs = 0, CD4514
All Outputs = 1, CD4515
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CD4514BC CD4515BC
Absolute Maximum Ratings(Note 2)
(Note 3) Recommended Operating
Conditions (Note 3)
Note 2: Absolute Maximum Ratings are those va lues beyond which the
safety of the device cannot be guaranteed. Except for Operat ing Tempera-
ture Range they are not mea nt to imply that t he devices should be oper-
ated at these limits. The tables of Recommended Operating Conditions
and Electrical Characteristics provide conditions for actual device opera-
tion.
Note 3: VSS = 0V unles s ot herwise s pecified .
DC Electrical Characteristics (Note 3)
CD4514BC, CD4515BC
Note 4: IOH and IOL are tes t ed one ou tp ut at a ti m e.
DC Supply V oltage (VDD) 0.5V to +18V
Input Voltage (VIN) 0.5V to VDD + 0.5V
Storage Temperature Range (TS) 65°C to +150°C
Power Dissipat i on (PD)
Dual-In-Line 700 mW
Small Outline 500 mW
Lead Temperature (TL)
(Soldering, 10 seconds) 260°C
DC Supply Voltage (VDD) 3V to 15V
Input Voltage (VIN) 0V to VDD
Operating Temperature Range (TA)
CD4514BC, CD4515BC
55°C to +125°C
Symbol Parameter Conditions 55°C +25°C+125°CUnits
Min Max Min Typ Max Min Max
IDD Quiescent Device VDD = 5V, VIN = VDD or V SS 5 0.005 5 150 µA Current VDD = 10V, VIN = VDD or V SS 10 0.010 10 300
VDD = 15V, VIN = VDD or V SS 20 0.015 20 600
VOL LOW Level VIL = 0V, VIH = VDD,
Output Voltage |IO| < 1 µA
VDD = 5V 0.05 0 0.05 0.05 V VDD = 10V 0.05 0 0.05 0.05
VDD = 15V 0.05 0 0.05 0.05
VOH HIGH Level VIL = 0V, VIH = VDD,
Output Voltage |IO| < 1 µA
VDD = 5V 4.95 4.95 5.0 4.95 V VDD = 10V 9.95 9.95 10.0 9.95
VDD = 15V 14.95 14.95 15.0 14.95
VIL LOW Level |IO| < 1 µA
Input Voltage VDD = 5V, VO = 0.5V or 4.5V 1.5 2.25 1.5 1.5 V VDD = 10V, VO = 1.0V or 9.0V 3.0 4.50 3.0 3.0
VDD = 15V, VO = 1.5V or 13.5V 4.0 6.75 4.0 4.0
VIH HIGH Level |IO| < 1 µA
Input Voltage VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 2.75 3.5 V VDD = 10V, VO = 1.0V or 9.0V 7.0 7.0 5.50 7.0
VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 8.25 11.0
IOL LOW Level Output VDD = 5V, VO = 0.4V 0.64 0.51 0.88 0.36 mA Current (Note 4) VDD = 10V, VO = 0.5V 1.6 1.3 2.25 0.90
VDD = 15V, VO = 1.5V 4.2 3.4 8.8 2.4
IOH HIGH Level Output VDD = 5V, VO = 4.6V 0.64 0.51 0.88 0.36 mA Current (Note 4) VDD = 10V, VO = 9.5V 1.6 1.3 2.25 0.90
VDD = 15V, VO = 13.5V 4.2 3.4 8.8 2.4
IIN Input Current VDD = 15V, VIN = 0V 0.1 105 0.1 1.0 µA
VDD = 15V, VIN = 15V 0.1 105 0.1 1.0
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CD4514BC CD4515BC
AC Electrical Characteristics (Note 5)
All types CL = 50 pF, TA = 25°C, tr = tf = 20 ns unless otherwise specified
Note 5: AC Parameters are guara nt eed by DC c orrelat ed testing.
Note 6: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see Family Characteristics application note,
AN-90.
Note 7: Capacita nce is guaranteed by periodic tes ti ng.
Symbol Parameter Conditions Min Typ Max Units
tTHL, tTLH Transition Times VDD = 5V 100 200 ns VDD = 10V 50 100
VDD = 15V 40 80
tPLH, tPHL Propagation Delay Times VDD = 5V 550 1100 ns VDD = 10V 225 450
VDD = 15V 150 300
tPLH, tPHL Inhibit Propagation VDD = 5V 400 800 ns Delay Times VDD = 10V 150 300
VDD = 15V 100 200
tSU Setup Time VDD = 5V 125 250 ns VDD = 10V 50 100
VDD = 15V 38 75
tWH Strobe Pulse Width VDD = 5V 175 350 ns VDD = 10V 50 100
VDD = 15V 38 75
CPD Power Dissipation Capacitance Per Package (Note 6) 150 pF
CIN Input Capacitance Any Input (Note 7) 5 7.5 pF
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CD4514BC CD4515BC
AC Test Circuit and Switching Time Waveforms
FIGURE 1.
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CD4514BC CD4515BC
Applications
Two CD4512 8- channel data selectors are used here with
the CD4514B 4-bit latch/d ecoder to effect a comple x data
routing system. A total o f 16 in puts fr om data r egis ters are
select ed and transf erred via a 3- STATE da ta bus t o a data
dist r ibu t or fo r r e ar ra n ge me nt an d en t ry i n t o 16 o ut p ut r egi s -
ters. In this way sequ ential data can be re-routed o r inter-
mixed according to p atte rn s dete rm ined by da ta select and
distribution inputs.
Data is place d into the routing schem e via the 8 inputs on
both CD4512 data selectors. One register is assigned to
each input. The signals on A0, A1 and A2 choose 1-of-8
inputs for transfer out to the 3-STATE data bus. A fourth
signa l, label led Dis , disabl es one of the CD4 512 sel ector s,
assuring tran sfer of data from only one register.
In addition to a choice of input registers, 116, the rate of
transfer of the sequential information can also be varied.
That is, if the CD4512 were addressed at a rate that is 8
times faster than the shift fre quency of the input re gisters,
the most significant bi t (MSB) fr om each reg ister could be
selected for transfer to the data bus. Therefore, all of the
most significant bits from all of the registers can be trans-
ferred to the data bus be for e the next mo st sign ifican t bit is
presented for transfer by the input registers.
Information from the 3-STATE bus is redistributed by the
CD4514B 4-bit latch/decoder. Using the 4-bit address,
INAIND, the information on the inhibit line can be trans-
ferred to the addressed output line to the desired output
registers, AP. This distribution of data bits to the output
registers can be made in many complex patterns. For
example, all of the most significant bits from the input regis-
ters can be routed into output register A, all of the next
most significant bits into register B, etc. In this way horizon-
tal, vert ical, or oth er method s of data sli cing can be i mple-
mented.
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CD4514BC CD4515BC
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M24B
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CD4514BC CD4515BC 4-Bit Latched/4-to- 16 Line Decoders
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600" Wide
Package Number N24A
Fairchild does not assu me any responsibility for use of any circuitry de scribed, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life suppor t de vices o r syste ms are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical compon ent i n any compon ent of a lif e supp ort
device or system whose failure to perform can be rea-
sonabl y ex pect ed to ca use the fa ilu re of the li fe su pp ort
device or system, or to affect its safety or effectiveness.
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