2015-2016 Microchip Technology Inc. DS60001324B-page 1
PIC32MM0064GPL036 FAMILY
Operating Conditions
• 2.0V to 3.6V, -40ºC to +85ºC, DC to 25 MHz
Low-Power Modes
• Low-Power modes:
- Idle: CPU off, peripherals run from system clock
- Sleep: CPU and peripherals off:
- Fast wake-up Sleep with retention
- Low-power Sleep with retention
•0.5 μA Sleep Current for Regulator Retention mode and
5 μA for Regulator Standby mode
• On-Chip 1.8V Voltage Regulator (VREG)
• On-Chip Ultra Low-Power Retention Regulator
High-Performance 32-Bit RISC CPU
• microAptiv™ UC 32-Bit Core with 5-Stage Pipeline
• microMIPS™ Instruction Set for 35% Smaller Code and
98% Performance compared to MIPS32 Instructions
• DC-25 MHz Operating Frequency
• 3.17 CoreMark
®
/MHz (79 CoreMark) Performance
• 1.53 DMIPS/MHz (37 DMIPS) (Dhrystone 2.1) Performance
• 16-Bit/32-Bit Wide Instructions with 32-Bit Wide Data Path
• Two Sets of 32 Core Register Files (32-bit) to Reduce
Interrupt Latency
• Single-Cycle 32x16 Multiply and Two-Cycle 32x32 Multiply
• Hardware Divide Unit
• 64-Bit, Zero Wait State Flash with ECC to Maximize
Endurance/Retention
Microcontroller Features
• Low Pin Count Packages, Ranging from 20 to 36 Pins,
including UQFN as Small as 4x4 mm
• Up to 64K Flash Memory:
- 20,000 erase/write cycle endurance
- 20 years minimum data retention
- Self-programmable under software control
• Up to 8K Data Memory
• Pin-Compatible with Most PIC24 MCU/dsPIC
®
DSC Devices
• Multiple Interrupt Vectors with Individually
Programmable Priority
• Fail-Safe Clock Monitor mode
• Configurable Watchdog Timer with On-Chip, Low-Power
RC Oscillator
• Programmable Code Protection
• Selectable Oscillator Options including:
- High-precision, 8 MHz internal Fast RC (FRC)
oscillator
- High-speed crystal/resonator oscillator or external
clock
- 2x/3x/4x/6x/12x/24x PLL, which can be clocked from the
FRC or primary oscillator
Peripheral Features
• Atomic Set, Clear and Invert Operation on Select
Peripheral Registers
• High-Current Sink/Source 11 mA/16 mA on All Ports
• Independent, Low-Power 32 kHz Timer Oscillator
• Two 4-Wire SPI modules (up to 25 Mbps):
- 16-byte FIFO
-I
2
S mode
• Two UARTs:
- RS-232, RS-485 and LIN/J2602 support
- IrDA
®
with on-chip hardware encoder and decoder
• External Edge and Level Change Interrupt on All Ports
• CRC module
• Hardware Real-Time Clock and Calendar (RTCC)
• Up to 20 Peripheral Pin Select (PPS) Remappable Pins
• Seven Total 16-Bit Timers:
- Timer1: Dedicated 16-bit timer/counter
- Two additional 16-bit timers in each MCCP and SCCP
module
• Capture/Compare/PWM/Timer modules:
- Two 16-bit timers or one 32-bit timer in each module
- PWM resolution down to 21 ns
- One Multiple Output (MCCP) module:
- Flexible configuration as PWM, input capture, output
compare or timers
- Six PWM outputs
- Programmable dead time
- Auto-shutdown
- Two Single Output (SCCP) modules:
- Flexible configuration as PWM, input capture, output
compare or timers
- Single PWM output
• Reference Clock Output (REFO)
• Two Configurable Logic Cells (CLC) with Internal
Connections to Select Peripherals and PPS
Debug Features
• Two Programming and Debugging Interfaces:
- 2-wire ICSP™ interface with non-intrusive access
and real-time data exchange with application
-4-wire MIPS
®
standard Enhanced JTAG interface
• IEEE Standard 1149.2 Compatible (JTAG) Boundary Scan
32-Bit Flash Microcontroller with MIPS 32
®
microAptiv™ UC Core
with Low Power and Low Pin Count
PIC32MM0064GPL036 FAMILY
DS60001324B-page 2 2015-2016 Microchip Technology Inc.
Analog Features
• Two Analog Comparators with Input
Multiplexing
• Programmable High/Low-Voltage
Detect (HLVD)
• 5-Bit DAC with Output Pin
• Up to 14-Channel, Software-Selectable 10/12-Bit SAR
Analog-to-Digital Converter (ADC):
- 12-bit, 200K samples/second conversion rate
(single Sample-and-Hold)
- 10-bit, 300K samples/second conversion rate
(single Sample-and-Hold)
- Sleep mode operation
- Band gap reference input feature
- Windowed threshold compare feature
- Auto-scan feature
• Brown-out Reset (BOR)
TABLE 1: PIC32MM0064GPL036 FAMILY DEVICES
Device
Pins
Program Memory (Kb ytes)
Data Memory (Kbytes)
General Purpose I/O/PPS
16-Bit Timers Maximum
PWM Outpu ts Maximum
Remappable
Peripherals
10/12-Bit AD C (Ch annels )
Comparators
CRC
RTCC
JTAG
Packages
UART
(1)
/LIN/J2602
16-Bit Timers
MCCP
(3)
SCCP
(4)
CLC
SPI
(2)
/I
2
S
PIC32MM0016GPL020 20 16 416/16 7 8 2 1 1 2 2 2 11 2Yes Yes Yes SSOP/QFN
PIC32MM0032GPL020 20 32 816/16 7 8 2 1 1 2 2 2 11 2Yes Yes Yes SSOP/QFN
PIC32MM0064GPL020 20 64 816/16 7 8 2 1 1 2 2 2 11 2Yes Yes Yes SSOP/QFN
PIC32MM0016GPL028 28 16 422/19 7 8 2 1 1 2 2 2 12 2Yes Yes Yes SSOP/SOIC/
QFN/UQFN
PIC32MM0032GPL028 28 32 822/19 7 8 2 1 1 2 2 2 12 2Yes Yes Yes SSOP/ SOIC/
QFN/UQFN
PIC32MM0064GPL028 28 64 822/19 7 8 2 1 1 2 2 2 12 2Yes Yes Yes SPDIP/SSOP/
SOIC/QFN/
UQFN
PIC32MM0016GPL036 36/40 16 429/20 7 8 2 1 1 2 2 2 14 2Yes Yes Yes VQFN/UQFN
PIC32MM0032GPL036 36/40 32 829/20 7 8 2 1 1 2 2 2 14 2Yes Yes Yes VQFN/UQFN
PIC32MM0064GPL036 36/40 64 829/20 7 8 2 1 1 2 2 2 14 2Yes Yes Yes VQFN/UQFN
Note 1: UART1 has assigned pins. UART2 is remappable.
2: SPI1 has assigned pins. SPI2 is remappable.
3: MCCP can be configured as a PWM with up to 6 outputs, input capture, output compare, 2 x 16-bit timers or
1 x 32-bit timer.
4: SCCP can be configured as a PWM with 1 output, input capture, output compare, 2 x 16-bit timers or 1 x 32-bit timer.
2015-2016 Microchip Technology Inc. DS60001324B-page 3
PIC32MM0064GPL036 FAMILY
Pin Diagrams
20-Pin SSOP
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
MCLR
PGEC2/RP1/RA0
PGED2/RP2/RA1
PGED1/RP14/RB0
PGEC1/RP15/RB1
RP16/RB2
CLKI/RP3/RA2
CLKO/RP4/RA3
(1)
PGED3/SOSCI/RP5/RB4
PGEC3/SOSCO/RP6/RA4 RP11/RB7
RP7/RB8
(1)
RP8/RB9
(1)
V
CAP
RP12/RB12
RP13/RB13
RP9/RB14
RP10/RB15
(1)
AV
SS
/V
SS
AV
DD
/V
DD
Legend: Shaded pins are up to 5V tolerant.
Note 1: Pin has an increased current drive strength. Refer to Section 26.0 “Electrical Characteristics” for details.
PIC32MMXXXXGPL020
TABLE 2: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 20-PIN SSOP DEVICES
Pin Function Pin Function
1MCLR 11 RP11/RB7
2PGEC2/VREF+/AN0/RP1/OCM1E/INT3/RA0 12 TCK/RP7/U1CTS/SCK1/OCM1A/RB8(1)
3PGED2/VREF-/AN1/RP2/OCM1F/RA1 13 TMS/REFCLKI/RP8/T1CK/T1G/U1RTS/U1BCLK/SDO1/C2OUT/OCM1B/
INT2/RB9(1)
4PGED1/AN2/C1IND/C2INB/RP14/RB0 14 VCAP
5PGEC1/AN3/C1INC/C2INA/RP15/RB1 15 TDO/AN7/LVDIN/RP12/RB12
6AN4/RP16/RB2 16 TDI/AN8/RP13/RB13
7OSC1/CLKI/AN5/C1INB/RP3/OCM1C/RA2 17 CDAC1/AN9/RP9/RTCC/U1TX/SDI1/C1OUT/INT1/RB14
8OSC2/CLKO/AN6/C1INA/RP4/OCM1D/RA3(1)18 AN10/REFCLKO/RP10/U1RX/SS1/FSYNC1/INT0/RB15(1)
9PGED3/SOSCI/RP5/RB4 19 AVSS/VSS
10 PGEC3/SOSCO/SCLKI/RP6/PWRLCLK/RA4 20 AVDD/VDD
Note 1: Pin has an increased current drive strength.
PIC32MM0064GPL036 FAMILY
DS60001324B-page 4 2015-2016 Microchip Technology Inc.
Pin Diagrams (Continued)
20-Pin QFN
PGEC1/RP15/RB1
RP16/RB2
CLKI/RP3/RA2
CLKO/RP4/RA3
(1)
PGED1/RP14/RB0
PGED3/SOSCI/RP5/RB4
PGEC3/SOSCO/RP6/RA4
RP11/RB7
RP7/RB8
(1)
RP8/RB9
(1)
RP12/RB12
RP13/RB13
V
CAP
RP9/RB14
RP10/RB15
(1)
AV
SS
/V
SS
PGEC2/RP1/RA0
AV
DD
/V
DD
MCLR
18 17 1620 19
PGED2/RP2/RA1
PIC32MMXXXXGPL020
2
3
1
5
4
14
13
15
11
12
891067
Legend: Shaded pins are up to 5V tolerant.
Note 1: Pin has an increased current drive strength. Refer to Section 26.0 “Electrical Characteristics” for details.
TABLE 3: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 20-PIN QFN DEVICES
Pin Function Pin Function
1PGED1/AN2/C1IND/C2INB/RP14/RB0 11 VCAP
2PGEC1/AN3/C1INC/C2INA/RP15/RB1 12 TDO/AN7/LVDIN/RP12/RB12
3AN4/RP16/RB2 13 TDI/AN8/RP13/RB13
4OSC1/CLKI/AN5/C1INB/RP3/OCM1C/RA2 14 CDAC1/AN9/RP9/RTCC/U1TX/SDI1/C1OUT/INT1/RB14
5OSC2/CLKO/AN6/C1INA/RP4/OCM1D/RA3(1)15 AN10/REFCLKO/RP10/U1RX/SS1/FSYNC1/INT0/RB15(1)
6PGED3/SOSCI/RP5/RB4 16 AVSS/VSS
7PGEC3/SOSCO/SCLKI/RP6/PWRLCLK/RA4 17 AVDD/VDD
8RP11/RB7 18 MCLR
9TCK/RP7/U1CTS/SCK1/OCM1A/RB8(1)19 PGEC2/VREF+/AN0/RP1/OCM1E/INT3/RA0
10 TMS/REFCLKI/RP8/T1CK/T1G/U1RTS/U1BCLK/SDO1/
C2OUT/OCM1B/INT2/RB9(1)20 PGED2/VREF-/AN1/RP2/OCM1F/RA1
Note 1: Pin has an increased current drive strength.
2015-2016 Microchip Technology Inc. DS60001324B-page 5
PIC32MM0064GPL036 FAMILY
Pin Diagrams (Continued)
28-Pin SPDIP
(2)
/SSOP/SOIC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
MCLR
RP1/RA0
RP2/RA1
PGED1/RP14/RB0
PGEC1/RP15/RB1
RP16/RB2
RB3
V
SS
CLKI/RP3/RA2
CLKO/RP4/RA3
(1)
SOSCI/RP5/RB4
SOSCO/RP6/RA4
V
DD
PGED3/RB5 PGEC3/RB6
RP11/RB7
RP7/RB8
(1)
RP8/RB9
(1)
RP19/RC9
V
CAP
PGED2/RP17/RB10
PGEC2/RP18/RB11
RP12/RB12
RP13/RB13
RP9/RB14
RP10/RB15
(1)
AV
SS
AV
DD
PIC32MMXXXXGPL028
Legend: Shaded pins are up to 5V tolerant.
Note 1: Pin has an increased current drive strength. Refer to Section 26.0 “Electrical Characteristics” for details.
2: Only PIC32MM0064GPL028 comes in a 28-pin SPDIP package.
TABLE 4: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 28-PIN SPDIP/SSOP/SOIC DEVICES
Pin Function Pin Function
1MCLR 15 PGEC3/RB6
2 VREF+/AN0/RP1/OCM1E/INT3/RA0 16 RP11/RB7
3 VREF-/AN1/RP2/OCM1F/RA1 17 TCK/RP7/U1CTS/SCK1/OCM1A/RB8(1)
4PGED1/AN2/C1IND/C2INB/RP14/RB0 18 TMS/REFCLKI/RP8/T1CK/T1G/U1RTS/U1BCLK/SDO1/C2OUT/OCM1B/INT2/RB9(1)
5PGEC1/AN3/C1INC/C2INA/RP15/RB1 19 RP19/RC9
6AN4/C1INB/RP16/RB2 20 VCAP
7AN11/C1INA/RB3 21 PGED2/TDO/RP17/RB10
8 VSS 22 PGEC2/TDI/RP18/RB11
9OSC1/CLKI/AN5/RP3/OCM1C/RA2 23 AN7/LVDIN/RP12/RB12
10 OSC2/CLKO/AN6/RP4/OCM1D/RA3(1)24 AN8/RP13/RB13
11 SOSCI/RP5/RB4 25 CDAC1/AN9/RP9/RTCC/U1TX/SDI1/C1OUT/INT1/RB14
12 SOSCO/SCLKI/RP6/PWRLCLK/RA4 26 AN10/REFCLKO/RP10/U1RX/SS1/FSYNC1/INT0/RB15(1)
13 VDD 27 AVSS
14 PGED3/RB5 28 AVDD
Note 1: Pin has an increased current drive strength.
PIC32MM0064GPL036 FAMILY
DS60001324B-page 6 2015-2016 Microchip Technology Inc.
Pin Diagrams (Continued)
28-Pin QFN/UQFN
10 11
2
3
6
1
18
19
20
21
22
12 13 14
15
8
7
16
17
232425262728
9
5
4
PGEC1/RP15/RB1
RP16/RB2
RB3
V
SS
CLKI/RP3/RA2
CLKO/RP4/RA3
(1)
PGED1/RP14/RB0
SOSCI/RP5/RB4
SOSCO/RP6/RA4
V
DD
PGED3/RB5
PGEC3/RB6
RP11/RB7
RP7/RB8
(1)
RP8/RB9
(1)
RP19/RC9
V
CAP
PGED2/RP17/RB10
PGEC2/RP18/RB11
RP12/RB12
RP13/RB13
RP9/RB14
RP10/RB15
(1)
AV
SS
AV
DD
MCLR
RP1/RA0
RP2/RA1
PIC32MMXXXXGPL028
Legend: Shaded pins are up to 5V tolerant.
Note 1: Pin has an increased current drive strength. Refer to Section 26.0 “Electrical Characteristics” for details.
TABLE 5: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 28-PIN QFN/UQFN DEVICES
Pin Function Pin Function
1PGED1/AN2/C1IND/C2INB/RP14/RB0 15 TMS/REFCLKI/RP8/T1CK/T1G/U1RTS/U1BCLK/SDO1/C2OUT/OCM1B/
INT2/RB9(1)
2PGEC1/AN3/C1INC/C2INA/RP15/RB1 16 RP19/RC9
3AN4/C1INB/RP16/RB2 17 VCAP
4AN11/C1INA/RB3 18 PGED2/TDO/RP17/RB10
5 VSS 19 PGEC2/TDI/RP18/RB11
6OSC1/CLKI/AN5/RP3/OCM1C/RA2 20 AN7/LVDIN/RP12/RB12
7OSC2/CLKO/AN6/RP4/OCM1D/RA3(1)21 AN8/RP13/RB13
8SOSCI/RP5/RB4 22 CDAC1/AN9/RP9/RTCC/U1TX/SDI1/C1OUT/INT1/RB14
9SOSCO/SCLKI/RP6/PWRLCLK/RA4 23 AN10/REFCLKO/RP10/U1RX/SS1/FSYNC1/INT0/RB15(1)
10 VDD 24 AVSS
11 PGED3/RB5 25 AVDD
12 PGEC3/RB6 26 MCLR
13 RP11/RB7 27 VREF+/AN0/RP1/OCM1E/INT3/RA0
14 TCK/RP7/U1CTS/SCK1/OCM1A/RB8(1)28 VREF-/AN1/RP2/OCM1F/RA1
Note 1: Pin has an increased current drive strength.
2015-2016 Microchip Technology Inc. DS60001324B-page 7
PIC32MM0064GPL036 FAMILY
Pin Diagrams (Continued)
36-Pin VQFN
RP16/RB2
RB3
RC0
RC1
RC2
V
SS
CLKI/RP3/RA2
CLKO/RP4/RA3
(1)
SOSCI/RP5/RB4
SOSCO/RP6/RA4
RP20/RA9
V
SS
V
DD
RC3
PGED3/RB5
PGEC3/RB6
RP11/RB7
RP7/RB8
(1)
RP8/RB9
(1)
RC8
RP19/RC9
V
CAP
V
DD
PGEC2/RP18/RB11
RP12/RB12
PGED2/RP17/RB10
RP13/RB13
RP9/RB14
RP10/RB15
(1)
AV
SS
AV
DD
MCLR
RP1/RA0
RP2/RA1
PGED1/RP14/RB0
PGEC1/RP15/RB1
9
1
2
3
4
5
16
17
18
10
11
12
13
31
7
6
36
35
34
33
32
14
15
24
25
26
27
19
20
21
22
23
29
28
8
30
PIC32MMXXXXGPL036
Legend: Shaded pins are up to 5V tolerant.
Note 1: Pin has an increased current drive strength. Refer to Section 26.0 “Electrical Characteristics” for details.
TABLE 6: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 36-PIN VQFN DEVICES
Pin Function Pin Function
1AN4/C1INB/RP16/RB2 19 TMS/REFCLKI/RP8/T1CK/T1G/U1RTS/U1BCLK/SDO1/C2OUT/OCM1B/INT2/RB9(1)
2AN11/C1INA/RB3 20 RC8
3AN12/RC0 21 RP19/RC9
4AN13/RC1 22 VCAP
5RC2 23 VDD
6 VSS 24 PGED2/TDO/RP17/RB10
7OSC1/CLKI/AN5/RP3/OCM1C/RA2 25 PGEC2/TDI/RP18/RB11
8OSC2/CLKO/AN6/RP4/OCM1D/RA3(1)26 AN7/LVDIN/RP12/RB12
9SOSCI/RP5/RB4 27 AN8/RP13/RB13
10 SOSCO/SCLKI/RP6/PWRLCLK/RA4 28 CDAC1/AN9/RP9/RTCC/U1TX/SDI1/C1OUT/INT1/RB14
11 RP20/RA9 29 AN10/REFCLKO/RP10/U1RX/SS1/FSYNC1/INT0/RB15(1)
12 VSS 30 AVSS
13 VDD 31 AVDD
14 RC3 32 MCLR
15 PGED3/RB5 33 VREF+/AN0/RP1/OCM1E/INT3/RA0
16 PGEC3/RB6 34 VREF-/AN1/RP2/OCM1F/RA1
17 RP11/RB7 35 PGED1/AN2/C1IND/C2INB/RP14/RB0
18 TCK/RP7/U1CTS/SCK1/OCM1A/RB8(1)36 PGEC1/AN3/C1INC/C2INA/RP15/RB1
Note 1: Pin has an increased current drive strength.
PIC32MM0064GPL036 FAMILY
DS60001324B-page 8 2015-2016 Microchip Technology Inc.
Pin Diagrams (Continued)
40-Pin UQFN
RP16/RB2
RB3
RC0
RC1
RC2
V
SS
OSCI/RP3/RA2
OSCO/RP4/RA3(1)
SOSCI/RP5/RB4
SOSCO/RP6/RA4
RP20/RA9
V
SS
V
DD
RC3
RB5/PGED3
RB6/PGEC3
RP11/RB7
RP7/RB8
(1)
N/C
RP8
/RB9
(1)
RC8
RP19/RC9
N/C
V
CAP
N/C
V
DD
RP17/RB10/PGED2
RP18/RB11/PGEC2
RP12/RB12
RP13/RB13
RP9
/RB14
RP10
/RB15(1)
AV
SS
AV
DD
MCLR
RP1
/RA0
RP2
/RA1
RP14
/RB0/PGED1
RP15
/RB1/PGEC1
N/C
PIC32MMXXXXGPL036
9
1
2
3
4
5
17
18
19
11
12
13
14
34
7
6
39
38
37
36
35
15
16
26
27
28
29
21
22
23
24
25
32
31
8
33
10
20
30
40
Legend: Shaded pins are up to 5V tolerant.
Note 1: Pin has an increased current drive strength. Refer to Section 26.0 “Electrical Characteristics” for details.
TABLE 7: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 40-PIN UQFN DEVICES
Pin Function Pin Function
1AN4/C1INB/RP16/RB2 21 RC8
2AN11/C1INA/RB3 22 RP19/RC9
3AN12/RC0 23 N/C
4AN13/RC1 24 VCAP
5RC2 25 N/C
6 VSS 26 VDD
7OSC1/CLKI/AN5/RP3/OCM1C/RA2 27 PGED2/TDO/RP17/RB10
8OSC2/CLKO/AN6/RP4/OCM1D/RA3(1)28 PGEC2/TDI/RP18/RB11
9SOSCI/RP5/RB4 29 AN7/LVDIN/RP12/RB12
10 SOSCO/SCLKI/RP6/PWRLCLK/RA4 30 AN8/RP13/RB13
11 RP20/RA9 31 CDAC1/AN9/RP9/RTCC/U1TX/SDI1/C1OUT/INT1/RB14
12 VSS 32 AN10/REFCLKO/RP10/U1RX/SS1/FSYNC1/INT0/RB15(1)
13 VDD 33 AVSS
14 RC3 34 AVDD
15 PGED3/RB5 35 MCLR
16 PGEC3/RB6 36 VREF+/AN0/RP1/OCM1E/INT3/RA0
17 RP11/RB7 37 VREF-/AN1/RP2/OCM1F/RA1
18 TCK/RP7/U1CTS/SCK1/OCM1A/RB8(1)38 PGED1/AN2/C1IND/C2INB/RP14/RB0
19 N/C 39 PGEC1/AN3/C1INC/C2INA/RP15/RB1
20 TMS/REFCLKI/RP8/T1CK/T1G/U1RTS/U1BCLK/SDO1/
C2OUT/OCM1B/INT2/RB9(1)40 N/C
Note 1: Pin has an increased current drive strength.
2015-2016 Microchip Technology Inc. DS60001324B-page 9
PIC32MM0064GPL036 FAMILY
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 13
2.0 Guidelines for Getting Started with 32-Bit Microcontrollers........................................................................................................ 19
3.0 CPU............................................................................................................................................................................................ 23
4.0 Memory Organization ................................................................................................................................................................. 33
5.0 Flash Program Memory.............................................................................................................................................................. 37
6.0 Resets ........................................................................................................................................................................................ 45
7.0 CPU Exceptions and Interrupt Controller ................................................................................................................................... 51
8.0 Oscillator Configuration .............................................................................................................................................................. 65
9.0 I/O Ports ..................................................................................................................................................................................... 77
10.0 Timer1 ........................................................................................................................................................................................ 87
11.0 Watchdog Timer (WDT) ............................................................................................................................................................. 91
12.0 Capture/Compare/PWM/Timer Modules (MCCP and SCCP) .................................................................................................... 95
13.0 Serial Peripheral Interface (SPI) and Inter-IC Sound (I
2
S)....................................................................................................... 109
14.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 117
15.0 Real-Time Clock and Calendar (RTCC)................................................................................................................................... 123
16.0 12-Bit Analog-to-Digital Converter with Threshold Detect........................................................................................................ 133
17.0 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator ........................................................................................ 147
18.0 Configurable Logic Cell (CLC).................................................................................................................................................. 151
19.0 Comparator .............................................................................................................................................................................. 163
20.0 Control Digital-to-Analog Converter (CDAC)............................................................................................................................ 169
21.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 173
22.0 Power-Saving Features ........................................................................................................................................................... 177
23.0 Special Features ...................................................................................................................................................................... 181
24.0 Development Support............................................................................................................................................................... 199
25.0 Instruction Set .......................................................................................................................................................................... 203
26.0 Electrical Characteristics.......................................................................................................................................................... 205
27.0 Packaging Information.............................................................................................................................................................. 233
Appendix A: Revision History............................................................................................................................................................. 257
Index .................................................................................................................................................................................................. 259
The Microchip Web Site..................................................................................................................................................................... 263
Customer Change Notification Service .............................................................................................................................................. 263
Customer Support .............................................................................................................................................................................. 263
Product Identification System ............................................................................................................................................................ 265
PIC32MM0064GPL036 FAMILY
DS60001324B-page 10 2015-2016 Microchip Technology Inc.
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2015-2016 Microchip Technology Inc. DS60001324B-page 11
PIC32MM0064GPL036 FAMILY
Referenced Sources
This device data sheet is based on the following
individual sections of the “PIC32 Family Reference
Manual”. These documents should be considered as
the general reference for the operation of a particular
module or device feature.
•Section 1. “Introduction” (DS60001127)
•Section 5. “Flash Pr ogram min g” (DS60001121)
•Section 7. “Resets” (DS60001118)
•Section 8. “Interrupts” (DS60001108)
•Section 10. “Power-Saving Modes” (DS60001130)
•Section 14. “Timers” (DS60001105)
•Section 19. “Comparator” (DS60001110)
•Section 21. “UART” (DS61107)
•Section 23. “Serial Peripheral Interface (SPI)” (DS61106)
•Section 25. “12-Bit Analog-to-Digital Converter (ADC) with Threshold Detect” (DS60001359)
•Section 28. “RTCC with Timestamp” (DS60001362)
•Section 30. “Capture/Compare/PWM/Timer (MCCP and SCCP)” (DS60001381)
•Section 33. “Programming and Diagnostics” (DS61129)
•Section 36. “Configurable Logic Cell” (DS60001363)
•Section 45. “Control Digital-to-Analog Converter (CDAC)” (DS60001327)
•Section 50. “CPU for Devices with MIPS32
®
microAptiv™ and M-Class Cores” (DS60001192)
•Section 59. “Oscillators with DCO” (DS60001329)
•Section 60. “32-Bit Programmable Cyclic Redundancy Check (CRC)” (DS60001336)
•Section 62. “Dual Watchdog Timer” (DS60001365)
Note: To access the documents listed below,
browse the documentation section of the
Microchip web site (www.microchip.com).
PIC32MM0064GPL036 FAMILY
DS60001324B-page 12 2015-2016 Microchip Technology Inc.
NOTES:
2015-2016 Microchip Technology Inc. DS60001324B-page 13
PIC32MM0064GPL036 FAMILY
1.0 DEVICE OVERVIEW
This data sheet contains device-specific information for
the PIC32MM0064GPL036 family devices.
Figure 1-1 illustrates a general block diagram of the core
and peripheral modules in the PIC32MM0064GPL036
family of devices.
Table 1-1 lists the pinout I/O descriptions for the pins
shown in the device pin tables.
FIGURE 1-1: PIC32MM0064GPL036 FAMILY BLOCK DIAGRAM
Note: This data sheet summarizes the features
of the PIC32MM0064GPL036 family of
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
the “PIC32 Family Reference Manual”,
which is available from the Microchip
web site (www.microchip.com/PIC32). The
information in this data sheet supersedes
the information in the FRM.
UART1,2
Comparators
PORTA
PORTB
JTAG Priority
ICD
IS DS
EJTAG INT
Bus Matrix
Line Buffer RAM Peripheral Bridge
64
64-Bit Wide Flash
32
32 32
Peripheral Bus Clocked by PBCLK
Program Flash Memory Controller
32
Module
32 32
Interrupt
Controller
Boundary
PORTC
CRC
5-Bit DAC
SPI1,2
SCCP2,3
MCCP1
OSC1/CLKI
OSC2/CLKO
VDD,
Timing
Generation
VSS
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Precision
Reference
Band Gap
Regulator
Voltage
VCAP
Primary
Dividers
SYSCLK
PBCLK (1:1 with SYSCLK)
Peripheral Bus Clocked by PBCLK
PLL
RTCC
12-Bit ADC
Timer1
32
32
Oscillator
FRC/LPRC
Oscillators
SOSCO/SCLKI Secondary
Oscillator
AVDD, AVSS
I/O Change
Notification
HLVD
MIPS32® microAptiv™ UC
CPU Core
SOSCI
Scan
PIC32MM0064GPL036 FAMILY
DS60001324B-page 14 2015-2016 Microchip Technology Inc.
TABLE 1-1: PIC32MM0064GPL036 FAMILY PINOUT DESCRIPTION
Pin Name
Pin Num b e r
Pin
Type Buffer
Type Description
20-Pin
QFN 20-Pin
SSOP
28-Pin
QFN/
UQFN
28-Pin
SPDIP/
SSOP/SOIC
36-Pin
VQFN 40-Pin
UQFN
AN0 19 2 27 2 33 36 I ANA Analog-to-Digital Converter input channels
AN1 20 3 28 3 34 37 I ANA
AN2 1 4 1 4 35 38 I ANA
AN3 2 5 2 5 36 39 I ANA
AN4 3 6 3 6 1 1 I ANA
AN5 4 7 6 9 7 7 I ANA
AN6 5 8 7 10 8 8 I ANA
AN7 12 15 20 23 26 29 I ANA
AN8 13 16 21 24 27 30 I ANA
AN9 14 17 22 25 28 31 I ANA
AN10 15 18 23 26 29 32 I ANA
AN11 — — 4 7 2 2 I ANA
AN12 — — — — 3 3 I ANA
AN13 — — — — 4 4 I ANA
AV
DD
17 20 25 28 31 34 P — Analog modules power supply
AV
SS
16 19 24 27 30 33 P — Analog modules ground
C1INA 5 8 4 7 2 2 I ANA Comparator 1 Input A
C1INB 4 7 3 6 1 1 I ANA Comparator 1 Input B
C1INC 2 5 2 5 36 39 I ANA Comparator 1 Input C
C1IND 1 4 1 4 35 38 I ANA Comparator 1 Input D
C1OUT 14 17 22 25 28 31 O DIG Comparator 1 output
C2INA 2 5 2 5 36 39 I ANA Comparator 2 Input A
C2INB 1 4 1 4 35 38 I ANA Comparator 2 Input B
C2OUT 10 13 15 18 19 20 O DIG Comparator 2 output
CLKI 4 7 6 9 7 7 I ST External Clock input (EC mode)
CLKO 5 8 7 10 8 8 O DIG System clock output
CDAC1 14 17 22 25 28 31 O ANA Digital-to-Analog Converter output
FSYNC1 15 18 23 26 29 32 I/O ST/DIG SPI1 frame signal input or output
INT0 15 18 23 26 29 32 I ST External Interrupt 0
INT1 14 17 22 25 28 31 I ST External Interrupt 1
INT2 10 13 15 18 19 20 I ST External Interrupt 2
INT3 19 2 27 2 33 36 I ST External Interrupt 3
LVDIN 12 15 20 23 26 29 I ANA High/Low-Voltage Detect input
MCLR 18 1 26 1 32 35 I ST Master Clear (device Reset)
OCM1A 9 12 14 17 18 18 O DIG MCCP1 Output A
OCM1B 10 13 15 18 19 20 O DIG MCCP1 Output B
OCM1C 4 7 6 9 7 7 O DIG MCCP1 Output C
OCM1D 5 8 7 10 8 8 O DIG MCCP1 Output D
OCM1E 19 2 27 2 33 36 O DIG MCCP1 Output E
OCM1F 20 3 28 3 34 37 O DIG MCCP1 Output F
OSC1 4 7 6 9 7 7 — — Primary Oscillator crystal
OSC2 5 8 7 10 8 8 — — Primary Oscillator crystal
Legend: ST = Schmitt Trigger input buffer DIG = Digital input/output ANA = Analog level input/output
2015-2016 Microchip Technology Inc. DS60001324B-page 15
PIC32MM0064GPL036 FAMILY
PGEC1 2 5 2 5 36 39 I ST ICSP Port 1 programming clock input
PGEC2 19 2 19 22 25 28 I ST ICSP Port 2 programming clock input
PGEC3 7 10 12 15 16 16 I ST ICSP Port 3 programming clock input
PGED1 1 4 1 4 35 38 I/O ST/DIG ICSP Port 1 programming data
PGED2 20 3 18 21 24 27 I/O ST/DIG ICSP Port 2 programming data
PGED3 6 9 11 14 15 15 I/O ST/DIG ICSP Port 3 programming data
PWRLCLK 7 10 9 12 10 10 I ST Real-Time Clock 50/60 Hz clock input
RA0 19 2 27 2 33 36 I/O ST/DIG PORTA digital I/O
RA1 20 3 28 3 34 37 I/O ST/DIG PORTA digital I/O
RA2 4 7 6 9 7 7 I/O ST/DIG PORTA digital I/O
RA3 5 8 7 10 8 8 I/O ST/DIG PORTA digital I/O
RA4 7 10 9 12 10 10 I/O ST/DIG PORTA digital I/O
RA9 — — — — 11 11 I/O ST/DIG PORTA digital I/O
RB0 1 4 1 4 35 38 I/O ST/DIG PORTB digital I/O
RB1 2 5 2 5 36 39 I/O ST/DIG PORTB digital I/O
RB2 3 6 3 6 1 1 I/O ST/DIG PORTB digital I/O
RB3 — — 4 7 2 2 I/O ST/DIG PORTB digital I/O
RB4 6 9 8 11 9 9 I/O ST/DIG PORTB digital I/O
RB5 — — 11 14 15 15 I/O ST/DIG PORTB digital I/O
RB6 — — 12 15 16 16 I/O ST/DIG PORTB digital I/O
RB7 8 11 13 16 17 17 I/O ST/DIG PORTB digital I/O
RB8 9 12 14 17 18 18 I/O ST/DIG PORTB digital I/O
RB9 10 13 15 18 19 20 I/O ST/DIG PORTB digital I/O
RB10 — — 18 21 24 27 I/O ST/DIG PORTB digital I/O
RB11 — — 19 22 25 28 I/O ST/DIG PORTB digital I/O
RB12 12 15 20 23 26 29 I/O ST/DIG PORTB digital I/O
RB13 13 16 21 24 27 30 I/O ST/DIG PORTB digital I/O
RB14 14 17 22 25 28 31 I/O ST/DIG PORTB digital I/O
RB15 15 18 23 26 29 32 I/O ST/DIG PORTB digital I/O
RC0 — — — — 3 3 I/O ST/DIG PORTC digital I/O
RC1 — — — — 4 4 I/O ST/DIG PORTC digital I/O
RC2 — — — — 5 5 I/O ST/DIG PORTC digital I/O
RC3 — — — — 14 14 I/O ST/DIG PORTC digital I/O
RC8 — — — — 20 21 I/O ST/DIG PORTC digital I/O
RC9 — — 16 19 21 22 I/O ST/DIG PORTC digital I/O
REFCLKI 10 13 15 18 19 20 I ST Reference clock input
REFCLKO 15 18 23 26 29 32 O DIG Reference clock output
TABLE 1-1: PIC32MM0064GPL036 FAMILY PINOUT DESCRIPTION (CONTINUED)
Pin Name
Pin Num b e r
Pin
Type Buffer
Type Description
20-Pin
QFN 20-Pin
SSOP
28-Pin
QFN/
UQFN
28-Pin
SPDIP/
SSOP/SOIC
36-Pin
VQFN 40-Pin
UQFN
Legend: ST = Schmitt Trigger input buffer DIG = Digital input/output ANA = Analog level input/output
PIC32MM0064GPL036 FAMILY
DS60001324B-page 16 2015-2016 Microchip Technology Inc.
RP1 19 2 27 2 33 36 I/O ST/DIG Remappable peripherals (input or output)
RP2 20 3 28 3 34 37 I/O ST/DIG
RP3 4 7 6 9 7 7 I/O ST/DIG
RP4 5 8 7 10 8 8 I/O ST/DIG
RP5 6 9 8 11 9 9 I/O ST/DIG
RP6 7 10 9 12 10 10 I/O ST/DIG
RP7 9 12 14 17 18 18 I/O ST/DIG
RP8 10 13 15 18 19 20 I/O ST/DIG
RP9 14 17 22 25 28 31 I/O ST/DIG
RP10 15 18 23 26 29 32 I/O ST/DIG
RP11 8 11 13 16 17 17 I/O ST/DIG
RP12 12 15 20 23 26 29 I/O ST/DIG
RP13 13 16 21 24 27 30 I/O ST/DIG
RP14 1 4 1 4 35 38 I/O ST/DIG
RP15 2 5 2 5 36 39 I/O ST/DIG
RP16 3 6 3 6 1 1 I/O ST/DIG
RP17 — — 18 21 24 27 I/O ST/DIG
RP18 — — 19 22 25 28 I/O ST/DIG
RP19 — — 16 19 21 22 I/O ST/DIG
RP20 — — — — 11 11 I/O ST/DIG
RTCC 14 17 22 25 28 31 O DIG Real-Time Clock alarm/seconds output
SCK1 9 12 14 17 18 18 I/O ST/DIG SPI1 clock (input or output)
SCLKI 7 10 9 12 10 10 I ST Secondary Oscillator external clock input
SDI1 14 17 22 25 28 31 I ST SPI1 data input
SDO1 10 13 15 18 19 20 O DIG SPI1 data output
SOSCI 6 9 8 11 9 9 — — Secondary Oscillator crystal
SOSCO 7 10 9 12 10 10 — — Secondary Oscillator crystal
SS1 15 18 23 26 29 32 I ST SPI1 slave select input
T1CK 10 13 15 18 19 20 I ST Timer1 external clock input
T1G 10 13 15 18 19 20 I ST Timer1 clock gate input
TCK 9 12 14 17 18 18 I ST JTAG clock input
TDI 13 16 19 22 25 28 I ST JTAG data input
TDO 12 15 18 21 24 27 O DIG JTAG data output
TMS 10 13 15 18 19 20 I ST JTAG mode select input
U1BCLK 10 13 15 18 19 20 O DIG UART1 IrDA
®
16x baud clock output
U1CTS 9 12 14 17 18 18 I ST UART1 transmission control input
U1RTS 10 13 15 18 19 20 O DIG UART1 reception control output
U1RX 15 18 23 26 29 32 I ST UART1 receive data input
U1TX 14 17 22 25 28 31 O DIG UART1 transmit data output
TABLE 1-1: PIC32MM0064GPL036 FAMILY PINOUT DESCRIPTION (CONTINUED)
Pin Name
Pin Num b e r
Pin
Type Buffer
Type Description
20-Pin
QFN 20-Pin
SSOP
28-Pin
QFN/
UQFN
28-Pin
SPDIP/
SSOP/SOIC
36-Pin
VQFN 40-Pin
UQFN
Legend: ST = Schmitt Trigger input buffer DIG = Digital input/output ANA = Analog level input/output
2015-2016 Microchip Technology Inc. DS60001324B-page 17
PIC32MM0064GPL036 FAMILY
V
CAP
11 14 17 20 22 24 P — Core voltage regulator filter capacitor
connection
V
DD
17 20 10,25 13,28 13,23,31 13,26,
34
P — Digital modules power supply
V
REF
- 20 3 28 3 34 37 I ANA ADC negative reference
V
REF
+ 19 2 27 2 33 36 I ANA ADC and DAC positive reference
V
SS
16 19 5,24 8,27 6,12,30 6,12,
33
P — Digital modules ground
TABLE 1-1: PIC32MM0064GPL036 FAMILY PINOUT DESCRIPTION (CONTINUED)
Pin Name
Pin Num b e r
Pin
Type Buffer
Type Description
20-Pin
QFN 20-Pin
SSOP
28-Pin
QFN/
UQFN
28-Pin
SPDIP/
SSOP/SOIC
36-Pin
VQFN 40-Pin
UQFN
Legend: ST = Schmitt Trigger input buffer DIG = Digital input/output ANA = Analog level input/output
PIC32MM0064GPL036 FAMILY
DS60001324B-page 18 2015-2016 Microchip Technology Inc.
NOTES:
2015-2016 Microchip Technology Inc. DS60001324B-page 19
PIC32MM0064GPL036 FAMILY
2.0 GUIDELINES FOR GETTING
STARTED WITH 32-BIT
MICROCONTROLLERS
2.1 Basic Connection Requirements
Getting started with the PIC32MM0064GPL036 family
of 32-bit Microcontrollers (MCUs) requires attention to
a minimal set of device pin connections before pro-
ceeding with development. The following is a list of pin
names, which must always be connected:
•All V
DD
and V
SS
pins
(see Section 2.2 “Decoupling Capacitors”)
•All AV
DD
and AV
SS
pins, even if the ADC module
is not used (see Section 2.2 “Decoupling
Capacitors”)
•MCLR pin (see Section 2.3 “Master Clear
(MCLR) Pin”)
•V
CAP
pin (see Section 2.4 “ Capacitor o n
Internal Voltage Regulato r (V
CAP
)”)
• PGECx/PGEDx pins, used for In-Circuit Serial
Programming™ (ICSP™) and debugging
purposes (see Section 2.5 “ICSP Pins”)
• OSC1 and OSC2 pins, when external oscillator
source is used (see Section 2.7 “ Ext ernal
Oscillator Pin s”)
The following pin(s) may be required as well:
V
REF
+/V
REF
- pins, used when external voltage
reference for the ADC module is implemented.
2.2 Decoupling Capacitors
The use of decoupling capacitors on power supply
pins, such as V
DD
, V
SS
, AV
DD
and AV
SS
, is required.
See Figure 2-1.
Consider the following criteria when using decoupling
capacitors:
•Value and type of capa cito r: A value of 0.1 µF
(100 nF), 10-20V is recommended. The capacitor
should be a low Equivalent Series Resistance
(low-ESR) capacitor and have resonance frequency
in the range of 20 MHz and higher. It is further
recommended that ceramic capacitors be used.
•Placement on the printed circuit board: The
decoupling capacitors should be placed as close to
the pins as possible. It is recommended that the
capacitors be placed on the same side of the board
as the device. If space is constricted, the capacitor
can be placed on another layer on the PCB using a
via; however, ensure that the trace length from the
pin to the capacitor is within one-quarter inch
(6 mm) in length.
•Handling high-frequency noise: If the board is
experiencing high-frequency noise, upward of tens
of MHz, add a second ceramic-type capacitor in par-
allel to the above described decoupling capacitor.
The value of the second capacitor can be in the
range of 0.01 µF to 0.001 µF. Place this second
capacitor next to the primary decoupling capacitor.
In high-speed circuit designs, consider implement-
ing a decade pair of capacitances, as close to the
power and ground pins as possible. For example,
0.1 µF in parallel with 0.001 µF.
•Maximiz ing perform anc e: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first, and
then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB track inductance.
Note: This data sheet summarizes the features
of the PIC32MM0064GPL036 family of
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
the “PIC32 Family Reference Manual”,
which is available from the Microchip
web site (www.microchip.com/PIC32).
The information in this data sheet
supersedes the information in the FRM.
Note: The AV
DD
and AV
SS
pins must be
connected, regardless of ADC use and
the ADC voltage reference source.
PIC32MM0064GPL036 FAMILY
DS60001324B-page 20 2015-2016 Microchip Technology Inc.
FIGURE 2-1: RECOMME NDED
MINIMUM CONNECTION
2.2.1 BULK CAPACITORS
The use of a bulk capacitor is recommended to improve
power supply stability. Typical values range from 4.7 µF
to 47 µF. This capacitor should be located as close to
the device as possible.
2.3 Master Clear (MCLR) Pin
The MCLR pin provides for two specific device
functions:
•Device Reset
• Device Programming and Debugging
Pulling The MCLR pin low generates a device Reset.
Figure 2-2 illustrates a typical MCLR circuit. During
device programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the MCLR pin. Consequently, specific voltage
levels (V
IH
and V
IL
) and fast signal transitions must
not be adversely affected. Therefore, specific values
of R and C will need to be adjusted based on the
application and PCB requirements.
For example, as illustrated in Figure 2-2, it is
recommended that the capacitor, C, be isolated from
the MCLR pin during programming and debugging
operations.
Place the components illustrated in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
FIGURE 2-2: EXAMPLE OF MCLR PIN
CONNECTIONS
(1,2,3)
2.4 Capacitor on Internal Voltage
Regulator (VCAP)
A low-ESR (<1 Ohm) capacitor is required on the V
CAP
pin, which is used to stabilize the internal voltage regu-
lator output. The V
CAP
pin must not be connected to
V
DD
and must have a C
EFC
capacitor, with at least a 6V
rating, connected to ground. The type can be ceramic
or tantalum. The recommended value of the C
EFC
capacitor is 10 μF. On the printed circuit board, it should
be placed as close to the V
CAP
pin as possible. If the
board is experiencing high-frequency noise, upward of
tens of MHz, add a second ceramic-type capacitor in
parallel to this capacitor. The value of the second
capacitor can be in the range of 0.01 μF to 0.001 μF.
PIC32
VDD
VSS
VDD
VSS
VSS
VDD
AVDD
AVSS
VDD
VSS
0.1 µF
Ceramic
0.1 µF
Ceramic
0.1 µF
Ceramic
0.1 µF
Ceramic
C
R
V
DD
MCLR
0.1 µF
Ceramic
R1
CEFC
10 µF
VCAP
Note 1: 470 R1 1 k will limit any current flowing into
MCLR from the external capacitor, C, in the event of
MCLR pin breakdown, due to Electrostatic Discharge
(ESD) or Electrical Overstress (EOS). Ensure that the
MCLR pin VIH and VIL specifications are met without
interfering with the debug/programmer tools.
2: The capacitor can be sized to prevent unintentional
Resets from brief glitches or to extend the device
Reset period during POR.
3: No pull-ups or bypass capacitors are allowed on active
debug/program PGECx/PGEDx pins.
R1(1)
10k
VDD
MCLR
PIC32
1 k
0.1 µF(2)
PGECx(3)
PGEDx(3)
ICSP™
1
5
4
2
3
6
VDD
VSS
NC
R
C
2015-2016 Microchip Technology Inc. DS60001324B-page 21
PIC32MM0064GPL036 FAMILY
2.5 ICSP Pins
The PGECx and PGEDx pins are used for In-Circuit
Serial Programming™ (ICSP™) and debugging pur-
poses. It is recommended to keep the trace length
between the ICSP connector and the ICSP pins on
the device as short as possible. If the ICSP connec-
tor is expected to experience an ESD event, a series
resistor is recommended, with the value in the range
of a few tens of Ohms, not to exceed 100 Ohms.
Pull-up resistors, series diodes and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communi-
cations to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective
device Flash programming specification for information
on capacitive loading limits and pin Input Voltage High
(V
IH
) and Input Voltage Low (V
IL
) requirements.
Ensure that the “Communication Channel Select”
(i.e., PGECx/PGEDx pins) programmed into the device
matches the physical connections for the ICSP to
MPLAB
®
ICD 3 or MPLAB REAL ICE™ In-Circuit
Emulator.
For more information on MPLAB ICD 3 and REAL ICE
connection requirements, refer to the following
documents that are available from the Microchip web site.
•“Using MPLAB
®
ICD 3 In-Circuit Debugger”
(poster) (DS51765)
•“Development Tools Design Advisory” (DS51764)
•“MPLAB
®
REAL ICE™ In-Circuit Em ulator User’s
Guide” (DS51616)
•“Using MPL AB
®
REAL ICE™ In-Circuit Emulator”
(poster) (DS51749)
2.6 JTAG
The TMS, TDO, TDI and TCK pins are used for testing
and debugging according to the Joint Test Action Group
(JTAG) standard. It is recommended to keep the trace
length between the JTAG connector, and the JTAG pins
on the device, as short as possible. If the JTAG connector
is expected to experience an ESD event, a series resistor
is recommended, with the value in the range of a few tens
of Ohms, not to exceed 100 Ohms.
Pull-up resistors, series diodes and capacitors on the
TMS, TDO, TDI and TCK pins are not recommended as
they will interfere with the programmer/debugger com-
munications to the device. If such discrete components
are an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective device
Flash programming specification for information on
capacitive loading limits, and pin Input Voltage High (V
IH
)
and Input Voltage Low (V
IL
) requirements.
2.7 External Oscillator Pins
The PIC32MM0064GPL036 family has options for two
external oscillators: a high-frequency primary oscillator
and a low-frequency secondary oscillator (refer to
Section 8.0 “Oscillator Configuration” for details).
The oscillator circuit should be placed on the same side
of the board as the device. Also, place the oscillator
circuit close to the respective oscillator pins, not
exceeding one-half inch (12 mm) distance between
them. The load capacitors should be placed next to the
oscillator itself, on the same side of the board. Use a
grounded copper pour around the oscillator circuit to
isolate them from surrounding circuits. The grounded
copper pour should be routed directly to the MCU
ground. Do not run any signal traces or power traces
inside the ground pour. Also, if using a two-sided board,
avoid any traces on the other side of the board where
the crystal is placed. A suggested layout is illustrated in
Figure 2-3.
FIGURE 2-3: SUGGESTED OSCILLATOR
CIRCUIT PLACEMENT
2.8 Unused I/Os
To minimize power consumption, unused I/O pins
should not be allowed to float as inputs. They can be
configured as outputs and driven to a logic low or logic
high state.
Alternatively, inputs can be reserved by ensuring the
pin is always configured as an input and externally con-
necting the pin to V
SS
or V
DD
. A current-limiting resistor
may be used to create this connection if there is any
risk of inadvertently configuring the pin as an output
with the logic output state opposite of the chosen power
rail.
Main Oscillator
Guard Ring
Guard Trace
Secondary
Oscillator
PIC32MM0064GPL036 FAMILY
DS60001324B-page 22 2015-2016 Microchip Technology Inc.
NOTES:
2015-2016 Microchip Technology Inc. DS60001324B-page 23
PIC32MM0064GPL036 FAMILY
3.0 CPU
The MIPS32
®
microAptiv™ UC microprocessor core is
the heart of the PIC32MM0064GPL036 family devices.
The CPU fetches instructions, decodes each
instruction, fetches source operands, executes each
instruction and writes the results of the instruction
execution to the proper destinations.
3.1 Features
The PIC32MM0064GPL036 family processor core key
features include:
• 5-Stage Pipeline
• 32-Bit Address and Data Paths
• MIPS32 Enhanced Architecture:
- Multiply-add and multiply-subtract instructions
- Targeted multiply instruction
- Zero and one detect instructions
-WAIT instruction
- Conditional move instructions
- Vectored interrupts
- Atomic interrupt enable/disable
- One GPR shadow set to minimize latency of
interrupts
- Bit field manipulation instructions
• microMIPS™ Instruction Set:
- microMIPS allows improving the code size
density over MIPS32, while maintaining
MIPS32 performance.
- microMIPS supports all MIPS32 instructions
(except for branch-likely instructions) with
new optimized 32-bit encoding. Frequent
MIPS32 instructions are available as 16-bit
instructions.
- Added seventeen new and thirty-five
MIPS32
®
corresponding commonly used
instructions in 16-bit opcode format.
- Stack Pointer implicit in instruction.
- MIPS32 assembly and ABI compatible.
• Memory Management Unit with Simple Fixed
Mapping Translation (FMT) Mechanism
• Multiply/Divide Unit (MDU):
- Configurable using high-performance
multiplier array.
- Maximum issue rate of one 32x16 multiply
per clock.
- Maximum issue rate of one 32x32 multiply
every other clock.
- Early-in iterative divide. Minimum 11 and
maximum 33 clock latency (dividend (rs) sign
extension dependent).
• Power Control:
- No minimum frequency: 0 MHz.
- Power-Down mode (triggered by WAIT
instruction).
• EJTAG Debug/Profiling:
- CPU control with start, stop and single
stepping.
- Software breakpoints via the SDBBP
instruction.
- Optional simple hardware breakpoints on
virtual addresses, 4 instruction and 2 data
breakpoints.
- PC and/or load/store address sampling for
profiling.
- Performance counters.
- Supports Fast Debug Channel (FDC).
A block diagram of the PIC32MM0064GPL036 family
processor core is shown in Figure 3-1.
Note: This data sheet summarizes the features
of the PIC32MM0064GPL036 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 50. “CPU for
Devices with MIPS32
®
microAptiv™
and M-Class Cores” (DS60001192) in
the “PIC32 Family Reference Manual”,
which is available from the Microchip
web site (www.microchip.com/PIC32).
MIPS32
®
microAptiv™ UC microproces-
sor core resources are available at:
www.imgtec.com. The information in this
data sheet supersedes the information in
the FRM.
PIC32MM0064GPL036 FAMILY
DS60001324B-page 24 2015-2016 Microchip Technology Inc.
FIGURE 3-1: PIC32M M00 64GP L 036 FAMILY MICROPROCESSOR CORE
BLOCK DIAGRAM
System Bus
Execution Unit
ALU/Shift
Atomic/LdSt
MCU ASE
System
Coprocessor
Enhanced MDU
GPR
(2 sets)
Debug/Profiling
Breakpoints
Fast Debug Channel
Performance Counters
Power
System
Interface
Interrupt
Interface
MMU
Decode
(microMIPS™)
EJTAG
2-Wire Debug
Management
SYSCLK
MIPS32® microAptiv™ UC Microprocessor Core
2015-2016 Microchip Technology Inc. DS60001324B-page 25
PIC32MM0064GPL036 FAMILY
3.2 Architecture Overview
The MIPS32
®
microAptiv™ UC microprocessor core in
the PIC32MM0064GPL036 family devices contains
several logic blocks, working together in parallel, pro-
viding an efficient high-performance computing engine.
The following blocks are included with the core:
• Execution Unit
• General Purpose Register (GPR)
• Multiply/Divide Unit (MDU)
• System Control Coprocessor (CP0)
• Memory Management Unit (MMU)
• Power Management
• microMIPS Instructions Decoder
• Enhanced JTAG (EJTAG) Controller
3.2.1 EXECUTION UNIT
The processor core execution unit implements a load/
store architecture with single-cycle ALU operations
(logical, shift, add, subtract) and an autonomous Multiply/
Divide Unit (MDU). The core contains thirty-two 32-bit
General Purpose Registers (GPRs) used for integer
operations and address calculation. One additional
register file shadow set (containing thirty-two registers) is
added to minimize context switching overhead during
interrupt/exception processing. The register file consists
of two read ports and one write port, and is fully bypassed
to minimize operation latency in the pipeline.
The execution unit includes:
• 32-bit adder used for calculating the data address
• Address unit for calculating the next instruction address
• Logic for branch determination and branch target
address calculation
• Load aligner
• Bypass multiplexers used to avoid Stalls when
executing instruction streams where data produc-
ing instructions are followed closely by consumers
for their results
• Leading zero/one detect unit for implementing the
CLZ and CLO instructions
• Arithmetic Logic Unit (ALU) for performing
arithmetic and bitwise logical operations
• Shifter and store aligner
3.2.2 MULTIPLY/DIVIDE UNIT (MDU)
The microAptiv UC core includes a Multiply/Divide Unit
(MDU) that contains a separate pipeline for multiply
and divide operations. This pipeline operates in parallel
with the Integer Unit (IU) pipeline and does not stall
when the IU pipeline stalls. This allows the long-
running MDU operations to be partially masked by
system Stalls and/or other Integer Unit instructions.
The high-performance MDU consists of a 32x16 booth
recoded multiplier, Result/Accumulation registers (HI
and LO), a divide state machine, and the necessary
multiplexers and control logic. The first number shown
(‘32’ of 32x16) represents the rs operand. The second
number (‘16’ of 32x16) represents the rt operand. The
microAptiv UC core only checks the value of the rt
operand to determine how many times the operation
must pass through the multiplier. The 16x16 and 32x16
operations pass through the multiplier once. A 32x32
operation passes through the multiplier twice.
The MDU supports execution of one 16x16 or 32x16
multiply operation every clock cycle; 32x32 multiply
operations can be issued every other clock cycle. Appro-
priate interlocks are implemented to stall the issuance of
back-to-back, 32x32 multiply operations. The multiply
operand size is automatically determined by logic built
into the MDU. Divide operations are implemented with a
simple 1-bit-per-clock iterative algorithm. An early-in
detection checks the sign extension of the dividend (rs)
operand. If rs is 8 bits wide, 23 iterations are skipped.
For a 16-bit wide rs, 15 iterations are skipped, and for a
24-bit wide rs, 7 iterations are skipped. Any attempt to
issue a subsequent MDU instruction while a divide is still
active causes an IU pipeline Stall until the divide
operation has completed.
Table 3-1 lists the repeat rate (peak issue rate of cycles
until the operation can be re-issued), and latency
(number of cycles until a result is available) for the
microAptiv UC core multiply and divide instructions.
The approximate latency and repeat rates are listed in
terms of pipeline clocks.
TABLE 3-1: MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES
Opcode Operand Size (mul rt) (div rs)Latency Repeat Rate
MULT/MULTU, MADD/MADDU,
MSUB/MSUBU 16 bits 1 1
32 bits 2 2
MUL (GPR destination) 16 bits 2 1
32 bits 3 2
DIV/DIVU 8 bits 12 11
16 bits 19 18
24 bits 26 25
32 bits 33 32
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DS60001324B-page 26 2015-2016 Microchip Technology Inc.
The MIPS
®
architecture defines that the result of a
multiply or divide operation be placed in the HI and LO
registers. Using the Move-From-HI (MFHI) and Move-
From-LO (MFLO) instructions, these values can be
transferred to the General Purpose Register file.
In addition to the HI/LO targeted operations, the MIPS
architecture also defines a Multiply instruction, MUL,
which places the least significant results in the primary
register file instead of the HI/LO register pair. By avoid-
ing the explicit MFLO instruction, required when using the
LO register, and by supporting multiple destination
registers, the throughput of multiply-intensive operations
is increased.
Two other instructions, Multiply-Add (MADD) and
Multiply-Subtract (MSUB), are used to perform the
multiply-accumulate and multiply-subtract operations.
The MADD instruction multiplies two numbers and then
adds the product to the current contents of the HI and
LO registers. Similarly, the MSUB instruction multiplies
two operands and then subtracts the product from the
HI and LO registers. The MADD and MSUB operations
are commonly used in DSP algorithms.
3.2.3 SYSTEM CONTROL
COPROCESSOR (CP0)
In the MIPS architecture, CP0 is responsible for the
virtual-to-physical address translation, the exception
control system, the processor’s diagnostics capability,
the operating modes (Kernel, User and Debug) and
whether interrupts are enabled or disabled. These
configuration options and other system information is
available by accessing the CP0 registers listed in
Table 3-2.
2015-2016 Microchip Technology Inc. DS60001324B-page 27
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TABLE 3-2: COPROCESSOR 0 REGISTERS
Register
Number Register
Name Function
0-3 Reserved Reserved in the microAptiv™ UC.
4 UserLocal User information that can be written by privileged software and read via
RDHWR, Register 29.
5-6 Reserved Reserved in the microAptiv UC.
7 HWREna Enables access via the RDHWR instruction to selected hardware registers in
Non-Privileged mode.
8BadVAddr
(1)
Reports the address for the most recent address related exception.
9 Count
(1)
Processor cycle count.
10 Reserved Reserved in the microAptiv UC.
11 Compare
(1)
Timer interrupt control.
12 Status/
IntCtl/
SRSCtl/
SRSMap1/
View_IPL/
SRSMAP2
Processor status and control; interrupt control and shadow set control.
13 Cause
(1)
/
View_RIPL
Cause of last exception.
14 EPC
(1)
Program Counter at last exception.
15 PRId/
EBase/
CDMMBase
Processor identification and revision; exception base address; Common Device
Memory Map Base register.
16 CONFIG/
CONFIG1/
CONFIG2/
CONFIG3/
CONFIG7
Configuration registers.
7-22 Reserved Reserved in the microAptiv UC.
23 Debug/
Debug2/
TraceControl/
TraceControl2/
UserTraceData1/
TraceBPC
(2)
EJTAG Debug register.
EJTAG Debug Register 2.
EJTAG Trace Control register.
EJTAG Trace Control Register 2.
EJTAG User Trace Data 1 register.
EJTAG Trace Breakpoint register.
24 DEPC
(2)
/
UserTraceData2
Program Counter at last debug exception.
EJTAG User Trace Data 2 register.
25 PerfCtl0/
PerfCnt0/
PerfCtl1/
PerfCnt1
Performance Counter 0 control.
Performance Counter 0.
Performance Counter 1 control.
Performance Counter 1.
26 ErrCtl Software parity check enable.
27 CacheErr Records information about SRAM parity errors.
28-29 Reserved Reserved in the PIC32 core.
30 ErrorEPC
(1)
Program Counter at last error.
31 DeSAVE
(2)
Debug Handler Scratchpad register.
Note 1: Registers used in exception processing.
2: Registers used in debug.
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DS60001324B-page 28 2015-2016 Microchip Technology Inc.
3.3 Power Management
The processor core offers a number of power
management features, including low-power design,
active power management and Power-Down modes
of operation. The core is a static design that
supports slowing or halting the clocks, which reduces
system power consumption during Idle periods.
The mechanism for invoking Power-Down mode is
implemented through execution of the WAIT
instruction. The majority of the power consumed by
the processor core is in the clock tree and clocking
registers. The PIC32MM family makes extensive use
of local gated clocks to reduce this dynamic power
consumption.
3.4 EJTAG Debug Support
The microAptiv UC core has an Enhanced JTAG
(EJTAG) interface for use in the software debug. In
addition to the standard mode of operation, the
microAptiv UC core provides a Debug mode that is
entered after a debug exception (derived from a hard-
ware breakpoint, single-step exception, etc.) is taken
and continues until a Debug Exception Return (DERET)
instruction is executed. During this time, the processor
executes the debug exception handler routine.
The EJTAG interface operates through the Test
Access Port (TAP), a serial communication port used
for transferring test data in and out of the microAptiv
UC core. In addition to the standard JTAG instructions,
special instructions defined in the EJTAG specification
specify which registers are selected and how they are
used.
3.5 MIPS32® microAptiv™ UC Core
Configuration
Register 3-1 through Register 3-4 show the default
configuration of the microAptiv UC core, which is
included on PIC32MM0064GPL036 family devices.
2015-2016 Microchip Technology Inc. DS60001324B-page 29
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REGISTER 3-1: CONFIG: CONFIGURATION REGISTER; CP0 REGISTER 16, SELECT 0
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
r-1 R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 r-0
— K23<2:0> KU<2:0> —
23:16
r-0 R-0 R-1 R-0 r-0 r-0 r-0 R-1
— UDI SB MDU — — —DS
15:8
R-0 R-0 R-0 R-0 R-0 R-1 R-0 R-1
BE AT<1:0> AR<2:0> MT<2:1>
7:0
R-1 r-0 r-0 r-0 r-0 R/W-0 R/W-1 R/W-0
MT<0> — — — — K0<2:0>
Legend: r = Reserved bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 Reserved: This bit is hardwired to ‘1’ to indicate the presence of the CONFIG1 register
bit 30-28 K23<2:0>: Cacheability of the kseg2 and kseg3 Segments bits
010 = Cache is not implemented
bit 27-25 KU<2:0>: Cacheability of the kuseg and useg Segments bits
010 = Cache is not implemented
bit 24-23 Reserved: Must be written as zeros; returns zeros on reads
bit 22 UDI: User-Defined bit
0 = CorExtend user-defined instructions are not implemented
bit 21 SB: SimpleBE bit
1 = Only simple byte enables are allowed on the internal bus interface
bit 20 MDU: Multiply/Divide Unit bit
0 = Fast, high-performance MDU
bit 19-17 Reserved: Must be written as zeros; returns zeros on reads
bit 16 DS: Dual SRAM Interface bit
1 = Dual instruction/data SRAM interface
bit 15 BE: Endian Mode bit
0 = Little-endian
bit 14-13 AT<1:0>: Architecture Type bits
00 = MIPS32
®
bit 12-10 AR<2:0>: Architecture Revision Level bits
001 = MIPS32
Release 2
bit 9-7 MT<2:0>: MMU Type bits
011 = Fixed mapping
bit 6-3 Reserved: Must be written as zeros; returns zeros on reads
bit 2-0 K0<2:0>: kseg0 Coherency Algorithm bits
010 = Cache is not implemented
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DS60001324B-page 30 2015-2016 Microchip Technology Inc.
REGISTER 3-2: CONFIG1: CONFIGURATION REGISTER 1; CP0 REGISTER 16, SELECT 1
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
r-1 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
U-0 U-0 U-0 R-1 R-0 R-0 R-1 R-0
— — —PCWRCAEPFP
Legend: r = Reserved bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 Reserved: This bit is hardwired to a ‘1’ to indicate the presence of the CONFIG2 register
bit 30-5 Unimplemented: Read as ‘0’
bit 4 PC: Performance Counter bit
1 = The processor core contains performance counters
bit 3 WR: Watch Register Presence bit
0 = No Watch registers are present
bit 2 CA: Code Compression Implemented bit
0 = No MIPS16e
®
are present
bit 1 EP: EJTAG Present bit
1 = Core implements EJTAG
bit 0 FP: Floating-Point Unit bit
0 = Floating-Point Unit is not implemented
2015-2016 Microchip Technology Inc. DS60001324B-page 31
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REGISTER 3-3: CONFIG3: CONFIGURATION REGISTER 3; CP0 REGISTER 16, SELECT 3
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
r-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 R-0 R-1 R-0 R-0 R-0 R-1 R-1
— IPLW<1:0> MMAR<2:0> MCU ISAONEXC
15:8
R-0 R-1 R-1 R-1 U-0 U-0 U-0 R-0
ISA<1:0> ULRI RXI — — —ITL
7:0
U-0 R-1 R-1 R-0 R-1 U-0 U-0 R-0
— VEIC VINT SP CDMM ——TL
Legend: r = Reserved bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 Reserved: This bit is hardwired as ‘0’
bit 30-23 Unimplemented: Read as ‘0’
bit 22-21 IPLW<1:0>: Width of the Status IPL and Cause RIPL bits
01 = IPL and RIPL bits are 8 bits in width
bit 20-18 MMAR<2:0>: microMIPS™ Architecture Revision Level bits
000 = Release 1
bit 17 MCU: MIPS
®
MCU ASE Implemented bit
1 = MCU ASE is implemented
bit 16 ISAONEXC: ISA on Exception bit
1 = microMIPS is used on entrance to an exception vector
bit 15-14 ISA<1:0>: Instruction Set Availability bits
01 = Only microMIPS is implemented
bit 13 ULRI: UserLocal Register Implemented bit
1 = UserLocal Coprocessor 0 register is implemented
bit 12 RXI: RIE and XIE Implemented in PageGrain bit
1 = RIE and XIE bits are implemented
bit 11-9 Unimplemented: Read as ‘0’
bit 8 ITL: Indicates that iFlowtrace™ Hardware is Present bit
0 = The iFlowtrace hardware is not implemented in the core
bit 7 Unimplemented: Read as ‘0’
bit 6 VEIC: External Vector Interrupt Controller bit
1 = Support for an external interrupt controller is implemented.
bit 5 VINT: Vector Interrupt bit
1 = Vector interrupts are implemented
bit 4 SP: Small Page bit
0 = 4-Kbyte page size
bit 3 CDMM: Common Device Memory Map bit
1 = CDMM is implemented
bit 2-1 Unimplemented: Read as ‘0’
bit 0 TL: Trace Logic bit
0 = Trace logic is not implemented
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DS60001324B-page 32 2015-2016 Microchip Technology Inc.
REGISTER 3-4: CONFIG5: CONFIGURATION REGISTER 5; CP0 REGISTER 16, SELECT 5
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-1
— — — — — — —NF
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-1 Unimplemented: Read as ‘0’
bit 0 NF: Nested Fault bit
1 = Nested Fault feature is implemented
2015-2016 Microchip Technology Inc. DS60001324B-page 33
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4.0 MEMORY ORGAN IZATION
PIC32MM microcontrollers provide 4 Gbytes of unified
virtual memory address space. All memory regions,
including program, data memory, SFRs and Configura-
tion registers, reside in this address space at their
respective unique addresses. The data memory can be
made executable, allowing the CPU to execute code
from data memory.
Key features include:
• 32-Bit Native Data Width
• Separate Boot Flash Memory (BFM) for
Protected Code
• Robust Bus Exception Handling to Intercept
Runaway Code
• Simple Memory Mapping with Fixed Mapping
Translation (FMT) Unit
The PIC32MM0064GPL036 family devices implement
two address spaces: virtual and physical. All hardware
resources, such as program memory, data memory and
peripherals, are located at their respective physical
addresses. Virtual addresses are exclusively used by the
CPU to fetch and execute instructions. Physical address-
es are used by peripherals, such as Flash controllers,
that access memory independently of the CPU.
The virtual address space is divided into two segments
of 512 Mbytes each, labeled kseg0 and kseg1. The
Program Flash Memory (PFM) and Data RAM Memory
(DRM) are accessible from either kseg0 or kseg1, while
the Boot Flash Memory (BFM) and peripheral SFRs are
accessible only from kseg1.
The Fixed Mapping Translation (FMT) unit translates
the memory segments into corresponding physical
address regions. Figure 4-1 through Figure 4-3 illus-
trate the fixed mapping scheme, implemented by the
PIC32MM0064GPL036 family core, between the virtual
and physical address space.
The mapping of the memory segments depends on the
CPU error level, set by the ERL bit in the CPU STATUS
Register (SR). Error level is set (ERL = 1) by the CPU
on a Reset, Soft Reset or NMI. In this mode, the CPU
can access memory by the physical address. This
mode is provided for compatibility with other MIPS
®
processor cores that use a TLB-based MMU. The C
start-up code clears the ERL bit to zero, so that when
application software starts up, it sees the proper virtual
to physical memory mapping.
4.1 Alter nate Configuration Bits
Space
Every Configuration Word has an associated Alternate
Word (designated by the letter A as the first letter in the
name of the word). During device start-up, Primary
Words are read, and if uncorrectable ECC errors are
found, the BCFGERR (RCON<27>) flag is set and
Alternate Words are used. If uncorrectable ECC errors
are found in Primary and Alternate Words, the
BCFGFAIL (RCON<26>) flag is set, and the default
configuration is used. The Primary Configuration bits
area is located at the address range, from 0x1FC01780
to 0x1FC017E8. The Alternate Configuration bits area
is located at the address range, from 0x1FC01700 to
0x1FC01768.
PIC32MM0064GPL036 FAMILY
DS60001324B-page 34 2015-2016 Microchip Technology Inc.
FIGURE 4-1: MEMORY MAP FOR DEVICES WITH 16 Kbytes OF PROGRAM MEMORY
(1)
Virtual
Memory Map
0x00000000 Reserved
0x7FFFFFFF
0x80000000 4 Kbytes RAM
0x80000FFF
0x80001000 Reserved
0x9CFFFFFF
0x9D000000 16 Kbytes Flash
0x9D003FFF
0x9D004000 Reserved Physical
Memory Map
0x9F7FFFFF
0x9F800000 SFRs(2)4 Kbytes RAM 0x00000000
0x9F80FFFF 0x00000FFF
0x9F810000 Reserved Reserved 0x00001000
0x9FBFFFFF 0x1CFFFFFF
0x9FC00000 Boot Flash(2)16 Kbytes Flash 0x1D000000
0x9FC016FF 0x1D003FFF
0x9FC01700 Configuration Bits(2,3)Reserved 0x1D004000
0x9FC017FF 0x1F7FFFFF
0x9FC01800 Reserved SFRs 0x1F800000
0x9FFFFFFF 0x1F80FFFF
0xA0000000 4 Kbytes RAM Reserved 0x1F810000
0xA0000FFF 0x1FBFFFFF
0xA0001000 Reserved Boot Flash 0x1FC00000
0xBCFFFFFF 0x1FC016FF
0xBD000000 16 Kbytes Flash Configuration Bits(3)0x1FC01700
0xBD003FFF 0x1FC017FF
0xBD004000 Reserved Reserved 0x1FC01800
0xBF7FFFFF 0xFFFFFFFF
0xBF800000 SFRs
0xBF80FFFF
0xBF810000 Reserved
0xBFBFFFFF
0xBFC00000 Boot Flash
0xBFC016FF
0xBFC01700 Configuration Bits(3)
0xBFC017FF
0xBFC01800 Reserved
0xFFFFFFFF
Note 1: Memory areas are not shown to scale.
2: This region should be accessed from kseg1 space only.
3: Primary Configuration bits area is located at the address range, from 0x1FC01780 to 0x1FC017E8.
Alternate Configuration bits area is located at the address range, from 0x1FC01700 to 0x1FC01768.
Refer to Section 4.1 “Alternate Configuration Bits Space” for more information.
kseg1 kseg0
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FIGURE 4-2: MEMORY MAP FOR DEVICES WITH 32 Kbytes OF PROGRAM MEMORY
(1)
Virtual
Memory Map
0x00000000 Reserved
0x7FFFFFFF
0x80000000 8 Kbytes RAM
0x80001FFF
0x80002000 Reserved
0x9CFFFFFF
0x9D000000 32 Kbytes Flash
0x9D007FFF
0x9D008000 Reserved Physical
Memory Map
0x9F7FFFFF
0x9F800000 SFRs(2)8 Kbytes RAM 0x00000000
0x9F80FFFF 0x00001FFF
0x9F810000 Reserved Reserved 0x00002000
0x9FBFFFFF 0x1CFFFFFF
0x9FC00000 Boot Flash(2)32 Kbytes Flash 0x1D000000
0x9FC016FF 0x1D007FFF
0x9FC01700 Configuration Bits(2,3)Reserved 0x1D008000
0x9FC017FF 0x1F7FFFFF
0x9FC01800 Reserved SFRs 0x1F800000
0x9FFFFFFF 0x1F80FFFF
0xA0000000 8 Kbytes RAM Reserved 0x1F810000
0xA0001FFF 0x1FBFFFFF
0xA0002000 Reserved Boot Flash 0x1FC00000
0xBCFFFFFF 0x1FC016FF
0xBD000000 32 Kbytes Flash Configuration Bits(3)0x1FC01700
0xBD007FFF 0x1FC017FF
0xBD008000 Reserved Reserved 0x1FC01800
0xBF7FFFFF 0xFFFFFFFF
0xBF800000 SFRs
0xBF80FFFF
0xBF810000 Reserved
0xBFBFFFFF
0xBFC00000 Boot Flash
0xBFC016FF
0xBFC01700 Configuration Bits(3)
0xBFC017FF
0xBFC01800 Reserved
0xFFFFFFFF
Note 1: Memory areas are not shown to scale.
2: This region should be accessed from kseg1 space only.
3: Primary Configuration bits area is located at the address range, from 0x1FC01780 to 0x1FC017E8.
Alternate Configuration bits area is located at the address range, from 0x1FC01700 to 0x1FC01768.
Refer to Section 4.1 “Alternate Configuration Bits Space” for more information.
kseg1 kseg0
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DS60001324B-page 36 2015-2016 Microchip Technology Inc.
FIGURE 4-3: MEMORY MAP FOR DEVICES WITH 64 Kbytes OF PROGRAM MEMORY
(1)
Virtual
Memory Map
0x00000000 Reserved
0x7FFFFFFF
0x80000000 8 Kbytes RAM
0x80001FFF
0x80002000 Reserved
0x9CFFFFFF
0x9D000000 64 Kbytes Flash
0x9D00FFFF
0x9D010000 Reserved Physical
Memory Map
0x9F7FFFFF
0x9F800000 SFRs(2)8 Kbytes RAM 0x00000000
0x9F80FFFF 0x00001FFF
0x9F810000 Reserved Reserved 0x00002000
0x9FBFFFFF 0x1CFFFFFF
0x9FC00000 Boot Flash(2)64 Kbytes Flash 0x1D000000
0x9FC016FF 0x1D00FFFF
0x9FC01700 Configuration Bits(2,3)Reserved 0x1D010000
0x9FC017FF 0x1F7FFFFF
0x9FC01800 Reserved SFRs 0x1F800000
0x9FFFFFFF 0x1F80FFFF
0xA0000000 8 Kbytes RAM Reserved 0x1F810000
0xA0001FFF 0x1FBFFFFF
0xA0002000 Reserved Boot Flash 0x1FC00000
0xBCFFFFFF 0x1FC016FF
0xBD000000 64 Kbytes Flash Configuration Bits(3)0x1FC01700
0xBD00FFFF 0x1FC017FF
0xBD010000 Reserved Reserved 0x1FC01800
0xBF7FFFFF 0xFFFFFFFF
0xBF800000 SFRs
0xBF80FFFF
0xBF810000 Reserved
0xBFBFFFFF
0xBFC00000 Boot Flash
0xBFC016FF
0xBFC01700 Configuration Bits(3)
0xBFC017FF
0xBFC01800 Reserved
0xFFFFFFFF
Note 1: Memory areas are not shown to scale.
2: This region should be accessed from kseg1 space only.
3: Primary Configuration bits area is located at the address range, from 0x1FC01780 to 0x1FC017E8.
Alternate Configuration bits area is located at the address range, from 0x1FC01700 to 0x1FC01768.
Refer to Section 4.1 “Alternate Configuration Bits Space” for more information.
kseg1 kseg0
2015-2016 Microchip Technology Inc. DS60001324B-page 37
PIC32MM0064GPL036 FAMILY
5.0 FLASH PROGRAM MEMORY
PIC32MM0064GPL036 family devices contain an
internal Flash program memory for executing user
code. The Program and Boot Flash Memory can be
write-protected. The erase page size is 512 32-bit
words. The program row size is 64 32-bit words. The
memory can be programmed by rows or by two 32-bit
words.
The devices implement an Error Correcting Code
(ECC). The memory control block contains a logic to
write and read ECC bits to and from the Flash memory.
The Flash is programmed at the same time as the cor-
responding ECC bits. The ECC provides improved
resistance to Flash errors. The ECC single-bit error will
be transparently corrected. The ECC double-bit error
results in a bus error exception.
There are three methods by which the user can
program this memory:
• Run-Time Self-Programming (RTSP)
• EJTAG Programming
• In-Circuit Serial Programming™ (ICSP™)
RTSP is performed by software executing from either
Flash or RAM memory. Information about RTSP tech-
niques is described in Section 5. “Flash Program-
ming” in the “PIC32 Family Reference Manual”.
EJTAG programming is performed using the JTAG port
of the device. ICSP programming requires fewer con-
nections than for EJTAG programming. The EJTAG
and ICSP methods are described in the “PIC32 Flash
Programming Specification” (DS60001145), which is
available for download from the Microchip web site.
5.1 Flash Con trol ler Registers Writ e
Protection
The NVMPWP and NVMBWP registers, and the WR bit
in the NVMCON register are protected (locked) from an
accidental write. A special unlock sequence is required
to modify the content of these registers or bits.
To unlock, the following steps should be done:
1. Disable interrupts prior to the unlock sequence.
2. Execute the system unlock sequence by writing
the key values of 0xAA996655 and
0x556699AA to the NVMKEY register in two
back-to-back Assembly or ‘C’ instructions.
3. Write the new value to the required bits.
4. Re-enable interrupts.
Note: This data sheet summarizes the features
of the PIC32MM0064GPL036 family of
devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to Sect ion 5. “Flash Programming”
(DS60001121) in the “ PIC32 Family Refer-
ence Manual”, which is available from the
Microchip web site (www.microchip.com/
PIC32). The information in this data sheet
supersedes the information in the FRM.
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DS60001324B-page 38 2015-2016 Microchip Technology Inc.
5.2 Flash Contr ol Registers
TABLE 5-1: FLASH CONTROLLER REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
2380 NVMCON(1)31:16 — — — — — — — — — — — — — — — — 0000
15:0 WR WREN WRERR LVDERR — — — — — — — — NVMOP<3:0> 0000
2390 NVMKEY 31:16 NVMKEY<31:0> 0000
15:0 0000
23A0 NVMADDR(1)31:16 NVMADDR<31:0> 0000
15:0 0000
23B0 NVMDATA0 31:16 NVMDATA0<31:0> 0000
15:0 0000
23C0 NVMDATA1 31:16 NVMDATA1<31:0> 0000
15:0 0000
23D0 NVMSRCADDR 31:16 NVMSRCADDR<31:0> 0000
15:0 0000
23E0 NVMPWP(1)31:16 PWPULOCK — — — — — — — PWP<23:16> 8000
15:0 PWP<15:0> 0000
23F0 NVMBWP(1)31:16 — — — — — — — — — — — — — — — — 0000
15:0 BWPULOCK — — — — BWP<2:0> — — — — — — — — 8700
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: These registers have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively.
2015-2016 Microchip Technology Inc. DS60001324B-page 39
PIC32MM0064GPL036 FAMILY
REGISTER 5-1: NVMCON: NVM PROGRAMMING CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8 R/W-0, HC R/W-0 R-0, HS, HC R-0, HS, HC r-0 U-0 U-0 U-0
WR
(1,4)
WREN
(1)
WRERR
(1,2)
LVDERR
(1,2)
— — — —
7:0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — —NVMOP<3:0>
(3)
Legend: HS = Hardware Settable bit HC = Hardware Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared r = Reserved bit
bit 31-16 Unimplemented: Read as ‘0’
bit 15 WR: Write Control bit
(1,4)
This bit cannot be cleared and can be set only when WREN = 1, and the unlock sequence has been performed.
1 = Initiates a Flash operation
0 = Flash operation is complete or inactive
bit 14 WREN: Write Enable bit
(1)
1 = Enables writes to the WR bit and disables writes to the NVMOP<3:0> bits
0 = Disables writes to the WR bit and enables writes to the NVMOP<3:0> bits
bit 13 WRERR: Write Error bit
(1,2)
This bit can be cleared only by setting the NVMOP<3:0> bits = 0000 and initiating a Flash operation.
1 = Program or erase sequence did not complete successfully
0 = Program or erase sequence completed normally
bit 12 LVDERR: Low-Voltage Detect Error bit
(1,2)
This bit can be cleared only by setting the NVMOP<3:0> bits = 0000 and initiating a Flash operation.
1 = Low voltage is detected (possible data corruption if WRERR is set)
0 = Voltage level is acceptable for programming
bit 11 Reserved: Maintain as ‘0’
bit 10-4 Unimplemented: Read as ‘0’
Note 1: These bits are only reset by a Power-on Reset (POR) and are not affected by other Reset sources.
2: These bits are cleared by setting NVMOP<3:0> = 0000 and initiating a Flash operation (i.e., WR).
3: NVMOP<3:0> bits are write-protected if the WREN bit is set.
4: Writes to the WR bit require an unlock sequence. Refer to Section 5.1 “Flash Controller Registers W rite
Protection” for details.
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DS60001324B-page 40 2015-2016 Microchip Technology Inc.
bit 3-0 NVMOP<3:0>: NVM Operation bits
(3)
These bits are only writable when WREN = 0.
1111 = Reserved
•
•
•
1000 = Reserved
0111 = Program Erase Operation: Erases all of Program Flash Memory (all pages must be unprotected in
the NVMPWP register, Boot Flash Memory is not erased)
0110 = Reserved
0101 = Reserved
0100 = Page Erase Operation: Erases page selected by NVMADDR (erases Boot or Program Flash
Memory, page must be unprotected in the NVMBWP or NVMPWP register)
0011 = Row Program Operation: Programs row selected by NVMADDR (programs Boot or Program Flash
Memory, page must be unprotected in the NVMBWP or NVMPWP register)
0010 = Double-Word Program Operation: Programs two words to the address selected by NVMADDR
(programs Boot or Program Flash Memory, page must be unprotected in the NVMBWP or
NVMPWP register)
0001 = Reserved
0000 = No operation, clears WRERR and LVDERR bits
REGISTER 5-1: NVMCON: NVM PROGRAMMING CONTROL REGISTER (CONTINUED)
Note 1: These bits are only reset by a Power-on Reset (POR) and are not affected by other Reset sources.
2: These bits are cleared by setting NVMOP<3:0> = 0000 and initiating a Flash operation (i.e., WR).
3: NVMOP<3:0> bits are write-protected if the WREN bit is set.
4: Writes to the WR bit require an unlock sequence. Refer to Section 5.1 “Flash Controller Registers W rite
Protection” for details.
2015-2016 Microchip Technology Inc. DS60001324B-page 41
PIC32MM0064GPL036 FAMILY
REGISTER 5-2: NVMKEY: NVM PROGRAMMING UNLOCK REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
NVMKEY<31:24>
23:16
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
NVMKEY<23:16>
15:8
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
NVMKEY<15:8>
7:0
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
NVMKEY<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 NVMKEY<31:0>: NVM Unlock Register bits
These bits are write-only and read as ‘0’ on any read.
REGISTER 5-3: NVMADDR: NVM FLASH ADDRESS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMADDR<31:24>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMADDR<23:16>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMADDR<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMADDR<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 NVMADDR<31:0>: NVM Flash Address bits
NVMOP<3:0>
Selection Flash Address Bits (NVMADDR<31:0>)
Page Erase Address identifies the page to erase (NVMADDR<10:0> are ignored).
Row Program Address identifies the row to program (NVMADDR<7:0> are ignored).
Double-Word Program
Address identifies the double-word (64-bit) to program (NVMADDR<1:0> bits are ignored).
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DS60001324B-page 42 2015-2016 Microchip Technology Inc.
REGISTER 5-4: NVMDATAx: NVM FLASH DATA x REGISTER (x = 0-1)
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMDATAx<31:24>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMDATAx<23:16>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMDATAx<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMDATAx<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 NVMDATAx<31:0>: NVM Flash Data x bits
Double-Word Program: Writes NVMDATA1:NVMDATA0 to the target Flash address defined in NVMADDR.
NVMDATA0 contains the least significant instruction word.
REGISTER 5-5: NVMSRCADDR: NVM SOURCE DATA ADDRESS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMSRCADDR<31:24>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMSRCADDR<23:16>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMSRCADDR<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMSRCADDR<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 NVMSRCADDR<31:0>: NVM Source Data Address bits
The system physical address of the data to be programmed into the Flash when the NVMOP<3:0> bits
(NVMCON<3:0>) are set to perform row programming.
2015-2016 Microchip Technology Inc. DS60001324B-page 43
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REGISTER 5-6: NVMPWP: NVM PROGRAM FLASH WRITE-PROTECT REGISTER
(1)
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-1 U-0 U-0 U-0 U-0 U-0 U-0 U-0
PWPULOCK — — — — — — —
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PWP<23:16>
(2)
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PWP<15:8>
(2)
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PWP<7:0>
(2)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 PWPULOCK: Program Flash Memory Page Write-Protect Unlock bit
1 = Register is not locked and can be modified
0 = Register is locked and cannot be modified
This bit is only clearable and cannot be set except by any Reset.
bit 30-24 Unimplemented: Read as ‘0’
bit 23-0 PWP<23:0>: Flash Program Write-Protect (Page) Address bits
(2)
Physical memory below address, 0x1DXXXXXX, is write-protected, where ‘XXXXXX’ is specified by
PWP<23:0>. When the PWP<23:0> bits have a value of ‘0’, write protection is disabled for the entire
Program Flash Memory. If the specified address falls within the page, the entire page and all pages below
the current page will be protected.
Note 1: Writes to this register require an NVMKEY unlock sequence. Refer to Section 5.1 “Fla sh Controller
Registers Write Protection” for details.
2: These bits can be modified only when the unlock bit (PWPULOCK) is set.
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DS60001324B-page 44 2015-2016 Microchip Technology Inc.
REGISTER 5-7: NVMBWP: NVM BOOT FLASH (PAGE) WR ITE-PR OTECT REGISTER
(1)
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-1 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1
BWPULOCK — — — —BWP2
(2)
BWP1
(2)
BWP0
(2)
7:0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 BWPULOCK: Boot Alias Write-Protect Unlock bit
1 = BWPx bits are not locked and can be modified
0 = BWPx bits are locked and cannot be modified
This bit is only clearable and cannot be set except by any Reset.
bit 14-11 Unimplemented: Read as ‘0’
bit 10 BWP2: Boot Alias Page 2 Write-Protect bit
(2)
1 = Write protection for physical address, 0x1FC00000 through 0x1FC007FF, is enabled
0 = Write protection for physical address, 0x1FC00000 through 0x1FC007FF, is disabled
bit 9 BWP1: Boot Alias Page 1 Write-Protect bit
(2)
1 = Write protection for physical address, 0x1FC00800 through 0x1FC00FFF, is enabled
0 = Write protection for physical address, 0x1FC00800 through 0x1FC00FFF, is disabled
bit 8 BWP0: Boot Alias Page 0 Write-Protect bit
(2)
1 = Write protection for physical address, 0x1FC01000 through 0x1FC017FF, is enabled
0 = Write protection for physical address, 0x1FC01000 through 0x1FC017FF, is disabled
bit 7-0 Unimplemented: Read as ‘0’
Note 1: Writes to this register require an NVMKEY unlock sequence. Refer to Section 5.1 “Flash Controller
Registers Write Protection” for details.
2: These bits can be modified only when the associated unlock bit (BWPULOCK) is set.
2015-2016 Microchip Technology Inc. DS60001324B-page 45
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6.0 RESETS
The Reset module combines all Reset sources and
controls the device Master Reset Signal, SYSRST. The
device Reset sources are as follows:
• Power-on Reset (POR)
• Master Clear Reset Pin (MCLR)
• Software Reset (SWR)
• Watchdog Timer Reset (WDTR)
• Brown-out Reset (BOR)
• Configuration Mismatch Reset (CMR)
A simplified block diagram of the Reset module is
illustrated in Figure 6-1.
FIGURE 6-1: SYSTE M RESET BLOCK DIAGRAM
Note: This data sheet summarizes the features of
the PIC32MM0064GPL036 family of
devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to Section 7. “Reset s” (DS60001118)
in the “PIC32 Family Reference Manual”,
which is available from the Microchip
web site (www.microchip.com/PIC32).
The information in this data sheet
supersedes the information in the FRM.
MCLR
V
DD
V
DD
Rise
Detect
POR
Sleep or Idle
Glitch Filter
BOR
Configuration
SYSRST
Software Reset
Power-up
Timer
Voltage Regulator
Reset
WDTR
SWR
CMR
MCLR
Mismatch
NMI
Time-out
WDT
Time-out
Brown-out
Reset
Enabled
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DS60001324B-page 46 2015-2016 Microchip Technology Inc.
6.1 Reset Control Registers
TABLE 6-1: RESETS REGISTER MAP
Virtual Address
(BF80_#)
Register
Name(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
1240 RCON 31:16 PORIO PORCORE — — BCFGERR BCFGFAIL — — — — — — — — — — C000
15:0 — — — — — — CMR —EXTR SWR —WDTO SLEEP IDLE BOR POR 0003
1250 RSWRST 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — — — — — — — — — SWRST 0000
1260 RNMICON 31:16 — — — — — — — WDTR SWNMI — — — GNMI —CF WDTS 0000
15:0 NMICNT<15:0> 0000
1270 PWRCON 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — — — — — — — SBOREN RETEN VREGS 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively.
2015-2016 Microchip Technology Inc. DS60001324B-page 47
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REGISTER 6-1: RCON: RESET CONTROL REGISTER
(1)
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-1, HS R/W-1, HS U-0 U-0 R/W-0, HS R/W-0, HS U-0 U-0
PORIO PORCORE —— BCFGERR BCFGFAIL — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HS U-0
— — — — — —CMR—
7:0
R/W-0, HS R/W-0, HS U-0 R/W-0, HS R/W-0, HS R/W-0, HS R/W-1, HS R/W-1, HS
EXTR SWR — WDTO SLEEP IDLE
(2)
BOR POR
Legend: HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 PORIO: V
DD
POR Flag bit
Set by hardware at detection of a V
DD
POR event.
1 = A Power-on Reset has occurred due to V
DD
voltage
0 = A Power-on Reset has not occurred due to V
DD
voltage
bit 30 PORCORE: Core Voltage POR Flag bit
Set by hardware at detection of a core POR event.
1 = A Power-on Reset has occurred due to core voltage
0 = A Power-on Reset has not occurred due to core voltage
bit 29-28 Unimplemented: Read as ‘0’
bit 27 BCFGERR: Primary Configuration Registers Error Flag bit
1 = An error occurred during a read of the Primary Configuration registers
0 = No error occurred during a read of the Primary Configuration registers
bit 26 BCFGFAIL: Primary/Secondary Configuration Registers Error Flag bit
1 = An error occurred during a read of the Primary and Alternate Configuration registers
0 = No error occurred during a read of the Primary and Alternate Configuration registers
bit 25-10 Unimplemented: Read as ‘0’
bit 9 CMR: Configuration Mismatch Reset Flag bit
1 = A Configuration Mismatch Reset has occurred
0 = A Configuration Mismatch Reset has not occurred
bit 8 Unimplemented: Read as ‘0’
bit 7 EXTR: External Reset (MCLR) Pin Flag bit
1 = Master Clear (pin) Reset has occurred
0 = Master Clear (pin) Reset has not occurred
bit 6 SWR: Software Reset Flag bit
1 = Software Reset was executed
0 = Software Reset was not executed
bit 5 Unimplemented: Read as ‘0’
bit 4 WDTO: Watchdog Timer Time-out Flag bit
1 = WDT time-out has occurred
0 = WDT time-out has not occurred
Note 1: User software must clear bits in this register to view the next detection.
2: The IDLE bit will also be set when the device wakes from Sleep mode.
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DS60001324B-page 48 2015-2016 Microchip Technology Inc.
bit 3 SLEEP: Wake from Sleep Flag bit
1 = Device was in Sleep mode
0 = Device was not in Sleep mode
bit 2 IDLE: Wake from Idle Flag bit
(2)
1 = Device was in Idle mode
0 = Device was not in Idle mode
bit 1 BOR: Brown-out Reset Flag bit
1 = Brown-out Reset has occurred
0 = Brown-out Reset has not occurred
bit 0 POR: Power-on Reset Flag bit
1 = Power-on Reset has occurred
0 = Power-on Reset has not occurred
REGISTER 6-1: RCON: RESET CONTROL REGISTER
(1)
(CONTINUED)
Note 1: User software must clear bits in this register to view the next detection.
2: The IDLE bit will also be set when the device wakes from Sleep mode.
REGISTER 6-2: RSWRST: SOFTWARE RESET REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 W-0, HC
— — — — — — — SWRST
(1,2)
Legend: HC = Hardware Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-1 Unimplemented: Read as ‘0’
bit 0 SWRST: Software Reset Trigger bit
(1,2)
1 = Enables Software Reset event
0 = No effect
Note 1: The system unlock sequence must be performed before the SWRST bit can be written. Refer to
Section 23.4 “System Registers Write Protection” for details.
2: Once this bit is set, any read of the RSWRST register will cause a Reset to occur.
2015-2016 Microchip Technology Inc. DS60001324B-page 49
PIC32MM0064GPL036 FAMILY
REGISTER 6-3: RNMICON: NON-MASKABLE INTERRUPT (NMI) CONTROL REGISTER
(1)
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — —WDTR
23:16
R/W-0 U-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0
SWNMI — — —GNMI —CFWDTS
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NMICNT<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NMICNT<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-25 Unimplemented: Read as ‘0’
bit 24 WDTR: Watchdog Timer Time-out in Run Mode Flag bit
1 = A Run mode WDT time-out has occurred and caused an NMI
0 = WDT time-out has not occurred
Setting this bit will cause a WDT NMI event and NMICNT<15:0> will begin counting.
bit 23 SWNMI: Software NMI Trigger bit
1 = An NMI has been generated
0 = An NMI was not generated
bit 22-20 Unimplemented: Read as ‘0’
bit 19 GNMI: Software General NMI Trigger bit
1 = A general NMI has been generated
0 = A general NMI was not generated
bit 18 Unimplemented: Read as ‘0’
bit 17 CF: Clock Fail Detect bit
1 = FSCM has detected clock failure and caused an NMI
0 = FSCM has not detected clock failure
Setting this bit will cause a CF NMI event, but will not cause a clock switch to the FRC.
bit 16 WDTS: Watchdog Timer Time-out in Sleep Mode Flag bit
1 = WDT time-out has occurred during Sleep mode and caused a wake-up from Sleep
0 = WDT time-out has not occurred during Sleep mode
Setting this bit will cause a WDT NMI.
bit 15-0 NMICNT<15:0>: NMI Reset Counter Value bits
These bits specify the reload value used by the NMI Reset counter.
FFFFh-0001h = Number of SYSCLK cycles before a device Reset occurs
(2)
0000h = No delay between NMI assertion and device Reset event
Note 1: Writes to this register require an unlock sequence. Refer to Secti on 2 3.4 “Syst em R egis ters Write
Protection” for details.
2: If a Watchdog Timer NMI event (when not in Sleep mode) is cleared before this counter reaches ‘0’, no
device Reset is asserted. This NMI Reset counter is only applicable to the Watchdog Timer NMI event.
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DS60001324B-page 50 2015-2016 Microchip Technology Inc.
REGISTER 6-4: PWRCON: POWER CONTROL REGISTER
(1)
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — SBOREN
(3)
RETEN
(2)
VREGS
(2)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-3 Unimplemented: Read as ‘0’
bit 2 SBOREN: BOR During Sleep Control bit
(3)
1 = BOR is turned on
0 = BOR is turned off
bit 1 RETEN: Output Level of the Regulator During Sleep Selection bit
(2)
1 = Writing a ‘1’ to this bit will cause the main regulator to be put in a low-power state during Sleep mode
0 = Writing a ‘0’ to this bit will have no effect
bit 0 VREGS: Voltage Regulator Standby Enable bit
(2)
1 = Voltage regulator will remain active during Sleep mode
0 = Voltage regulator will go to Standby mode during Sleep mode
Note 1: Writes to this register require an unlock sequence. Refer to Secti on 2 3.4 “Syst em R egis ters Write
Protection” for details.
2: Refer to Section 22.4 “On-Chip Voltage Regulator Low-Power Modes” for details.
3: This bit is enabled only when the BOREN<1:0> Configuration bits (FPOR<1:0>) are set to ‘01’.
2015-2016 Microchip Technology Inc. DS60001324B-page 51
PIC32MM0064GPL036 FAMILY
7.0 CPU EXCE PTIONS AND
INTERRUPT CONTROLLER
PIC32MM0064GPL036 family devices generate inter-
rupt requests in response to interrupt events from
peripheral modules. The interrupt control module exists
externally to the CPU logic and prioritizes the interrupt
events before presenting them to the CPU.
The CPU handles interrupt events as part of the excep-
tion handling mechanism, which is described in
Section 7.1 “CPU Exceptions”.
The PIC32MM0064GPL036 family device interrupt
module includes the following features:
• Single Vector or Multivector mode Operation
• Five External Interrupts with Edge Polarity Control
• Interrupt Proximity Timer
• Module Freeze in Debug mode
• Seven User-Selectable Priority Levels for each
Vector
• Four User-Selectable Subpriority Levels within
each Priority
• One Shadow Register Set that can be used for
any Priority Level, Eliminating Software Context
Switching and Reducing Interrupt Latency
• Software can Generate any Interrupt
• User-Configurable Interrupt Vectors’ Offset and
Vector Table Location
Figure 7-1 shows the block diagram for the interrupt
controller and CPU exceptions.
FIGURE 7-1: CPU EXCEPTIONS AND INTERRUPT CONTROLLER MODULE BLOCK DIAGRAM
Note: This data sheet summarizes the features
of the PIC32MM0064GPL036 family of
devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to Section 8. “Interrupts”
(DS60001108) and Section 50. “CPU for
Devices with MIPS32
®
microApti v™ and
M-Class Cores” (DS60001192) in the
“PIC32 Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32). The informa-
tion in this data sheet supersedes the
information in the FRM
Interrupt Requests
Vector Number and Offset
CPU Core
Priority Level
Shadow Set Number
SYSCLK
(Exception Handling)
Interrupt Controller
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DS60001324B-page 52 2015-2016 Microchip Technology Inc.
7.1 CPU Exceptions
CPU Coprocessor 0 contains the logic for identifying and managing exceptions. Exceptions can be caused by a variety of sources, including boundary cases in data,
external events or program errors. Ta b l e 7-1 lists the exception types in order of priority.
TABLE 7-1: MIPS32
®
microAptiv™ UC MICROPROCESSOR CORE EXCEPTION TYPES
Exception T ype
(In Order of
Priority) Description Branches to Status
Bits Set Debug Bits
Set EXCCODE XC32 Funct ion Nam e
Highest Priority
Reset Assertion of MCLR.0xBFC0_0000 BEV, ERL — — _on_reset
Soft Reset Execution of a RESET instruction. 0xBFC0_0000 BEV, SR,
ERL
— — _on_reset
DSS EJTAG debug single step. 0xBFC0_0480
(ProbEn = 0 in ECR)
0xBFC0_0200
(ProbEn = 1 in ECR)
—DSS — —
DINT EJTAG debug interrupt. Caused by setting the
EjtagBrk bit in the ECR register.
0xBFC0_0480
(ProbEn = 0 in ECR)
0xBFC0_0200
(ProbEn = 1 in ECR)
—DINT — —
NMI Non-maskable interrupt. 0xBFC0_0000 BEV, NMI,
ERL
— — _nmi_handler
Interrupt Assertion of unmasked hardware or software
interrupt signal.
See Ta b l e 7-2 IPL<2:0> —Int (0x00) See Ta b l e 7-2
DIB EJTAG debug hardware instruction break matched. 0xBFC0_0480
(ProbEn = 0 in ECR)
0xBFC0_0200
(ProbEn = 1 in ECR)
—DIB — —
AdEL Load address alignment error. EBASE + 0x180 EXL —ADEL (0x04) _general_exception_handler
IBE Instruction fetch bus error. EBASE + 0x180 EXL —IBE (0x06) _general_exception_handler
DBp EJTAG breakpoint (execution of SDBBP
instruction).
0xBFC0_0480
(ProbEn = 0 in ECR)
0xBFC0_0200
(ProbEn = 1 in ECR)
DBp — — —
Sys Execution of SYSCALL instruction. EBASE + 0x180 EXL —Sys (0x08) _general_exception_handler
Bp Execution of BREAK instruction. EBASE + 0x180 EXL —Bp (0x09) _general_exception_handler
2015-2016 Microchip Technology Inc. DS60001324B-page 53
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CpU Execution of a coprocessor instruction for a
coprocessor that is not enabled.
EBASE + 0x180 CU, EXL —CpU (0x0B) _general_exception_handler
RI Execution of a reserved instruction. EBASE + 0x180 EXL —RI (0x0A) _general_exception_handler
Ov Execution of an arithmetic instruction that
overflowed.
EBASE + 0x180 EXL —Ov (0x0C) _general_exception_handler
Tr Execution of a trap (when trap condition is true). EBASE + 0x180 EXL —Tr (0x0D) _general_exception_handler
DDBL EJTAG data address break (address only) or
EJTAG data value break on load (address and
value).
0xBFC0_0480
(ProbEn = 0 in ECR)
0xBFC0_0200
(ProbEn = 1 in ECR)
—DDBL for a
load
instruction
or DDBS for
a store
instruction
— —
DDBS EJTAG data address break (address only) or
EJTAG data value break on store (address and
value).
0xBFC0_0480
(ProbEn = 0 in ECR)
0xBFC0_0200
(ProbEn = 1 in ECR)
—DDBL for a
load
instruction
or DDBS for
a store
instruction
— —
AdES Store address alignment error. EBASE + 0x180 EXL —ADES
(0x05)
_general_exception_handler
DBE Load or store bus error. EBASE + 0x180 EXL —DBE (0x07) _general_exception_handler
CBrk EJTAG complex breakpoint. 0xBFC0_0480
(ProbEn = 0 in ECR)
0xBFC0_0200
(ProbEn = 1 in ECR)
—DIBImpr,
DDBLImpr
and/or
DDBSImpr
— —
Lowest Priority
TABLE 7-1: MIPS32
®
microAptiv™ UC MICROPROCESSOR CORE EXCEPTION TYPES (CONTINUED)
Exception T ype
(In Order of
Priority) Description Branches to Status
Bits Set Debug Bits
Set EXCCODE XC32 Function Name
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DS60001324B-page 54 2015-2016 Microchip Technology Inc.
7.2 Interrupts
The PIC32MM0064GPL036 family uses fixed offset for vector spacing. For details, refer to Section 8. “Interrupts” (DS60001108) in the “PIC32 Family Reference
Manual”. Table 7-2 provides the interrupt related vectors and bits information.
TABLE 7-2: INTERRUPTS
Interrupt Source MPLAB
®
XC32 Vector Name Vector
Number
Interrupt Related Bits Location Persistent
Interrupt
Flag Enable Priority Subpriority
Core Timer _CORE_TIMER_VECTOR 0IFS0<0> IEC0<0> IPC0<4:2> IPC0<1:0> No
Core Software 0 _CORE_SOFTWARE_0_VECTOR 1IFS0<1> IEC0<1> IPC0<12:10> IPC0<9:8> No
Core Software 1 _CORE_SOFTWARE_1_VECTOR 2IFS0<2> IEC0<2> IPC0<20:18> IPC0<17:16> No
External 0 _EXTERNAL_0_VECTOR 3IFS0<3> IEC0<3> IPC0<28:26> IPC0<25:24> No
External 1 _EXTERNAL_1_VECTOR 4IFS0<4> IEC0<4> IPC1<4:2> IPC1<1:0> No
External 2 _EXTERNAL_2_VECTOR 5IFS0<5> IEC0<5> IPC1<12:10> IPC1<9:8> No
External 3 _EXTERNAL_3_VECTOR 6IFS0<6> IEC0<6> IPC1<20:18> IPC1<17:16> No
External 4 _EXTERNAL_4_VECTOR 7IFS0<7> IEC0<7> IPC1<28:26> IPC1<25:24> No
PORTA Change Notification _CHANGE_NOTICE_A_VECTOR 8IFS0<8> IEC0<8> IPC2<4:2> IPC2<1:0> No
PORTB Change Notification _CHANGE_NOTICE_B_VECTOR 9IFS0<9> IEC0<9> IPC2<12:10> IPC2<9:8> No
PORTC Change Notification _CHANGE_NOTICE_C_VECTOR 10 IFS0<10> IEC0<10> IPC2<20:18> IPC2<17:16> No
Timer1 _TIMER_1_VECTOR 11 IFS0<11> IEC0<11> IPC2<28:26> IPC2<25:24> No
Comparator 1 _COMPARATOR_1_VECTOR 12 IFS0<12> IEC0<12> IPC3<4:2> IPC3<1:0> No
Comparator 2 _COMPARATOR_2_VECTOR 13 IFS0<13> IEC0<13> IPC3<12:10> IPC3<9:8> No
Real-Time Clock Alarm _RTCC_VECTOR 14 IFS0<14> IEC0<14> IPC3<20:18> IPC3<17:16> No
ADC Conversion _ADC_VECTOR 15 IFS0<15> IEC0<15> IPC3<28:26> IPC3<25:24> No
CRC _CRC_VECTOR 16 IFS0<16> IEC0<16> IPC4<4:2> IPC4<1:0> Yes
High/Low-Voltage Detect _HLVD_VECTOR 17 IFS0<17> IEC0<17> IPC4<12:10> IPC4<9:8> Yes
Logic Cell 1 _CLC1_VECTOR 18 IFS0<18> IEC0<18> IPC4<20:18> IPC4<17:16> No
Logic Cell 2 _CLC2_VECTOR 19 IFS0<19> IEC0<19> IPC4<28:26> IPC4<25:24> No
SPI1 Error _SPI1_ERR_VECTOR 20 IFS0<20> IEC0<20> IPC5<4:2> IPC5<1:0> Yes
SPI1 Transmission _SPI1_TX_VECTOR 21 IFS0<21> IEC0<21> IPC5<12:10> IPC5<9:8> Yes
SPI1 Reception _SPI1_RX_VECTOR 22 IFS0<22> IEC0<22> IPC5<20:18> IPC5<17:16> Yes
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UART1 Reception _UART1_RX_VECTOR 23 IFS0<23> IEC0<23> IPC5<28:26> IPC5<25:24> Yes
UART1 Transmission _UART1_TX_VECTOR 24 IFS0<24> IEC0<24> IPC6<4:2> IPC6<1:0> Yes
UART1 Error _UART1_ERR_VECTOR 25 IFS0<25> IEC0<25> IPC6<12:10> IPC6<9:8> Yes
CCP1 Input Capture or Output Compare _CCP1_VECTOR 29 IFS0<29> IEC0<29> IPC7<12:10> IPC7<9:8> No
CCP1 Timer _CCT1_VECTOR 30 IFS0<30> IEC0<30> IPC7<20:18> IPC7<17:16> No
CCP2 Input Capture or Output Compare _CCP2_VECTOR 31 IFS0<31> IEC0<31> IPC7<28:26> IPC7<25:24> No
CCP2 Timer _CCT2_VECTOR 32 IFS1<0> IEC1<0> IPC8<4:2> IPC8<1:0> No
CCP3 Input Capture or Output Compare _CCP3_VECTOR 33 IFS1<1> IEC1<1> IPC8<12:10> IPC8<9:8> No
CCP3 Timer _CCT3_VECTOR 34 IFS1<2> IEC1<2> IPC8<20:18> IPC8<17:16> No
RESERVED —35 — — — — —
RESERVED —36 — — — — —
SPI2 Error _SPI2_ERR_VECTOR 37 IFS1<5> IEC1<5> IPC9<12:10> IPC9<9:8> Yes
SPI2 Transmission _SPI2_TX_VECTOR 38 IFS1<6> IEC1<6> IPC9<20:18> IPC9<17:16> Yes
SPI2 Reception _SPI2_RX_VECTOR 39 IFS1<7> IEC1<7> IPC9<28:26> IPC9<25:24> Yes
UART2 Reception _UART2_RX_VECTOR 40 IFS1<8> IEC1<8> IPC10<4:2> IPC10<1:0> Yes
UART2 Transmission _UART2_TX_VECTOR 41 IFS1<9> IEC1<9> IPC10<12:10> IPC10<9:8> Yes
UART2 Error _UART2_ERR_VECTOR 42 IFS1<10> IEC1<10> IPC10<20:18> IPC10<17:16> Yes
NVM Program or Erase Complete _NVM_VECTOR 46 IFS1<14> IEC1<14> IPC11<20:18> IPC11<17:16> Yes
Core Performance Counter _PERFORMANCE_COUNTER_VECTOR 47 IFS1<15> IEC1<15> IPC11<28:26> IPC11<25:24> No
TABLE 7-2: INTERRUPTS (CONTINUED)
Interrupt Source MPLAB
®
XC32 Vector Name Vector
Number
Interrupt Related Bits Location Persistent
Interrupt
Flag Enable Priority Subpriority
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DS60001324B-page 56 2015-2016 Microchip Technology Inc.
TABLE 7-3: INTERRUPT REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
(1)
Bit Range
Bits
All R ese t s
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
F000 INTCON 31:16 — — — — — — — — — VS<6:0>
0000
15:0 ———MVEC —TPC<2:0>— — — INT4EP INT3EP INT2EP INT1EP INT0EP
0000
F010 PRISS 31:16 PRI7SS<3:0> PRI6SS<3:0> PRI5SS<3:0> PRI4SS<3:0>
0000
15:0 PRI3SS<3:0> PRI2SS<3:0> PRI1SS<3:0> — — —SS0
0000
F020 INTSTAT 31:16 — — — — — — — — — — — — — — — —
0000
15:0 — — — — — SRIPL<2:0> SIRQ<7:0>
0000
F030 IPTMR 31:16 IPTMR<31:0>
0000
15:0
0000
F040 IFS0 31:16 CCP2IF CCT1IF CCP1IF — — — U1EIF U1TXIF U1RXIF SPI1RXIF SPI1TXIF SPI1EIF CLC2IF CLC1IF LVDIF CRCIF
0000
15:0 AD1IF RTCCIF CMP2IF CMP1IF T1IF CNCIF
(2)
CNBIF CNAIF INT4IF INT3IF INT2IF INT1IF INT0IF CS1IF CS0IF CTIF
0000
F050 IFS1 31:16 — — — — — — — — — — — — — — — —
0000
15:0 CPCIF NVMIF — — — U2EIF U2TXIF U2RXIF SPI2RXIF SPI2TXIF SPI2EIF —— CCT3IF CCP3IF CCT2IF
0000
F0C0 IEC0 31:16 CCP2IE CCT1IE CCP1IE — — — U1EIE U1TXIE U1RXIE SPI1RXIE SPI1TXIE SPI1EIE CLC2IE CLC1IE LVDIE CRCIE
0000
15:0 AD1IE RTCCIE CMP2IE
CMP1IE
T1IE CNCIE
(2)
CNBIE CNAIE INT4IE INT3IE INT2IE INT1IE INT0IE CS1IE CS0IE CTIE
0000
F0D0 IEC1 31:16 — — — — — — — — — — — — — — — —
0000
15:0 CPCIE NVMIE — — — U2EIE U2TXIE U2RXIE SPI2RXIE SPI2TXIE SPI2EIE —— CCT3IE CCP3IE CCT2IE
0000
F140 IPC0 31:16 ——— INT0IP<2:0> INT0IS<1:0> — — — CS1IP<2:0> CS1IS<1:0>
0000
15:0 ——— CS0IP<2:0> CS0IS<1:0> — — — CTIP<2:0> CTIS<1:0>
0000
F150 IPC1 31:16 ——— INT4IP<2:0> INT4IS<1:0> — — — INT3IP<2:0> INT3IS<1:0>
0000
15:0 ——— INT2IP<2:0> INT2IS<1:0> — — — INT1IP<2:0> INT1IS<1:0>
0000
F160 IPC2 31:16 ——— T1IP<2:0> T1IS<1:0> — — — CNCIP<2:0>
(2)
CNCIS<1:0>
(2)
0000
15:0 ——— CNBIP<2:0> CNBIS<1:0> — — — CNAIP<2:0> CNAIS<1:0>
0000
F170 IPC3 31:16 ——— AD1IP<2:0> AD1IS<1:0> — — — RTCCIP<2:0> RTCCIS<1:0>
0000
15:0 ——— CMP2IP<2:0> CMP2IS<1:0> — — — CMP1IP<2:0> CMP1IS<1:0>
0000
F180 IPC4 31:16 ——— CLC2IP<2:0> CLC2IS<1:0> — — — CLC1IP<2:0> CLC1IS<1:0>
0000
15:0 ——— LVDIP<2:0> LVDIS<1:0> — — — CRCIP<2:0> CRCIS<1:0>
0000
F190 IPC5 31:16 ——— U1RXIP<2:0> U1RXIS<1:0> — — — SPI1RXIP<2:0> SPI1RXIS<1:0>
0000
15:0 ——— SPI1TXIP<2:0> SPI1TXIS<1:0> — — — SPI1EIP<2:0> SPI1EIS<1:0>
0000
F1A0 IPC6 31:16 — — — — — — — — — — — — — — — —
0000
15:0 ——— U1EIP<2:0> U1EIS<1:0> — — — U1TXIP<2:0> U1TXIS<1:0>
0000
F1B0 IPC7 31:16 CCP2IP<2:0> CCP2IS<1:0> — — — CCT1IP<2:0> CCT1IS<1:0>
0000
15:0 ——— CCP1IP<2:0> CCP1IS<1:0> — — — — — — — —
0000
Legend:
— = unimplemented, read as ‘
0
’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively.
2: These bits are not available on 20-pin devices.
2015-2016 Microchip Technology Inc. DS60001324B-page 57
PIC32MM0064GPL036 FAMILY
F1C0 IPC8 31:16 — — — — — — — — — — — CCT3IP<2:0> CCT3IS<1:0>
0000
15:0 ——— CCP3IP<2:0> CCP3IS<1:0> — — — CCT2IP<2:0> CCT2IS<1:0>
0000
F1D0 IPC9 31:16 ——— SPI2RXIP<2:0> SPI2RXIS<1:0> — — — SPI2TXIP<2:0> SPI2TXIS<1:0>
0000
15:0 ——— SPI2EIP<2:0> SPI2EIS<1:0> — — — — — — — —
0000
F1E0 IPC10 31:16 — — — — — — — — — — — U2EIP<2:0> U2EIS<1:0>
0000
15:0 ——— U2TXIP<2:0> U2TXIS<1:0> — — — U2RXIP<2:0> U2RXIS<1:0>
0000
F1F0 IPC11 31:16 ——— CPCIP<2:0> CPCIS<1:0> — — — NVMIP<2:0> NVMIS<1:0>
0000
15:0 — — — — — — — — — — — — — — — —
0000
TABLE 7-3: INTERRUPT REGISTER MAP (CONTINUED)
Virtual Address
(BF80_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
Legend:
— = unimplemented, read as ‘
0
’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively.
2: These bits are not available on 20-pin devices.
PIC32MM0064GPL036 FAMILY
DS60001324B-page 58 2015-2016 Microchip Technology Inc.
REGISTER 7-1: INTCON: INTERRUPT CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—VS<6:0>
15:8
U-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
— — — MVEC —TPC<2:0>
7:0
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — INT4EP INT3EP INT2EP INT1EP INT0EP
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-23 Unimplemented: Read as ‘0’
bit 22-16 VS<6:0>: Vector Spacing bits
Spacing Between Vectors:
0000000 = 0 Bytes
0000001 = 8 Bytes
0000010 = 16 Bytes
0000100 = 32 Bytes
0001000 = 64 Bytes
0010000 = 128 Bytes
0100000 = 256 Bytes
1000000 = 512 Bytes
All other values are reserved. The operation of this device is undefined if a reserved value is written to this
field. If MVEC = 0, this field is ignored.
bit 15-13 Unimplemented: Read as ‘0’
bit 12 MVEC: Multivector Configuration bit
1 = Interrupt controller configured for Multivectored mode
0 = Interrupt controller configured for Single Vectored mode
bit 11 Unimplemented: Read as ‘0’
bit 10-8 TPC<2:0>: Interrupt Proximity Timer Control bits
111 = Interrupts of Group Priority 7 or lower start the interrupt proximity timer
110 = Interrupts of Group Priority 6 or lower start the interrupt proximity timer
101 = Interrupts of Group Priority 5 or lower start the interrupt proximity timer
100 = Interrupts of Group Priority 4 or lower start the interrupt proximity timer
011 = Interrupts of Group Priority 3 or lower start the interrupt proximity timer
010 = Interrupts of Group Priority 2 or lower start the interrupt proximity timer
001 = Interrupts of Group Priority 1 start the interrupt proximity timer
000 = Disables interrupt proximity timer
bit 7-5 Unimplemented: Read as ‘0’
bit 4 INT4EP: External Interrupt 4 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
bit 3 INT3EP: External Interrupt 3 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
2015-2016 Microchip Technology Inc. DS60001324B-page 59
PIC32MM0064GPL036 FAMILY
bit 2 INT2EP: External Interrupt 2 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
bit 1 INT1EP: External Interrupt 1 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
bit 0 INT0EP: External Interrupt 0 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
REGISTER 7-1: INTCON: INTERRUPT CONTROL REGISTER (CONTINUED)
REGISTER 7-2: PRISS: PRIORITY SHADOW SELECT REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PRI7SS<3:0>
(1)
PRI6SS<3:0>
(1)
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PRI5SS<3:0>
(1)
PRI4SS<3:0>
(1)
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PRI3SS<3:0>
(1)
PRI2SS<3:0>
(1)
7:0
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0
PRI1SS<3:0>
(1)
— — — SS0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-28 PRI7SS<3:0>: Interrupt with Priority Level 7 Shadow Set bits
(1)
11111 = Reserved
•
•
•
0010 = Reserved
0001 = Interrupt with a priority level of 7 uses Shadow Set 1
0000 = Interrupt with a priority level of 7 uses Shadow Set 0
bit 27-24 PRI6SS<3:0>: Interrupt with Priority Level 6 Shadow Set bits
(1)
1111 = Reserved
•
•
•
0010 = Reserved
0001 = Interrupt with a priority level of 6 uses Shadow Set 1
0000 = Interrupt with a priority level of 6 uses Shadow Set 0
Note 1: These bits are ignored if the MVEC bit (INTCON<12>) = 0.
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DS60001324B-page 60 2015-2016 Microchip Technology Inc.
bit 23-20 PRI5SS<3:0>: Interrupt with Priority Level 5 Shadow Set bits
(1)
1111 = Reserved
•
•
•
0010 = Reserved
0001 = Interrupt with a priority level of 5 uses Shadow Set 1
0000 = Interrupt with a priority level of 5 uses Shadow Set 0
bit 19-16 PRI4SS<3:0>: Interrupt with Priority Level 4 Shadow Set bits
(1)
1111 = Reserved
•
•
•
0010 = Reserved
0001 = Interrupt with a priority level of 4 uses Shadow Set 1
0000 = Interrupt with a priority level of 4 uses Shadow Set 0
bit 15-12 PRI3SS<3:0>: Interrupt with Priority Level 3 Shadow Set bits
(1)
1111 = Reserved
•
•
•
0010 = Reserved
0001 = Interrupt with a priority level of 3 uses Shadow Set 1
0000 = Interrupt with a priority level of 3 uses Shadow Set 0
bit 11-8 PRI2SS<3:0>: Interrupt with Priority Level 2 Shadow Set bits
(1)
1111 = Reserved
•
•
•
0010 = Reserved
0001 = Interrupt with a priority level of 2 uses Shadow Set 1
0000 = Interrupt with a priority level of 2 uses Shadow Set 0
bit 7-4 PRI1SS<3:0>: Interrupt with Priority Level 1 Shadow Set bits
(1)
1111 = Reserved
•
•
•
0010 = Reserved
0001 = Interrupt with a priority level of 1 uses Shadow Set 1
0000 = Interrupt with a priority level of 1 uses Shadow Set 0
bit 3-1 Unimplemented: Read as ‘0’
bit 0 SS0: Single Vector Shadow Register Set bit
1 = Single vector is presented with a shadow set
0 = Single vector is not presented with a shadow set
REGISTER 7-2: PRISS: PRIORITY SHADOW SELECT REGISTER (CONTINUED)
Note 1: These bits are ignored if the MVEC bit (INTCON<12>) = 0.
2015-2016 Microchip Technology Inc. DS60001324B-page 61
PIC32MM0064GPL036 FAMILY
REGISTER 7-3: INTSTAT: INTERRUPT STATUS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 U-0 R-0, HS, HC R-0, HS, HC R-0, HS, HC
— — — — — SRIPL<2:0>
(1)
7:0
R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC
SIRQ<7:0>
Legend: HS = Hardware Settable bit HC = Hardware Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-11 Unimplemented: Read as ‘0’
bit 10-8 SRIPL<2:0>: Requested Priority Level for Single Vector Mode bits
(1)
111-000 = The priority level of the latest interrupt presented to the CPU
bit 7-0 SIRQ<7:0>: Last Interrupt Request Serviced Status bits
11111111-00000000 = The last interrupt request number serviced by the CPU
Note 1: This value should only be used when the interrupt controller is configured for Single Vector mode.
REGISTER 7-4: IPTMR: INTERRUPT PROXIMITY TIMER REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IPTMR<31:24>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IPTMR<23:16>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IPTMR<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IPTMR<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 IPTMR<31:0>: Interrupt Proximity Timer Reload bits
Used by the interrupt proximity timer as a reload value when the interrupt proximity timer is triggered by an
interrupt event.
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DS60001324B-page 62 2015-2016 Microchip Technology Inc.
REGISTER 7-5: IFSx: INTERRUPT FLAG STATUS REGISTER x
(1)
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IFS<31:24>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IFS<23:16>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IFS<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IFS<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 IFS<31:0>: Interrupt Flag Status bits
1 = Interrupt request has occurred
0 = No interrupt request has occurred
Note 1: This register represents a generic definition of the IFSx register. Refer to Table 7-3 for the exact bit
definitions.
REGISTER 7-6: IECx: INTERRUPT ENABLE CONTROL REGISTER x
(1)
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IEC<31:24>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IEC<23:16>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IEC<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IEC<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 IEC<31-0>: Interrupt Enable bits
1 = Interrupt is enabled
0 = Interrupt is disabled
Note 1: This register represents a generic definition of the IECx register. Refer to Table 7-3 for the exact bit
definitions.
2015-2016 Microchip Technology Inc. DS60001324B-page 63
PIC32MM0064GPL036 FAMILY
REGISTER 7-7: IPCx: INTERRUPT PRIORITY CONTROL REGISTER x
(1)
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — IP3<2:0> IS3<1:0>
23:16
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — IP2<2:0> IS2<1:0>
15:8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — IP1<2:0> IS1<1:0>
7:0
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — IP0<2:0> IS0<1:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-26 IP3<2:0>: Interrupt Priority bits
111 = Interrupt priority is 7
•
•
•
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
bit 25-24 IS3<1:0>: Interrupt Subpriority bits
11 = Interrupt subpriority is 3
10 = Interrupt subpriority is 2
01 = Interrupt subpriority is 1
00 = Interrupt subpriority is 0
bit 23-21 Unimplemented: Read as ‘0’
bit 20-18 IP2<2:0>: Interrupt Priority bits
111 = Interrupt priority is 7
•
•
•
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
bit 17-16 IS2<1:0>: Interrupt Subpriority bits
11 = Interrupt subpriority is 3
10 = Interrupt subpriority is 2
01 = Interrupt subpriority is 1
00 = Interrupt subpriority is 0
bit 15-13 Unimplemented: Read as ‘0’
Note 1: This register represents a generic definition of the IPCx register. Refer to Table 7-3 for the exact bit
definitions.
PIC32MM0064GPL036 FAMILY
DS60001324B-page 64 2015-2016 Microchip Technology Inc.
bit 12-10 IP1<2:0>: Interrupt Priority bits
111 = Interrupt priority is 7
•
•
•
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
bit 9-8 IS1<1:0>: Interrupt Subpriority bits
11 = Interrupt subpriority is 3
10 = Interrupt subpriority is 2
01 = Interrupt subpriority is 1
00 = Interrupt subpriority is 0
bit 7-5 Unimplemented: Read as ‘0’
bit 4-2 IP0<2:0>: Interrupt Priority bits
111 = Interrupt priority is 7
•
•
•
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
bit 1-0 IS0<1:0>: Interrupt Subpriority bits
11 = Interrupt subpriority is 3
10 = Interrupt subpriority is 2
01 = Interrupt subpriority is 1
00 = Interrupt subpriority is 0
REGISTER 7-7: IPCx: INTERRUPT PRIORITY CONTROL REGISTER x
(1)
(CONTINUED)
Note 1: This register represents a generic definition of the IPCx register. Refer to Table 7-3 for the exact bit
definitions.
2015-2016 Microchip Technology Inc. DS60001324B-page 65
PIC32MM0064GPL036 FAMILY
8.0 OSCILLATOR
CONFIGURATION
The PIC32MM0064GPL036 family oscillator system
has the following modules and features:
• On-Chip PLL with User-Selectable Multiplier and
Output Divider to Boost Operating Frequency on
Select Internal and External Oscillator Sources
• Primary High-Frequency Crystal Oscillator
• Secondary Low-Frequency and Low-Power
Crystal Oscillator
• On-Chip Fast RC (FRC) Oscillator with
User-Selectable Output Divider
• Software-Controllable Switching between Various
Clock Sources
• Fail-Safe Clock Monitor (FSCM) that Detects
Clock Failure and Permits Safe Application
Recovery or Shutdown
• Flexible Reference Clock Output (REFO)
A block diagram of the oscillator system is provided in
Figure 8-1.
8.1 Fail-Safe Clock Monitor (FSCM)
The PIC32MM0064GPL036 family oscillator system
includes a Fail-Safe Clock Monitor (FSCM). The FSCM
monitors the SYSCLK for continuous operation. If it
detects that the SYSCLK has failed, it switches the
SYSCLK over to the FRC oscillator and triggers a Non-
Maskable Interrupt (NMI). When the NMI is executed,
software can attempt to restart the main oscillator or
shut down the system.
In Sleep mode, both the SYSCLK and the FSCM halt,
which prevents FSCM detection.
Note: This data sheet summarizes the features
of the PIC32MM0064GPL036 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 59. “Oscillators
with D CO” (DS60001329) in the “PIC32
Family Refe rence Man ual” , which is avail-
able from the Microchip web site
(www.microchip.com/PIC32). The infor-
mation in this data sheet supersedes the
information in the FRM.
PIC32MM0064GPL036 FAMILY
DS60001324B-page 66 2015-2016 Microchip Technology Inc.
FIGURE 8-1: PIC32M M00 64GP L 036 FAMILY OSCILLATOR DIAGRAM
Note 1: Refer to Table 26-18 in Section 26.0 “Electrical Characteristics” for frequency limitations.
To Timer1, RTCC, MCCP/SCCP and CLC
Clock Control Logic
Fail-Safe
Clock
Monitor
COSC<2:0>
NOSC<2:0>
OSWEN
FCKSM<1:0>
Secondary Oscillator (SOSC)
SOSCSEL
SOSCO/
SOSCI
POSC (HS, EC)
FRCDIV<2:0>
To Timer1, WDT, RTCC
FRC
Oscillator
LPRC
Oscillator
SOSC
LPRC
FRCDIV
TUN<5:0>
Postscaler
N
PLLICLK
F
IN(1)
PLLODIV<2:0>
32.768 kHz
PLLMULT<6:0>
SYSCLK (F
SYS
)
(N)
(N)
REFCLKO
OE
To MCCP, SCCP
Reference Clock
RODIV<14:0> (N)
ROTRIM<8:0> (M)
N
SPLL
REFCLKI
POSC
FRC
LPRC
SOSC
SYSCLK
ROSEL<3:0>
OSC2
OSC1/
Primary
(M)
PLL x M
F
PLL
(1)
To ADC, WDT, UART
Fvco
(1)
System PLL
REFO1CON REFO1TRIM
2N
M
512
----------+
8 MHz
Oscillator (POSC)
2 MHz ≤ F
IN
≤ 24 MHz
16 MHz ≤ F
VCO
≤ 96 MHz
SPLLVCO
and SPIx
POSCMOD<1:0>
and Flash Controller
PBCLK (F
PB
)
32 kHz
SOSCEN
FNOSC<2:0>
SCLKI
CLKI
2015-2016 Microchip Technology Inc. DS60001324B-page 67
PIC32MM0064GPL036 FAMILY
8.2 Oscillator Control Registers
TABLE 8-1: OSCILLATOR CONFIGURATION REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
(2)
Bit Range
Bits
All Resets
(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
2000 OSCCON 31:16 — — — — — FRCDIV<2:0> — — — — — — — — 0000
15:0 —COSC<2:0> —NOSC<2:0> CLKLOCK — — SLPEN CF —SOSCEN OSWEN xx0x
2020 SPLLCON 31:16 — — — — — PLLODIV<2:0> —PLLMULT<6:0> 0001
15:0 — — — — — — — — PLLICLK — — — — — — — 0000
20A0 REFO1CON 31:16 —RODIV<14:0> 0000
15:0 ON —SIDL OE RSLP —DIVSWEN ACTIVE — — — — ROSEL<3:0> 0000
20B0 REFO1TRIM 31:16 ROTRIM<8:0> — — — — — — — 0000
15:0 — — — — — — — — — — — — — — — — 0000
21D0 CLKSTAT 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — — SPLLRDY — LPRCRDY SOSCRDY —POSCRDY SPDIVRDY FRCRDY 0000
2200 OSCTUN 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — — — — TUN<5:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Reset values are dependent on the FOSCSEL Configuration bits and the type of Reset.
2: All registers in this table have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively.
PIC32MM0064GPL036 FAMILY
DS60001324B-page 68 2015-2016 Microchip Technology Inc.
REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER
(1)
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — FRCDIV<2:0>
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 R-y R-y R-y U-0 R/W-y R/W-y R/W-y
—COSC<2:0>
(3)
—NOSC<2:0>
(3)
7:0
R/W-0 U-0 U-0 R/W-0 R/W-0, HS U-0 R/W-y R/W-y
CLKLOCK —— SLPEN CF —SOSCEN
(4)
OSWEN
(2)
Legend: HS = Hardware Settable bit y = Value set from Configuration bits on Reset
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-27 Unimplemented: Read as ‘0’
bit 26-24 FRCDIV<2:0>: Internal Fast RC (FRC) Oscillator Clock Divider bits
111 = FRC divided by 256
110 = FRC divided by 64
101 = FRC divided by 32
100 = FRC divided by 16
011 = FRC divided by 8
010 = FRC divided by 4
001 = FRC divided by 2
000 = FRC divided by 1 (default setting)
bit 23-15 Unimplemented: Read as ‘0’
bit 14-12 COSC<2:0>: Current Oscillator Selection bits
(3)
111 and 110 = Reserved (selects internal Fast RC (FRC) Oscillator divided by the FRCDIV<2:0> bits
(FRCDIV))
101 = Internal Low-Power RC (LPRC) Oscillator
100 = Secondary Oscillator (SOSC)
011 = Reserved
010 = Primary Oscillator (POSC) (XT, HS or EC)
001 = System PLL (SPLL)
000 = Internal Fast RC (FRC) Oscillator divided by FRCDIV<2:0> bits (FRCDIV)
bit 11 Unimplemented: Read as ‘0’
Note 1: Writes to this register require an unlock sequence. Refer to Section 2 3.4 “S yst em Regis ter s Write
Protection” for details.
2: The Reset value for this bit depends on the setting of the IESO (FOSCSEL<7>) Configuration bit. When
IESO = 1, the Reset value is ‘1’. When IESO = 0, the Reset value is ‘0’.
3: The Reset value for these bits matches the setting of the FNOSC<2:0> (FOSCSEL<2:0>) Configuration
bits.
4: The Reset value for this bit matches the setting of the SOSCEN (FOSCSEL<6>) Configuration bit.
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bit 10-8 NOSC<2:0>: New Oscillator Selection bits
(3)
111 and 110 = Reserved (selects internal Fast RC (FRC) Oscillator divided by FRCDIV<2:0> bits
(FRCDIV))
101 = Internal Low-Power RC (LPRC) Oscillator
100 = Secondary Oscillator (SOSC)
011 = Reserved
010 = Primary Oscillator (POSC) (XT, HS or EC)
001 = System PLL (SPLL)
000 = Internal Fast RC (FRC) Oscillator divided by FRCDIV<2:0> bits (FRCDIV)
On Reset, these bits are set to the value of the FNOSC<2:0> Configuration bits (FOSCSEL<2:0>).
bit 7 CLKLOCK: Clock Selection Lock Enable bit
1 = Clock and PLL selections are locked
0 = Clock and PLL selections are not locked and may be modified
bit 6-5 Unimplemented: Read as ‘0’
bit 4 SLPEN: Sleep Mode Enable bit
1 = Device will enter Sleep mode when a WAIT instruction is executed
0 = Device will enter Idle mode when a WAIT instruction is executed
bit 3 CF: Clock Fail Detect bit
1 = FSCM has detected a clock failure
0 = No clock failure has been detected
bit 2 Unimplemented: Read as ‘0’
bit 1 SOSCEN: Secondary Oscillator (SOSC) Enable bit
(4)
1 = Enables Secondary Oscillator
0 = Disables Secondary Oscillator
bit 0 OSWEN: Oscillator Switch Enable bit
(2)
1 = Initiates an oscillator switch to a selection specified by the NOSC<2:0> bits
0 = Oscillator switch is complete
REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER
(1)
(CONTINUED)
Note 1: Writes to this register require an unlock sequence. Refer to Section 2 3.4 “S yst em Regis ter s Write
Protection” for details.
2: The Reset value for this bit depends on the setting of the IESO (FOSCSEL<7>) Configuration bit. When
IESO = 1, the Reset value is ‘1’. When IESO = 0, the Reset value is ‘0’.
3: The Reset value for these bits matches the setting of the FNOSC<2:0> (FOSCSEL<2:0>) Configuration
bits.
4: The Reset value for this bit matches the setting of the SOSCEN (FOSCSEL<6>) Configuration bit.
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DS60001324B-page 70 2015-2016 Microchip Technology Inc.
REGISTER 8-2: SPLLCON: SYSTEM PLL CONTROL REGISTER
(1)
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — PLLODIV<2:0>
23:16
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1
— PLLMULT<6:0>
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
R/W-y U-0 U-0 U-0 U-0 U-0 U-0 U-0
PLLICLK — — — — — — —
Legend: y = Values set from Configuration bits on Reset
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-27 Unimplemented: Read as ‘0’
bit 26-24 PLLODIV<2:0>: System PLL Output Clock Divider bits
111 = PLL divide-by-256
110 = PLL divide-by-64
101 = PLL divide-by-32
100 = PLL divide-by-16
011 = PLL divide-by-8
010 = PLL divide-by-4
001 = PLL divide-by-2
000 = PLL divide-by-1 (default setting)
bit 23 Unimplemented: Read as ‘0’
bit 22-16 PLLMULT<6:0>: System PLL Multiplier bits
111111-0000111 = Reserved
0000110 = 24x
0000101 = 12x
0000100 = 8x
0000011 = 6x
0000010 = 4x
0000001 = 3x (default setting)
0000000 = 2x
bit 15-8 Unimplemented: Read as ‘0’
bit 7 PLLICLK: System PLL Input Clock Source bit
1 = FRC is selected as the input to the system PLL (not divided)
0 = POSC is selected as the input to the system PLL
The POR default value is specified by the PLLSRC Configuration bit in the FOSCSEL register. Refer to
Register 23-9 in Section 23.0 “Special Features” for more information.
bit 6-0 Unimplemented: Read as ‘0’
Note 1: Writes to this register require an unlock sequence. Refer to Section 2 3.4 “S yst em Regis ter s Write
Protection” for details. All bits in this register must be modified only if the PLL is not used.
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REGISTER 8-3: REFO1CON: REFERENCE OSCILLATOR CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—RODIV<14:8>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
RODIV<7:0>
15:8
R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R-0, HS, HC
ON
(1)
—SIDL OERSLP
(2)
— DIVSWEN ACTIVE
(1)
7:0
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — ROSEL<3:0>
(3)
Legend: HC = Hardware Clearable bit HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 Unimplemented: Read as ‘0’
bit 30-16 RODIV<14:0> Reference Clock Divider bits
The value selects the reference clock divider bits (see Figure 8-1 for details). A value of ‘0’ selects no divider.
bit 15 ON: Reference Oscillator Output Enable bit
(1)
1 = Reference oscillator module is enabled
0 = Reference oscillator module is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Peripheral Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12 OE: Reference Clock Output Enable bit
1 = Reference clock is driven out on the REFCLKO pin
0 = Reference clock is not driven out on the REFCLKO pin
bit 11 RSLP: Reference Oscillator Module Run in Sleep bit
(2)
1 = Reference oscillator module output continues to run in Sleep
0 = Reference oscillator module output is disabled in Sleep
bit 10 Unimplemented: Read as ‘0’
bit 9 DIVSWEN: Divider Switch Enable bit
1 = Divider switch is in progress
0 = Divider switch is complete
bit 8 ACTIVE: Reference Clock Request Status bit
(1)
1 = Reference clock request is active
0 = Reference clock request is not active
bit 7-4 Unimplemented: Read as ‘0’
Note 1: Do not write to this register when the ON bit is not equal to the ACTIVE bit.
2: This bit is ignored when the ROSEL<3:0> bits = 0000.
3: The ROSEL<3:0> bits should not be written while the ACTIVE bit is ‘1’, as undefined behavior may result.
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DS60001324B-page 72 2015-2016 Microchip Technology Inc.
bit 3-0 ROSEL<3:0>: Reference Clock Source Select bits
(3)
1111 = Reserved
•
•
•
1010 = Reserved
1001 = REFCLKI pin
1000 = Reserved
0111 = System PLL output (not divided)
0110 = Reserved
0101 = Secondary Oscillator (SOSC)
0100 = Low-Power RC Oscillator (LPRC)
0011 = Fast RC Oscillator (FRC)
0010 = Primary Oscillator (POSC)
0001 = Instruction/System Clock (SYSCLK)
0000 = Instruction/System Clock (SYSCLK)
REGISTER 8-3: REFO1CON: REFERENCE OSCILLATOR CONTROL REGISTER (CONTINUED)
Note 1: Do not write to this register when the ON bit is not equal to the ACTIVE bit.
2: This bit is ignored when the ROSEL<3:0> bits = 0000.
3: The ROSEL<3:0> bits should not be written while the ACTIVE bit is ‘1’, as undefined behavior may result.
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REGISTER 8-4: REFO1TRIM: REFERENCE OSCILLATOR TRIM REGISTER
(1,2,3)
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ROTRIM<8:1>
23:16
R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
ROTRIM<0> ———————
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-23 ROTRIM<8:0>: Reference Oscillator Trim bits
111111111 = 511/512 divisor added to the RODIVx value
111111110 = 510/512 divisor added to the RODIVx value
•
•
•
100000000 = 256/512 divisor added to the RODIVx value
•
•
•
000000010 = 2/512 divisor added to the RODIVx value
000000001 = 1/512 divisor added to the RODIVx value
000000000 = 0 divisor added to the RODIVx value
bit 22-0 Unimplemented: Read as ‘0’
Note 1: While the ON bit (REFO1CON<15>) is ‘1’, writes to this register do not take effect until the DIVSWEN bit
is also set to ‘1’.
2: Do not write to this register when the ON bit (REFO1CON<15>) is not equal to the ACTIVE bit
(REFO1CON<8>).
3: Specified values in this register do not take effect if RODIV<14:0> (REFO1CON<30:16>) = 0.
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REGISTER 8-5: CLKSTAT: CLOCK STATUS REGISTER
Bit
Range Bit
31/23/15/7
Bit
30/22/14/
6
Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
R-0, HS, HC U-0 R-0, HS, HC R-0, HS, HC U-0 R-0, HS, HC R-0, HS, HC R-0, HS, HC
SPLLRDY — LPRCRDY SOSCRDY — POSCRDY SPDIVRDY FRCRDY
Legend: HS = Hardware Settable bit HC = Hardware Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7 SPLLRDY: PLL Lock bit
1 = PLL is locked and ready
0 = PLL is not locked
bit 6 Unimplemented: Read as ‘0’
bit 5 LPRCRDY: LPRC Oscillator Ready bit
1 = LPRC oscillator is stable and ready
0 = LPRC oscillator is not stable
bit 4 SOSCRDY: Secondary Oscillator (SOSC) Ready bit
1 = SOSC is stable and ready
0 = SOSC is not stable
bit 3 Unimplemented: Read as ‘0’
bit 2 POSCRDY: Primary Oscillator (POSC) Ready bit
1 = POSC is stable and ready
0 = POSC is not stable
bit 1 SPDIVRDY: System PLL (with postscaler, SPLLDIV) Clock Ready Status bit
1 = SPLLDIV is stable and ready
0 = SPLLDIV is not stable
bit 0 FRCRDY: Fast RC (FRC) Oscillator Ready bit
1 = FRC oscillator is stable and ready
0 = FRC oscillator is not stable
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REGISTER 8-6: OSCTUN: FRC TUNING REGISTER
(1)
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— TUN<5:0>
(2)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-6 Unimplemented: Read as ‘0’
bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits
(2)
100000 = Center frequency – 1.5%
100001
•
•
•
111111
000000 = Center frequency; oscillator runs at 8 MHz
000001
•
•
•
011110
011111 = Center frequency + 1.5%
Note 1: Writes to this register require an unlock sequence. Refer to Secti on 2 3.4 “Syst em R egis ters Write
Protection” for details.
2: OSCTUN functionality has been provided to help customers compensate for temperature effects on the
FRC frequency over a wide range of temperatures. The tuning step-size is an approximation and is
neither characterized nor tested.
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NOTES:
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9.0 I/O PORTS
Many of the device pins are shared among the periph-
erals and the Parallel I/O (PIO) ports. All I/O input ports
feature Schmitt Trigger inputs for improved noise
immunity. Some pins in the devices are 5V tolerant
pins. Some of the key features of the I/O ports are:
• Individual Output Pin Open-Drain Enable/Disable
• Individual Input Pin Weak Pull-up and Pull-Down
• Monitor Selective Inputs and Generate Interrupt
when Change-in-Pin State is Detected
• Operation during Sleep and Idle modes
• Fast Bit Manipulation using the CLR, SET and
INV registers
Figure 9-1 illustrates a block diagram of a typical
multiplexed I/O port.
FIGURE 9-1: BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE
Note: This data sheet summarizes the features
of the PIC32MM0064GPL036 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 12. “I/O Ports”
(DS60001120) in the “PIC32 Family
Reference Manual”, which is available
from the Microchip web site
(www.microchip.com/PIC32). The infor-
mation in this data sheet supersedes the
information in the FRM.
QD
CK
WR LATx +
TRISx Latch
I/O Pin
WR PORTx
Data Bus
QD
CK
Data Latch
Read PORTx
Read TRISx
1
0
1
0
WR TRISx
Peripheral Output Data
Output Enable
Peripheral Input Data
I/O
Peripheral Module
Peripheral Output Enable
PIO Module
Output Multiplexers
Output Data
Input Data
Peripheral Module Enable
Read LATx
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DS60001324B-page 78 2015-2016 Microchip Technology Inc.
9.1 CLR, SET and INV Registers
Every I/O module register has a corresponding CLR
(Clear), SET (Set) and INV (Invert) register designed to
provide fast atomic bit manipulations. As the name of
the register implies, a value written to a SET, CLR or
INV register effectively performs the implied operation,
but only on the corresponding base register and only
bits specified as ‘1’ are modified. Bits specified as ‘0’
are not modified.
Reading SET, CLR and INV registers returns undefined
values. To see the affects of a write operation to a SET,
CLR or INV register, the base register must be read.
9.2 Parallel I/O (PIO) Ports
All port pins have 14 registers directly associated with
their operation as digital I/Os. The Data Direction register
(TRISx) determines whether the pin is an input or an out-
put. If the data direction bit is a ‘1’, then the pin is an input.
All port pins are defined as inputs after a Reset. The LATx
register controls the pin level when it is configured as an
output. Reads from the PORTx register read the port pins,
while writes to the port pins write the latch, LATx. The I/Os
state reflected in the PORTx register is synchronized with
the system clock and delayed by 3 system clock cycles.
9.3 Open-Drain Configuration
In addition to the PORTx, LATx and TRISx registers for
data control, the port pins can also be individually config-
ured for either digital or open-drain outputs. This is
controlled by the Open-Drain Control register, ODCx,
associated with each port. Setting any of the bits config-
ures the corresponding pin to act as an open-drain output.
The open-drain feature allows the generation of
outputs higher than V
DD
(e.g., 5V), on any desired 5V
tolerant pins, by using external pull-up resistors. The
maximum open-drain voltage allowed is the same as
the maximum V
IH
specification.
9.4 Configuring Analog and Digital
Port Pins
When the PORTx register is read, all pins configured as
analog input channels are read as cleared (a low level).
Pins configured as digital inputs do not convert an
analog input. Analog levels on any pin defined as a
digital input (including the ANx pins) can cause the input
buffer to consume current that exceeds the device spec-
ifications. The ANSELx register controls the operation of
the analog port pins. The port pins that are to function as
analog inputs must have their corresponding ANSELx
and TRISx bits set. In order to use port pins for I/O func-
tionality with digital modules, such as timers, UARTs,
etc., the corresponding ANSELx bit must be cleared.
The ANSELx register has a default value of 0xFFFF.
Therefore, all pins that share analog functions are
analog (not digital) by default. If the TRISx bit is cleared
(output) while the ANSELx bit is set, the digital output
level (V
OH
or V
OL
) is used by an analog peripheral, such
as the ADC or comparator module.
9.5 I/O Po rt Write/Read Timing
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically, this instruction
would be a NOP.
9.6 Input Change Notification (ICN)
The Input Change Notification function of the I/O ports
allows the PIC32MM devices to generate interrupt
requests to the processor in response to a Change-of-
State (COS) on selected input pins. This feature can
detect input Change-of-States even in Sleep mode,
when the clocks are disabled. Every I/O port pin can be
selected (enabled) for generating an interrupt request on
a Change-of-State. Five control registers are associated
with the Change Notification (CN) functionality of each
I/O port. To enable the Change Notification feature for
the port, the ON bit (CNCONx<15>) must be set.
The CNEN0x and CNEN1x registers contain the CN
interrupt enable control bits for each of the input pins.
The setting of these bits enables a CN interrupt for the
corresponding pins. Also, these bits, in combination
with the CNSTYLE bit (CNCONx<11>), define a type of
transition when the interrupt is generated. Possible CN
event options are listed in Table 9-1.
The CNSTATx register indicates whether a change
occurred on the corresponding pin since the last read
of the PORTx bit. In addition to the CNSTATx register,
the CNFx register is implemented for each port. This
register contains flags for Change Notification events.
These flags are set if the valid transition edge, selected
in the CNEN0x and CNEN1x registers, is detected.
CNFx stores the occurrence of the event. CNFx bits
must be cleared in software to get the next Change
Notification interrupt. The CN interrupt is generated
only for the I/Os configured as inputs (corresponding
TRISx bits must be set).
TABLE 9-1: CHANGE NOTIFICATION
EVENT OPTIONS
CNST YLE Bit
(CNCONx<11>) CNEN1x
Bit CNEN0x
Bit Change Notification Even t
Description
0
Does not
matter
0
Disabled
0
Does not
matter
1
Detects a mismatch between
the last read state and the
current state of the pin
1 0 0
Disabled
1 0 1
Detects a positive transition
only (from ‘
0
’ to ‘
1
’)
1 1 0
Detects a negative transition
only (from ‘
1
’ to ‘
0
’)
1 1 1
Detects both positive and
negative transitions
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9.7 Pin Pull-up and Pull-Down
Each I/O pin also has a weak pull-up and a weak pull-
down connected to it. The pull-ups act as a current
source, or sink source, connected to the pin and
eliminate the need for external resistors when push
button or keypad devices are connected. The pull-ups
and pull-downs are enabled separately using the
CNPUx and the CNPDx registers, which contain the
control bits for each of the pins. Setting any of the control
bits enables the weak pull-ups and/or pull-downs for the
corresponding pins.
9.8 Peripher al Pin Select (PPS)
A major challenge in general purpose devices is provid-
ing the largest possible set of peripheral features, while
minimizing the conflict of features on I/O pins. The
challenge is even greater on low pin count devices. In
an application where more than one peripheral needs
to be assigned to a single pin, inconvenient work
arounds in application code, or a complete redesign,
may be the only option.
PPS configuration provides an alternative to these
choices by enabling peripheral set selection and their
placement on a wide range of I/O pins. By increasing
the pinout options available on a particular device,
users can better tailor the device to their entire
application, rather than trimming the application to fit
the device.
The PPS configuration feature operates over a fixed
subset of digital I/O pins. Users may independently
map the input and/or output of most digital peripherals
to these I/O pins. PPS is performed in software
and generally does not require the device to be
reprogrammed. Hardware safeguards are included that
prevent accidental or spurious changes to the
peripheral mapping once it has been established.
9.8.1 AVAILABLE PINS
The number of available pins is dependent on the
particular device and its pin count. Pins that support the
PPS feature include the designation, “RPn”, in their full
pin designation, where “RP” designates a Remappable
Peripheral and “n” is the remappable port number.
9.8.2 AVAILABLE PERIPHERALS
The peripherals managed by the PPS are all digital
only peripherals. These include general serial commu-
nications (UART and SPI), general purpose timer clock
inputs, timer related peripherals (MCCP, SCCP) and
others.
In comparison, some digital only peripheral modules are
never included in the PPS feature. This is because the
peripheral’s function requires special I/O circuitry on a
specific port and cannot be easily connected to multiple
pins. A similar requirement excludes all modules with
analog inputs, such as the Analog-to-Digital Converter
(ADC).
A key difference between remappable and non-
remappable peripherals is that remappable peripherals
are not associated with a default I/O pin. The peripheral
must always be assigned to a specific I/O pin before it
can be used. In contrast, non-remappable peripherals
are always available on a default pin, assuming that the
peripheral is active and not conflicting with another
peripheral.
When a remappable peripheral is active on a given I/O
pin, it takes priority over all other digital I/Os and digital
communication peripherals associated with the pin.
Priority is given regardless of the type of peripheral that
is mapped. Remappable peripherals never take priority
over any analog functions associated with the pin.
9.8.3 CONTROLLING PPS
PPS features are controlled through two sets of SFRs:
one to map peripheral inputs and one to map outputs.
Because they are separately controlled, a particular
peripheral’s input and output (if the peripheral has both)
can be placed on any selectable function pin without
constraint.
The association of a peripheral to a peripheral-selectable
pin is handled in two different ways, depending on
whether an input or output is being mapped.
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9.8.4 INPUT MAPPING
The RPINRx registers are used to assign the peripheral
input to the required remappable pin, RPn (refer to the
peripheral inputs and the corresponding RPINRx regis-
ters listed in Table 9-2). Each RPINRx register contains
sets of 5-bit fields. Programming these bits with the
remappable pin number will connect the peripheral to
this RPn pin. Example 9-1 and Figure 9-2 illustrate the
remappable pin selection for the U2RX input.
EXAMPLE 9-1: UART2 RX INPUT
ASSIGNMENT TO
RP9/RB 14 PIN
FIGURE 9-2: REMAPPABLE INPUT
EXAMPLE FOR U2RX
RPINR9bits.U2RXR = 9; // connect UART2 RX
// input to RP9 pin
RP1
RP2
RP3
1
2
3
U2RX Input
U2RXR<4:0>
to Peripheral
RPn
n
Note: For input only, PPS functionality does not
have priority over TRISx settings. Therefore,
when configuring an RPn pin for input, the
corresponding bit in the TRISx register must
also be configured for input (set to ‘1’).
TABLE 9-2: INPUT PIN SELECTION
Input Name Function Name Register Function Bits
External Interrupt 4 INT4 RPINR1 INT4R<4:0>
MCCP1 Input Capture ICM1 RPINR2 ICM1R<4:0>
SCCP2 Input Capture ICM2 RPINR2 ICM2R<4:0>
SCCP3 Input Capture ICM3 RPINR3 ICM3R<4:0>
Output Compare Fault A OCFA RPINR5 OCFAR<4:0>
Output Compare Fault B OCFB RPINR5 OCFBR<4:0>
CCP Clock Input A TCKIA RPINR6 TCKIAR<4:0>
CCP Clock Input B TCKIB RPINR6 TCKIBR<4:0>
UART2 Receive U2RX RPINR9 U2RXR<4:0>
UART2 Clear-to-Send U2CTS RPINR9 U2CTSR<4:0>
SPI2 Data Input SDI2 RPINR11 SDI2R<4:0>
SPI2 Clock Input SCK2IN RPINR11 SCK2INR<4:0>
SPI2 Slave Select Input SS2IN RPINR11 SS2INR<4:0>
CLC Input A CLCINA RPINR12 CLCINAR<4:0>
CLC Input B CLCINB RPINR12 CLCINBR<4:0>
2015-2016 Microchip Technology Inc. DS60001324B-page 81
PIC32MM0064GPL036 FAMILY
9.8.5 OUTPUT MAPPING
The RPORx registers are used to assign the peripheral
output to the required remappable pin, RPn. Each
RPORx register contains 4-bit fields corresponding to
the remappable pins. A special value is defined for
each peripheral output. This value should be written to
the remappable pin bit field in the RPORx register to
connect the peripheral output to the RPn pin. All
possible (implemented) values for the peripheral’s
outputs are listed in Table 9-3.
Example 9-2 and Figure 9-3 illustrate the peripheral’s
output selection for the remappable pin.
EXAMPLE 9-2: UART2 TX OUTPUT
ASSIGNMENT TO
RP13/RB13 PIN
FIGURE 9-3: EXAMPL E OF
MULTIPLEXI NG OF
REMAPPABLE OUTPUT
FOR RP1
9.8.6 CONTROLLING CONFIGURATION
CHANGES
Because peripheral remapping can be changed during
run time, some restrictions on peripheral remapping
are needed to prevent accidental configuration
changes. PIC32MM0064GPL036 family devices
include two features to prevent alterations to the
peripheral map:
• Control register lock sequence
• Configuration bit select lock
9.8.6.1 Control Register Lock
Under normal operation, the RPORx and RPINRx
registers can be written, but they can also be locked
to prevent accidental writes. This feature is con-
trolled by the IOLOCK bit in the RPCON register. If
the IOLOCK bit is set, then the contents of the
RPORx and RPINRx registers cannot be changed.
To modify the IOLOCK bit, an unlock sequence must be
executed. Refer to Section 23.4 “System Registers
Write Protection” for details.
RPOR4bits.RP13R = 1; // connect UART2 TX (= 1)
// to RP13 pin
RP1R<3:0>
0
9
1
Default
U2TX Output
SDO2 Output 2
Output Data RP1
CLC2OUT
TABLE 9-3: OUTPUT PIN SELECTION
Output Function Number Function O utput Name
0None (not connected) —
1U2TX UART2 Transmit
2U2RTS UART2 Request-to-Send
3SDO2 SPI2 Data Output
4SCK2OUT SPI2 Clock Output
5SS2OUT SPI2 Slave Select Output
6OCM2 SCCP2 Output Compare
7OCM3 SCCP3 Output Compare
8CLC1OUT CLC1 Output
9CLC2OUT CLC2 Output
PIC32MM0064GPL036 FAMILY
DS60001324B-page 82 2015-2016 Microchip Technology Inc.
9.9 I/O Ports Control Registers
TABLE 9-4: PORTA REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
(3)
Bit Range
Bits
All
Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
2600 ANSELA 31:16 — — — — — — — — — — — — — — — —
0000
15:0 — — — — — — — — — — — — ANSA<3:0>
000F
2610 TRISA 31:16 — — — — — — — — — — — — — — — —
0000
15:0 — — — — — — TRISA9
(1,2)
— — — — TRISA<4:0>
021F
2620 PORTA 31:16 — — — — — — — — — — — — — — — —
0000
15:0 — — — — — — RA9
(1,2)
— — — — RA<4:0>
xxxx
2630 LATA 31:16 — — — — — — — — — — — — — — — —
0000
15:0 — — — — — — LATA9
(1,2)
— — — — LATA<4:0>
0000
2640 ODCA 31:16 — — — — — — — — — — — — — — — —
0000
15:0 — — — — — — ODCA9
(1,2)
— — — — ODCA<4:0>
0000
2650 CNPUA 31:16 — — — — — — — — — — — — — — — —
0000
15:0 — — — — — — CNPUA9
(1,2)
— — — — CNPUA<4:0>
0000
2660 CNPDA 31:16 — — — — — — — — — — — — — — — —
0000
15:0 — — — — — — CNPDA9
(1,2)
— — — — CNPDA<4:0>
0000
2670 CNCONA 31:16 — — — — — — — — — — — — — — — —
0000
15:0 ON — — — CNSTYLE — — — — — — — — — — —
0000
2680 CNEN0A 31:16 — — — — — — — — — — — — — — — —
0000
15:0 — — — — — — CNIEA9
(1,2)
— — — — CNIEA<4:0>
0000
2690 CNSTATA 31:16 — — — — — — — — — — — — — — — —
0000
15:0 — — — — — — CNSTATA9
(1,2)
— — — — CNSTATA<4:0>
0000
26A0 CNEN1A 31:16 — — — — — — — — — — — — — — — —
0000
15:0 — — — — — — CNIE1A9
(1,2)
— — — — CNIE1A<4:0>
0000
26B0 CNFA 31:16 — — — — — — — — — — — — — — — —
0000
15:0 — — — — — — CNFA9
(1,2)
— — — CNFA<4:0>
0000
Legend:
x
= unknown value on Reset; — = unimplemented, read as ‘
0
’. Reset values are shown in hexadecimal.
Note 1:
These bits are not implemented in 20-pin devices.
2:
These bits are not implemented in 28-pin devices.
3:
All registers in this table have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively.
2015-2016 Microchip Technology Inc. DS60001324B-page 83
PIC32MM0064GPL036 FAMILY
TABLE 9-5: PORTB REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
(2)
Bit Range
Bits
All
Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
2700 ANSELB 31:16 — — — — — — — — — — — — — — — — 0000
15:0 ANSB<15:12> — — — — — — — — ANSB<3:0>
(1)
F00F
2710 TRISB 31:16 — — — — — — — — — — — — — — — — 0000
15:0 TRISB<15:0>
(1)
FFFF
2720 PORTB 31:16 — — — — — — — — — — — — — — — — 0000
15:0 RB<15:0>
(1)
0000
2730 LATB 31:16 — — — — — — — — — — — — — — — — 0000
15:0 LATB<15:0>
(1)
0000
2740 ODCB 31:16 — — — — — — — — — — — — — — — — 0000
15:0 ODCB<15:0>
(1)
0000
2750 CNPUB 31:16 — — — — — — — — — — — — — — — — 0000
15:0 CNPUB<15:0>
(1)
0000
2760 CNPDB 31:16 — — — — — — — — — — — — — — — — 0000
15:0 CNPDB<15:0>
(1)
0000
2770 CNCONB 31:16 — — — — — — — — — — — — — — — — 0000
15:0 ON — — — CNSTYLE — — — — — — — — — — — 0000
2780 CNEN0B 31:16 — — — — — — — — — — — — — — — — 0000
15:0 CNIEB<15:0>
(1)
0000
2790 CNSTATB 31:16 — — — — — — — — — — — — — — — — 0000
15:0 CNSTATB<15:0>
(1)
0000
27A0 CNEN1B 31:16 — — — — — — — — — — — — — — — — 0000
15:0 CNIE1B<15:0>
(1)
0000
27B0 CNFB 31:16 — — — — — — — — — — — — — — — — 0000
15:0 CNFB<15:0>
(1)
0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Bits<11:10,6:5,3> are not implemented in 20-pin devices.
2: All registers in this table have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively.
PIC32MM0064GPL036 FAMILY
DS60001324B-page 84 2015-2016 Microchip Technology Inc.
TABLE 9-6: PORTC REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
(3)
Bit Range
Bits
All
Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
2800 ANSELC 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — — — — — — — — ANSC<1:0>
(1,2)
0003
2810 TRISC 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — TRISC<9:8>
(1,2)
— — — — TRISC<3:0>
(1,2)
030F
2820 PORTC 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — RC<9:8>
(1,2)
— — — — RC<3:0>
(1,2)
0000
2830 LATC 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — LATC<9:8>
(1,2)
— — — — LATC<3:0>
(1,2)
0000
2840 ODCC 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — ODCC<9:8>
(1,2)
— — — — ODCC<3:0>
(1,2)
0000
2850 CNPUC 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — CNPUC<9:8>
(1,2)
— — — — CNPUC<3:0>
(1,2)
0000
2860 CNPDC 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — CNPDC<9:8>
(1,2)
— — — — CNPDC<3:0>
(1,2)
0000
2870 CNCONC 31:16 — — — — — — — — — — — — — — — — 0000
15:0 ON
(1)
— — — CNSTYLE
(1)
— — — — — — — — — — — 0000
2880 CNEN0C 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — CNIE0C<9:8>
(1,2)
— — — — CNIE0C<3:0>
(1,2)
0000
2890 CNSTATC 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — CNSTATC<9:8>
(1,2)
— — — — CNSTATC<3:0>
(1,2)
0000
28A0 CNEN1C 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — CNIE1C<9:8>
(1,2)
— — — — CNIE1C<3:0>
(1,2)
0000
28B0 CNFC 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — CNFC<9:8>
(1,2)
— — — — CNFC<3:0>
(1,2)
0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Bits<15,11,9:8,3:0> are not implemented in 20-pin devices.
2: Bits<8,3:0> are not implemented in 28-pin devices.
3: All registers in this table have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively.
2015-2016 Microchip Technology Inc. DS60001324B-page 85
PIC32MM0064GPL036 FAMILY
TABLE 9-7: PERIPHERAL PIN SELECT REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
2480 RPCON 31:16 — — — — — — — — — — — — — — — — 0000
15:0 ——— — IOLOCK — — — — — — — — — — — 0000
24A0 RPINR1 31:16 — — — — — — — — — — — — — — — — 0000
15:0 INT4R<4:0> 0000
24B0 RPINR2 31:16 ——— ICM2R<4:0> — — — ICM1R<4:0> 0000
15:0 — — — — — — — — — — — — — — — — 0000
24C0 RPINR3 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — — — — — ICM3R<4:0> 0000
24E0 RPINR5 31:16 ——— OCFBR<4:0> — — — OCFAR<4:0> 0000
15:0 — — — — — — — — — — — — — — — — 0000
24F0 RPINR6 31:16 — — — — — — — — — — — — — — — — 0000
15:0 TCKIBR<4:0> — — — TCKIAR<4:0> 0000
2520 RPINR9 31:16 ——— U2CTSR<4:0> — — — U2RXR<4:0> 0000
15:0 — — — — — — — — — — — — — — — — 0000
2540 RPINR11 31:16 — — — — — — — — — — — SS2INR<4:0> 0000
15:0 ——— SCK2INR<4:0> — — — SDI2R<4:0> 0000
2550 RPINR12 31:16 ——— CLCINBR<4:0> — — — CLCINAR<4:0> 0000
15:0 — — — — — — — — — — — — — — — — 0000
2590 RPOR0 31:16 RP4R<3:0> — — — — RP3R<3:0> 0000
15:0 ——— —RP2R<3:0>— — — — RP1R<3:0> 0000
25A0 RPOR1 31:16 ——— —RP8R<3:0>— — — — RP7R<3:0> 0000
15:0 ——— —RP6R<3:0>— — — — RP5R<3:0> 0000
25B0 RPOR2 31:16 ——— — RP12R<3:0> — — — — RP11R<3:0> 0000
15:0 ——— — RP10R<3:0> — — — — RP9R<3:0> 0000
25C0 RPOR3 31:16 ——— — RP16R<3:0> — — — — RP15R<3:0> 0000
15:0 ——— — RP14R<3:0> — — — — RP13R<3:0> 0000
25D0 RPOR4 31:16 ——— — RP20R<3:0> — — — — RP19R<3:0> 0000
15:0 ——— — RP18R<3:0> — — — — RP17R<3:0> 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively.
PIC32MM0064GPL036 FAMILY
DS60001324B-page 86 2015-2016 Microchip Technology Inc.
REGISTER 9-1: CNCONx: CHANGE NOTIFICATION CONTROL FOR PORTx REGISTER (x = A-C)
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0
ON — — —CNSTYLE — — —
7:0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ON: Change Notification (CN) Control On bit
1 = CN is enabled
0 = CN is disabled
bit 14-12 Unimplemented: Read as ‘0’
bit 11 CNSTYLE: Change Notification Style Selection bit
1 = Edge style (detects edge transitions, CNFx bits are used for a Change Notice event)
0 = Mismatch style (detects change from last PORTx read, CNSTATx bits are used for a Change Notification
event)
bit 10-0 Unimplemented: Read as ‘0’
2015-2016 Microchip Technology Inc. DS60001324B-page 87
PIC32MM0064GPL036 FAMILY
10.0 TIMER1
PIC32MM0064GPL036 family devices feature one
synchronous/asynchronous 16-bit timer that can operate
as a free-running interval timer for various timing
applications and counting external events. This timer
can be clocked from different sources, such as the
Peripheral Bus Clock (PBCLK, 1:1 with SYSCLK),
Secondary Oscillator (SOSC), T1CK pin or LPRC
oscillator.
The following modes are supported by Timer1:
• Synchronous Internal Timer
• Synchronous Internal Gated Timer
• Synchronous External Timer
• Asynchronous External Timer
The timer has a selectable clock prescaler and can
operate in Sleep and Idle modes.
FIGU RE 10 - 1: TI MER 1 BL OCK DI AGRA M
Note: This data sheet summarizes the features
of the PIC32MM0064GPL036 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 14. “Timers”
(DS60001105) in the “PIC32 Family
Reference Manual”, which is available
from the Microchip web site
(www.microchip.com/PIC32). The infor-
mation in this data sheet supersedes the
information in the FRM.
ON
LPRC
SOSC
PR1
T1IF
Equal
16-Bit Comparator
TMR1
Reset
Event Flag
1
0
TSYNC
TGATE
TGATE
PBCLK
1
0
TCS
TCKPS<1:0>
2
x1
10
00
Q
QD
Trigger
T1CK
00
10
01
TECS<1:0>
to ADC
Gate
Sync
Prescaler
1, 8, 64, 256
Sync
(1:1 with SYSCLK)
PIC32MM0064GPL036 FAMILY
DS60001324B-page 88 2015-2016 Microchip Technology Inc.
10.1 Timer1 Control Register
TABLE 10-1: TIMER1 REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
8000 T1CON 31:16 — — — — — — — — — — — — — — — — 0000
15:0 ON —SIDL TWDIS TWIP —TECS<1:0> TGATE —TCKPS<1:0> —TSYNC TCS —0000
8010 TMR1 31:16 — — — — — — — — — — — — — — — — 0000
15:0 TMR1<15:0> 0000
8020 PR1 31:16 — — — — — — — — — — — — — — — — 0000
15:0 PR1<15:0> FFFF
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively.
2015-2016 Microchip Technology Inc. DS60001324B-page 89
PIC32MM0064GPL036 FAMILY
REGISTER 10-1: T1CON: TIMER1 CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 U-0 R/W-0 R/W-0 R-0 U-0 R/W-0 R/W-0
ON — SIDL TWDIS TWIP — TECS<1:0>
7:0
R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0
TGATE — TCKPS<1:0> — TSYNC TCS —
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ON: Timer1 On bit
1 = Timer1 is enabled
0 = Timer1 is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Timer1 Stop in Idle Mode bit
1 = Discontinues operation when device enters Idle mode
0 = Continues operation even in Idle mode
bit 12 TWDIS: Asynchronous Timer1 Write Disable bit
1 = Writes to TMR1 are ignored until pending write operation completes
0 = Back-to-back writes are enabled (Legacy Asynchronous Timer mode functionality)
bit 11 TWIP: Asynchronous Timer1 Write in Progress bit
In Asynchronous Timer1 mode:
1 = Asynchronous write to TMR1 register is in progress
0 = Asynchronous write to TMR1 register is complete
In Synchronous Timer1 mode:
This bit is read as ‘0’.
bit 10 Unimplemented: Read as ‘0’
bit 9-8 TECS<1:0>: Timer1 External Clock Selection bits
11 = Reserved
10 = External clock comes from the LPRC
01 = External clock comes from the T1CK Pin
00 = External clock comes from the Secondary Oscillator (SOSC)
bit 7 TGATE: Timer1 Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 6 Unimplemented: Read as ‘0’
bit 5-4 TCKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:256 prescale value
10 = 1:64 prescale value
01 = 1:8 prescale value
00 = 1:1 prescale value
PIC32MM0064GPL036 FAMILY
DS60001324B-page 90 2015-2016 Microchip Technology Inc.
bit 3 Unimplemented: Read as ‘0’
bit 2 TSYNC: Timer1 External Clock Input Synchronization Selection bit
When TCS = 1:
1 = External clock input is synchronized
0 = External clock input is not synchronized
When TCS = 0:
This bit is ignored.
bit 1 TCS: Timer1 Clock Source Select bit
1 = External clock is defined by the TECS<1:0> bits
0 = Internal peripheral clock
bit 0 Unimplemented: Read as ‘0’
REGISTER 10-1: T1CON: TIMER1 CONTROL REGISTER (CONTINUED)
2015-2016 Microchip Technology Inc. DS60001324B-page 91
PIC32MM0064GPL036 FAMILY
11.0 WATCHDOG TIMER (WDT)
When enabled, the Watchdog Timer (WDT) can be
used to detect system software malfunctions by
resetting the device if the WDT is not cleared
periodically in software. Various WDT time-out periods
can be selected using the WDT postscaler. The WDT
can also be used to wake the device from Sleep or Idle
mode.
Some of the key features of the WDT module are:
• Configuration or Software Controlled
• User-Configurable Time-out Period
• Different Time-out Periods for Run and Sleep/Idle
modes
• Operates from LPRC Oscillator in Sleep/Idle
modes
• Different Clock Sources for Run mode
• Can Wake the Device from Sleep or Idle
FIGURE 11-1: WATCHDOG TIMER BLOCK DIAGRAM
Note: This data sheet summarizes the features
of the PIC32MM0064GPL036 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 62. “Dual Watch-
dog Timer” (DS60001365) in the “PIC32
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32). The infor-
mation in this data sheet supersedes the
information in the FRM.
00
10
CLKSEL<1:0>
SYSCLK
Reserved
FRC Oscillator
LPRC Oscillator
01
11
WDTCLRKEY<15:0> = 5743h
ON
All Resets
Reset
25-Bit Counter Comparator
RUNDIV<4:0>
ON
25-Bit Counter Comparator
Power Save
Power Save SLPDIV<4:0>
Power Save
LPRC Oscillator
Wake-up and
NMI
NMI and Start
NMI Counter
Reset
Power Save
Mode WDT
Run Mode WDT
System Clock Switching
PIC32MM0064GPL036 FAMILY
DS60001324B-page 92 2015-2016 Microchip Technology Inc.
11.1 Watc hdog Timer Control Registers
TABLE 11-1: WATCHDOG TIMER REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
3E80 WDTCON
(1)
31:16 WDTCLRKEY<15:0> 0000
15:0 ON — — RUNDIV<4:0> CLKSEL<1:0> SLPDIV<4:0> WDTWINEN xxxx
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively.
2015-2016 Microchip Technology Inc. DS60001324B-page 93
PIC32MM0064GPL036 FAMILY
REGISTER 11-1: WDTCON: WA TCHDOG TIMER CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
WDTCLRKEY<15:8>
23:16
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
WDTCLRKEY<7:0>
15:8
R/W-0 U-0 U-0 R-y R-y R-y R-y R-y
ON
(1)
—— RUNDIV<4:0>
7:0
R-y R-y R-y R-y R-y R-y R-y R/W-y
CLKSEL<1:0> SLPDIV<4:0> WDTWINEN
Legend: y = Values set from Configuration bits on Reset
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 WDTCLRKEY<15:0>: Watchdog Timer Clear Key bits
To clear the Watchdog Timer to prevent a time-out, software must write the value, 0x5743, to this location
using a single 16-bit write.
bit 15 ON: Watchdog Timer Enable bit
(1)
1 = The WDT is enabled
0 = The WDT is disabled
bit 14-13 Unimplemented: Read as ‘0’
bit 12-8 RUNDIV<4:0>: Shadow Copy of Watchdog Timer Postscaler Value for Run Mode from Configuration bits
On Reset, these bits are set to the values of the RWDTPS<4:0> Configuration bits in FWDT.
bit 7-6 CLKSEL<1:0>: Shadow Copy of Watchdog Timer Clock Selection Value for Run Mode from Configuration bits
On Reset, these bits are set to the values of the RCLKSEL<1:0> Configuration bits in FWDT.
bit 5-1 SLPDIV<4:0>: Shadow Copy of Watchdog Timer Postscaler Value for Sleep/Idle Mode from Configuration bits
On Reset, these bits are set to the values of the SWDTPS<4:0> Configuration bits in FWDT.
bit 0 WDTWINEN: Watchdog Timer Window Enable bit
On Reset, this bit is set to the value of the WINDIS Configuration bit in FWDT.
1 = Windowed mode is enabled
0 = Windowed mode is disabled
Note 1: This bit only has control when FWDTEN (FWDT<15>) = 0.
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DS60001324B-page 94 2015-2016 Microchip Technology Inc.
NOTES:
2015-2016 Microchip Technology Inc. DS60001324B-page 95
PIC32MM0064GPL036 FAMILY
12.0 CAPTURE/COMPARE/PWM/
TIMER MODULES (MCCP AND
SCCP)
12.1 Introduction
PIC32MM0064GPL036 family devices include three
Capture/Compare/PWM/Timer (CCP) modules. These
modules are similar to the multipurpose timer modules
found on many other 32-bit microcontrollers. They also
provide the functionality of the comparable input
capture, output compare and general purpose timer
peripherals found in all earlier PIC32 devices.
CCP modules can operate in one of three major
modes:
• General Purpose Timer
• Input Capture
• Output Compare/PWM
There are two different forms of the module, distinguished
by the number of PWM outputs that the module can gen-
erate. Single Capture/Compare/PWM/Timer (SCCPs)
output modules provide only one PWM output. Multiple
Capture/Compare/PWM/Timer (MCCPs) output modules
can provide up to six outputs and an extended range of
output control features, depending on the pin count of the
particular device.
All modules (SCCP and MCCP) include these features:
• User-Selectable Clock Inputs, including System
Clock and External Clock Input Pins
• Input Clock Prescaler for Time Base
• Output Postscaler for module Interrupt Events or
Triggers
• Synchronization Output Signal for Coordinating
other MCCP/SCCP modules with
User-Configurable Alternate and Auxiliary Source
Options
• Fully Asynchronous Operation in all modes and in
Low-Power Operation
• Special Output Trigger for ADC Conversions
• 16-Bit and 32-Bit General Purpose Timer modes
with Optional Gated Operation for Simple Time
Measurements
• Capture modes:
- Backward compatible with previous input
capture peripherals of the PIC32 family
- 16-bit or 32-bit capture of time base on
external event
- Up to four-level deep FIFO capture buffer
- Capture source input multiplexer
- Gated capture operation to reduce
noise-induced false captures
• Output Compare/PWM modes:
- Backward compatible with previous output
compare peripherals of the PIC32 family
- Single Edge and Dual Edge Compare modes
- Center-Aligned Compare mode
- Variable Frequency Pulse mode
- External Input mode
MCCP modules also include these extended PWM
features:
• Single Output Steerable mode
• Brush DC Motor (Forward and Reverse) modes
• Half-Bridge with Dead-Time Delay mode
• Push-Pull PWM mode
• Output Scan mode
• Auto-Shutdown with Programmable Source and
Shutdown State
• Programmable Output Polarity
The SCCP and MCCP modules can be operated in
only one of the three major modes (Capture, Compare
or Timer) at any time. The other modes are not
available unless the module is reconfigured.
A conceptual block diagram for the module is shown in
Figure 12-1. All three modes use the time base gener-
ator and the common Timer register pair (CCPxTMR).
Other shared hardware components, such as
comparators and buffer registers, are activated and
used as a particular mode requires.
Note: This data sheet summarizes the features of
the PIC32MM0064GPL036 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 30. “Cap-
ture/Compare/PWM/Timer (MCCP and
SCCP)” (DS60001381) in the “PIC32
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32). The infor-
mation in this data sheet supersedes the
information in the FRM.
PIC32MM0064GPL036 FAMILY
DS60001324B-page 96 2015-2016 Microchip Technology Inc.
FIGURE 12-1: MCCP/SCCP CONCEPTUAL BLOCK DIAGRAM
12.2 Registers
Each MCCP/SCCP module has up to seven control
and status registers:
• CCPxCON1 (Register 12-1) controls many of the
features common to all modes, including input
clock selection, time base prescaling, timer
synchronization, Trigger mode operations and
postscaler selection for all modes. The module is
also enabled and the operational mode is
selected from this register.
• CCPxCON2 (Register 12-2) controls auto-
shutdown and restart operation, primarily for
PWM operations, and also configures other input
capture and output compare features, and
configures auxiliary output operation.
• CCPxCON3 (Register 12-3) controls multiple
output PWM dead time, controls the output of the
output compare and PWM modes, and configures
the PWM Output mode for the MCCP modules.
• CCPxSTAT (Register 12-4) contains read-only
status bits showing the state of module operations.
Each module also includes eight buffer/counter
registers that serve as Timer Value registers or data
holding buffers:
• CCPxTMR is the 32-Bit Timer/Counter register
• CCPxPR is the 32-Bit Timer Period register
• CCPxR is the 32-bit primary data buffer for output
compare operations
• CCPxBUF(H/L) registers are the 32-Bit Buffer
register pair, which are used in input capture FIFO
operations
Time Base
Generator
Clock
Sources
Input Capture
Output Compare/
PWM
T32
CCSEL
MOD<3:0>
Sync and
Gating
Sources
16/32-Bit
Auxiliary Output
CCPxIF
CCTxIF
External
Capture
Compare/PWM
Output(s)
OCFA/OCFB
Timer
CCP Sync Out
Special Event Trigger Out (ADC)
Input
CCPxTMR
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TABLE 12-1: MCCP/SCCP REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
(1)
Bit Range
Bits
All
Reset s
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
0100 CCP1CON1 31:16 OPSSRC RTRGEN —— OPS<3:0> TRIGEN ONESHOT ALTSYNC SYNC<4:0>
0000
15:0 ON — SIDL CCPSLP TMRSYNC CLKSEL<2:0> TMRPS<1:0> T32 CCSEL MOD<3:0>
0000
0110 CCP1CON2 31:16 OENSYNC — OCFEN OCEEN OCDEN OCCEN OCBEN OCAEN ICGSM<1:0> — AUXOUT<1:0> ICS<2:0>
0100
15:0 PWMRSEN ASDGM — SSDG — — — — ASDG<7:0>
0000
0120 CCP1CON3 31:16 OETRIG OSCNT<2:0> — OUTM<2:0> —— POLACE POLBDF PSSACE<1:0> PSSBDF<1:0>
0000
15:0 — — — — — — — — — — DT<5:0>
0000
0130 CCP1STAT 31:16 — — — — — — — — — — — PRLWIP TMRHWIP TMRLWIP RBWIP RAWIP
0000
15:0 — — — — —ICGARM—— CCPTRIG TRSET TRCLR ASEVT SCEVT ICDIS ICOV ICBNE
0000
0140 CCP1TMR 31:16 CCP1 TMRH<15:0>
0000
15:0 CCP1 TMRL<15:0>
0000
0150 CCP1PR 31:16 CCP1 PRH<15:0>
0000
15:0 CCP1 PRL<15:0>
0000
0160 CCP1RA 31:16 — — — — — — — — — — — — — — — —
0000
15:0 CMPA<15:0>
0000
0170 CCP1RB 31:16 — — — — — — — — — — — — — — — —
0000
15:0 CMPB<15:0>
0000
0180 CCP1BUF 31:16 CCP1 BUFH<15:0>
0000
15:0 CCP1 BUFL<15:0>
0000
0200 CCP2CON1 31:16 OPSSRC RTRGEN —— OPS<3:0> TRIGEN ONESHOT ALTSYNC SYNC<4:0>
0000
15:0 ON — SIDL CCPSLP TMRSYNC CLKSEL<2:0> TMRPS<1:0> T32 CCSEL MOD<3:0>
0000
0210 CCP2CON2 31:16 OENSYNC — — — — — — OCAEN ICGSM<1:0> — AUXOUT<1:0> ICS<2:0>
0100
15:0 PWMRSEN ASDGM — SSDG — — — — ASDG<7:0>
0000
0220 CCP2CON3 31:16 OETRIG — — — — — — — — —POLACE— PSSACE<1:0> — —
0000
15:0 — — — — — — — — — — — — — — — —
0000
0230 CCP2STAT 31:16 — — — — — — — — — — — PRLWIP TMRHWIP TMRLWIP RBWIP RAWIP
0000
15:0 — — — — —ICGARM—— CCPTRIG TRSET TRCLR ASEVT SCEVT ICDIS ICOV ICBNE
0000
0240 CCP2TMR 31:16 CCP2 TMRH<15:0>
0000
15:0 CCP2 TMRL<15:0>
0000
0250 CCP2PR 31:16 CCP2 PRH<15:0>
0000
15:0 CCP2 PRL<15:0>
0000
Legend:
— = unimplemented, read as ‘
0
’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively.
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DS60001324B-page 98 2015-2016 Microchip Technology Inc.
0260 CCP2RA 31:16 — — — — — — — — — — — — — — — —
0000
15:0 CMPA<15:0>
0000
0270 CCP2RB 31:16 — — — — — — — — — — — — — — — —
0000
15:0 CMPB<15:0>
0000
0280 CCP2BUF 31:16 CCP2 BUFH<15:0>
0000
15:0 CCP2 BUFL<15:0>
0000
0300 CCP3CON1 31:16 OPSSRC RTRGEN —— OPS<3:0> TRIGEN ONESHOT ALTSYNC SYNC<4:0>
0000
15:0 ON — SIDL CCPSLP TMRSYNC CLKSEL<2:0> TMRPS<1:0> T32 CCSEL MOD<3:0>
0000
0310 CCP3CON2 31:16 OENSYNC — — — — — — OCAEN ICGSM<1:0> — AUXOUT<1:0> ICS<2:0>
0100
15:0 PWMRSEN ASDGM — SSDG — — — — ASDG<7:0>
0000
0320 CCP3CON3 31:16 OETRIG OSCNT<2:0> — — — — — —POLACE— PSSACE<1:0> — —
0000
15:0 — — — — — — — — — — — — — — — —
0000
0330 CCP3STAT 31:16 — — — — — — — — — — — PRLWIP TMRHWIP TMRLWIP RBWIP RAWIP
0000
15:0 — — — — —ICGARM—— CCPTRIG TRSET TRCLR ASEVT SCEVT ICDIS ICOV ICBNE
0000
0340 CCP3TMR 31:16 CCP3 TMRH<15:0>
0000
15:0 CCP3 TMRL<15:0>
0000
0350 CCP3PR 31:16 CCP3 PRH<15:0>
0000
15:0 CCP3 PRL<15:0>
0000
0360 CCP3RA 31:16 — — — — — — — — — — — — — — — —
0000
15:0 CMPA<15:0>
0000
0370 CCP3RB 31:16 — — — — — — — — — — — — — — — —
0000
15:0 CMPB<15:0>
0000
0380 CCP3BUF 31:16 CCP3 BUFH<15:0>
0000
15:0 CCP3 BUFL<15:0>
0000
TABLE 12-1: MCCP/SCCP REGISTER MAP (CONTINUED)
Virtual Address
(BF80_#)
Register
Name
(1)
Bit Range
Bits
All
Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
Legend:
— = unimplemented, read as ‘
0
’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively.
2015-2016 Microchip Technology Inc. DS60001324B-page 99
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REGISTER 12-1: CCPxCON1: CAPTURE/COMPARE/PWMx CONTROL 1 REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
OPSSRC
(1)
RTRGEN
(2)
—— OPS<3:0>
(3)
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TRIGEN ONESHOT ALTSYNC SYNC<4:0>
15:8
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ON
(1)
— SIDL CCPSLP TMRSYNC CLKSEL<2:0>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TMRPS<1:0> T32 CCSEL MOD<3:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 OPSSRC: Output Postscaler Source Select bit
(1)
1 = Output postscaler scales the Special Event Trigger output events
0 = Output postscaler scales the timer interrupt events
bit 30 RTRGEN: Retrigger Enable bit
(2)
1 = Time base can be retriggered when CCPTRIG = 1
0 = Time base may not be retriggered when CCPTRIG = 1
bit 29-28 Unimplemented: Read as ‘0’
bit 27-24 OPS<3:0>: CCPx Interrupt Output Postscale Select bits
(3)
1111 = Interrupt every 16th time base period match
1110 = Interrupt every 15th time base period match
. . .
0100 = Interrupt every 5th time base period match
0011 = Interrupt every 4th time base period match or 4th input capture event
0010 = Interrupt every 3rd time base period match or 3rd input capture event
0001 = Interrupt every 2nd time base period match or 2nd input capture event
0000 = Interrupt after each time base period match or input capture event
bit 23 TRIGEN: CCPx Triggered Enable bit
1 = Triggered operation of the timer is enabled
0 = Triggered operation of the timer is disabled
bit 22 ONESHOT: One-Shot Mode Enable bit
1 = One-Shot Triggered mode is enabled; trigger duration is set by OSCNT<2:0>
0 = One-Shot Triggered mode is disabled
bit 21 ALTSYNC: CCPx Clock Select bit
1 = An alternate signal is used as the module synchronization output signal
0 = The module synchronization output signal is the Time Base Reset/rollover event
Note 1: This control bit has no function in Input Capture modes.
2: This control bit has no function when TRIGEN = 0.
3: Values greater than ‘0011’ will cause a FIFO buffer overflow in Input Capture mode.
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bit 20-16 SYNC<4:0>: CCPx Synchronization Source Select bits
11111 = Timer is in the Free-Running mode and rolls over at FFFFh (Timer Period register is ignored)
11110 = Reserved
. . .
11100 = Reserved
11011 = Time base is synchronized to the start of ADC conversion
11010 = Reserved
11001 = Time base is synchronized to Comparator 2
11000 = Time base is synchronized to Comparator 1
10111 = Reserved
. . .
10010 = Reserved
10001 = Time base is synchronized to CLC2
10001 = Time base is synchronized to CLC1
01111 = Reserved
01110 = Reserved
01101 = Time base is synchronized to the INT4 pin (remappable)
01100 = Time base is synchronized to the INT3 pin
01011 = Time base is synchronized to the INT2 pin
01010 = Time base is synchronized to the INT1 pin
01001 = Time base is synchronized to the INT0 pin
01000 = Reserved
. . .
00101 = Reserved
00100 = Time base is synchronized to SCCP3
00011 = Time base is synchronized to SCCP2
00010 = Time base is synchronized to MCCP1
00001 = Time base is synchronized to this MCCP/SCCP
00000 = No external synchronization; timer rolls over at FFFFh or matches with the Timer Period register
bit 15 ON: CCPx Module Enable bit
(1)
1 = Module is enabled with the operating mode specified by the MOD<3:0> bits
0 = Module is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: CCPx Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12 CCPSLP: CCPx Sleep Mode Enable bit
1 = Module continues to operate in Sleep modes
0 = Module does not operate in Sleep modes
bit 11 TMRSYNC: Time Base Clock Synchronization bit
1 = Module time base clock is synchronized to internal system clocks; timing restrictions apply
0 = Module time base clock is not synchronized to internal system clocks
bit 10-8 CLKSEL<2:0>: CCPx Time Base Clock Select bits
111 = TCKIA pin (remappable)
110 = TCKIB pin (remappable)
101 = Reserved
100 = Reserved
011 = CLC1 output for MCCP1 and SCCP2/CLC2 output for SCCP3
010 = Secondary Oscillator (SOSC) clock
001 = REFCLKO output clock
000 = System clock (F
SYS
)
REGISTER 12-1: CCPxCON1: CAPTURE/COMPARE/PWMx CONTROL 1 REGISTER (CONTINUED)
Note 1: This control bit has no function in Input Capture modes.
2: This control bit has no function when TRIGEN = 0.
3: Values greater than ‘0011’ will cause a FIFO buffer overflow in Input Capture mode.
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bit 7-6 TMRPS<1:0>: CCPx Time Base Prescale Select bits
11 = 1:64 prescaler
10 = 1:16 prescaler
01 = 1:4 prescaler
00 = 1:1 prescaler
bit 5 T32: 32-Bit Time Base Select bit
1 = 32-bit time base for timer, single edge output compare or input capture function
0 = 16-bit time base for timer, single edge output compare or input capture function
bit 4 CCSEL: Capture/Compare Mode Select bit
1 = Input Capture mode
0 = Output Compare/PWM or Timer mode (exact function is selected by the MOD<3:0> bits)
bit 3-0 MOD<3:0>: CCPx Mode Select bits
CCSEL = 1 (Input Capture modes):
1xxx = Reserved
011x = Reserved
0101 = Capture every 16th rising edge
0100 = Capture every 4th rising edge
0011 = Capture every rising and falling edge
0010 = Capture every falling edge
0001 = Capture every rising edge
0000 = Capture every rising and falling edge (Edge Detect mode)
CCSEL = 0 (Output Compare modes):
1111 = External Input mode: Pulse generator is disabled, source is selected by ICS<2:0>
1110 = Reserved
110x = Reserved
10xx = Reserved
0111 = Variable Frequency Pulse mode
0110 = Center-Aligned Pulse Compare mode, buffered
0101 = Dual Edge Compare mode, buffered
0100 = Dual Edge Compare mode
0011 = 16-Bit/32-Bit Single Edge mode: Toggles output on compare match
0010 = 16-Bit/32-Bit Single Edge mode: Drives output low on compare match
0001 = 16-Bit/32-Bit Single Edge mode: Drives output high on compare match
0000 = 16-Bit/32-Bit Timer mode: Output functions are disabled
REGISTER 12-1: CCPxCON1: CAPTURE/COMPARE/PWMx CONTROL 1 REGISTER (CONTINUED)
Note 1: This control bit has no function in Input Capture modes.
2: This control bit has no function when TRIGEN = 0.
3: Values greater than ‘0011’ will cause a FIFO buffer overflow in Input Capture mode.
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REGISTER 12-2: CCPxCON2: CAPTURE/COMPARE/PWMx CONTROL 2 REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1
OENSYNC —OCFEN
(1)
OCEEN
(1)
OCDEN
(1)
OCCEN
(1)
OCBEN
(1)
OCAEN
23:16
R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ICGSM<1:0> — AUXOUT<1:0> ICS<2:0>
15:8
R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0
PWMRSEN ASDGM — SSDG — — — —
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ASDG<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 OENSYNC: Output Enable Synchronization bit
1 = Update by output enable bits occurs on the next Time Base Reset or rollover
0 = Update by output enable bits occurs immediately
bit 30 Unimplemented: Read as ‘0’
bit 29-24 OC<F:A>EN: Output Enable/Steering Control bits
(1)
1 = OCx pin is controlled by the CCPx module and produces an output compare or PWM signal
0 = OCx pin is not controlled by the CCPx module; the pin is available to the port logic or another peripheral
multiplexed on the pin
bit 23-22 ICGSM<1:0>: Input Capture Gating Source Mode Control bits
11 = Reserved
10 = One-Shot mode: Falling edge from gating source disables future capture events (ICDIS = 1)
01 = One-Shot mode: Rising edge from gating source enables future capture events (ICDIS = 0)
00 = Level-Sensitive mode: A high level from gating source will enable future capture events; a low level
will disable future capture events
bit 21 Unimplemented: Read as ‘0’
bit 20-19 AUXOUT<1:0>: Auxiliary Output Signal on Event Selection bits
11 = Input capture or output compare event; no signal in Timer mode
10 = Signal output depends on module operating mode
01 = Time base rollover event (all modes)
00 = Disabled
bit 18-16 ICS<2:0>: Input Capture Source Select bits
111 = Reserved
110 = Reserved
101 = CLC2 output
100 = CLC1 output
011 = Reserved
010 = Comparator 2 output
001 = Comparator 1 output
000 = ICMx pin (remappable)
bit 15 PWMRSEN: CCPx PWM Restart Enable bit
1 = ASEVT bit clears automatically at the beginning of the next PWM period, after the shutdown input has ended
0 = ASEVT must be cleared in software to resume PWM activity on output pins
Note 1: OCFEN through OCBEN (bits<29:25>) are implemented in MCCP modules only.
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bit 14 ASDGM: CCPx Auto-Shutdown Gate Mode Enable bit
1 = Waits until the next Time Base Reset or rollover for shutdown to occur
0 = Shutdown event occurs immediately
bit 13 Unimplemented: Read as ‘0’
bit 12 SSDG: CCPx Software Shutdown/Gate Control bit
1 = Manually forces auto-shutdown, timer clock gate or input capture signal gate event (setting the ASDGM
bit still applies)
0 = Normal module operation
bit 11-8 Unimplemented: Read as ‘0’
bit 7-0 ASDG<7:0>: CCPx Auto-Shutdown/Gating Source Enable bits
1xxx xxxx = Auto-shutdown is controlled by the OCFB pin (remappable)
x1xx xxxx = Auto-shutdown is controlled by the OCFA pin (remappable)
xx1x xxxx = Auto-shutdown is controlled by CLC1 for MCCP1/SCCP2 and by CLC2 for SCCP3
xxx1 xxxx = Auto-shutdown is controlled by the SCCP2 output for MCCP1 and by MCCP1 for
SCCP2/SCCP3
xxxx 1xxx = Auto-shutdown is controlled by the SCCP3 output for MCCP1/SCCP2 and by SCCP2 for
SCCP3
xxxx x1xx = Reserved
xxxx xx1x = Auto-shutdown is controlled by Comparator 2
xxxx xxx1 = Auto-shutdown is controlled by Comparator 1
REGISTER 12-2: CCPxCON2: CAPTURE/COMPARE/PWMx CONTROL 2 REGISTER (CONTINUED)
Note 1: OCFEN through OCBEN (bits<29:25>) are implemented in MCCP modules only.
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REGISTER 12-3: CCPxCON3: CAPTURE/COMPARE/PWMx CONTROL 3 REGISTER
Bit Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
OETRIG OSCNT<2:0> —OUTM<2:0>
(1)
23:16
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— POLACE POLBDF
(1)
PSSACE<1:0> PSSBDF<1:0>
(1)
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
——DT<5:0>
(1)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 OETRIG: PWM Dead-Time Select bit
1 = For Triggered mode (TRIGEN = 1), the module does not drive enabled output pins until triggered
0 = Normal output pin operation
bit 30-28 OSCNT<2:0>: One-Shot Event Count bits
Extends the duration of a one-shot trigger event by an additional n clock cycles (n+1 total cycles).
111 = 7 timer count periods (8 cycles total)
110 = 6 timer count periods (7 cycles total)
101 = 5 timer count periods (6 cycles total)
100 = 4 timer count periods (5 cycles total)
011 = 3 timer count periods (4 cycles total)
010 = 2 timer count periods (3 cycles total)
001 = 1 timer count period (2 cycles total)
000 = Does not extend the one-shot trigger event (the event takes 1 timer count period)
bit 27 Unimplemented: Read as ‘0’
bit 26-24 OUTM<2:0>: PWMx Output Mode Control bits
(1)
111 = Reserved
110 = Output Scan mode
101 = Brush DC Output mode, forward
100 = Brush DC Output mode, reverse
011 = Reserved
010 = Half-Bridge Output mode
001 = Push-Pull Output mode
000 = Steerable Single Output mode
bit 23-22 Unimplemented: Read as ‘0’
bit 21 POLACE: CCPx Output Pins, OCxA, OCxC and OCxE, Polarity Control bit
1 = Output pin polarity is active-low
0 = Output pin polarity is active-high
bit 20 POLBDF: CCPx Output Pins, OCxB, OCxD and OCxF, Polarity Control bit
(1)
1 = Output pin polarity is active-low
0 = Output pin polarity is active-high
bit 19-18 PSSACE<1:0>: PWMx Output Pins, OCxA, OCxC and OCxE, Shutdown State Control bits
11 = Pins are driven active when a shutdown event occurs
10 = Pins are driven inactive when a shutdown event occurs
0x = Pins are in a high-impedance state when a shutdown event occurs
Note 1: These bits are implemented in MCCP modules only.
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bit 17-16 PSSBDF<1:0>: PWMx Output Pins, OCxB, OCxD and OCxF, Shutdown State Control bits
(1)
11 = Pins are driven active when a shutdown event occurs
10 = Pins are driven inactive when a shutdown event occurs
0x = Pins are in a high-impedance state when a shutdown event occurs
bit 15-6 Unimplemented: Read as ‘0’
bit 5-0 DT<5:0>: PWM Dead-Time Select bits
(1)
111111 = Insert 63 dead-time delay periods between complementary output signals
111110 = Insert 62 dead-time delay periods between complementary output signals
. . .
000010 = Insert 2 dead-time delay periods between complementary output signals
000001 = Insert 1 dead-time delay period between complementary output signals
000000 = Dead-time logic is disabled
REGISTER 12-3: CCPxCON3: CAPTURE/COMPARE/PWMx CONTROL 3 REGISTER (CONTINUED)
Note 1: These bits are implemented in MCCP modules only.
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REGISTER 12-4: CCPxSTAT: CAPTURE/COMPARE/PWMx STATUS REGISTER
Bit Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0
— — — PRLWIP TMRHWIP TMRLWIP RBWIP RAWIP
15:8
U-0 U-0 U-0 U-0 U-0 R/C-0 U-0 U-0
— — — — —ICGARM
(1)
— —
7:0
R-0 W1-0 W1-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0
CCPTRIG TRSET TRCLR ASEVT SCEVT ICDIS ICOV ICBNE
Legend: C = Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-21 Unimplemented: Read as ‘0’
bit 20 PRLWIP: CCPxPRL Write in Progress Status bit
1 = An update to the CCPxPRL register with the buffered contents is in progress
0 = An update to the CCPxPRL register is not in progress
bit 19 TMRHWIP: CCPxTMRH Write in Progress Status bit
1 = An update to the CCPxTMRH register with the buffered contents is in progress
0 = An update to the CCPxTMRH register is not in progress
bit 18 TMRLWIP: CCPxTMRL Write in Progress Status bit
1 = An update to the CCPxTMRL register with the buffered contents is in progress
0 = An update to the CCPxTMRL register is not in progress
bit 17 RBWIP: CCPxRB Write in Progress Status bit
1 = An update to the CCPxRB register with the buffered contents is in progress
0 = An update to the CCPxRB register is not in progress
bit 16 RAWIP: CCPxRA Write in Progress Status bit
1 = An update to the CCPxRA register with the buffered contents is in progress
0 = An update to the CCPxRA register is not in progress
bit 15-11 Unimplemented: Read as ‘0’
bit 10 ICGARM: Input Capture Gate Arm bit
(1)
A write of ‘1’ to this location will arm the input capture gating logic for a one-shot gate event when
ICGSM<1:0> = 01 or 10. The bit location reads as ‘0’.
bit 9-8 Unimplemented: Read as ‘0’
bit 7 CCPTRIG: CCPx Trigger Status bit
1 = Timer has been triggered and is running (set by hardware or writing to TRSET)
0 = Timer has not been triggered and is held in Reset (cleared by writing to TRCLR)
bit 6 TRSET: CCPx Trigger Set Request bit
Write ‘1’ to this location to trigger the timer when TRIGEN = 1 (location always reads ‘0’).
bit 5 TRCLR: CCPx Trigger Clear Request bit
Write ‘1’ to this location to cancel the timer trigger when TRIGEN = 1 (location always reads ‘0’).
bit 4 ASEVT: CCPx Auto-Shutdown Event Status/Control bit
1 = A shutdown event is in progress; CCPx outputs are in the shutdown state
0 = CCPx outputs operate normally
Note 1: This is not a physical bit location and will always read as ‘0’. A write of ‘1’ will initiate the hardware event.
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bit 3 SCEVT: Single Edge Compare Event Status bit
1 = A single edge compare event has occurred
0 = A single edge compare event has not occurred
bit 2 ICDIS: Input Capture Disable bit
1 = Event on input capture pin does not generate a capture event
0 = Event on input capture pin will generate a capture event
bit 1 ICOV: Input Capture Buffer Overflow Status bit
1 = The input capture FIFO buffer has overflowed
0 = The input capture FIFO buffer has not overflowed
bit 0 ICBNE: Input Capture Buffer Status bit
1 = The input capture buffer has data available
0 = The input capture buffer is empty
REGISTER 12-4: CCPxSTAT: CAPTURE/COMPARE/PWMx ST ATUS REGISTER (CONTINUED)
Note 1: This is not a physical bit location and will always read as ‘0’. A write of ‘1’ will initiate the hardware event.
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NOTES:
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13.0 SERIAL PERIPHERAL
INTERFACE (SPI ) AND
INTER-IC SOUND (I
2S)
The SPI/I
2
S module is a synchronous serial interface
that is useful for communicating with external
peripherals and other microcontroller devices, as well
as digital audio devices. These peripheral devices may
be serial EEPROMs, shift registers, display drivers,
Analog-to-Digital Converters (ADC), etc.
The SPI/I
2
S module is compatible with Motorola
®
SPI
and SIOP interfaces.
Some of the key features of the SPI module are:
• Master and Slave modes Support
• Four Different Clock Formats
• Enhanced Framed SPI Protocol Support
• User-Configurable 8-Bit, 16-Bit and 32-Bit Data Width
• Separate SPI FIFO Buffers for Receive and Transmit:
- FIFO buffers act as 4/8/16-level deep FIFOs
based on 32/16/8-bit data width
• Programmable Interrupt Event on Every 8-Bit,
16-Bit and 32-Bit Data Transfer
• Operation during Sleep and Idle modes
• Audio Codec Support:
-I
2
S protocol
FIGURE 13-1: SPI/I
2
S MODULE BLOCK DIAGRAM
Note: This data sheet summarizes the features
of the PIC32MM0064GPL036 family of
devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to Section 23. “Serial Peripheral
Interface (SPI)” (DS61106) in the “PIC32
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32). The informa-
tion in this data sheet supersedes the
information in the FRM.
Internal
Data Bus
SDIx
SDOx
SSx/FSYNC1
SCKx
SPIxSR
bit 0
Shift
Control
MSTEN
Transmit
Receive
Note: Access the SPIxTXB and SPIxRXB FIFOs via the SPIxBUF register.
FIFOs Share Address SPIxBUF
SPIxBUF
PBCLK
WriteRead
SPIxTXB FIFOSPIxRXB FIFO
REFOCLK
MCLKSEL
Edge
Select
Slave Select
Sync Control
Clock
Control
and Frame
Generator
Baud Rate
(1:1 with SYSCLK)
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13.1 SPI Control Registers
TABLE 13-1: SPI1 AND SPI2 REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
(1)
Bit Range
Bits
All Re set s
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
8080 SPI1CON 31:16 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW FRMCNT<2:0> MCLKSEL — — — — — SPIFE ENHBUF
0000
15:0 ON —SIDL DISSDO MODE32 MODE16 SMP CKE SSEN CKP MSTEN DISSDI STXISEL<1:0> SRXISEL<1:0>
0000
8090 SPI1STAT 31:16 — — — RXBUFELM<4:0> — — — TXBUFELM<4:0>
0000
15:0 — — — FRMERR SPIBUSY — — SPITUR SRMT SPIROV SPIRBE —SPITBE —SPITBF SPIRBF
0008
80A0 SPI1BUF 31:16 DATA<31:0>
0000
15:0
0000
80B0 SPI1BRG 31:16 — — — — — — — — — — — — — — — —
0000
15:0 — — — BRG<12:0>
0000
80C0 SPI1CON2 31:16 — — — — — — — — — — — — — — — —
0000
15:0 SPISGNEXT — — FRMERREN SPIROVEN SPITUREN IGNROV IGNTUR AUDEN — — — AUDMONO —AUDMOD<1:0>
0000
8100 SPI2CON 31:16 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW FRMCNT<2:0> MCLKSEL — — — — — SPIFE ENHBUF
0000
15:0 ON —SIDL DISSDO MODE32 MODE16 SMP CKE SSEN CKP MSTEN DISSDI STXISEL<1:0> SRXISEL<1:0>
0000
8110 SPI2STAT 31:16 — — — RXBUFELM<4:0> — — — TXBUFELM<4:0>
0000
15:0 — — — FRMERR SPIBUSY — — SPITUR SRMT SPIROV SPIRBE —SPITBE —SPITBF SPIRBF
0008
8120 SPI2BUF 31:16 DATA<31:0>
0000
15:0
0000
8130 SPI2BRG 31:16 — — — — — — — — — — — — — — — —
0000
15:0 — — — BRG<12:0>
0000
8140 SPI2CON2 31:16 — — — — — — — — — — — — — — — —
0000
15:0 SPISGNEXT — — FRMERREN SPIROVEN SPITUREN IGNROV IGNTUR AUDEN — — — AUDMONO —AUDMOD<1:0>
0000
Legend:
— = unimplemented, read as ‘
0
’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table, except SPIxBUF, have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively.
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REGISTER 13-1: SPIxCON: SPIx CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW FRMCNT<2:0>
23:16
R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
MCLKSEL
(1)
— — — — — SPIFE ENHBUF
(1)
15:8
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ON — SIDL DISSDO
(4)
MODE32 MODE16 SMP CKE
(2)
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SSEN CKP
(3)
MSTEN DISSDI
(4)
STXISEL<1:0> SRXISEL<1:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 FRMEN: Framed SPI Support bit
1 = Framed SPI support is enabled (SSx pin is used as the FSYNC1 input/output)
0 = Framed SPI support is disabled
bit 30 FRMSYNC: Frame Sync Pulse Direction Control on SSx Pin bit (Framed SPI mode only)
1 = Frame sync pulse input (Slave mode)
0 = Frame sync pulse output (Master mode)
bit 29 FRMPOL: Frame Sync Polarity bit (Framed SPI mode only)
1 = Frame pulse is active-high
0 = Frame pulse is active-low
bit 28 MSSEN: Master Mode Slave Select Enable bit
1 = Slave select SPI support is enabled; the SSx pin is automatically driven during transmission in Master
mode, polarity is determined by the FRMPOL bit
0 = Slave select SPI support is disabled
bit 27 FRMSYPW: Frame Sync Pulse-Width bit
1 = Frame sync pulse is one character wide
0 = Frame sync pulse is one clock wide
bit 26-24 FRMCNT<2:0>: Frame Sync Pulse Counter bits
Controls the number of data characters transmitted per pulse. This bit is only valid in Framed mode.
111 = Reserved
110 = Reserved
101 = Generates a frame sync pulse on every 32 data characters
100 = Generates a frame sync pulse on every 16 data characters
011 = Generates a frame sync pulse on every 8 data characters
010 = Generates a frame sync pulse on every 4 data characters
001 = Generates a frame sync pulse on every 2 data characters
000 = Generates a frame sync pulse on every data character
Note 1: These bits can only be written when the ON bit = 0. Refer to Sectio n 26.0 “Electr ical Characte ristics” for
maximum clock frequency requirements.
2: This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI
mode (FRMEN = 1).
3: When AUDEN = 1, the SPI/I
2
S module functions as if the CKP bit is equal to ‘1’, regardless of the actual
value of the CKP bit.
4: These bits are present for legacy compatibility and are superseded by PPS functionality on these devices
(see Section 9.8 “Peripheral Pin Select (PPS)” for more information).
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bit 23 MCLKSEL: Master Clock Enable bit
(1)
1 = REFCLKO is used by the Baud Rate Generator
0 = PBCLK is used by the Baud Rate Generator (1:1 with SYSCLK)
bit 22-18 Unimplemented: Read as ‘0’
bit 17 SPIFE: SPIx Frame Sync Pulse Edge Select bit (Framed SPI mode only)
1 = Frame synchronization pulse coincides with the first bit clock
0 = Frame synchronization pulse precedes the first bit clock
bit 16 ENHBUF: Enhanced Buffer Enable bit
(1)
1 = Enhanced Buffer mode is enabled
0 = Enhanced Buffer mode is disabled
bit 15 ON: SPIx Module On bit
1 = SPIx module is enabled
0 = SPIx module is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: SPIx Stop in Idle Mode bit
1 = Discontinues operation when CPU enters Idle mode
0 = Continues operation in Idle mode
bit 12 DISSDO: Disable SDOx Pin bit
(4)
1 = SDOx pin is not used by the module; the pin is controlled by the associated PORTx register
0 = SDOx pin is controlled by the module
bit 11-10 MODE<32,16>: 32/16/8-Bit Communication Select bits
When AUDEN = 1:
MODE32 MODE16 Communication
1124-bit data, 32-bit FIFO, 32-bit channel/64-bit frame
1032-bit data, 32-bit FIFO, 32-bit channel/64-bit frame
0116-bit data, 16-bit FIFO, 32-bit channel/64-bit frame
0016-bit data, 16-bit FIFO, 16-bit channel/32-bit frame
When AUDEN = 0:
MODE32 MODE16 Communication
1x32-bit
0116-bit
008-bit
bit 9 SMP: SPIx Data Input Sample Phase bit
Master mode (MSTEN = 1):
1 = Input data is sampled at the end of data output time
0 = Input data is sampled at the middle of data output time
Slave mode (MSTEN = 0):
SMP value is ignored when SPIx is used in Slave mode. The module always uses SMP = 0.
bit 8 CKE: SPIx Clock Edge Select bit
(2)
1 = Serial output data changes on transition from active clock state to Idle clock state (see the CKP bit)
0 = Serial output data changes on transition from Idle clock state to active clock state (see the CKP bit)
REGISTER 13-1: SPIxCON: SPIx CONTROL REGISTER (CONTINUED)
Note 1: These bits can only be written when the ON bit = 0. Refer to Sectio n 26.0 “Electr ical Characte ristics” for
maximum clock frequency requirements.
2: This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI
mode (FRMEN = 1).
3: When AUDEN = 1, the SPI/I
2
S module functions as if the CKP bit is equal to ‘1’, regardless of the actual
value of the CKP bit.
4: These bits are present for legacy compatibility and are superseded by PPS functionality on these devices
(see Section 9.8 “Peripheral Pin Select (PPS)” for more information).
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bit 7 SSEN: Slave Select Enable (Slave mode) bit
1 = SSx pin is used for Slave mode
0 = SSx pin is not used for Slave mode, pin is controlled by port function
bit 6 CKP: Clock Polarity Select bit
(3)
1 = Idle state for clock is a high level; active state is a low level
0 = Idle state for clock is a low level; active state is a high level
bit 5 MSTEN: Master Mode Enable bit
1 = Master mode
0 =Slave mode
bit 4 DISSDI: Disable SDIx bit
(4)
1 = SDIx pin is not used by the SPIx module (pin is controlled by port function)
0 = SDIx pin is controlled by the SPIx module
bit 3-2 STXISEL<1:0>: SPIx Transmit Buffer Empty Interrupt Mode bits
11 = Interrupt is generated when the buffer is not full (has one or more empty elements)
10 = Interrupt is generated when the buffer is empty by one-half or more
01 = Interrupt is generated when the buffer is completely empty
00 = Interrupt is generated when the last transfer is shifted out of SPIxSR and transmit operations are complete
bit 1-0 SRXISEL<1:0>: SPIx Receive Buffer Full Interrupt Mode bits
11 = Interrupt is generated when the buffer is full
10 = Interrupt is generated when the buffer is full by one-half or more
01 = Interrupt is generated when the buffer is not empty
00 = Interrupt is generated when the last word in the receive buffer is read (i.e., buffer is empty)
REGISTER 13-1: SPIxCON: SPIx CONTROL REGISTER (CONTINUED)
Note 1: These bits can only be written when the ON bit = 0. Refer to Sectio n 26.0 “Electr ical Characte ristics” for
maximum clock frequency requirements.
2: This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI
mode (FRMEN = 1).
3: When AUDEN = 1, the SPI/I
2
S module functions as if the CKP bit is equal to ‘1’, regardless of the actual
value of the CKP bit.
4: These bits are present for legacy compatibility and are superseded by PPS functionality on these devices
(see Section 9.8 “Peripheral Pin Select (PPS)” for more information).
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REGISTER 13-2: SPIxCON2: SPIx CONTROL REGISTER 2
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SPISGNEXT —— FRMERREN SPIROVEN SPITUREN IGNROV IGNTUR
7:0
R/W-0 U-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0
AUDEN
(1)
— — — AUDMONO
(1,2)
— AUDMOD<1:0>
(1,2)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 SPISGNEXT: SPIx Sign-Extend Read Data from the RX FIFO bit
1 = Data from RX FIFO is sign-extended
0 = Data from RX FIFO is not sign-extended
bit 14-13 Unimplemented: Read as ‘0’
bit 12 FRMERREN: Enable Interrupt Events via FRMERR bit
1 = Frame error overflow generates error events
0 = Frame error does not generate error events
bit 11 SPIROVEN: Enable Interrupt Events via SPIROV bit
1 = Receive Overflow (ROV) generates error events
0 = Receive Overflow does not generate error events
bit 10 SPITUREN: Enable Interrupt Events via SPITUR bit
1 = Transmit Underrun (TUR) generates error events
0 = Transmit Underrun does not generate error events
bit 9 IGNROV: Ignore Receive Overflow (ROV) bit (for audio data transmissions)
1 = A ROV is not a critical error; during ROV, data in the FIFO is not overwritten by receive data
0 = A ROV is a critical error which stops SPIx operation
bit 8 IGNTUR: Ignore Transmit Underrun (TUR) bit (for audio data transmissions)
1 = A TUR is not a critical error and zeros are transmitted until the SPIxTXB is not empty
0 = A TUR is a critical error which stops SPIx operation
bit 7 AUDEN: Enable Audio Codec Support bit
(1)
1 = Audio protocol is enabled
0 = Audio protocol is disabled
bit 6-4 Unimplemented: Read as ‘0’
bit 3 AUDMONO: Transmit Audio Data Format bit
(1,2)
1 = Audio data is mono (each data word is transmitted on both left and right channels)
0 = Audio data is stereo
bit 2 Unimplemented: Read as ‘0’
bit 1-0 AUDMOD<1:0>: Audio Protocol Mode bits
(1,2)
11 = PCM/DSP mode
10 = Right Justified mode
01 = Left Justified mode
00 = I
2
S mode
Note 1: These bits can only be written when the ON bit = 0.
2: These bits are only valid for AUDEN = 1.
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REGISTER 13-3: SPIxSTAT: SPIx STATUS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0
— — — RXBUFELM<4:0>
23:16
U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0
— — — TXBUFELM<4:0>
15:8
U-0 U-0 U-0 R/C-0, HS R-0 U-0 U-0 R-0
— — — FRMERR SPIBUSY —— SPITUR
7:0
R-0 R/W-0 R-0 U-0 R-1 U-0 R-0 R-0
SRMT SPIROV SPIRBE — SPITBE — SPITBF SPIRBF
Legend: C = Clearable bit HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-24 RXBUFELM<4:0>: Receive Buffer Element Count bits (valid only when ENHBUF = 1)
bit 23-21 Unimplemented: Read as ‘0’
bit 20-16 TXBUFELM<4:0>: Transmit Buffer Element Count bits (valid only when ENHBUF = 1)
bit 15-13 Unimplemented: Read as ‘0’
bit 12 FRMERR: SPIx Frame Error status bit
1 = Frame error is detected
0 = No frame error is detected
This bit is only valid when FRMEN = 1.
bit 11 SPIBUSY: SPIx Activity Status bit
1 = SPIx peripheral is currently busy with some transactions
0 = SPIx peripheral is currently Idle
bit 10-9 Unimplemented: Read as ‘0’
bit 8 SPITUR: SPIx Transmit Underrun (TUR) bit
1 = Transmit buffer has encountered an underrun condition
0 = Transmit buffer has no underrun condition
This bit is only valid in Framed Sync mode; the underrun condition must be cleared by disabling/re-enabling
the module.
bit 7 SRMT: Shift Register Empty bit (valid only when ENHBUF = 1)
1 = When the SPIx Shift register is empty
0 = When the SPIx Shift register is not empty
bit 6 SPIROV: SPIx Receive Overflow (ROV) Flag bit
1 = New data is completely received and discarded; the user software has not read the previous data in the
SPIxBUF register
0 = No overflow has occurred
This bit is set in hardware; it can only be cleared (= 0) in software.
bit 5 SPIRBE: SPIx RX FIFO Empty bit (valid only when ENHBUF = 1)
1 = RX FIFO is empty (CPU Read Pointer (CRPTR) = SPI Write Pointer (SWPTR))
0 = RX FIFO is not empty (CRPTR SWPTR)
bit 4 Unimplemented: Read as ‘0’
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bit 3 SPITBE: SPIx Transmit Buffer Empty Status bit
1 = Transmit buffer, SPIxTXB, is empty
0 = Transmit buffer, SPIxTXB, is not empty
Automatically set in hardware when SPIx transfers data from SPIxTXB to SPIxSR. Automatically cleared in
hardware when SPIxBUF is written to, loading SPIxTXB.
bit 2 Unimplemented: Read as ‘0’
bit 1 SPITBF: SPIx Transmit Buffer Full Status bit
1 = Transmit has not yet started, SPIxTXB is full
0 = Transmit buffer is not full
Standard Buffer mode:
Automatically set in hardware when the core writes to the SPIxBUF location, loading SPIxTXB. Automatically
cleared in hardware when the SPIx module transfers data from SPIxTXB to SPIxSR.
Enhanced Buffer mode:
Set when the CPU Write Pointer (CWPTR) + 1 = SPI Read Pointer (SRPTR); cleared otherwise.
bit 0 SPIRBF: SPIx Receive Buffer Full Status bit
1 = Receive buffer, SPIxRXB, is full
0 = Receive buffer, SPIxRXB, is not full
Standard Buffer mode:
Automatically set in hardware when the SPIx module transfers data from SPIxSR to SPIxRXB. Automatically
cleared in hardware when SPIxBUF is read from, reading SPIxRXB.
Enhanced Buffer mode:
Set when SWPTR + 1 = CRPTR; cleared otherwise.
REGISTER 13-3: SPIxSTAT: SPIx STATUS REGISTER (CONTINUED)
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14.0 UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
The UART module is one of the serial I/O modules
available in the PIC32MM0064GPL036 family
devices. The UART is a full-duplex, asynchronous
communication channel that communicates with
peripheral devices and personal computers through
protocols, such as RS-232, RS-485, LIN/J2602 and
IrDA
®
. The module also supports the hardware flow
control option with the UxCTS and UxRTS pins, and
also includes an IrDA encoder and decoder.
The primary features of the UART module are:
• Full-Duplex, 8-Bit or 9-Bit Data Transmission
• Even, Odd or No Parity Options (for 8-bit data)
• One or Two Stop Bits
• Hardware Auto-Baud Feature
• Hardware Flow Control Option
• Fully Integrated Baud Rate Generator (BRG) with
16-Bit Prescaler
• Baud Rates Ranging from 47.7 bps to 6.26 Mbps
at 25 MHz
• 8-Level Deep First-In-First-Out (FIFO) Transmit
Data Buffer
• 8-Level Deep FIFO Receive Data Buffer
• Parity, Framing and Buffer Overrun Error
Detection
• Support for Interrupt Only on Address Detect
(9th bit = 1)
• Separate Transmit and Receive Interrupts
• Loopback mode for Diagnostic Support
• LIN/J2602 Protocol Support
• IrDA Encoder and Decoder with 16x Baud Clock
Output for External IrDA Encoder/Decoder Support
• Supports Separate UART Baud Clock Input
• Ability to Continue to Run when a Receive
Overflow (ROV) Condition Exists
• Ability to Run and Receive Data during Sleep mode
Figure 14-1 illustrates a simplified block diagram of the
UART module.
FIGUR E 14-1 : UARTx SIMPLIFIED BLOCK DIAGRAM
Note: This data sheet summarizes the features
of the PIC32MM0064GPL036 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 21. “UART”
(DS61107) in the “ PIC32 Family Ref erence
Manual”, which is available from the
Microchip web site (www.microchip.com/
PIC32). The information in this data sheet
supersedes the information in the FRM.
Baud Rate Generator
UxRX
Hardware Flow Control
UARTx Receiver
UARTx Transmitter UxTX
UxCTS
UxRTS/BCLKx
IrDA®
PBCLK
(1:1 with SYSCLK)
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14.1 UART Control Registers
TABLE 14-1: UART1 AND UART2 REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
0600 U1MODE
(1)
31:16 — — — — — — — — SLPEN ACTIVE — — — CLKSEL<1:0> OVFDIS 0000
15:0 ON —SIDL IREN RTSMD —UEN<1:0> WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL 0000
0610 U1STA
(1)
31:16 UART1 MASK<7:0> UART1 ADDR<7:0> 0000
15:0 UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110
0620 U1TXREG 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — TX8 UART1 Transmit Register 0000
0630 U1RXREG 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — RX8 UART1 Receive Register 0000
0640 U1BRG
(1)
31:16 — — — — — — — — — — — — — — — — 0000
15:0 Baud Rate Generator Prescaler 0000
0680 U2MODE
(1)
31:16
15:0
— — — — — — — — SLPEN ACTIVE — — — CLKSEL<1:0> OVFDIS 0000
ON —SIDL IREN RTSMD —UEN<1:0> WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL 0000
0690 U2STA
(1)
31:16 UART2 MASK<7:0> UART2 ADDR<7:0> 0000
15:0 UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110
06A0 U2TXREG 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — TX8 UART2 Transmit Register 0000
06B0 U2RXREG 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — RX8 UART2 Receive Register 0000
06C0 U2BRG
(1)
31:16 — — — — — — — — — — — — — — — — 0000
15:0 Baud Rate Generator Prescaler 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: These registers have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively.
2015-2016 Microchip Technology Inc. DS60001324B-page 119
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REGISTER 14-1: UxMODE: UARTx MODE REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
SLPEN ACTIVE — — — CLKSEL<1:0> OVFDIS
15:8
R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
ON —SIDLIRENRTSMD—UEN<1:0>
(1)
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23 SLPEN: Run During Sleep Enable bit
1 = UARTx clock runs during Sleep
0 = UARTx clock is turned off during Sleep
bit 22 ACTIVE: UARTx Running Status bit
1 = UARTx is active (UxMODE register shouldn’t be updated)
0 = UARTx is not active (UxMODE register can be updated)
bit 21-19 Unimplemented: Read as ‘0’
bit 18-17 CLKSEL<1:0>: UARTx Clock Selection bits
11 = The UARTx clock is the Reference Clock Output (REFCLKO)
10 = The UARTx clock is the FRC oscillator clock
01 = The UARTx clock is the SYSCLK
00 = The UARTx clock is the PBCLK (1:1 with SYSCLK)
bit 16 OVFDIS: Run During Overflow Condition Mode bit
1 = When an Overflow Error (OERR) condition is detected, the Shift register continues to run to remain
synchronized
0 = When an Overflow Error (OERR) condition is detected, the Shift register stops accepting new data
(Legacy mode)
bit 15 ON: UARTx Enable bit
1 = UARTx is enabled; UARTx pins are controlled by UARTx, as defined by the UEN<1:0> and UTXEN
control bits
0 = UARTx is disabled; all UARTx pins are controlled by the corresponding bits in the PORTx, TRISx and
LATx registers; UARTx power consumption is minimal
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: UARTx Stop in Idle Mode bit
1 = Discontinues operation when device enters Idle mode
0 = Continues operation in Idle mode
bit 12 IREN: IrDA
®
Encoder and Decoder Enable bit
1 = IrDA is enabled
0 = IrDA is disabled
Note 1: These bits are present for legacy compatibility and are superseded by PPS functionality on these devices
(see Section 9.8 “Peripheral Pin Select (PPS)” for more information).
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DS60001324B-page 120 2015-2016 Microchip Technology Inc.
bit 11 RTSMD: Mode Selection for UxRTS Pin bit
1 = UxRTS pin is in Simplex mode
0 = UxRTS pin is in Flow Control mode
bit 10 Unimplemented: Read as ‘0’
bit 9-8 UEN<1:0>: UARTx Enable bits
(1)
11 = UxTX, UxRX and UxBCLK pins are enabled and used; UxCTS pin is controlled by corresponding bits
in the PORTx register
10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by corresponding bits
in the PORTx register
00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/UxBCLK pins are controlled by
corresponding bits in the PORTx register
bit 7 WAKE: Enable Wake-up on Start Bit Detect During Sleep Mode bit
1 = Wake-up is enabled
0 = Wake-up is disabled
bit 6 LPBACK: UARTx Loopback Mode Select bit
1 = Loopback mode is enabled
0 = Loopback mode is disabled
bit 5 ABAUD: Auto-Baud Enable bit
1 = Enables baud rate measurement on the next character – requires reception of a Sync character (0x55);
cleared by hardware upon completion
0 = Baud rate measurement is disabled or has completed
bit 4 RXINV: Receive Polarity Inversion bit
1 = UxRX Idle state is ‘0’
0 = UxRX Idle state is ‘1’
bit 3 BRGH: High Baud Rate Enable bit
1 = High-Speed mode – 4x baud clock is enabled
0 = Standard Speed mode – 16x baud clock is enabled
bit 2-1 PDSEL<1:0>: Parity and Data Selection bits
11 = 9-bit data, no parity
10 = 8-bit data, odd parity
01 = 8-bit data, even parity
00 = 8-bit data, no parity
bit 0 STSEL: Stop Selection bit
1 = 2 Stop bits
0 = 1 Stop bit
REGISTER 14-1: UxMODE: UARTx MODE REGISTER (CONTINUED)
Note 1: These bits are present for legacy compatibility and are superseded by PPS functionality on these devices
(see Section 9.8 “Peripheral Pin Select (PPS)” for more information).
2015-2016 Microchip Technology Inc. DS60001324B-page 121
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REGISTER 14-2: UxSTA: UARTx STATUS AND CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
MASK<7:0>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADDR<7:0>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-1
UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT
7:0
R/W-0 R/W-0 R/W-0 R-1 R-0 R-0 R/W-0 R-0
URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-24 MASK<7:0>: UARTx Address Match Mask bits
Used to mask the ADDR<7:0> bits.
For MASK<x>:
1 = ADDR<x> is used to detect the address match
0 = ADDR<x> is not used to detect the address match
bit 23-16 ADDR<7:0>: UARTx Automatic Address Mask bits
When the ADDEN bit is ‘1’, this value defines the address character to use for automatic address detection.
bit 15-14 UTXISEL<1:0>: UARTx TX Interrupt Mode Selection bits
11 = Reserved, do not use
10 = Interrupt is generated and asserted while the transmit buffer is empty
01 = Interrupt is generated and asserted when all characters have been transmitted
00 = Interrupt is generated and asserted while the transmit buffer contains at least one empty space
bit 13 UTXINV: UARTx Transmit Polarity Inversion bit
If IrDA mode is Disabled (i.e., IREN (UxMODE<12>) is ‘0’):
1 = UxTX Idle state is ‘0’
0 = UxTX Idle state is ‘1’
If IrDA mode is enabled (i.e., IREN (UxMODE<12>) is ‘1’):
1 =IrDA
®
encoded UxTX Idle state is ‘1’
0 = IrDA encoded UxTX Idle state is ‘0’
bit 12 URXEN: UARTx Receiver Enable bit
1 = UARTx receiver is enabled, UxRX pin is controlled by UARTx (if ON = 1)
0 = UARTx receiver is disabled, UxRX pin is ignored by the UARTx module
bit 11 UTXBRK: UARTx Transmit Break bit
1 = Sends Break on next transmission; Start bit, followed by twelve ‘0’ bits, followed by Stop bit, cleared by
hardware upon completion
0 = Break transmission is disabled or has completed
bit 10 UTXEN: UARTx Transmit Enable bit
1 = UARTx transmitter is enabled, UxTX pin is controlled by UARTx (if ON = 1)
0 = UARTx transmitter is disabled, any pending transmission is aborted and the buffer is reset
bit 9 UTXBF: UARTx Transmit Buffer Full Status bit (read-only)
1 = Transmit buffer is full
0 = Transmit buffer is not full, at least one more character can be written
bit 8 TRMT: Transmit Shift Register (TSR) is Empty bit (read-only)
1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0 = Transmit Shift Register is not empty, a transmission is in progress or queued in the transmit buffer
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DS60001324B-page 122 2015-2016 Microchip Technology Inc.
bit 7-6 URXISEL<1:0>: UARTx Receive Interrupt Mode Selection bits
11 = Reserved
10 = Interrupt flag bit is asserted while receive buffer is 3/4 or more full
01 = Interrupt flag bit is asserted while receive buffer is 1/2 or more full
00 = Interrupt flag bit is asserted while receive buffer is not empty (i.e., has at least 1 data character)
bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1 = Address Detect mode is enabled; if 9-bit mode is not selected, this control bit has no effect
0 = Address Detect mode is disabled
bit 4 RIDLE: Receiver Idle bit (read-only)
1 = Receiver is Idle
0 = Data is being received
bit 3 PERR: Parity Error Status bit (read-only)
1 = Parity error has been detected for the current character
0 = Parity error has not been detected
bit 2 FERR: Framing Error Status bit (read-only)
1 = Framing error has been detected for the current character
0 = Framing error has not been detected
bit 1 OERR: Receive Buffer Overrun Error Status bit
This bit is set in hardware and can only be cleared (= 0) in software. Clearing a previously set OERR bit
resets the receiver buffer and RSR to the empty state.
1 = Receive buffer has overflowed
0 = Receive buffer has not overflowed
bit 0 URXDA: UARTx Receive Buffer Data Available bit (read-only)
1 = Receive buffer has data, at least one more character can be read
0 = Receive buffer is empty
REGISTER 14-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
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15.0 REAL-TIME CLOCK AND
CALENDAR (RTCC)
The RTCC module is intended for applications in which
accurate time must be maintained for extended periods
of time with minimal or no CPU intervention. Low-
power optimization provides extended battery lifetime
while keeping track of time.
Key features of the RTCC module are:
• Time: Hours, Minutes and Seconds
• 24-Hour Format (military time)
• Visibility of One-Half Second Period
• Provides Calendar: Weekday, Date, Month and Year
• Alarm Intervals are Configurable for Half of a
second, One Second, 10 Seconds, One Minute,
10 Minutes, One Hour, One Day, One Week,
One Month and One Year
• Alarm Repeat with Decrementing Counter
• Alarm with Indefinite Repeat: Chime
• Year Range: 2000 to 2099
• Leap Year Correction
• BCD Format for Smaller Firmware Overhead
• Optimized for Long-Term Battery Operation
• Fractional Second Synchronization
• User Calibration of the Clock Crystal Frequency
with Auto-Adjust
• Uses External 32.768 kHz Crystal, 32 kHz Internal
Oscillator, PWRLCLK Input Pin or Peripheral Clock
• Alarm Pulse, Seconds Clock or Internal Clock
Output on RTCC Pin
FIGURE 15-1: RT CC BLOCK DIAGRAM
Note: This data sheet summarizes the features
of the PIC32MM0064GPL036 family of
devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to Section 28. “RTCC with
Timestamp” (DS60001362) in the “PIC32
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32). The informa-
tion in this data sheet supersedes the
information in the FRM.
RTCC Prescalers
RTCC Timer
Compare Registers
Repeat Counter
YEAR, MTH, DAY
WKDAY
HR, MIN, SEC
MTH, DAY
WKDAY
HR, MIN, SEC
with Masks
RTCC Interrupt Logic
Alarm
Event
32.768 kHz Input from
Secondary Oscillator (SOSC)
0.5 seconds
RTCC Interrupt
RTCTIME/ALMTIME
RTCTIME/ALMTIME
RTCC Pin
RTCOE
32 kHz Input from
Internal Oscillator (LPRC)
CLKSEL<1:0>
T
RTC
T
RTC
OUTSEL<2:0>
PWRLCLK Input Pin
Peripheral Clock
Comparator
Alarm Pulse
Seconds Pulse
(PBCLK, 1.1 with SYSCLK)
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DS60001324B-page 124 2015-2016 Microchip Technology Inc.
15.1 RTCC Control Registers
TABLE 15-1: RTCC REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
0000 RTCCON1 31:16 ALRMEN CHIME — — AMASK<3:0> ALMRPT<7:0> 0000
15:0 ON — — — WRLOCK — — — RTCOE OUTSEL<2:0> — — — — 0000
0010 RTCCON2 31:16 DIV<15:0> 0000
15:0 FDIV<4:0> — — — — — — — — — CLKSEL<1:0> 0000
0030 RTCSTAT 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — — — — ALMEVT — — SYNC ALMSYNC HALFSEC 0000
0040 RTCTIME 31:16 —HRTEN<2:0> HRONE<3:0> —MINTEN<2:0> MINONE<3:0> xxxx
15:0 SECTEN<3:0> SECONE<3:0> — — — — — — — — xx00
0050 RTCDATE 31:16 YRTEN<3:0> YRONE<3:0> — — — MTHTEN MTHONE<3:0> 0000
15:0 — — DAYTEN<1:0> DAYONE<3:0> — — — — — WDAY<2:0> 0000
0060 ALMTIME 31:16 —HRTEN<2:0> HRONE<3:0> —MINTEN<2:0> MINONE<3:0> xxxx
15:0 SECTEN<3:0> SECONE<3:0> — — — — — — — — xx00
0070 ALMDATE 31:16 — — — — — — — — — — — MTHTEN MTHONE<3:0> 0000
15:0 — — DAYTEN<1:0> DAYONE<3:0> — — — — — WDAY<2:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively.
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REGISTER 15-1: RTCCON1: RTCC CONTROL 1 REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
ALRMEN CHIME — — AMASK<3:0>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ALMRPT<7:0>
(1)
15:8
R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0
ON — — —WRLOCK
(2)
— — —
7:0
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
RTCOE OUTSEL<2:0> — — — —
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 ALRMEN: Alarm Enable bit
1 = Alarm is enabled
0 = Alarm is disabled
bit 30 CHIME: Chime Enable bit
1 = Chime is enabled; ALMRPT<7:0> bits are allowed to underflow from ‘00’ to ‘FF’
0 = Chime is disabled; ALMRPT<7:0> bits stop once they reach ‘00’
bit 29-28 Unimplemented: Read as ‘0’
bit 27-24 AMASK<3:0>: Alarm Mask Configuration bits
11xx = Reserved, do not use
101x = Reserved, do not use
1001 = Once a year (or once every 4 years when configured for February 29th)
1000 = Once a month
0111 = Once a week
0110 = Once a day
0101 = Every hour
0100 = Every 10 minutes
0011 = Every minute
0010 = Every 10 seconds
0001 = Every second
0000 = Every half second
bit 23-16 ALMRPT<7:0>: Alarm Repeat Counter Value bits
(1)
11111111 = Alarm will repeat 255 more times
11111110 = Alarm will repeat 254 more times
• • •
00000010 = Alarm will repeat 2 more times
00000001 = Alarm will repeat 1 more time
00000000 = Alarm will not repeat
bit 15 ON: RTCC Enable bit
1 = RTCC is enabled and counts from selected clock source
0 = RTCC is disabled
bit 14-12 Unimplemented: Read as ‘0’
Note 1: The counter decrements on any alarm event. The counter is prevented from rolling over from ‘00’ to ‘FF’
unless CHIME = 1.
2: To clear this bit, an unlock sequence is required. Refer to Section 23.4 “Syst em Regi ster s Write
Protection” for details.
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bit 11 WRLOCK: RTCC Registers Write Lock bit
(2)
1 = Registers associated with accurate timekeeping are locked
0 = Registers associated with accurate timekeeping may be written to by user
bit 10-8 Unimplemented: Read as ‘0’
bit 7 RTCOE: RTCC Output Enable bit
1 = RTCC clock output is enabled; signal selected by OUTSEL<2:0> is presented on the RTCC pin
0 = RTCC clock output is disabled
bit 6-4 OUTSEL<2:0>: RTCC Signal Output Selection bits
111 = Reserved
• • •
011 = Reserved
010 = RTCC input clock source
001 = Seconds clock
000 = Alarm event
bit 3-0 Unimplemented: Read as ‘0’
REGISTER 15-1: RTCCON1: RTCC CONTROL 1 REGISTER (CONTINUED)
Note 1: The counter decrements on any alarm event. The counter is prevented from rolling over from ‘00’ to ‘FF’
unless CHIME = 1.
2: To clear this bit, an unlock sequence is required. Refer to S ection 23.4 “Syst em Regi ster s Write
Protection” for details.
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REGISTER 15-2: RTCCON2: RTCC CONTROL 2 REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DIV<15:8>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DIV<7:0>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0
FDIV<4:0> — — —
7:0
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — CLKSEL<1:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 DIV<15:0>: Clock Divide bits
Sets the period of the clock divider counter; value should cause a nominal 1/2 second underflow.
bit 15-11 FDIV<4:0>: Fractional Clock Divide bits
11111 = Clock period increases by 31 RTCC input clock cycles every 16 seconds
11101 = Clock period increases by 30 RTCC input clock cycles every 16 seconds
• • •
00010 = Clock period increases by 2 RTCC input clock cycles every 16 seconds
00001 = Clock period increases by 1 RTCC input clock cycle every 16 seconds
00000 = No fractional clock division
bit 10-2 Unimplemented: Read as ‘0’
bit 1-0 CLKSEL<1:0>: Clock Select bits
11 = Peripheral clock (F
CY
)
10 = PWRLCLK input pin
01 = LPRC
00 = SOSC
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REGISTER 15-3: RTCSTAT: RTCC STATUS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
U-0 U-0 R-0, HS, HC U-0 U-0 R-0, HS, HC R-0, HS, HC R-0, HS, HC
— — ALMEVT — — SYNC ALMSYNC HALFSEC
Legend: HC = Hardware Clearable bit HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-6 Unimplemented: Read as ‘0’
bit 5 ALMEVT: Alarm Event bit
1 = An alarm event has occurred
0 = An alarm event has not occurred
bit 4-3 Unimplemented: Read as ‘0’
bit 2 SYNC: Synchronization Status bit
1 = Time registers may change during software read
0 = Time registers may be read safely
bit 1 ALMSYNC: Alarm Synchronization status bit
1 = Alarm registers (ALMTIME and ALMDATE) and RTCCON1 should not be modified; the ALRMEN and
ALMRPT<7:0> bits may change during software read
0 = Alarm registers and Alarm Control registers may be modified safely
bit 0 HALFSEC: Half Second Status bit
1 = Second half of 1-second period
0 = First half of 1-second period
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REGISTER 15-4: RTCTIME/ALMTIME: RTCC/ALARM TIME REGISTERS
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— HRTEN<2:0> HRONE<3:0>
23:16
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— MINTEN<2:0> MINONE<3:0>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SECTEN<3:0> SECONE<3:0>
7:0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 Unimplemented: Read as ‘0’
bit 30-28 HRTEN<2:0>: Binary Coded Decimal Value of Hours 10-Digit bits
Contains a value from 0 to 2.
bit 27-24 HRONE<3:0>: Binary Coded Decimal Value of Hours 1-Digit bits
Contains a value from 0 to 9.
bit 23 Unimplemented: Read as ‘0’
bit 22-20 MINTEN<2:0>: Binary Coded Decimal Value of Minutes 10-Digit bits
Contains a value from 0 to 5.
bit 19-16 MINONE<3:0>: Binary Coded Decimal Value of Minutes 1-Digit bits
Contains a value from 0 to 9.
bit 15-12 SECTEN<3:0>: Binary Coded Decimal Value of Seconds 10-Digit bits
Contains a value from 0 to 5.
bit 11-8 SECONE<3:0>: Binary Coded Decimal Value of Seconds 1-Digit bits
Contains a value from 0 to 9.
bit 7-0 Unimplemented: Read as ‘0’
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REGISTER 15-5: RTCDATE: RTCC DATE REGISTERS
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
YRTEN<3:0> YRONE<3:0>
23:16
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — MTHTEN MTHONE<3:0>
15:8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— DAYTEN<1:0> DAYONE<3:0>
7:0
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — WDAY<2:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-28 YRTEN<3:0>: Binary Coded Decimal Value of Years 10-Digit bits
bit 27-24 YRONE<3:0>: Binary Coded Decimal Value of Years 1-Digit bits
bit 23-21 Unimplemented: Read as ‘0’
bit 20 MTHTEN: Binary Coded Decimal Value of Months 10-Digit bit
Contains a value from 0 to 1.
bit 19-16 MTHONE<3:0>: Binary Coded Decimal Value of Months 1-Digit bits
Contains a value from 0 to 9.
bit 15-14 Unimplemented: Read as ‘0’
bit 13-12 DAYTEN<1:0>: Binary Coded Decimal Value of Days 10-Digit bits
Contains a value from 0 to 3.
bit 11-8 DAYONE<3:0>: Binary Coded Decimal Value of Days 1-Digit bits
Contains a value from 0 to 9.
bit 7-3 Unimplemented: Read as ‘0’
bit 2-0 WDAY<2:0>: Binary Coded Decimal Value of Weekdays Digit bits
Contains a value from 0 to 6.
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REGISTER 15-6: ALMDATE: ALARM DATE REGISTERS
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — —
23:16
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — MTHTEN MTHONE<3:0>
15:8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— DAYTEN<1:0> DAYONE<3:0>
7:0
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — WDAY<2:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-21 Unimplemented: Read as ‘0’
bit 20 MTHTEN: Binary Coded Decimal Value of Months 10-Digit bit
Contains a value from 0 to 1.
bit 19-16 MTHONE<3:0>: Binary Coded Decimal Value of Months 1-Digit bits
Contains a value from 0 to 9.
bit 15-14 Unimplemented: Read as ‘0’
bit 13-12 DAYTEN<1:0>: Binary Coded Decimal Value of Days 10-Digit bits
Contains a value from 0 to 3.
bit 11-8 DAYONE<3:0>: Binary Coded Decimal Value of Days 1-Digit bits
Contains a value from 0 to 9.
bit 7-3 Unimplemented: Read as ‘0’
bit 2-0 WDAY<2:0>: Binary Coded Decimal Value of Weekdays Digit bits
Contains a value from 0 to 6.
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NOTES:
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16.0 12-BIT ANALOG-TO-DIGITAL
CONVERTER WITH
THRESHOLD DETECT
16.1 Introduction
The 12-bit ADC Converter with Threshold Detect
includes the following features:
• Successive Approximation Register (SAR)
Conversion
• User-Selectable Resolution of 10 or 12 Bits
• Conversion Speeds of up to 200 ksps for
12-bit mode and 300 ksps for 10-bit mode
• Up to 17 Analog Inputs (internal and external)
• External Voltage Reference Input Pins
• Unipolar Differential Sample-and-Hold Amplifier
(SHA)
• Automated Threshold Scan and Compare
Operation to Pre-Evaluate Conversion Results
• Selectable Conversion Trigger Source
• Fixed-Length Configurable Conversion Result
Buffer
• Eight Options for Result Alignment and Encoding
• Configurable Interrupt Generation
• Operation during CPU Sleep and Idle modes
Figure 16-1 illustrates a block diagram of the 12-bit
ADC. The 12-bit ADC has 14 external analog inputs,
AN0 through AN13, and 3 internal analog inputs con-
nected to V
DD
, V
SS
and band gap. In addition, there are
two analog input pins for external voltage reference
connections.
The analog inputs are connected through a multiplexer
to the SHA. Unipolar differential conversions are
possible on all inputs (see Figure 16-1).
The Automatic Input Scan mode sequentially converts
multiple analog inputs. A special control register speci-
fies which inputs will be included in the scanning
sequence. The 12-bit ADC is connected to a 16-word
result buffer. The 12-bit result is converted to one of
eight output formats in either 32-bit or 16-bit word
widths.
FIGURE 16-1: ADC BLOCK DIAGRAM
Note: This data sheet summarizes the features
of the PIC32MM0064GPL036 family of
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
Section 25. “12-Bit Analog-to-Digital
Converter (ADC) with Threshold
Detect” (DS60001359) in the “PIC32
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32). The informa-
tion in this data sheet supersedes the
information in the FRM.
SHA
ADC1BUF0
ADC1BUF1
ADC1BUF2
AN13
AN0
CH0SA<4:0>
Channel
Scan
CSCNA
V
REF
+AV
DD
AV
SS
V
REF
-
VCFG<2:0>
SAR ADC
V
REFH
V
REFL
AV
DD
AV
SS
Band Gap
AVss
ADC1BUF14
ADC1BUF15
+
–
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DS60001324B-page 134 2015-2016 Microchip Technology Inc.
16.2 Control Registers
The ADC module has the following Special Function
Registers (SFRs):
•AD1CON1: ADC Control Register 1
•AD1CON2: ADC Control Register 2
•AD1CON3: ADC Control Register 3
•AD1CON5: ADC Control Register 5
The AD1CON1, AD1CON2, AD1CON3 and
AD1CON5 registers control the operation of the
ADC module.
•AD1CHS: ADC Input Select Register
The AD1CHS register selects the input pins to be
connected to the SHA.
•AD1CSS: ADC Input Scan Select Register
The AD1CSS register selects inputs to be
sequentially scanned.
•AD1CHIT: ADC Compare Hit Register
The AD1CHIT register indicates the channels
meeting specified comparison requirements.
Table 16-1 provides a summary of all ADC module
related registers, including their addresses and
formats. Corresponding registers appear after the
summary, followed by a detailed description of each
register. All unimplemented registers and/or bits within
a register read as zero.
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TABLE 16-1: ADC REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
(3)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
0700 ADC1BUF0 31:16 ADC1BUF0<31:0> 0000
15:0 0000
0710 ADC1BUF1 31:16 ADC1BUF1<31:0> 0000
15:0 0000
0720 ADC1BUF2 31:16 ADC1BUF2<31:0> 0000
15:0 0000
0730 ADC1BUF3 31:16 ADC1BUF3<31:0> 0000
15:0 0000
0740 ADC1BUF4 31:16 ADC1BUF4<31:0> 0000
15:0 0000
0750 ADC1BUF5 31:16 ADC1BUF5<31:0> 0000
15:0 0000
0760 ADC1BUF6 31:16 ADC1BUF6<31:0> 0000
15:0 0000
0770 ADC1BUF7 31:16 ADC1BUF7<31:0> 0000
15:0 0000
0780 ADC1BUF8 31:16 ADC1BUF8<31:0> 0000
15:0 0000
0790 ADC1BUF9 31:16 ADC1BUF9<31:0> 0000
15:0 0000
07A0 ADC1BUF10 31:16 ADC1BUF10<31:0> 0000
15:0 0000
07B0 ADC1BUF11 31:16 ADC1BUF11<31:0> 0000
15:0 0000
07C0 ADC1BUF12 31:16 ADC1BUF12<31:0> 0000
15:0 0000
07D0 ADC1BUF13 31:16 ADC1BUF13<31:0> 0000
15:0 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: The CSS<13:11> and CHH<13:11> bits are not implemented in 20-pin devices.
2: The CSS<13:12> and CHH<13:12> bits are not implemented in 28-pin devices.
3: All registers in this table have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively.
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07E0 ADC1BUF14 31:16 ADC1BUF14<31:0> 0000
15:0 0000
07F0 ADC1BUF15 31:16 ADC1BUF15<31:0> 0000
15:0 0000
0800 AD1CON1 31:16 — — — — — — — — — — — — — — — — 0000
15:0 ON SIDL — — FORM<2:0> SSRC<3:0> MODE12 ASAM SAMP DONE 0000
0810 AD1CON2 31:16 — — — — — — — — — — — — — — — — 0000
15:0 VCFG<2:0> OFFCAL BUFREGEN CSCNA — — BUFS —SMPI<3:0> BUFM —0000
0820 AD1CON3 31:16 — — — — — — — — — — — — — — — — 0000
15:0 ADRC EXTSAM —SAMC<4:0> ADCS<7:0> 0000
0840 AD1CHS 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — — CH0NA<2:0> CH0SA<4:0> 0000
0850 AD1CSS 31:16 —CSS<30:28> — — — — — — — — — — — — 0000
15:0 — — CSS<13:0>
(1,2)
0000
0870 AD1CON5 31:16 — — — — — — — — — — — — — — — — 0000
15:0 ASEN LPEN —BGREQ — — ASINT<1:0> — — — — WM<1:0> CM<1:0> 0000
0880 AD1CHIT 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — CHH<13:0>
(1,2)
0000
TABLE 16-1: ADC REGISTER MAP (CONTINUED)
Virtual Address
(BF80_#)
Register
Name
(3)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: The CSS<13:11> and CHH<13:11> bits are not implemented in 20-pin devices.
2: The CSS<13:12> and CHH<13:12> bits are not implemented in 28-pin devices.
3: All registers in this table have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively.
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REGISTER 16-1: AD1CON1: ADC CONTROL REGISTER 1
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0
ON —SIDL ——FORM<2:0>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0, HSC R/W-0, HSC
SSRC<3:0> MODE12 ASAM SAMP
(1)
DONE
(2)
Legend: HSC = Hardware Settable/Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ON: ADC Operating Mode bit
1 = ADC module is operating
0 = ADC is off
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: ADC Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-11 Unimplemented: Read as ‘0’
bit 10-8 FORM<2:0>: Data Output Format bits
For 12-Bit Operation (MODE12 bit = 1):
111 = Signed Fractional 32-bit (DOUT = sddd dddd dddd 0000 0000 0000 0000)
110 = Fractional 32-bit (DOUT = dddd dddd dddd 0000 0000 0000 0000 0000)
101 = Signed Integer 32-bit (DOUT = ssss ssss ssss ssss ssss sddd dddd dddd)
100 = Integer 32-bit (DOUT = 0000 0000 0000 0000 0000 dddd dddd dddd)
011 = Signed Fractional 16-bit (DOUT = 0000 0000 0000 0000 sddd dddd dddd 0000)
010 = Fractional 16-bit (DOUT = 0000 0000 0000 0000 dddd dddd dddd 0000)
001 = Signed Integer 16-bit (DOUT = 0000 0000 0000 0000 ssss sddd dddd dddd)
000 = Integer 16-bit (DOUT = 0000 0000 0000 0000 0000 dddd dddd dddd)
For 10-Bit Operation (MODE12 bit = 0):
111 = Signed Fractional 32-bit (DOUT = sddd dddd dd00 0000 0000 0000 0000)
110 = Fractional 32-bit (DOUT = dddd dddd dd00 0000 0000 0000 0000 0000)
101 = Signed Integer 32-bit (DOUT = ssss ssss ssss ssss ssss sssd dddd dddd)
100 = Integer 32-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd)
011 = Signed Fractional 16-bit (DOUT = 0000 0000 0000 0000 sddd dddd dd00 0000)
010 = Fractional 16-bit (DOUT = 0000 0000 0000 0000 dddd dddd dd00 0000)
001 = Signed Integer 16-bit (DOUT = 0000 0000 0000 0000 ssss sssd dddd dddd)
000 = Integer 16-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd)
Note 1: The SAMP bit is cleared and cannot be written if the ADC is disabled (ON bit = 0).
2: The DONE bit is not persistent in Automatic modes; it is cleared by hardware at the beginning of the
next sample.
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bit 7-4 SSRC<3:0>: Conversion Trigger Source Select bits
1111-1101 = Reserved
1100 = CLC2 module event ends sampling and starts conversion
1011 = CLC1 module event ends sampling and starts conversion
1010 = SCCP3 module event ends sampling and starts conversion
1001 = SCCP2 module event ends sampling and starts conversion
1000 = MCCP1 module event ends sampling and starts conversion
0111 = Internal counter ends sampling and starts conversion (auto-convert)
0110 = Timer1 period match ends sampling and starts conversion (can trigger during Sleep mode)
0101 = Timer1 period match ends sampling and starts conversion (will not trigger during Sleep mode)
0100-0010 = Reserved
0001 = Active transition on INT0 pin ends sampling and starts conversion
0000 = Clearing the SAMP bit ends sampling and starts conversion
bit 3 MODE12: 12-Bit Operation Mode bit
1 = 12-bit ADC operation
0 = 10-bit ADC operation
bit 2 ASAM: ADC Sample Auto-Start bit
1 = Sampling begins immediately after last conversion completes; SAMP bit is automatically set
0 = Sampling begins when SAMP bit is set
bit 1 SAMP: ADC Sample Enable bit
(1)
1 = The ADC Sample-and-Hold Amplifier (SHA) is sampling
0 = The ADC Sample-and-Hold Amplifier is holding
bit 0 DONE: ADC Conversion Status bit
(2)
1 = Analog-to-Digital conversion is done
0 = Analog-to-Digital conversion is not done or has not started
Clearing this bit will not affect any operation in progress.
REGISTER 16-1: AD1CON1: ADC CONTROL REGISTER 1 (CONTINUED)
Note 1: The SAMP bit is cleared and cannot be written if the ADC is disabled (ON bit = 0).
2: The DONE bit is not persistent in Automatic modes; it is cleared by hardware at the beginning of the
next sample.
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REGISTER 16-2: AD1CON2: ADC CONTROL REGISTER 2
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0
VCFG<2:0> OFFCAL BUFREGEN
(1)
CSCNA — —
7:0
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0
BUFS —SMPI<3:0>BUFM—
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-13 VCFG<2:0>: Voltage Reference Configuration bits
ADC V
R
+ ADC V
R
-
000 AV
DD
AV
SS
001 AV
DD
External V
REF
- Pin
010 External V
REF
+ Pin AV
SS
011 External V
REF
+ Pin External V
REF
- Pin
1xx Unimplemented; do not use
bit 12 OFFCAL: Input Offset Calibration Mode Select bit
1 = Enables Offset Calibration mode: The inputs of the SHA are connected to the negative reference
0 = Disables Offset Calibration mode: The inputs to the SHA are controlled by AD1CHS or AD1CSS
bit 11 BUFREGEN: ADC Buffer Register Enable bit
(1)
1 = Conversion result is loaded into the buffer location determined by the converted channel
0 = ADC result buffer is treated as a FIFO
bit 10 CSCNA: Scan Mode bit
1 = Scans inputs
0 = Does not scan inputs
bit 9-8 Unimplemented: Read as ‘0’
bit 7 BUFS: Buffer Fill Status bit
Only valid when BUFM = 1 (ADC buffers split into 2 x 8-word buffers).
1 = ADC is currently filling Buffers 8-15, user should access data in 0-7
0 = ADC is currently filling Buffers 0-7, user should access data in 8-15
bit 6 Unimplemented: Read as ‘0’
bit 5-2 SMPI<3:0>: Sample/Convert Sequences per Interrupt Selection bits
1111 = Interrupts at the completion of conversion for each 16
th
sample/convert sequence
1110 = Interrupts at the completion of conversion for each 15
th
sample/convert sequence
•
•
•
0001 = Interrupts at the completion of conversion for each 2
nd
sample/convert sequence
0000 = Interrupts at the completion of conversion for each sample/convert sequence
bit 1 BUFM: ADC Result Buffer Mode Select bit
1 = Buffer configured as two 8-word buffers, ADC1BUF(0...7), ADC1BUF(8...15)
0 = Buffer configured as one 16-word buffer, ADC1BUF(0...15)
bit 0 Unimplemented: Read as ‘0’
Note 1: This bit only takes effect when the auto-scan feature is enabled (ASEN (AD1CON5<15>) = 1.
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DS60001324B-page 140 2015-2016 Microchip Technology Inc.
REGISTER 16-3: AD1CON3: ADC CONTROL REGISTER 3
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADRC EXTSAM — SAMC<4:0>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADCS<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ADRC: ADC Conversion Clock Source (T
SRC
) bit
1 = Clock derived from Fast RC (FRC) oscillator
0 = Clock derived from Peripheral Bus Clock (PBCLK, 1:1 with SYSCLK)
bit 14 EXTSAM: Extended Sampling Time bit
1 = ADC is still sampling after SAMP bit = 0
0 = ADC stops sampling when SAMP bit = 0
bit 13 Unimplemented: Read as ‘0’
bit 12-8 SAMC<4:0>: Auto-Sample Time bits
11111 = 31 T
AD
•
•
•
00001 = 1 T
AD
00000 = 0 T
AD
(Not allowed)
bit 7-0 ADCS<7:0>: ADC Conversion Clock Select bits
11111111 = 2 • T
SRC
• ADCS<7:0> = 510 • T
SRC
= T
AD
•
•
•
00000001 = 2 • T
SRC
• ADCS<7:0> = 2 • T
SRC
= T
AD
00000000 = 1 • T
SRC
= T
AD
Where T
SRC
is a period of clock selected by the ADRC bit (AD1CON3<15>).
2015-2016 Microchip Technology Inc. DS60001324B-page 141
PIC32MM0064GPL036 FAMILY
REGISTER 16-4: AD1CON5: ADC CONTROL REGISTER 5
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0
ASEN
(1)
LPEN —BGREQ—— ASINT<1:0>
(2)
7:0
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — WM<1:0> CM<1:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ASEN: Auto-Scan Enable bit
(1)
1 = Auto-scan is enabled
0 = Auto-scan is disabled
bit 14 LPEN: Low-Power Enable bit
1 = Low power is enabled after scan
0 = Full power is enabled after scan
bit 13 Unimplemented: Read as ‘0’
bit 12 BGREQ: Band Gap Request bit
1 = Band gap is enabled when the ADC is enabled and active
0 = Band gap is not enabled by the ADC
bit 11-10 Unimplemented: Read as ‘0’
bit 9-8 ASINT<1:0>: Auto-Scan (Threshold Detect) Interrupt Mode bits
(2)
11 = Interrupt after Threshold Detect sequence has completed and a valid compare has occurred
10 = Interrupt after valid compare has occurred
01 = Interrupt after Threshold Detect sequence has completed
00 = No interrupt
bit 7-4 Unimplemented: Read as ‘0’
bit 3-2 WM<1:0>: Write Mode bits
11 = Reserved
10 = Auto-compare only (conversion results are not saved, but interrupts are generated when a valid match
occurs, as defined by the CM<1:0> and ASINT<1:0> bits)
01 = Convert and save (conversion results saved to ADC1BUFx registers when a match occurs, as defined
by the CM<1:0> bits)
00 = Threshold (Comparison) mode is disabled, legacy operation (conversion data saved to ADC1BUFx
registers)
Note 1: When auto-scan is enabled (ASEN (AD1CON5<15>) = 1), the CSCNA (AD1CON2<10>) and SMPI<3:0>
(AD1CON2<5:2>) bits are ignored.
2: The ASINT<1:0> bits setting only takes effect when ASEN (AD1CON5<15>) = 1. Interrupt generation is
governed by the SMPI<3:0> bits field.
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DS60001324B-page 142 2015-2016 Microchip Technology Inc.
bit 1-0 CM<1:0>: Compare Mode bits
11 = Outside Window mode (valid match occurs if the conversion result is outside of the window defined
by the corresponding buffer pair)
10 = Inside Window mode (valid match occurs if the conversion result is inside the window defined by the
corresponding buffer pair)
01 = Greater Than mode (valid match occurs if the result is greater than the value in the corresponding
buffer register)
00 = Less Than mode (valid match occurs if the result is less than the value in the corresponding buffer
register)
REGISTER 16-4: AD1CON5: ADC CONTROL REGISTER 5 (CONTINUED)
Note 1: When auto-scan is enabled (ASEN (AD1CON5<15>) = 1), the CSCNA (AD1CON2<10>) and SMPI<3:0>
(AD1CON2<5:2>) bits are ignored.
2: The ASINT<1:0> bits setting only takes effect when ASEN (AD1CON5<15>) = 1. Interrupt generation is
governed by the SMPI<3:0> bits field.
2015-2016 Microchip Technology Inc. DS60001324B-page 143
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REGISTER 16-5: AD1CHS: ADC INPUT SELECT REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH0NA<2:0> CH0SA<4:0>
(1)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7-5 CH0NA<2:0>: Negative Input Select bits
111-001 = Reserved
000 = Negative input is AV
SS
bit 4-0 CH0SA<4:0>: Positive Input Select bits
(1)
11111 = Reserved
11110 = Positive input is AV
DD
11101 = Positive input is AV
SS
11100 = Positive input is Band Gap Reference (V
BG
)
11011-01110 = Reserved
01101 = Positive input is AN13
(2,3)
01100 = Positive input is AN12
(2,3)
01011 = Positive input is AN11
(2)
01010 = Positive input is AN10
01001 = Positive input is AN9
01000 = Positive input is AN8
00111 = Positive input is AN7
00110 = Positive input is AN6
00101 = Positive input is AN5
00100 = Positive input is AN4
00011 = Positive input is AN3
00010 = Positive input is AN2
00001 = Positive input is AN1
00000 = Positive input is AN0
Note 1: The CH0SA<4:0> positive input selection is only used when CSCNA (AD1CON2<10>) = 0 and
ASEN (AD1CON5<15>) = 0. The AD1CSS bits specify the positive inputs when CSCNA = 1 or ASEN = 1.
2: This option is not implemented in the 20-pin devices.
3: This option is not implemented in the 28-pin devices.
PIC32MM0064GPL036 FAMILY
DS60001324B-page 144 2015-2016 Microchip Technology Inc.
)
REGISTER 16-6: AD1CSS: ADC INPUT SCAN SELECT REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
— CSS<30:28> — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— CSS<13:8>
(1,2)
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CSS<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 Unimplemented: Read as ‘0’
bit 30-28 CSS<30:28>: ADC Input Pin Scan Selection bits
1 = Selects ANx for the input scan
0 = Skips ANx for the input scan
bit 27-14 Unimplemented: Read as ‘0’
bit 13-0 CSS<13:0>: ADC Input Pin Scan Selection bits
(1,2)
1 = Selects ANx for the input scan
0 = Skips ANx for the input scan
Note 1: The CSS<13:11> bits are not implemented in 20-pin devices.
2: The CSS<13:12> bits are not implemented in 28-pin devices.
2015-2016 Microchip Technology Inc. DS60001324B-page 145
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REGISTER 16-7: AD1CHIT: ADC COMPARE HIT REGISTER
Bit Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— CHH<13:8>
(1,2)
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CHH<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-14 Unimplemented: Read as ‘0’
bit 13-0 CHH<13:0>: ADC Compare Hit bits
(1,2)
If CM<1:0> = 11:
1 = ADC Result Buffer x has been written with data or a match has occurred
0 = ADC Result Buffer x has not been written with data
For All Other Values of CM<1:0>:
1 = A match has occurred on ADC Result Channel n
0 = No match has occurred on ADC Result Channel n
Note 1: The CHH<13:11> bits are not implemented in 20-pin devices.
2: The CHH<13:12> bits are not implemented in 28-pin devices.
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DS60001324B-page 146 2015-2016 Microchip Technology Inc.
NOTES:
2015-2016 Microchip Technology Inc. DS60001324B-page 147
PIC32MM0064GPL036 FAMILY
17.0 32-BIT PROGRAMMABLE
CYCLIC REDUNDANCY CHECK
(CRC) GENERATOR
The 32-bit programmable CRC generator provides a
hardware implemented method of quickly generating
checksums for various networking and security
applications. It offers the following features:
• User-Programmable CRC Polynomial Equation,
up to 32 Bits
• Programmable Shift Direction (little or big-endian)
• Independent Data and Polynomial Lengths
• Configurable Interrupt Output
• Data FIFO
Figure 17-1 displays a simplified block diagram of the
CRC generator.
FIGURE 17-1: CRC BLOCK DIAGRAM
Note: This data sheet summarizes the features
of the PIC32MM0064GPL036 family of
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
Section 60. “32-Bit Programmable Cyclic
Redundancy Check” (DS60001336) in the
“PIC32 Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32). The informa-
tion in this data sheet supersedes the
information in the FRM.
CRC
Interrupt
Variable FIFO
(4x32, 8x16 or 16x8)
CRCDAT
CRC Shift Engine
CRCWDAT
Shifter Clock
PBCLK
LENDIAN
CRCISEL
1
0
FIFO Empty
Event
Shift
Complete
Event
1
0
Shift Buffer
(1:1 with SYSCLK)
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DS60001324B-page 148 2015-2016 Microchip Technology Inc.
TABLE 17-1: CRC REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
0A00 CRCCON 31:16 — — — DWIDTH<4:0> — — — PLEN<4:0> 0000
15:0 ON —SIDL VWORD<4:0> CRCFUL CRCMPT CRCISEL CRCGO LENDIAN MOD — — 0000
0A10 CRCXOR 31:16 X<31:16> 0000
15:0 X<15:1> —0000
0A20 CRCDAT 31:16 CRCDAT<31:0> 0000
15:0 0000
0A30 CRCWDAT 31:16 CRCWDAT<31:0> 0000
15:0 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively.
2015-2016 Microchip Technology Inc. DS60001324B-page 149
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REGISTER 17-1: CRCCON: CRC CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — DWIDTH<4:0>
23:16
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — PLEN<4:0>
15:8
R/W-0 U-0 R/W-0 R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC
ON — SIDL VWORD<4:0>
7:0
R-0, HS, HC R-1, HS, HC R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0
CRCFUL CRCMPT CRCISEL CRCGO LENDIAN MOD — —
Legend: HC = Hardware Clearable bit HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-24 DWIDTH<4:0>: Data Word Width Configuration bits
Configures the width of the data word (Data Word Width – 1).
bit 23-21 Unimplemented: Read as ‘0’
bit 20-16 PLEN<4:0>: Polynomial Length Configuration bits
Configures the length of the polynomial (Polynomial Length – 1).
bit 15 ON: CRC Enable bit
1 = Enables module
0 = Disables module
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: CRC Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-8 VWORD<4:0>: Counter Value bits
Indicates the number of valid words in the FIFO. Has a maximum value of 16 when DWIDTH<4:0> < (data words,
8-bit wide or less). Has a maximum value of 8 when DWIDTH<4:0> < 15 (data words from 9 to 16-bit wide). Has
a maximum value of 4 when DWIDTH<4:0> < 31 (data words from 17 to 32-bit wide).
bit 7 CRCFUL: CRC FIFO Full bit
1 = FIFO is full
0 = FIFO is not full
bit 6 CRCMPT: CRC FIFO Empty bit
1 = FIFO is empty
0 = FIFO is not empty
bit 5 CRCISEL: CRC Interrupt Selection bit
1 = Interrupt on FIFO is empty; final word of data is still shifted through CRC
0 = Interrupt on shift is complete (FIFO is empty and no data is shifted from the shift buffer)
bit 4 CRCGO: Start CRC bit
1 = Starts CRC serial shifter; clearing the bit aborts shifting
0 = CRC serial shifter is turned off
bit 3 LENDIAN: Data Word Little-Endian Configuration bit
1 = Data word is shifted into the CRC, starting with the LSb (little-endian); reflected input data
0 = Data word is shifted into the CRC, starting with the MSb (big-endian); non-reflected input data
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DS60001324B-page 150 2015-2016 Microchip Technology Inc.
bit 2 MOD: CRC Calculation Mode bit
1 = Alternate mode
0 = Legacy mode
bit 1-0 Unimplemented: Read as ‘0’
REGISTER 17-1: CRCCON: CRC CONTROL REGISTER (CONTINUED)
REGISTER 17-2: CRCXOR:CRC XOR REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
X<31:24>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
X<23:16>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
X<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0
X<7:1> —
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-1 X<31:1>: XOR of Polynomial Term X
n
Enable bits
bit 0 Unimplemented: Read as ‘0’
2015-2016 Microchip Technology Inc. DS60001324B-page 151
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18.0 CONFIGURABLE LOGIC CELL
(CLC)
The Configurable Logic Cell (CLC) module allows the
user to specify combinations of signals as inputs to a
logic function and to use the logic output to control
other peripherals or I/O pins. This provides greater flex-
ibility and potential in embedded designs since the CLC
module can operate outside the limitations of software
execution, and supports a vast amount of output
designs.
There are four input gates to the selected logic func-
tion. These four input gates select from a pool of up to
32 signals that are selected using four data source
selection multiplexers. Figure 18-1 shows an overview
of the module. Figure 18-3 shows the details of the data
source multiplexers and logic input gate connections.
FIGURE 18-1: CLCx MODULE
Note: This data sheet summarizes the features of
the PIC32MM0064GPL036 family of
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
Section 36. “Configurable Logic Cell”
(DS60001363) in the “PIC32 Family Refer -
ence Manual”, which is available from the
Microchip web site (www.microchip.com/
PIC32). The information in this data sheet
supersedes the information in the FRM.
Gate 1
Gate 2
Gate 3
Gate 4
Interrupt
det
Logic
Function
Input Data Selection Gates
CLCx
LCOE
Logic
LCPOL
MODE<2:0>
CLCx
CLCIN[0]
CLCIN[1]
CLCIN[2]
CLCIN[3]
CLCIN[4]
CLCIN[5]
CLCIN[6]
CLCIN[7]
CLCIN[8]
CLCIN[9]
CLCIN[10]
CLCIN[11]
CLCIN[12]
CLCIN[13]
CLCIN[14]
CLCIN[15]
Interrupt
det
INTP
INTN
ON
CLCxIF
Sets
Flag
Note: All register bits shown in this figure can be found in the CLCxCON register.
Output
Output
CLCIN[16]
CLCIN[17]
CLCIN[18]
CLCIN[19]
CLCIN[20]
CLCIN[21]
CLCIN[22]
CLCIN[23]
CLCIN[24]
CLCIN[25]
CLCIN[26]
CLCIN[27]
CLCIN[28]
CLCIN[29]
CLCIN[30]
CLCIN[31]
See Figure 18-2
See Figure 18-3
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DS60001324B-page 152 2015-2016 Microchip Technology Inc.
FIGURE 18-2: CLCx LOGIC FUNCTION COMBINATORIAL OPTIONS
Gate 1
Gate 2
Gate 3
Gate 4
Logic Output
Gate 1
Gate 2
Gate 3
Gate 4
Logic Output
Gate 1
Gate 2
Gate 3
Gate 4
Logic Output
S
R
Q
Gate 1
Gate 2
Gate 3
Gate 4
Logic Output
DQ
Gate 1
Gate 2
Gate 3
Gate 4
Logic Output
S
R
JQ
Gate 2
Gate 3
Gate 4
Logic Output
R
Gate 1
K
DQ
Gate 1
Gate 2
Gate 3
Gate 4
Logic Output
S
R
DQ
Gate 1
Gate 3
Logic Output
R
Gate 4
Gate 2
MODE<2:0> = 000
MODE<2:0> = 010
MODE<2:0> = 001
MODE<2:0> = 011
MODE<2:0> = 100
MODE<2:0> = 110
MODE<2:0> = 101
MODE<2:0> = 111
LE
AND – OR OR – XOR
4-Input AND S-R Latch
1-Input D Flip-Flop with S and R 2-I nput D Flip-Flop wi th R
1-Input Transparent Latch with S and R
J-K Flip-Flop with R
2015-2016 Microchip Technology Inc. DS60001324B-page 153
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FIGURE 18-3: CLCx INPUT SOURCE SELECTION DIAGRAM
Gate 1
G1POL
Data Gate 1
G1D1T
Gate 2
Gate 3
Gate 4
Data Gate 2
Data Gate 3
Data Gate 4
G1D1N
DS1x (CLCxSEL<2:0>)
DS2x (CLCxSEL<6:4>)
CLCIN[0]
CLCIN[1]
CLCIN[2]
CLCIN[5]
CLCIN[6]
CLCIN[7]
Dat a Sele ction
Data 1 Non-Inverted
Data 1
Data 2 Non-Inverted
Data 2
Data 3 Non-Inverted
Data 3
Data 4 Non-Inverted
Data 4
(Same as Data Gate 1)
(Same as Data Gate 1)
(Same as Data Gate 1)
G1D2T
G1D2N
G1D3T
G1D3N
G1D4T
G1D4N
Inverted
Inverted
Inverted
Inverted
CLCIN[8]
CLCIN[9]
CLCIN[10]
CLCIN[13]
CLCIN[14]
CLCIN[15]
CLCIN[3]
CLCIN[4]
CLCIN[11]
CLCIN[12]
CLCIN[18]
CLCIN[21]
CLCIN[22]
CLCIN[23]
CLCIN[19]
CLCIN[20]
CLCIN[17]
CLCIN[16]
DS3x (CLCxSEL<10:8>)
CLCIN[26]
CLCIN[29]
CLCIN[30]
CLCIN[31]
CLCIN[27]
CLCIN[28]
CLCIN[25]
CLCIN[24]
DS4x (CLCxSEL<14:12>)
000
111
000
111
000
111
000
111
(CLCxCON<16>)
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DS60001324B-page 154 2015-2016 Microchip Technology Inc.
18.1 Control Registers
The CLCx module is controlled by the following registers:
•CLCxCON
• CLCxSEL
•CLCxGLS
The CLCx Control register (CLCxCON) is used to
enable the module and interrupts, control the output
enable bit, select output polarity and select the logic
function. The CLCx Control registers also allow the user
to control the logic polarity of not only the cell output, but
also some intermediate variables.
The CLCx Input MUX Select register (CLCxSEL)
allows the user to select up to 4 data input sources
using the 4 data input selection multiplexers. Each
multiplexer has a list of 8 data sources available.
The CLCx Gate Logic Input Select register (CLCxGLS)
allows the user to select which outputs from each of the
selection MUXes are used as inputs to the input gates
of the logic cell. Each data source MUX outputs both a
true and a negated version of its output. All of these
8 signals are enabled, ORed together by the logic cell
input gates.
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TABLE 18-1: CLC1 AND CLC2 REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
0A80 CLC1CON 32:16 — — — — — — — — — — — — G4POL G3POL G2POL G1POL 0000
15:0 ON — — — INTP INTN — — LCOE LCOUT LCPOL — — MODE<2:0> 0000
0A90 CLC1SEL 32:16 — — — — — — — — — — — — — — — — 0000
15:0 —DS4<2:0> —DS3<2:0> —DS2<2:0> —DS1<2:0> 0000
0AA0 CLC1GLS 32:16 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N 0000
15:0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N 0000
0B00 CLC2CON 32:16 — — — — — — — — — — — — G4POL G3POL G2POL G1POL 0000
15:0 ON — — — INTP INTN — — LCOE LCOUT LCPOL — — MODE<2:0> 0000
0B10 CLC2SEL 32:16 — — — — — — — — — — — — — — — — 0000
15:0 —DS4<2:0> —DS3<2:0> —DS2<2:0> —DS1<2:0> 0000
0B20 CLC2GLS 32:16 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N 0000
15:0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively.
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REGISTER 18-1: CLCxCON: CLCx CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — G4POL G3POL G2POL G1POL
15:8
R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0
ON — — —INTP
(1)
INTN
(1)
— —
7:0
R/W-0 R-0, HS, HC R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0
LCOE LCOUT LCPOL —— MODE<2:0>
Legend: HC = Hardware Clearable bit HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-20 Unimplemented: Read as ‘0’
bit 19 G4POL: Gate 4 Polarity Control bit
1 = The output of Channel 4 logic is inverted when applied to the logic cell
0 = The output of Channel 4 logic is not inverted
bit 18 G3POL: Gate 3 Polarity Control bit
1 = The output of Channel 3 logic is inverted when applied to the logic cell
0 = The output of Channel 3 logic is not inverted
bit 17 G2POL: Gate 2 Polarity Control bit
1 = The output of Channel 2 logic is inverted when applied to the logic cell
0 = The output of Channel 2 logic is not inverted
bit 16 G1POL: Gate 1 Polarity Control bit
1 = The output of Channel 1 logic is inverted when applied to the logic cell
0 = The output of Channel 1 logic is not inverted
bit 15 ON: CLCx Enable bit
1 = CLCx is enabled and mixing input signals
0 = CLCx is disabled and has logic zero outputs
bit 14-12 Unimplemented: Read as ‘0’
bit 11 INTP: CLCx Positive Edge Interrupt Enable bit
(1)
1 = Interrupt will be generated when a rising edge occurs on LCOUT
0 = Interrupt will not be generated
bit 10 INTN: CLCx Negative Edge Interrupt Enable bit
(1)
1 = Interrupt will be generated when a falling edge occurs on LCOUT
0 = Interrupt will not be generated
bit 9-8 Unimplemented: Read as ‘0’
bit 7 LCOE: CLCx Port Enable bit
1 = CLCx port pin output is enabled
0 = CLCx port pin output is disabled
bit 6 LCOUT: CLCx Data Output Status bit
1 = CLCx output high
0 = CLCx output low
Note 1: The INTP and INTN bits should not be set at the same time for proper interrupt functionality.
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bit 5 LCPOL: CLCx Output Polarity Control bit
1 = The output of the module is inverted
0 = The output of the module is not inverted
bit 4-3 Unimplemented: Read as ‘0’
bit 2-0 MODE<2:0>: CLCx Mode bits
111 = Cell is a 1-input transparent latch with S and R
110 = Cell is a JK flip-flop with R
101 = Cell is a 2-input D flip-flop with R
100 = Cell is a 1-input D flip-flop with S and R
011 = Cell is an SR latch
010 = Cell is a 4-input AND
001 = Cell is an OR-XOR
000 = Cell is a AND-OR
REGISTER 18-1: CLCxCON: CLCx CONTROL REGISTER (CONTINUED)
Note 1: The INTP and INTN bits should not be set at the same time for proper interrupt functionality.
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REGISTER 18-2: CLCxSEL: CLCx INPUT MUX SELECT REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
—DS4<2:0>— DS3<2:0>
7:0
U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
—DS2<2:0>— DS1<2:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-15 Unimplemented: Read as ‘0’
bit 14-12 DS4<2:0>: Data Selection MUX 4 Signal Selection bits
For CLC1:
111 = SCCP3 compare match event
110 = MCCP1 compare match event
101 = RTCC event
100 = Reserved
011 = SPI1 SDI input
010 = SCCP3 OCM3 output
001 = CLC2 output
000 = CLCINB I/O pin
For CLC2:
111 = SCCP3 compare match event
110 = MCCP1 compare match event
101 = RTCC event
100 = Reserved
011 = SPI2 SDI input
010 = SCCP3 OCM3 output
001 = CLC1 output
000 = CLCINB I/O pin
bit 11 Unimplemented: Read as ‘0’
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bit 10-8 DS3<2:0>: Data Selection MUX 3 Signal Selection bits
For CLC1:
111 = SCCP3 compare match event
110 = SCCP2 compare match event
101 = SCCP2 OCM2 output
100 = UART1 RX input
011 = SPI1 SDO output
010 = Comparator 2 output
001 = CLC1 output
000 = CLCINA I/O pin
For CLC2:
111 = SCCP3 compare match event
110 = SCCP2 compare match event
101 = SCCP2 OCM2 output
100 = UART2 RX input
011 = SPI2 SDO output
010 = Comparator 2 output
001 = CLC2 output
000 = CLCINA I/O pin
bit 7 Unimplemented: Read as ‘0’
bit 6-4 DS2<2:0>: Data Selection MUX 2 Signal Selection bits
For CLC1:
111 = Reserved
110 = MCCP1 compare match event
101 = Reserved
100 = ADC End-of-Conversion (EOC) event
011 = UART1 TX output
010 = Comparator 1 output
001 = CLC2 output
000 = CLCINB I/O pin
For CLC2:
111 = Reserved
110 = MCCP1 compare match event
101 = Reserved
100 = ADC End-of-Conversion event
011 = UART2 TX output
010 = Comparator 1 output
001 = CLC1 output
000 = CLCINB I/O pin
bit 3 Unimplemented: Read as ‘0’
bit 2-0 DS1<2:0>: Data Selection MUX 1 Signal Selection bits
111 = MCCP1 OCM1C output
110 = MCCP1 OCM1B output
101 = MCCP1 OCM1A output
100 = REFCLKO output
011 = LPRC clock source
010 = SOSC clock source
001 = System clock (F
SYS
)
000 = CLCINA I/O pin
REGISTER 18-2: CLCxSEL: CLCx INPUT MUX SELECT REGISTER (CONTINUED)
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REGISTER 18-3: CLCxGLS: CLCx GATE LOGIC INPUT SELECT REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 G4D4T: Gate 4 Data Source 4 True Enable bit
1 = The Data Source 4 signal is enabled for Gate 4
0 = The Data Source 4 signal is disabled for Gate 4
bit 30 G4D4N: Gate 4 Data Source 4 Negated Enable bit
1 = The Data Source 4 inverted signal is enabled for Gate 4
0 = The Data Source 4 inverted signal is disabled for Gate 4
bit 29 G4D3T: Gate 4 Data Source 3 True Enable bit
1 = The Data Source 3 signal is enabled for Gate 4
0 = The Data Source 3 signal is disabled for Gate 4
bit 28 G4D3N: Gate 4 Data Source 3 Negated Enable bit
1 = The Data Source 3 inverted signal is enabled for Gate 4
0 = The Data Source 3 inverted signal is disabled for Gate 4
bit 27 G4D2T: Gate 4 Data Source 2 True Enable bit
1 = The Data Source 2 signal is enabled for Gate 4
0 = The Data Source 2 signal is disabled for Gate 4
bit 26 G4D2N: Gate 4 Data Source 2 Negated Enable bit
1 = The Data Source 2 inverted signal is enabled for Gate 4
0 = The Data Source 2 inverted signal is disabled for Gate 4
bit 25 G4D1T: Gate 4 Data Source 1 True Enable bit
1 = The Data Source 1 signal is enabled for Gate 4
0 = The Data Source 1 signal is disabled for Gate 4
bit 24 G4D1N: Gate 4 Data Source 1 Negated Enable bit
1 = The Data Source 1 inverted signal is enabled for Gate 4
0 = The Data Source 1 inverted signal is disabled for Gate 4
bit 23 G3D4T: Gate 3 Data Source 4 True Enable bit
1 = The Data Source 4 signal is enabled for Gate 3
0 = The Data Source 4 signal is disabled for Gate 3
bit 22 G3D4N: Gate 3 Data Source 4 Negated Enable bit
1 = The Data Source 4 inverted signal is enabled for Gate 3
0 = The Data Source 4 inverted signal is disabled for Gate 3
bit 21 G3D3T: Gate 3 Data Source 3 True Enable bit
1 = The Data Source 3 signal is enabled for Gate 3
0 = The Data Source 3 signal is disabled for Gate 3
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bit 20 G3D3N: Gate 3 Data Source 3 Negated Enable bit
1 = The Data Source 3 inverted signal is enabled for Gate 3
0 = The Data Source 3 inverted signal is disabled for Gate 3
bit 19 G3D2T: Gate 3 Data Source 2 True Enable bit
1 = The Data Source 2 signal is enabled for Gate 3
0 = The Data Source 2 signal is disabled for Gate 3
bit 18 G3D2N: Gate 3 Data Source 2 Negated Enable bit
1 = The Data Source 2 inverted signal is enabled for Gate 3
0 = The Data Source 2 inverted signal is disabled for Gate 3
bit 17 G3D1T: Gate 3 Data Source 1 True Enable bit
1 = The Data Source 1 signal is enabled for Gate 3
0 = The Data Source 1 signal is disabled for Gate 3
bit 16 G3D1N: Gate 3 Data Source 1 Negated Enable bit
1 = The Data Source 1 inverted signal is enabled for Gate 3
0 = The Data Source 1 inverted signal is disabled for Gate 3
bit 15 G2D4T: Gate 2 Data Source 4 True Enable bit
1 = The Data Source 4 signal is enabled for Gate 2
0 = The Data Source 4 signal is disabled for Gate 2
bit 14 G2D4N: Gate 2 Data Source 4 Negated Enable bit
1 = The Data Source 4 inverted signal is enabled for Gate 2
0 = The Data Source 4 inverted signal is disabled for Gate 2
bit 13 G2D3T: Gate 2 Data Source 3 True Enable bit
1 = The Data Source 3 signal is enabled for Gate 2
0 = The Data Source 3 signal is disabled for Gate 2
bit 12 G2D3N: Gate 2 Data Source 3 Negated Enable bit
1 = The Data Source 3 inverted signal is enabled for Gate 2
0 = The Data Source 3 inverted signal is disabled for Gate 2
bit 11 G2D2T: Gate 2 Data Source 2 True Enable bit
1 = The Data Source 2 signal is enabled for Gate 2
0 = The Data Source 2 signal is disabled for Gate 2
bit 10 G2D2N: Gate 2 Data Source 2 Negated Enable bit
1 = The Data Source 2 inverted signal is enabled for Gate 2
0 = The Data Source 2 inverted signal is disabled for Gate 2
bit 9 G2D1T: Gate 2 Data Source 1 True Enable bit
1 = The Data Source 1 signal is enabled for Gate 2
0 = The Data Source 1 signal is disabled for Gate 2
bit 8 G2D1N: Gate 2 Data Source 1 Negated Enable bit
1 = The Data Source 1 inverted signal is enabled for Gate 2
0 = The Data Source 1 inverted signal is disabled for Gate 2
bit 7 G1D4T: Gate 1 Data Source 4 True Enable bit
1 = The Data Source 4 signal is enabled for Gate 1
0 = The Data Source 4 signal is disabled for Gate 1
bit 6 G1D4N: Gate 1 Data Source 4 Negated Enable bit
1 = The Data Source 4 inverted signal is enabled for Gate 1
0 = The Data Source 4 inverted signal is disabled for Gate 1
bit 5 G1D3T: Gate 1 Data Source 3 True Enable bit
1 = The Data Source 3 signal is enabled for Gate 1
0 = The Data Source 3 signal is disabled for Gate 1
REGISTER 18-3: CLCxGLS: CLCx GATE LOGIC INPUT SELECT REGISTER (CONTINUED)
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bit 4 G1D3N: Gate 1 Data Source 3 Negated Enable bit
1 = The Data Source 3 inverted signal is enabled for Gate 1
0 = The Data Source 3 inverted signal is disabled for Gate 1
bit 3 G1D2T: Gate 1 Data Source 2 True Enable bit
1 = The Data Source 2 signal is enabled for Gate 1
0 = The Data Source 2 signal is disabled for Gate 1
bit 2 G1D2N: Gate 1 Data Source 2 Negated Enable bit
1 = The Data Source 2 inverted signal is enabled for Gate 1
0 = The Data Source 2 inverted signal is disabled for Gate 1
bit 1 G1D1T: Gate 1 Data Source 1 True Enable bit
1 = The Data Source 1 signal is enabled for Gate 1
0 = The Data Source 1 signal is disabled for Gate 1
bit 0 G1D1N: Gate 1 Data Source 1 Negated Enable bit
1 = The Data Source 1 inverted signal is enabled for Gate 1
0 = The Data Source 1 inverted signal is disabled for Gate 1
REGISTER 18-3: CLCxGLS: CLCx GATE LOGIC INPUT SE LECT REGISTER (CONTINUED)
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19.0 COMPARATOR
The comparator module provides two dual input
comparators. The inputs to the comparator can be con-
figured to use any one of five external analog inputs
(CxINA, CxINB, CxINC, CxIND and V
REF
+). The
comparator outputs may be directly connected to the
CxOUT pins. When the respective COE bit equals ‘1’,
the I/O pad logic makes the unsynchronized output of
the comparator available on the pin.
A simplified block diagram of the module is shown in
Figure 19-1. Each comparator has its own control
register, CMxCON (Register 19-2), for enabling and
configuring its operation. The output and event status
of two comparators is provided in the CMSTAT register
(Register 19-1).
FIGURE 19-1: DUAL COMPARATOR MODULE BLOCK DIAGRAM
Note: This data sheet summarizes the features
of the PIC32MM0064GPL036 family of
devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to Section 19. “Comparator”
(DS60001110) in the “PIC32 Family Refer-
ence Manual”, which is available from the
Microchip web site (www.microchip.com/
PIC32). The information in this data sheet
supersedes the information in the FRM.
C1
V
IN
-
V
IN
+
CxINB
CxINC
(1)
CxINA
CxIND
(1)
V
REF
+ Pin
C2
V
IN
-
V
IN
+
COE
C1OUT
Pin
CPOL
CEVT
EVPOL<1:0>
COUT
Input
Select
Logic
CCH<1:0>
CREF
COE
C2OUT
Pin
CPOL
CEVT
EVPOL<1:0>
COUT
–
CVREFSEL
+
01
00
10
11
1
0
0
1
CDAC1 Output
Band Gap
Trigger/Interrupt
Logic
Trigger/Interrupt
Logic
Note 1: This input is not available for Comparator 2.
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19.1 Comparator Control Registers
TABLE 19-1: COMPARATOR 1 AND 2 REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
0900 CMSTAT 31:16 — — — — — — — — — — — — — — C2EVT C1EVT 0000
15:0 — — SIDL — — — — CVREFSEL — — — — — — C2OUT C1OUT 0000
0910 CM1CON 31:16 — — — — — — — — — — — — — — — — 0000
15:0 ON COE CPOL — — — CEVT COUT EVPOL<1:0> —CREF — — CCH<1:0> 0000
0930 CM2CON 31:16 — — — — — — — — — — — — — — — — 0000
15:0 ON COE CPOL — — — CEVT COUT EVPOL<1:0> —CREF — — CCH<1:0> 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively.
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REGISTER 19-1: CMSTAT: COMPARATOR MODULE STATUS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 R-0, HS, HC R-0, HS, HC
— — — — — — C2EVT C1EVT
15:8
U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0
——SIDL — — — — CVREFSEL
7:0
U-0 U-0 U-0 U-0 U-0 U-0 R-0, HS, HC R-0, HS, HC
— — — — — — C2OUT C1OUT
Legend: HC = Hardware Clearable bit HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-18 Unimplemented: Read as ‘0’
bit 17 C2EVT: Comparator 2 Event Status bit (read-only)
Shows the current event status of Comparator 2 (CM2CON<9>).
bit 16 C1EVT: Comparator 1 Event Status bit (read-only)
Shows the current event status of Comparator 1 (CM1CON<9>).
bit 15-14 Unimplemented: Read as ‘0’
bit 13 SIDL: Comparator Stop in Idle Mode bit
1 = Discontinues operation of all comparators when device enters Idle mode
0 = Continues operation of all enabled comparators in Idle mode
bit 12-9 Unimplemented: Read as ‘0’
bit 8 CVREFSEL: Comparator Reference Voltage Select Enable bit
1 = External voltage reference from the V
REF
+ pin is selected
0 = Voltage from CDAC1 is selected
bit 7-2 Unimplemented: Read as ‘0’
bit 1 C2OUT: Comparator 2 Output Status bit (read-only)
Shows the current output of Comparator 2 (CM2CON<8>).
bit 0 C1OUT: Comparator 1 Output Status bit (read-only)
Shows the current output of Comparator 1 (CM1CON<8>).
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REGISTER 19-2: CMxCON: COMPARATOR x CONTROL REGISTERS
(COMPARATORS 1 AND 2)
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R-0, HS, HC R-0, HS, HC
ON COE CPOL — — — CEVT COUT
7:0
R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0
EVPOL<1:0> — CREF —— CCH<1:0>
Legend: HC = Hardware Clearable bit HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ON: Comparator Enable bit
1 = Comparator is enabled
0 = Comparator is disabled
bit 14 COE: Comparator Output Enable bit
1 = Comparator output is present on the CxOUT pin
0 = Comparator output is internal only
bit 13 CPOL: Comparator Output Polarity Select bit
1 = Comparator output is inverted
0 = Comparator output is not inverted
bit 12-10 Unimplemented: Read as ‘0’
bit 9 CEVT: Comparator Event bit
1 = Comparator event that is defined by EVPOL<1:0> has occurred; subsequent triggers and interrupts are
disabled until the bit is cleared
0 = Comparator event has not occurred
bit 8 COUT: Comparator Output bit
When CPOL = 0:
1 = V
IN
+ > V
IN
-
0 = V
IN
+ < V
IN
-
When CPOL = 1:
1 = V
IN
+ < V
IN
-
0 = V
IN
+ > V
IN
-
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bit 7-6 EVPOL<1:0>: Trigger/Event/Interrupt Polarity Select bits
11 = Trigger/event/interrupt is generated on any change of the comparator output (while CEVT = 0)
10 = Trigger/event/interrupt is generated on transition of the comparator output:
If CPOL = 0 (non-inverted polarity):
High-to-low transition only.
If CPOL = 1 (inverted polarity):
Low-to-high transition only.
01 = Trigger/event/interrupt is generated on transition of the comparator output:
If CPOL = 0 (non-inverted polarity):
Low-to-high transition only.
If CPOL = 1 (inverted polarity):
High-to-low transition only.
00 = Trigger/event/interrupt generation is disabled
bit 5 Unimplemented: Read as ‘0’
bit 4 CREF: Comparator Reference Select bit (non-inverting input)
1 = Non-inverting input connects to the internal reference defined by the CVREFSEL bit in the CMSTAT register
0 = Non-inverting input connects to the CxINA pin
bit 3-2 Unimplemented: Read as ‘0’
bit 1-0 CCH<1:0>: Comparator Channel Select bits
11 = Inverting input of the comparator connects to the band gap reference voltage
10 = Inverting input of the comparator connects to the CxIND pin
01 = Inverting input of the comparator connects to the CxINC pin
00 = Inverting input of the comparator connects to the CxINB pin
REGISTER 19-2: CMxCON: COMPARATOR x CONTROL REGISTERS
(COMPARATORS 1 AND 2) (CONTINUED)
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NOTES:
2015-2016 Microchip Technology Inc. DS60001324B-page 169
PIC32MM0064GPL036 FAMILY
20.0 CONTROL DIGITAL-TO-
ANALOG CONVERTER (CDAC)
The Control Digital-to-Analog Converter (CDAC)
generates analog voltage corresponding to the digital
input.
The CDAC has the following features:
• 32 Output Levels are Available
• Internally Connected to Comparators to Conserve
Device Pins
• Output can be Connected to a Pin
A block diagram of the CDAC module is illustrated in
Figure 20-1.
FIGURE 20-1: CDAC BLOCK DIAGRAM
Note: This data sheet summarizes the
features of the PIC32MM0064GPL036
family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 45. “Control
Digital-to-Analog Converter (CDAC)”
(DS60001327) in the “PIC32 Family
Reference Manual”, which is available
from the Microchip web site
(www.microchip.com/PIC32). The infor-
mation in this data sheet supersedes
the information in the FRM.
DACDAT<4:0>
R
AV
DD
V
REF
+
R
R
R
R
R
R
32 Steps CDAC1
AV
SS
DACOE
32-to-1 MUX
Output to
Comparators
REFSEL<1:0>
PIC32MM0064GPL036 FAMILY
DS60001324B-page 170 2015-2016 Microchip Technology Inc.
20.1 CDAC Control Registers
TABLE 20-1: CDAC REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
0980 DAC1CON 31:16 — — — — — — — — — — — DACDAT<4:0> 0000
15:0 ON — — — — — — DACOE — — — — — — REFSEL<1:0> 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: The register in this table has corresponding CLR, SET and INV registers at its virtual address, plus offsets of 0x4, 0x8 and 0xC, respectively.
2015-2016 Microchip Technology Inc. DS60001324B-page 171
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REGISTER 20-1: DAC1CON: CDAC CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — —DACDAT<4:0>
15:8
R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
ON — — — — — —DACOE
7:0
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — REFSEL<1:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-21 Unimplemented: Read as ‘0’
bit 20-16 DACDAT<4:0>: CDAC Voltage Reference Selection bits
11111 = (DACDAT<4:0> * V
REF
+/32) or (DACDAT<4:0> * AV
DD
/32) volts depending on the REFSEL<1:0> bits
•
•
•
00000 = 0.0 volts
bit 15 ON: Voltage Reference Enable bit
1 = Voltage reference is enabled
0 = Voltage reference is disabled
bit 14-9 Unimplemented: Read as ‘0’
bit 8 DACOE: CDAC Voltage Reference Output Enable bit
1 = Voltage level is output on the CDAC1 pin
0 = Voltage level is disconnected from the CDAC1 pin
bit 7-2 Unimplemented: Read as ‘0’
bit 1-0 REFSEL<1:0>: CDAC Voltage Reference Source Select bits
11 = Reference voltage is AV
DD
10 = No reference is selected – output is AV
SS
01 = Reference voltage is the V
REF
+ input pin voltage
00 = No reference is selected – output is AV
SS
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NOTES:
2015-2016 Microchip Technology Inc. DS60001324B-page 173
PIC32MM0064GPL036 FAMILY
21.0 HIGH/LOW-VOLTAGE DETECT
(HLVD)
The High/Low-Voltage Detect (HLVD) module is a
programmable circuit that allows the user to specify
both the device voltage trip point and the direction of
change.
An interrupt flag is set if the device experiences an
excursion past the trip point in the direction of change.
If the interrupt is enabled, the program execution will
branch to the interrupt vector address and the software
can then respond to the interrupt.
The HLVD Control register (see Register 21-1)
completely controls the operation of the HLVD module.
This allows the circuitry to be “turned off” by the user
under software control, which minimizes the current
consumption for the device.
FIGURE 21-1: HIGH/LOW-VOLTAGE DETECT (HLVD) MODULE BLOCK DIAGRAM
Set
V
DD
16-to-1 MUX
ON
HLVDL<3:0>
LVDIN
V
DD
Externally Generated
Trip Point
HLVDIF
ON
Band Gap
VDIR
1.2V Typical
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DS60001324B-page 174 2015-2016 Microchip Technology Inc.
21.1 High/Low-Voltage Detect Registers
TABLE 21-1: HIGH/LOW-VOLTAGE DETECT REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
2310 HLVDCON 31:16 — — — — — — — — — — — — — — — — 0000
15:0 ON —SIDL —VDIR BGVST IRVST HLEVT — — — — HLVDL<3:0> 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: The register in this table has corresponding CLR, SET and INV registers at its virtual address, plus offsets of 0x4, 0x8 and 0xC, respectively.
2015-2016 Microchip Technology Inc. DS60001324B-page 175
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REGISTER 21-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — —
15:8
R/W-0 U-0 R/W-0 U-0 R/W-0 R-0, HS, HC R-0, HS, HC R-0, HS, HC
ON —SIDL — VDIR BGVST IRVST HLEVT
7:0
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — —HLVDL<3:0>
Legend: HC = Hardware Clearable bit HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ON: HLVD Power Enable bit
1 = HLVD is enabled
0 = HLVD is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: HLVD Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12 Unimplemented: Read as ‘0’
bit 11 VDIR: Voltage Change Direction Select bit
1 = Event occurs when voltage equals or exceeds the trip point (HLVDL<3:0>)
0 = Event occurs when voltage equals or falls below the trip point (HLVDL<3:0>)
bit 10 BGVST: Band Gap Voltage Stable Flag bit
1 = Indicates that the band gap voltage is stable
0 = Indicates that the band gap voltage is unstable
bit 9 IRVST: Internal Reference Voltage Stable Flag bit
1 = Internal reference voltage is stable; the High-Voltage Detect logic generates the interrupt flag at the
specified voltage range
0 = Internal reference voltage is unstable; the High-Voltage Detect logic will not generate the interrupt flag
at the specified voltage range and the HLVD interrupt should not be enabled
bit 8 HLEVT: High/Low-Voltage Detection Event Status bit
1 = Indicates HLVD event is active
0 = Indicates HLVD event is not active
bit 7-4 Unimplemented: Read as ‘0’
Note 1: The voltage is typical. It is for design guidance only and not tested. Refer to Table 26-13 in Section 26.0
“Electri cal Characteristics” for minimum and maximum values.
PIC32MM0064GPL036 FAMILY
DS60001324B-page 176 2015-2016 Microchip Technology Inc.
bit 3-0 HLVDL<3:0>: High/Low-Voltage Detection Limit bits
1111 = External analog input is used (input comes from the LVDIN pin and is compared with 1.2V band gap)
1110 = V
DD
trip point is 2.11V
(1)
1101 = V
DD
trip point is 2.21V
(1)
1100 = V
DD
trip point is 2.30V
(1)
1011 = V
DD
trip point is 2.40V
(1)
1010 = V
DD
trip point is 2.52V
(1)
1001 = V
DD
trip point is 2.63V
(1)
1000 = V
DD
trip point is 2.82V
(1)
0111 = V
DD
trip point is 2.92V
(1)
0110 = V
DD
trip point is 3.13V
(1)
0101 = V
DD
trip point is 3.44V
(1)
0100-0000 = Reserved; do not use
REGISTER 21-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER (CONTINUED)
Note 1: The voltage is typical. It is for design guidance only and not tested. Refer to Table 26-13 in Section 26.0
“Electri cal Characteristics” for minimum and maximum values.
2015-2016 Microchip Technology Inc. DS60001324B-page 177
PIC32MM0064GPL036 FAMILY
22.0 POWER-SA VING FEATURES
This section describes power-saving features for the
PIC32MM0064GPL036 family devices. These devices
offer various methods and modes that allow the appli-
cation to balance power consumption with device
performance. In all of the methods and modes
described in this section, power saving is controlled by
software. The peripherals and CPU can be halted or
disabled to reduce power consumption.
22.1 Sleep Mode
In Sleep mode, the CPU and most peripherals are
halted, and the associated clocks are disabled. Some
peripherals can continue to operate in Sleep mode and
can be used to wake the device from Sleep. See the
individual peripheral module sections for descriptions
of behavior in Sleep. The device enters Sleep mode
when the SLPEN bit (OSCCON<4>) is set and a WAIT
instruction is executed.
Sleep mode includes the following characteristics:
• There can be a wake-up delay based on the
oscillator selection.
• The Fail-Safe Clock Monitor (FSCM) does not
operate during Sleep mode.
• The BOR circuit remains operative during Sleep mode.
• If WDT is enabled, the Run mode counter is not
cleared upon entry to Sleep and the Sleep mode
counter is reset upon entering Sleep.
• Some peripherals can continue to operate at
limited functionality in Sleep mode. These periph-
erals include I/O pins that detect a change in the
input signal, WDT, ADC, UART and peripherals
that use an external clock input or the internal
LPRC oscillator (e.g., RTCC and Timer1).
• I/O pins continue to sink or source current in the same
manner as they do when the device is not in Sleep.
• The on-chip regulator enters Standby mode if the
VREGS bit (PWRCON<0>) is set.
• A separate special low-power, low-voltage/
retention regulator is activated if the RETVR
Configuration bit (FPOR<2>) is programmed to
zero and the RETEN bit (PWRCON<1>) is set.
The processor will exit, or “wake-up”, from Sleep on
one of the following events:
• On any interrupt from an enabled source that is
operating in Sleep. The interrupt priority must be
greater than the current CPU priority.
• On any form of device Reset.
• On a WDT time-out.
If the interrupt priority is lower than, or equal to, the
current priority, the CPU will remain halted, but the
Peripheral Bus Clock (PBCLK) will start running and
the device will enter into Idle mode. To set or clear the
SLPEN bit, an unlock sequence must be executed.
Refer to Section 23.4 “System Registers Write
Protection” for details.
22.2 Idle Mode
In Idle mode, the CPU is halted; however, all clocks are
still enabled. This allows peripherals to continue to
operate. Peripherals can be individually configured to
halt when entering Idle by setting their respective SIDL
bit. Latency, when exiting Idle mode, is very low due to
the CPU oscillator source remaining active.
The device enters Idle mode when the SLPEN bit
(OSCCON<4>) is clear and a WAIT instruction is
executed.
The processor will wake or exit from Idle mode on the
following events:
• On any interrupt event for which the interrupt
source is enabled. The priority of the interrupt
event must be greater than the current priority of
the CPU. If the priority of the interrupt event is
lower than, or equal to, the current priority of the
CPU, the CPU will remain halted and the device
will remain in Idle mode.
• On any form of device Reset.
• On a WDT time-out interrupt.
To set or clear the SLPEN bit, an unlock sequence
must be executed. Refer to Section 23.4 “System
Registers Write Protection” for details.
Note: This data sheet summarizes the features
of the PIC32MM0064GPL036 family of
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
Section 10. “Power-Saving Modes”
(DS60001130) in the “PIC32 Family
Reference Manual”, which is available
from the Microchip web site
(www.microchip.com/PIC32). The infor-
mation in this data sheet supersedes the
information in the FRM.
PIC32MM0064GPL036 FAMILY
DS60001324B-page 178 2015-2016 Microchip Technology Inc.
22.3 Peripheral Module Disable
The Peripheral Module Disable (PMD) registers pro-
vide a method to disable a peripheral module by
stopping all clock sources supplied to that module.
When a peripheral is disabled using the appropriate
PMD control bit, the peripheral is in a minimum power
consumption state. The control and status registers
associated with the peripheral are also disabled, so
writes to those registers do not take effect and read
values are invalid.
To disable a peripheral, the associated PMDx bit must
be set to ‘1’. To enable a peripheral, the associated
PMDx bit must be cleared (default).
To prevent accidental configuration changes under
normal operation, writes to the PMDx registers are not
allowed. Attempted writes appear to execute normally,
but the contents of the registers remain unchanged. To
change these registers, they must be unlocked in
hardware. The register lock is controlled by the
PMDLOCK bit in PMDCON register (PMDCON<11>).
Setting PMDLOCK prevents writes to the control regis-
ters; clearing PMDLOCK allows writes. To set or clear
PMDLOCK, an unlock sequence must be executed.
Refer to Section 23.4 “System Registers Write
Protection” for details.
Table 22-1 lists the module disable bits and locations
for all modules.
TABLE 22-1: PERIPHERAL MODULE DISABLE BITS AND LOCATIONS
Peripheral PMDx Bit Name Register Name and Bit Location
Analog-to-Digital Converter (ADC) ADCMD PMD1<0>
Voltage Reference (VR) VREFMD PMD1<12>
High/Low-Voltage Detect (HLVD) HLVDMD PMD1<20>
Comparator 1 (CMP1) CMP1MD PMD2<0>
Comparator 2 (CMP2) CMP2MD PMD2<1>
Configurable Logic Cell 1 (CLC1) CLC1MD PMD2<24>
Configurable Logic Cell 2 (CLC2) CLC2MD PMD2<25>
Multiple Outputs Capture/Compare/PWM/
Timer1 (MCCP1)
CCP1MD PMD3<8>
Single Output Capture/Compare/PWM/Timer2
(SCCP2)
CCP2MD PMD3<9>
Single Output Capture/Compare/PWM/Timer3
(SCCP3)
CCP3MD PMD3<10>
Timer1 (TMR1) T1MD PMD4<0>
Universal Asynchronous Receiver
Transmitter 1 (UART1)
U1MD PMD5<0>
Universal Asynchronous Receiver
Transmitter 2 (UART2)
U2MD PMD5<1>
Serial Peripheral Interface 1 (SPI1) SPI1MD PMD5<8>
Serial Peripheral Interface 2 (SPI2) SPI2MD PMD5<9>
Real-Time Clock and Calendar (RTCC) RTCCMD PMD6<0>
Reference Clock Output (REFCLKO) REFOMD PMD6<8>
Programmable Cyclic Redundancy Check
(CRC)
CRCMD PMD7<3>
2015-2016 Microchip Technology Inc. DS60001324B-page 179
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22.4 On-Chip Voltage Regulator
Low-Power Modes
The main on-chip regulator always consumes an incre-
mental amount of current over I
DD
/I
PD
, including when
the device is in Sleep mode, even though the core digital
logic does not require power. To provide additional sav-
ings in applications where power resources are critical,
the regulator can be made to enter Standby mode and/
or Retention mode. Standby mode is controlled by the
VREGS bit (PWRCON<0>), and Retention mode is con-
trolled by the RETEN (PWRCON<1>) and RETVR
(FPOR<2>) bits. The available Regulator Low-Power
modes are listed in Table 22-2. For more information
about the wake-up time and the current consumption for
different modes, refer to the electrical specifications
listed in Table 26-6 and Table 26-22.
22.4.1 REGULATOR STANDBY MODE
Whenever the device goes into Sleep mode, the regu-
lator can be made to enter Standby mode. This feature
is controlled by the VREGS bit (PWRCON<0>). Clear-
ing the VREGS bit enables Standby mode. If Standby
mode is used, the voltage regulator needs some time
to switch to normal operation mode and generate
output. During this time, the code execution is disabled.
The delay is applied every time the device resumes
operation after Standby mode.
22.4.2 REGULATOR RETENTION MODE
When in Sleep mode, the device can use a separate
low-power, low-voltage/retention regulator to power
critical circuits. This regulator, which operates at 1V
nominal, maintains power to data RAM, WDT, Timer1
and the RTCC, while all other core digital logic is
powered down. The low-voltage/retention regulator is
available only when Sleep mode is invoked. It is con-
trolled by the RETVR Configuration bit (FPOR<2>) and
in firmware by the RETEN bit (PWRCON<1>). RETVR
must be programmed to zero (= 0) and the RETEN bit
must be set (= 1) for the retention regulator to be
enabled.
22.5 Low-Power Brown-out Reset
The PIC32MM0064GPL036 family devices have a
second low-power Brown-out Reset circuit with a
reduced precision of the trip point. This low-power BOR
circuit can be activated when the main BOR is disabled.
The circuit is enabled by programming the LPBOREN
Configuration bit (FPOR<3>) to ‘1’.
TABLE 22-2: VOLTAGE REGULATOR LOW-POWER MODES
Mode VREGS Bit
(PWRCON<0>) RETEN Bit
(PWRCON<1>) RETVR Bit
(FPOR<2>) Wake-up Time
(Table 26-22)Current
(Table 26-6)
Normal 1 0 1 Fastest Highest
Standby Only 0 0 1 Medium Medium
Retention Only 1 1 0 Medium Medium
Standby and
Retention
0 1 0 Slowest Lowest
PIC32MM0064GPL036 FAMILY
DS60001324B-page 180 2015-2016 Microchip Technology Inc.
TABLE 22-3: PERIPHERAL MODULE DISABLE REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
2C00 PMDCON 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — —PMDLOCK— — — — — — — — — — — 0000
2C10 PMD1 31:16 — — — — — — — — — — —HLVDMD— — — — FFEF
15:0 — — —VREFMD — — — — — — — — — — — ADCMD EFFE
2C20 PMD2 31:16 — — — — — — CLC2MD CLC1MD — — — — — — — — FCFF
15:0 — — — — — — — — — — — — — —CMP2MDCMP1MDFFFC
2C30 PMD3 31:16 — — — — — — — — — — — — — — — — FFFF
15:0 — — — — — CCP3MD CCP2MD CCP1MD — — — — — — — — F8FF
2C40 PMD4 31:16 — — — — — — — — — — — — — — — — FFFF
15:0 — — — — — — — — — — — — — — —T1MDFFFE
2C50 PMD5 31:16 — — — — — — — — — — — — — — r r FFFC
15:0 — — — — — — SPI2MD SPI1MD — — — — — —U2MDU1MDFCFC
2C60 PMD6 31:16 — — — — — — — — — — — — — — — — FFFF
15:0 — — — — — — —REFOMD— — — — — — — RTCCMD FEFE
2C70 PMD7 31:16 — — — — — — — — — — — — — — — — FFFF
15:0 — — — — — — — — — — — — CRCMD — — — FFF7
Legend: — = unimplemented, read as ‘1’; r = reserved bit, maintain as ‘1’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively.
2015-2016 Microchip Technology Inc. DS60001324B-page 181
PIC32MM0064GPL036 FAMILY
23.0 SPECIAL FEATURES
23.1 Configuration Bits
PIC32MM0064GPL036 family devices contain a
Boot Flash Memory (BFM) with an associated config-
uration space. All Configuration Words are listed in
Table 23-3 and Table 23-4; Register 23-1 through
Register 23-6 describe the configuration options.
23.2 Code Execution from RAM
PIC32MM0064GPL036 family devices allow executing
the code from RAM. The starting boundary of this
special RAM space can be adjusted using the
EXECADDR<7:0> bits in the CFGCON register with a
1-Kbyte step. Writing a non-zero value to these bits will
move the boundary, effectively reducing the total
amount of program memory space in RAM. Refer to
Table 23-5 and Register 23-7 for more information.
23.3 Device ID
The Device ID identifies the device used. The ID can be
read from the DEVID register. The Device IDs for
PIC32MM0064GPL036 family devices are listed in
Table 23-1. Also refer to Table 23-5 and Register 23-8
for more information.
23.4 System Registers Write Protection
The critical registers in the PIC32MM0064GPL036 family
devices are protected (locked) from an accidental write.
If the registers are locked, a special unlock sequence is
required to modify the content of these registers.
To unlock the registers, the following steps should be
done:
1. Disable interrupts prior to the system unlock
sequence.
2. Execute the system unlock sequence by writing
the key values of 0xAA996655 and
0x556699AA to the SYSKEY register, in two
back-to-back assembly or ‘C’ instructions.
3. Write the new value to the required register.
4. Write a non-key value (such as 0x00000000) to
the SYSKEY register to perform a lock.
5. Re-enable interrupts.
The registers that require this unlocking sequence are
listed in Ta b l e 23-2.
The SYSKEY register read value indicates the status.
A value of ‘0’ indicates the system registers are locked.
A value of ‘1’ indicates the system registers are
unlocked. For more information about the SYSKEY
register, refer to Tab le 23-5 and Register 23-9.
Note: This data sheet summarizes the features
of the PIC32MM0064GPL036 family of
devices. However, it is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Se ction 33. “ Programmi ng
and Diagnostics” (DS61129) in the
“PIC32 Family Refere nce Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32). The informa-
tion in this data sheet supersedes the
information in the FRM.
TABLE 23-1: DEVICE IDs FOR
PIC32MM0064GPL036 FAMILY
DEVICES
Device DEVID
PIC32MM0016GPL020 0x06B04053
PIC32MM0032GPL020 0x06B0C053
PIC32MM0064GPL020 0x06B14053
PIC32MM0016GPL028 0x06B02053
PIC32MM0032GPL028 0x06B0A053
PIC32MM0064GPL028 0x06B12053
PIC32MM0016GPL036 0x06B06053
PIC32MM0032GPL036 0x06B0E053
PIC32MM0064GPL036 0x06B16053
TABLE 23-2: SYSTEM LOCKED REGISTERS
Register
Name Register Description Peripheral
OSCCON Oscillator Control Oscillator
SPLLCON System PLL Control Oscillator
OSCTUN FRC Tuning Oscillator
PMDCON Peripheral Module
Disable Control
PMD
RSWRST Software Reset Reset
RPCON Peripheral Pin Select
Configuration
I/O Ports
RNMICON Non-Maskable Interrupt
Control
Reset
PWRCON Power Control Reset
RTCCON1 RTCC Control 1 RTCC
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DS60001324B-page 182 2015-2016 Microchip Technology Inc.
23.5 Band Gap Voltage Refer ence
PIC32MM0064GPL036 family devices have a precision
voltage reference band gap circuit used by many
modules. The analog buffers are implemented between
the band gap circuit and these modules. The buffers
are automatically enabled by the hardware if some part
of the device needs the band gap reference. The stabi-
lization time is required when the buffer is switched on.
The software can enable these buffers in advance to
allow the band gap voltage to stabilize before the
module uses it. The ANCFG register contains bits to
enable the band gap buffers for the comparators
(VBGCMP bit) and ADC (VBGADC bit). Refer to
Ta b l e 23-6 and Register 23-10 for more information.
23.6 Programming and Diagnostics
PIC32MM0064GPL036 family devices provide a
complete range of programming and diagnostic
features:
• Simplified Field Programmability using Two-Wire
In-Circuit Serial Programming™ (ICSP™)
Interfaces
• Debugging using ICSP
• Programming and Debugging Capabilities using
the EJTAG Extension of JTAG
• JTAG Boundary Scan Testing for Device and
Board Diagnostics
23.7 Unique Device Identi fier (UDID)
PIC32MM0064GPL036 family devices are individually
encoded during final manufacturing with a Unique
Device Identifier or UDID. The UDID cannot be erased
by a bulk erase command or any other user accessible
means. This feature allows for manufacturing trace-
ability of Microchip Technology devices in applications
where this is a requirement. It may also be used by the
application manufacturer for any number of things that
may require unique identification, such as:
• Tracking the device
• Unique serial number
• Unique security key
The UDID comprises five 32-bit program words. When
taken together, these fields form a unique 160-bit
identifier.
The UDID is stored in five read-only locations, located
from 0xBFC41840 to 0xBFC41854 in the device
configuration space. Tab le 23-7 lists the addresses of
the Identifier Words.
23.8 Reserved Registers
PIC32MM0064GPL036 family devices have 3 reserved
registers, located at 0xBF800400, 0xBF800480 and
0xBF802280. The application code must not modify
these reserved locations. Table 23-8 lists the addresses
of these reserved registers.
2015-2016 Microchip Technology Inc. DS60001324B-page 183
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23.9 Configuration Words and System Registers
TABLE 23-3: CONFIGURATION WORDS SUMMARY
Virtual Address
(BFC0_#)
Register
Name
Bit Range
Bits
31\15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
17C0 RESERVED 31:16 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
15:0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
17C4 FDEVOPT 31:16 USERID<15:0>
15:0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 SOSCHP r-1 r-1 r-1
17C8 FICD 31:16 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
15:0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 ICS<1:0> JTAGEN r-1 r-1
17CC FPOR 31:16 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
15:0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 LPBOREN RETVR BOREN<1:0>
17D0 FWDT 31:16 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
15:0 FWDTEN RCLKSEL<1:0> RWDTPS<4:0> WINDIS FWDTWINSZ<1:0> SWDTPS<4:0>
17D4 FOSCSEL 31:16 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
15:0 FCKSM<1:0> r-1 SOSCSEL r-1 OSCIOFNC POSCMOD<1:0> IESO SOSCEN r-1 PLLSRC r-1 FNOSC<2:0>
17D8 FSEC 31:16 CP r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
15:0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
17DC RESERVED 31:16 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
15:0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
17E0 RESERVED 31:16 r-0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
15:0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
17E4 RESERVED 31:16 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
15:0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
Legend: r-0 = Reserved bit, must be programmed as ‘0’; r-1 = Reserved bit, must be programmed as ‘1’.
PIC32MM0064GPL036 FAMILY
DS60001324B-page 184 2015-2016 Microchip Technology Inc.
TABLE 23-4: ALTERNATE CONFIGURATION WORDS SUMMARY
Virtual Address
(BFC0_#)
Register
Name
Bit Range
Bits
31\15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
1740 RESERVED 31:16 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
15:0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
1744 AFDEVOPT 31:16 USERID<15:0>
15:0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 SOSCHP r-1 r-1 r-1
1748 AFICD 31:16 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
15:0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 ICS<1:0> JTAGEN r-1 r-1
174C AFPOR 31:16 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
15:0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 LPBOREN RETVR BOREN<1:0>
1750 AFWDT 31:16 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
15:0 FWDTEN RCLKSEL<1:0> RWDTPS<4:0> WINDIS FWDTWINSZ<1:0> SWDTPS<4:0>
1754 AFOSCSEL 31:16 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
15:0 FCKSM<1:0> r-1 SOSCSEL r-1 OSCIOFNC POSCMOD<1:0> IESO SOSCEN r-1 PLLSRC r-1 FNOSC<2:0>
1758 AFSEC 31:16 CP r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
15:0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
175C RESERVED 31:16 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
15:0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
1760 RESERVED 31:16 r-0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
15:0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
1764 RESERVED 31:16 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
15:0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
Legend: r-0 = Reserved bit, must be programmed as ‘0’; r-1 = Reserved bit, must be programmed as ‘1’.
2015-2016 Microchip Technology Inc. DS60001324B-page 185
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REGISTER 23-1: FDEVOPT/AFDEVOPT: DEVICE OPTIONS CONFIGURATION REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/P R/P R/P R/P R/P R/P R/P R/P
USERID<15:8>
23:16
R/P R/P R/P R/P R/P R/P R/P R/P
USERID<7:0>
15:8
r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
— — — — — — — —
7:0
r-1 r-1 r-1 r-1 R/P r-1 r-1 r-1
— — — — SOSCHP ———
Legend: r = Reserved bit P = Programmable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 USERID<15:0>: User ID bits (2 bytes which can be programmed to any value)
bit 15-4 Reserved: Program as ‘1’
bit 3 SOSCHP: Secondary Oscillator (SOSC) High-Power Enable bit
1 = SOSC operates in Normal Power mode
0 = SOSC operates in High-Power mode
bit 2-0 R eserved: Program as ‘1’
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DS60001324B-page 186 2015-2016 Microchip Technology Inc.
REGISTER 23-2: FICD/AFICD: ICD/DEBUG CONFIGURATION REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
— — — — — — — —
23:16
r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
— — — — — — — —
15:8
r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
— — — — — — — —
7:0
r-1 r-1 r-1 R/P R/P R/P r-1 r-1
— — — ICS<1:0> JTAGEN — —
Legend: r = Reserved bit P = Programmable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-5 Reserved: Program as ‘1’
bit 4-3 ICS<1:0>: ICE/ICD Communication Channel Selection bits
11 = Communicates on PGEC1/PGED1
10 = Communicates on PGEC2/PGED2
01 = Communicates on PGEC3/PGED3
00 = Not connected
bit 2 JTAGEN: JTAG Enable bit
1 = JTAG is enabled
0 = JTAG is disabled
bit 1-0 Reserved: Program as ‘1’
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REGISTER 23-3: FPOR/AFPOR: POWER-UP SETTINGS CONFIGURATION REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
— — — — — — — —
23:16
r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
— — — — — — — —
15:8
r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
— — — — — — — —
7:0
r-1 r-1 r-1 r-1 R/P R/P R/P R/P
— — — — LPBOREN RETVR BOREN<1:0>
Legend: r = Reserved bit P = Programmable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-4 Reserved: Program as ‘1’
bit 3 LPBOREN: Low-Power BOR Enable bit
1 = Low-Power BOR is enabled when the main BOR is disabled
0 = Low-Power BOR is disabled
bit 2 RETVR: Retention Voltage Regulator Enable bit
1 = Retention regulator is disabled
0 = Retention regulator is enabled and controlled by the RETEN bit during Sleep
bit 1-0 BOREN<1:0>: Brown-out Reset Enable bits
11 = Brown-out Reset is enabled in hardware; SBOREN bit is disabled
10 = Brown-out Reset is enabled only while device is active and is disabled in Sleep; SBOREN bit is disabled
01 = Brown-out Reset is controlled with the SBOREN bit setting
00 = Brown-out Reset is disabled in hardware; SBOREN bit is disabled
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DS60001324B-page 188 2015-2016 Microchip Technology Inc.
REGISTER 23-4: FWDT/AFWDT: WATCHDOG TIMER CONFIGURATION REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
— — — — — — — —
23:16
r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
— — — — — — — —
15:8
R/P R/P R/P R/P R/P R/P R/P R/P
FWDTEN RCLKSEL<1:0> RWDTPS<4:0>
7:0
R/P R/P R/P R/P R/P R/P R/P R/P
WINDIS FWDTWINSZ<1:0> SWDTPS<4:0>
Legend: r = Reserved bit P = Programmable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Reserved: Program as ‘1’
bit 15 FWDTEN: Watchdog Timer Enable bit
1 = WDT is enabled
0 = WDT is disabled
bit 14-13 RCLKSEL<1:0>: Run Mode Watchdog Timer Clock Source Selection bits
11 = Clock source is the LPRC oscillator (same as for Sleep mode)
10 = Clock source is the FRC oscillator
01 = Reserved
00 = Clock source is the system clock
bit 12-8 RWDTPS<4:0>: Run Mode Watchdog Timer Postscale Select bits
From 10100 to 11111 = 1:1048576.
10011 = 1:524288
10010 = 1:262144
10001 = 1:131072
10000 = 1:65536
01111 = 1:32768
01110 = 1:16384
01101 = 1:8192
01100 = 1:4096
01011 = 1:2048
01010 = 1:1024
01001 = 1:512
01000 = 1:256
00111 = 1:128
00110 = 1:64
00101 = 1:32
00100 = 1:16
00011 = 1:8
00010 = 1:4
00001 = 1:2
00000 = 1:1
bit 7 WINDIS: Windowed Watchdog Timer Disable bit
1 = Windowed mode is disabled
0 = Windowed mode is enabled
2015-2016 Microchip Technology Inc. DS60001324B-page 189
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bit 6-5 FWDTWINSZ<1:0>: Watchdog Timer Window Size bits
11 = Watchdog Timer window size is 25%
10 = Watchdog Timer window size is 37.5%
01 = Watchdog Timer window size is 50%
00 = Watchdog Timer window size is 75%
bit 4-0 SWDTPS<4:0>: Sleep Mode Watchdog Timer Postscale Select bits
From 10100 to 11111 = 1:1048576.
10011 = 1:524288
10010 = 1:262144
10001 = 1:131072
10000 = 1:65536
01111 = 1:32768
01110 = 1:16384
01101 = 1:8192
01100 = 1:4096
01011 = 1:2048
01010 = 1:1024
01001 = 1:512
01000 = 1:256
00111 = 1:128
00110 = 1:64
00101 = 1:32
00100 = 1:16
00011 = 1:8
00010 = 1:4
00001 = 1:2
00000 = 1:1
REGISTER 23-4: FWDT/AFWDT: WATCHDOG TIMER CONFIGURATION REGISTER (CONTINUED)
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DS60001324B-page 190 2015-2016 Microchip Technology Inc.
REGISTER 23-5: FOSCSEL/AFOSCSEL: OSCILLATOR SELECTION CONFIGURATION
REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
— — — — — — — —
23:16
r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
— — — — — — — —
15:8
R/P R/P r-1 R/P r-1 R/P R/P R/P
FCKSM<1:0> — SOSCSEL — OSCIOFNC POSCMOD<1:0>
7:0
R/P R/P r-1 R/P r-1 R/P R/P R/P
IESO SOSCEN —PLLSRC—FNOSC<2:0>
Legend: r = Reserved bit P = Programmable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Reserved: Program as ‘1’
bit 15-14 FCKSM<1:0>: Clock Switching and Fail-Safe Clock Monitor Enable bits
11 = Clock switching is enabled; Fail-Safe Clock Monitor is enabled
10 = Clock switching is disabled; Fail-Safe Clock Monitor is enabled
01 = Clock switching is enabled; Fail-Safe Clock Monitor is disabled
00 = Clock switching is disabled; Fail-Safe Clock Monitor is disabled
bit 13 Reserved: Program as ‘1’
bit 12 SOSCSEL: Secondary Oscillator (SOSC) External Clock Enable bit
1 = Crystal is used (RA4 and RB4 pins are controlled by SOSC)
0 = External clock is connected to the SOSCO pin (RA4 and RB4 pins are controlled by I/O PORTx registers)
bit 11 Reserved: Program as ‘1’
bit 10 OSCIOFNC: System Clock on CLKO Pin Enable bit
1 = OSC2/CLKO pin operates as normal I/O
0 = System clock is connected to the OSC2/CLKO pin
bit 9-8 POSCMOD<1:0>: Primary Oscillator (POSC) Mode Selection bits
11 = Primary Oscillator is disabled
10 = HS Oscillator mode is selected
01 = XT Oscillator mode is selected
00 = External Clock (EC) mode is selected
bit 7 IESO: Two-Speed Start-up Enable bit
1 = Two-Speed Start-up is enabled
0 = Two-Speed Start-up is disabled
bit 6 SOSCEN: Secondary Oscillator (SOSC) Enable bit
1 = Secondary Oscillator is enabled
0 = Secondary Oscillator is disabled
bit 5 Reserved: Program as ‘1’
bit 4 PLLSRC: System PLL Input Clock Selection bit
1 = FRC oscillator is selected as the PLL reference input on a device Reset
0 = Primary Oscillator (POSC) is selected as the PLL reference input on a device Reset
bit 3 Reserved: Program as ‘1’
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bit 2-0 FNOSC<2:0>: Oscillator Selection bits
110 and 111 = Reserved (selects Fast RC (FRC) Oscillator with Divide-by-N)
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Reserved
010 = Primary Oscillator (XT, HS, EC)
001 = Primary or FRC Oscillator with PLL
000 = Fast RC (FRC) Oscillator with Divide-by-N
REGISTER 23-5: FOSCSEL/AFOSCSEL: OSCILLATOR SELECTION CONFIGURATION
REGISTER (CONTINUED)
REGISTER 23-6: FSEC/AFSEC: CODE-PROTECT CONFIGURATION REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/P r-1 r-1 r-1 r-1 r-1 r-1 r-1
CP — — — — — — —
23:16
r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
— — — — — — — —
15:8
r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
— — — — — — — —
7:0
r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
— — — — — — — —
Legend: r = Reserved bit P = Programmable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 CP: Code Protection Enable bit
1 = Code protection is disabled
0 = Code protection is enabled
bit 30-0 Reserved: Program as ‘1’
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DS60001324B-page 192 2015-2016 Microchip Technology Inc.
TABLE 23-5: RAM CONFIGURATION, DEVICE ID AND SYSTEM LOCK REGISTERS MAP
Virtual Address
(BF80_#)
Register
Name
Bit Range
Bits
All Resets
(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
3B00 CFGCON 31:16 — — — — — — — — EXECADDR<7:0> 0000
15:0 — — — — — — — — — — — — JTAGEN — — — 000x
3B20 DEVID 31:16 VER<3:0> ID<27:16> xxxx
15:0 ID<15:0> xxxx
3B30 SYSKEY 31:16 SYSKEY<31:0> 0000
15:0 0001
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Reset values are dependent on the device variant.
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REGISTER 23-7: CFGCON: CONFIGURATION CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 r-0 U-0 r-0 r-0
— — — — — — — —
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
EXECADDR<7:0>
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
U-0 U-0 U-0 U-0 R/W-y U-0 r-1 r-1
— — — — JTAGEN — — —
Legend: r = Reserved bit y = Value set from Configuration bits on Reset
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-28 Unimplemented: Read as ‘0’
bit 27 Reserved: Must be written as ‘0’
bit 26 Unimplemented: Read as ‘0’
bit 25-24 Reserved: Must be written as ‘0’
bit 23-16 EXECADDR<7:0>: RAM Program Space Start Address bits
11111111 = RAM program space starts at the 255-Kbyte boundary (from 0xA003FC00)
•
•
•
00000010 = RAM program space starts at the 2-Kbyte boundary (from 0xA0000800)
00000001 = RAM program space starts at the 1-Kbyte boundary (from 0xA0000400)
00000000 = All data RAM is allocated to program space (from 0xA0000000)
bit 15-4 Unimplemented: Read as ‘0’
bit 3 JTAGEN: JTAG Enable bit
1 = JTAG port is enabled
0 = JTAG port is disabled
The Reset value of this bit is the value of the JTAGEN (FICD<2>) Configuration bit.
bit 2 Unimplemented: Read as ‘0’
bit 1-0 Reserved: Must be written as ‘1’
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DS60001324B-page 194 2015-2016 Microchip Technology Inc.
REGISTER 23-8: DEVID: DEVICE ID REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R-x R-x R-x R-x R-x R-x R-x R-x
VER<3:0>
(1)
ID<27:24>
(1)
23:16
R-x R-x R-x R-x R-x R-x R-x R-x
ID<23:16>
(1)
15:8
R-x R-x R-x R-x R-x R-x R-x R-x
ID<15:8>
(1)
7:0
R-x R-x R-x R-x R-x R-x R-x R-x
ID<7:0>
(1)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-28 VER<3:0>: Revision Identifier bits
(1)
bit 27-0 DEVID<27:0>: Device ID bits
(1)
Note 1: Reset values are dependent on the device variant.
REGISTER 23-9: SYSKEY: SYSTEM UNLOCK REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
SYSKEY<31:24>
23:16
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
SYSKEY<23:16>
15:8
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
SYSKEY<15:8>
7:0
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
SYSKEY<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 SYSKEY<31:0>: Unlock and Lock Key bits
2015-2016 Microchip Technology Inc. DS60001324B-page 195
PIC32MM0064GPL036 FAMILY
TABLE 23-6: BAND GAP REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
2300 ANCFG
(1)
31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — — — — — — — VBGADC VBGCMP —0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively.
PIC32MM0064GPL036 FAMILY
DS60001324B-page 196 2015-2016 Microchip Technology Inc.
REGISTER 23-10: ANCFG: BAND GAP CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
U-0 U-0 U-0 U-0 U-0 R/W-0, HS, HC R/W-0, HS, HC U-0
— — — — — VBGADC VBGCMP —
Legend: HC = Hardware Clearable bit HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-3 Unimplemented: Read as ‘0’
bit 2 VBGADC: ADC Band Gap Enable bit
1 = ADC band gap is enabled
0 = ADC band gap is disabled
bit 1 VBGCMP: Comparator Band Gap Enable bit
1 = Comparator band gap is enabled
0 = Comparator band gap is disabled
bit 0 Unimplemented: Read as ‘0’
2015-2016 Microchip Technology Inc. DS60001324B-page 197
PIC32MM0064GPL036 FAMILY
TABLE 23-7: UNIQUE DEVICE IDENTIFIER (UDID) REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
1840 UDID1 31:16 UDID Word 1<31:0> xxxx
15:0 xxxx
1844 UDID2 31:16 UDID Word 2<31:0> xxxx
15:0 xxxx
1848 UDID3 31:16 UDID Word 3<31:0> xxxx
15:0 xxxx
184C UDID4 31:16 UDID Word 4<31:0> xxxx
15:0 xxxx
1850 UDID5 31:16 UDID Word 5<31:0> xxxx
15:0 xxxx
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 23-8: RESERVED REGISTERS MAP
Virtual Address
(BF80_#)
Register
Name
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
0400 RESERVED1 31:16 Reserved Register 1<31:0> 0000
15:0 0000
0480 RESERVED2 31:16 Reserved Register 2<31:0> 0000
15:0 0000
2280 RESERVED3 31:16 Reserved Register 3<31:0> 0C00
15:0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
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DS60001324B-page 198 2015-2016 Microchip Technology Inc.
NOTES:
2015-2016 Microchip Technology Inc. DS60001324B-page 199
PIC32MM0064GPL036 FAMILY
24.0 DEVELOPMENT SUPPORT
The PIC
®
microcontrollers (MCU) and dsPIC
®
digital
signal controllers (DSC) are supported with a full range
of software and hardware development tools:
• Integrated Development Environment
- MPLAB
®
X IDE Software
• Compilers/Assemblers/Linkers
- MPLAB XC Compiler
- MPASM
TM
Assembler
-MPLINK
TM
Object Linker/
MPLIB
TM
Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB X SIM Software Simulator
•Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers/Programmers
- MPLAB ICD 3
- PICkit™ 3
• Device Programmers
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation Kits and Starter Kits
• Third-party development tools
24.1 MPLAB X Integrated Developme nt
Environment Software
The MPLAB X IDE is a single, unified graphical user
interface for Microchip and third-party software, and
hardware development tool that runs on Windows
®
,
Linux and Mac OS
®
X. Based on the NetBeans IDE,
MPLAB X IDE is an entirely new IDE with a host of free
software components and plug-ins for high-
performance application development and debugging.
Moving between tools and upgrading from software
simulators to hardware debugging and programming
tools is simple with the seamless user interface.
With complete project management, visual call graphs,
a configurable watch window and a feature-rich editor
that includes code completion and context menus,
MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
multiple projects with simultaneous debugging, MPLAB
X IDE is also suitable for the needs of experienced
users.
Feature-Rich Editor:
• Color syntax highlighting
• Smart code completion makes suggestions and
provides hints as you type
• Automatic code formatting based on user-defined
rules
• Live parsing
User-Friendly, Customizable Interface:
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project-Based Workspaces:
• Multiple projects
• Multiple tools
• Multiple configurations
• Simultaneous debugging sessions
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker
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DS60001324B-page 200 2015-2016 Microchip Technology Inc.
24.2 MPLAB XC Compilers
The MPLAB XC Compilers are complete ANSI C
compilers for all of Microchip’s 8, 16 and 32-bit MCU
and DSC devices. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use. MPLAB XC Compilers run on Windows,
Linux or MAC OS X.
For easy source level debugging, the compilers provide
debug information that is optimized to the MPLAB X
IDE.
The free MPLAB XC Compiler editions support all
devices and commands, with no time or memory
restrictions, and offer sufficient code optimization for
most applications.
MPLAB XC Compilers include an assembler, linker and
utilities. The assembler generates relocatable object
files that can then be archived or linked with other
relocatable object files and archives to create an exe-
cutable file. MPLAB XC Compiler uses the assembler
to produce its object file. Notable features of the
assembler include:
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command-line interface
• Rich directive set
• Flexible macro language
• MPLAB X IDE compatibility
24.3 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel
®
standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code, and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process
24.4 MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
24.5 MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
then be archived or linked with other relocatable object
files and archives to create an executable file. Notable
features of the assembler include:
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command-line interface
• Rich directive set
• Flexible macro language
• MPLAB X IDE compatibility
2015-2016 Microchip Technology Inc. DS60001324B-page 201
PIC32MM0064GPL036 FAMILY
24.6 MPLAB X SIM Software Simulator
The MPLAB X SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB X SIM Software Simulator fully supports
symbolic debugging using the MPLAB XC Compilers,
and the MPASM and MPLAB Assemblers. The soft-
ware simulator offers the flexibility to develop and
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software
development tool.
24.7 MPLAB REAL IC E In-Circ u it
Emulator System
The MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs all 8, 16 and 32-bit MCU, and DSC devices
with the easy-to-use, powerful graphical user interface of
the MPLAB X IDE.
The emulator is connected to the design engineer’s
PC using a high-speed USB 2.0 interface and is
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11)
or with the new high-speed, noise tolerant, Low-
Voltage Differential Signal (LVDS) interconnection
(CAT5).
The emulator is field upgradable through future firmware
downloads in MPLAB X IDE. MPLAB REAL ICE offers
significant advantages over competitive emulators
including full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, logic
probes, a ruggedized probe interface and long (up to
three meters) interconnection cables.
24.8 MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB ICD 3 In-Circuit Debugger System is
Microchip’s most cost-effective, high-speed hardware
debugger/programmer for Microchip Flash DSC and
MCU devices. It debugs and programs PIC Flash
microcontrollers and dsPIC DSCs with the powerful,
yet easy-to-use graphical user interface of the MPLAB
IDE.
The MPLAB ICD 3 In-Circuit Debugger probe is
connected to the design engineer’s PC using a high-
speed USB 2.0 interface and is connected to the target
with a connector compatible with the MPLAB ICD 2 or
MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
supports all MPLAB ICD 2 headers.
24.9 PICkit 3 In-C ircuit Debugger/
Programmer
The MPLAB PICkit 3 allows debugging and program-
ming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
interface of the MPLAB IDE. The MPLAB PICkit 3 is
connected to the design engineer’s PC using a full-
speed USB interface and can be connected to the
target via a Microchip debug (RJ-11) connector (com-
patible with MPLAB ICD 3 and MPLAB REAL ICE). The
connector uses two device I/O pins and the Reset line
to implement in-circuit debugging and In-Circuit Serial
Programming™ (ICSP™).
24.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at V
DDMIN
and V
DDMAX
for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages, and a mod-
ular, detachable socket assembly to support various
package types. The ICSP cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.
PIC32MM0064GPL036 FAMILY
DS60001324B-page 202 2015-2016 Microchip Technology Inc.
24.11 Demonstration/Development
Boards, Evaluati on Kits and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully
functional systems. Most boards include prototyping
areas for adding custom circuitry and provide applica-
tion firmware and source code for examination and
modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a line of evaluation kits and demonstra-
tion software for analog filter design, K
EE
L
OQ
®
security
ICs, CAN, IrDA
®
, PowerSmart battery management,
SEEVAL
®
evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
24.12 Third-Party Development Tools
Microchip also offers a great collection of tools from
third-party vendors. These tools are carefully selected
to offer good value and unique functionality.
• Device Programmers and Gang Programmers
from companies, such as SoftLog and CCS
• Software Tools from companies, such as Gimpel
and Trace Systems
• Protocol Analyzers from companies, such as
Saleae and Total Phase
• Demonstration Boards from companies, such as
MikroElektronika, Digilent
®
and Olimex
• Embedded Ethernet Solutions from companies,
such as EZ Web Lynx, WIZnet and IPLogika
®
2015-2016 Microchip Technology Inc. DS60001324B-page 203
PIC32MM0064GPL036 FAMILY
25.0 INSTRUCTION SET
The PIC32MM0064GPL036 family instruction set
complies with the MIPS
®
Release 3 instruction set
architecture. Only microMIPS32™ instructions are
supported. The PIC32MM0064GPL036 family does not
have the following features:
• Core extend instructions
• Coprocessor 1 instructions
• Coprocessor 2 instructions
Note: Refer to the “MIPS
®
Architecture for
Programmers Volume II-B: The
microMIPS32™ Instruction Set” at
www.imgtec.com for more information.
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DS60001324B-page 204 2015-2016 Microchip Technology Inc.
NOTES:
2015-2016 Microchip Technology Inc. DS60001324B-page 205
PIC32MM0064GPL036 FAMILY
26.0 ELECTRICAL CHARACTERISTICS
This section provides an overview of the PIC32MM0064GPL036 family electrical characteristics. Additional information
will be provided in future revisions of this document as it becomes available.
Absolute maximum ratings for the PIC32MM0064GPL036 family are listed below. Exposure to these maximum rating
conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other
conditions above the parameters indicated in the operation listings of this specification, is not implied.
Absolute Maximum Ratings
(†)
Ambient temperature under bias.............................................................................................................-40°C to +105°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on V
DD
with respect to V
SS
......................................................................................................... -0.3V to +4.0V
Voltage on any general purpose digital or analog pin (not 5.5V tolerant) with respect to V
SS
....... -0.3V to (V
DD
+ 0.3V)
Voltage on any general purpose digital or analog pin (5.5V tolerant) with respect to V
SS
:
When V
DD
= 0V: .......................................................................................................................... -0.3V to +4.0V
When V
DD
2.0V: ....................................................................................................................... -0.3V to +6.0V
Voltage on AV
DD
with respect to V
SS
...................................................(V
DD
– 0.3V) to (lesser of: 4.0V or (V
DD
+ 0.3V))
Voltage on AV
SS
with respect to V
SS
........................................................................................................ -0.3V to +0.3V
Maximum current out of V
SS
pin ...........................................................................................................................100 mA
Maximum current into V
DD
pin
(1)
...........................................................................................................................300 mA
Maximum output current sunk by I/O pin ............................................................................................................... 11 mA
Maximum output current sourced by I/O pin ...........................................................................................................16 mA
Maximum output current sunk by I/O pin with increased current drive strength (RA3, RB8, RB9 and RB15)........17 mA
Maximum output current sourced by I/O pin with increased current drive strength (RA3, RB8, RB9 and RB15) ..........24 mA
Maximum current sunk by all ports .......................................................................................................................300 mA
Maximum current sourced by all ports
(1)
...............................................................................................................300 mA
Note 1: Maximum allowable current is a function of device maximum power dissipation (see Tab le 26-1).
†NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
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DS60001324B-page 206 2015-2016 Microchip Technology Inc.
26.1 DC Characteristi cs
FIGURE 26-1: PIC32MM00 64G PL 036 FA MILY VOLTAGE-FREQUENCY GRAPH
Frequency
Voltage (V
DD
)
2.0V
(1)
25 MHz
3.6V 3.6V
2.0V
(1)
PIC32MM00XXGPL0XX
DC
Note 1: Lower operating boundary is 2.0V or V
BOR
when BOR is enabled.
TABLE 26-1: THERMAL OPERATING CONDITIONS
Rating Symbol Min Typ Max Unit
PIC32MM00XXGPL0XX:
Operating Junction Temperature Range T
J
-40 —+105 °C
Operating Ambient Temperature Range T
A
-40 —+85 °C
Power Dissipation:
Internal Chip Power Dissipation:
P
INT
= V
DD
x (I
DD
– I
OH
)P
D
P
INT
+ P
I
/
O
W
I/O Pin Power Dissipation:
P
I
/
O
= ({V
DD
– V
OH
} x I
OH
) + (V
OL
x I
OL
)
Maximum Allowed Power Dissipation P
DMAX
(T
J
– T
A
)/
JA
W
TABLE 26-2: PACKAGE THERMAL RESISTANCE
(1)
Package Symbol Typ Unit
20-Pin SSOP
JA
87.3 °C/W
20-Pin QFN
JA
43.0 °C/W
28-Pin SPDIP
JA
60.0 °C/W
28-Pin SSOP
JA
71.0 °C/W
28-Pin SOIC
JA
69.7 °C/W
28-Pin UQFN
JA
27.5 °C/W
28-Pin QFN
JA
20.0 °C/W
36-Pin VQFN
JA
31.1 °C/W
40-Pin UQFN
JA
41.0 °C/W
Note 1: Junction to ambient thermal resistance; Theta-
JA
(
JA
) numbers are achieved by package simulations.
2015-2016 Microchip Technology Inc. DS60001324B-page 207
PIC32MM0064GPL036 FAMILY
TABLE 26-3: OPERATING VOLTAGE SPECIFICATIONS
Operating Conditions: 2.0V < V
DD
< 3.6V, -40°C < T
A
< +85°C (unless otherwise stated)
Param
No. Symbol Characteristic Min Max Units Conditions
DC10 V
DD
Supply Voltage 2.0 3.6 V
DC16 V
POR(1)
V
DD
Start Voltage
to Ensure Internal
Power-on Reset Signal
V
SS
— V
DC17A SV
DD(1)
V
DD
Rise Rate
to Ensure Internal
Power-on Reset Signal
0.05 — V/ms 0-3.3V in 66 ms,
0-2.0V in 40 ms
DC17B V
BOR
Brown-out Reset
Voltage on V
DD
Transition, High-to-Low
2.0 2.22 V
Note 1: If the V
POR
or SV
DD
parameters are not met, or the application experiences slow power-down V
DD
ramp
rates, it is recommended to enable and use BOR.
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DS60001324B-page 208 2015-2016 Microchip Technology Inc.
TABLE 26-4: OPERATING CURRENT (I
DD
)
(2)
Operating Conditions: -40°C < T
A
< +85°C (unless otherwise stated)
Parameter No. Typical
(1)
Max Units V
DD
Conditions
DC19 0.45 0.65 mA 2.0V F
SYS
= 1 MHz
0.45 0.65 mA 3.3V
DC23 2.5 3.5 mA 2.0V F
SYS
= 8 MHz
2.5 3.5 mA 3.3V
DC24 7.0 9.2 mA 2.0V F
SYS
= 25 MHz
7.0 9.2 mA 3.3V
DC25 0.26 0.35 mA 2.0V F
SYS
= 32 kHz
0.26 0.35 mA 3.3V
Note 1: Data in the “Typical” column is at +25°C unless otherwise stated. Parameters are for design
guidance only and are not tested.
2: Base I
DD
current is measured with:
• Oscillator is configured in EC mode without PLL (FNOSC<2:0> (FOSCSEL<2:0>) = 010 and
POSCMOD<1:0> (FOSCSEL<9:8>) = 00)
• OSC1 pin is driven with external square wave with levels from 0.3V to V
DD
– 0.3V
• OSC2 is configured as an I/O in Configuration Words (OSCIOFNC (FOSCSEL<10>) = 1)
• FSCM is disabled (FCKSM<1:0> (FOSCSEL<15:14>) = 00)
• Secondary Oscillator circuits are disabled (SOSCEN (FOSCSEL<6>) = 0 and
SOSCSEL (FOSCSEL<12>) = 0)
• Main and low-power BOR circuits are disabled (BOREN<1:0> (FPOR<1:0>) = 00 and
LPBOREN (FPOR<3>) = 0)
• Watchdog Timer is disabled (FWDTEN (FWDT<15>) = 0)
• All I/O pins (except OSC1) are configured as outputs and driving low
• No peripheral modules are operating or being clocked (defined PMDx bits are all ones)
•NOP instructions are executed
2015-2016 Microchip Technology Inc. DS60001324B-page 209
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TABLE 26-5: IDLE CURRENT (I
IDLE
)
(2)
Operating Conditions: -40°C < T
A
< +85°C (unless otherwise stated)
Parameter No. Typical
(1)
Max Units V
DD
Conditions
DC40 0.26 0.46 mA 2.0V F
SYS
= 1 MHz
0.26 0.46 mA 3.3V
DC41 0.85 1.5 mA 2.0V F
SYS
= 8 MHz
0.85 1.5 mA 3.3V
DC42 2.3 3.7 mA 2.0V F
SYS
= 25 MHz
2.3 3.7 mA 3.3V
DC44 0.18 0.34 mA 2.0V F
SYS
= 32 kHz
0.18 0.34 mA 3.3V
Note 1: Data in the “Typical” column is at +25°C unless otherwise stated. Parameters are for design
guidance only and are not tested.
2: Base I
IDLE
current is measured with:
• Oscillator is configured in EC mode without PLL (FNOSC<2:0> (FOSCSEL<2:0>) = 010 and
POSCMOD<1:0> (FOSCSEL<9:8>) = 00)
• OSC1 pin is driven with external square wave with levels from 0.3V to V
DD
– 0.3V
• OSC2 is configured as I/O in Configuration Words (OSCIOFNC (FOSCSEL<10>) = 1)
• FSCM is disabled (FCKSM<1:0> (FOSCSEL<15:14>) = 00)
• Secondary Oscillator circuits are disabled (SOSCEN (FOSCSEL<6>) = 0 and
SOSCSEL (FOSCSEL<12>) = 0)
• Main and low-power BOR circuits are disabled (BOREN<1:0> (FPOR<1:0>) = 00 and
LPBOREN (FPOR<3>) = 0)
• Watchdog Timer is disabled (FWDTEN (FWDT<15>) = 0)
• All I/O pins (excepting OSC1) are configured as outputs and driving low
• No peripheral modules are operating or being clocked (defined PMDx bits are all ones)
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TABLE 26-6: POWER-DOWN CURRENT (I
PD
)
(2)
Parameter
No. Typical
(1)
Max Units Operating
Temperature V
DD
Conditions
DC60 134 198 µA -40°C
2.0V
Sleep with active main voltage regulator
(VREGS (PWRCON<0>) = 1,
RETEN (PWRCON<1>) =0)
136 208 µA +25°C
141 217 µA +85°C
139 209 µA -40°C
3.3V141 217 µA +25°C
143 231 µA +85°C
DC61 4.3 11.7 µA -40°C
2.0V Sleep with main voltage regulator in
Standby mode
(VREGS (PWRCON<0>) = 0,
RETEN (PWRCON<1>) = 0)
5.1 15.6 µA +25°C
11.4 34.3 µA +85°C
6.1 16.8 µA -40°C
3.3V6.9 20.1 µA +25°C
12.7 36.0 µA +85°C
DC62 2.3 — µA -40°C
2.0V Sleep with enabled retention voltage
regulator (VREGS (PWRCON<0>) = 1,
RETEN (PWRCON<1>) = 1,
RETVR (FPOR<2>) = 0)
2.7 — µA +25°C
5.2 — µA +85°C
2.3 — µA -40°C
3.3V2.7 — µA +25°C
5.4 — µA +85°C
DC63 0.28 — µA -40°C
2.0V Sleep with enabled retention voltage
regulator (VREGS (PWRCON<0>) = 0,
RETEN (PWRCON<1>) = 1,
RETVR (FPOR<2>) = 0)
0.44 — µA +25°C
2.52 — µA +85°C
0.29 — µA -40°C
3.3V0.44 — µA +25°C
2.62 — µA +85°C
Note 1: Data in the “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design
guidance only and are not tested.
2: Base I
PD
is measured with:
• Oscillator is configured in FRC mode without PLL (FNOSC<2:0> (FOSCSEL<2:0>) = 000)
• OSC2 is configured as I/O in Configuration Words (OSCIOFNC (FOSCSEL<10>) = 1)
• FSCM is disabled (FCKSM<1:0> (FOSCSEL<15:14>) = 00)
• Secondary Oscillator circuits are disabled (SOSCEN (FOSCSEL<6>) = 0 and
SOSCSEL (FOSCSEL<12>) = 0)
• Main and low-power BOR circuits are disabled (BOREN<1:0> (FPOR<1:0>) = 00 and
LPBOREN (FPOR<3>) = 0)
• Watchdog Timer is disabled (FWDTEN (FWDT<15>) = 0)
• All I/O pins are configured as outputs and driving low
• No peripheral modules are operating or being clocked (defined PMDx bits are all ones)
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TABLE 26-7: INCREMENTAL PERIPHERALCURRENT
(2)
Operating Conditions: 2.0V < V
DD
< 3.6V, -40°C < T
A
< +85°C (unless otherwise stated)
Parameter No. Typ
(1)
Units Conditions
Brown-out Reset Incremental Current (BOR)
DC71 2.7 µA
Watchdog Timer Incremental Current (WDT)
DC72 80 nA with LPRC
High/Low-Voltage Detect Incremental Current (HLVD)
DC73 2.1 µA
Real-Time Clock and Cale ndar Incremental Current (RTCC)
DC74 1.0 µA with SOSC
DC75 0.4 µA with LPRC
ADC Incremental Current (ADC
DC76 450 µA 12-bit, 100 ksps, with FRC
FRC Oscillator Incremental Current (FRC)
DC78 305 µA
PLL Incremen tal Curr ent (PLL)
DC79 1230 µA F
VCO
= 24 MHz
DC80 1550 µA F
VCO
= 48 MHz
Digital-to-Analog Converter Incremental Current, CDAC (DAC)
DC81 27.5 µA
Low- Powe r BO R In cremen tal Curre n t (LPBOR)
DC82 200 nA
Comparator Incremental Curr ent (CMP)
DC83 24.0 µA
Note 1: Data in the “Typ” column is for design guidance only and is not tested.
2: The current is an additional current consumed when the module is enabled. This current should be
added to the base I
PD
current.
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TABLE 26-8: I/O PIN INPUT SPECIFICATIONS
Operating Conditions: 2.0V V
DD
3.6V, -40°C T
A
+85°C (unless otherwise stated)
Param
No. Symbol Characteristic Min Typ
(1)
Max Units Conditions
V
IL
Input Low Voltage
(2)
DI10 I/O Pins with ST Buffer V
SS
—0.2 V
DD
V
DI15 MCLR V
SS
—0.2 V
DD
V
DI16 OSC1/CLKI (XT mode) V
SS
—0.2 V
DD
V
DI17 OSC1/CLKI (HS mode) V
SS
—0.2 V
DD
V
V
IH
Input High Voltage
(2)
DI20 I/O Pins with ST Buffer:
without 5V Tolerance
with 5V Tolerance
0.8 V
DD
0.8 V
DD
—
—
V
DD
5.5
V
V
DI25 MCLR 0.8 V
DD
— V
DD
V
DI26 OSCI/CLKI (XT mode) 0.7 V
DD
— V
DD
V
DI27 OSC1/CLKI (HS mode) 0.7 V
DD
— V
DD
V
DI30 I
CNPU
CNPUx Pull-up Current —350 — µA V
PIN
= 0V, V
DD
= 3.3V
DI30A I
CNPD
CNPDx Pull-Down Current —300 — µA V
PIN
= 3.3V, V
DD
= 3.3V
I
IL
Input Le ak age Cu rren t
DI50 I/O Pins – 5V Tolerant —0.1 1.0 µA V
PIN
= 3.3V, V
DD
= 3.3V,
pin at high-impedance
DI51 I/O Pins – Not 5V Tolerant —0.1 1.0 µA V
PIN
= 3.3V, V
DD
= 3.3V,
pin at high-impedance
DI55 MCLR —0.1 1.0 µA V
PIN
= 3.3V, V
DD
= 3.3V
DI56 OSC1/CLKI —0.1 1.0 µA V
PIN
= 3.3V, V
DD
= 3.3V
Note 1: Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
2: Refer to Ta b l e 1-1 for I/O pin buffer types.
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TABLE 26-9: I/O PIN INPUT INJECTION CURRE NT SPECIFICATIONS
Operating Conditions: 2.0V V
DD
3.6V, -40°C T
A
+85°C (unless otherwise stated)
Param.
No. Symbol Characteristics Min. Max. Units Conditions
DI60a I
ICL
Input Low Injection
Current 0-5
(1,4)
mA This parameter applies to all pins.
DI60b I
ICH
Input High Injection
Current 0+5
(2,3,4)
mA This parameter applies to all pins,
with the exception of all 5V tolerant
pins and SOSCI. Maximum I
ICH
current for these exceptions is
0 mA.
DI60c I
ICT
Total Input Injection
Current (sum of all I/O
and control pins)
-20
(5)
+20
(5)
mA Absolute instantaneous sum of
all ± input injection currents from
all I/O pins,
( | I
ICL
+ | I
ICH
| ) I
ICT
Note 1: V
IL
Source < (V
SS
– 0.3). Characterized but not tested.
2: V
IH
Source > (V
DD
+ 0.3) for non-5V tolerant pins only.
3: Digital 5V tolerant pins do not have an internal high-side diode to V
DD
, and therefore, cannot tolerate any
“positive” input injection current.
4: Injection currents can affect the ADC results.
5: Any number and/or combination of I/O pins, not excluded under I
ICL
or I
ICH
conditions, are permitted
provided the “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit.
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TABLE 26-10: I/O PIN OUTPUT SPECIFICATIONS
Operating Conditions: 2.0V V
DD
3.6V, -40°C TA +85°C (unless otherwise stated)
Param
No. Symbol Characteristic Min Max Units Conditions
V
OL
Output Low Voltage
DO10 I/O Ports —0.36 V I
OL
= 6.0 mA, V
DD
= 3.6V
—0.21 V I
OL
= 3.0 mA, V
DD
= 2V
DO16 RA3, RB8, RB9 and RB15 I/O Ports —0.16 V I
OL
= 6.0 mA, V
DD
= 3.6V
—0.12 V I
OL
= 3.0 mA, V
DD
= 2V
V
OH
Output High Voltage
DO20 I/O Ports 3.25 — V I
OH
= -6.0 mA, V
DD
= 3.6V
1.4 — V I
OH
= -3.0 mA, V
DD
= 2V
DO26 RA3, RB8, RB9 and RB15 I/O Ports 3.3 — V I
OH
= -6.0 mA, V
DD
= 3.6V
1.55 — V I
OH
= -3.0 mA, V
DD
= 2V
TABLE 26-11: PROGRAM FLASH MEMORY SPECIFICATIONS
Operating Conditions: 2.0V V
DD
3.6V, -40°C T
A
+85°C (unless otherwise stated)
Param
No. Symbol Characteristic Min Typ
(1)
Max Units Conditions
D130 E
P
Cell Endurance 10000 20000 — E/W
D131 V
ICSP
V
DD
for In-Circuit Serial
Programming™ (ICSP™)
V
BOR
—3.6 V
D132 V
RTSP
V
DD
for Run-Time
Self-Programming (RTSP)
2.0 —3.6 V
D133 T
IW
Self-Timed Double-Word
Write Cycle Time
19.7 21.0 22.3 µs 8 bytes, data is not all ‘1’s
Self-Timed Row Write
Cycle Time
1.3 1.4 1.5 ms 256 bytes, data is not all ‘1’s,
SYSCLK > 2 MHz
D133 T
IE
Self-Timed Page Erase
Time
15.0 16.0 17.0 ms 2048 bytes
D134 T
RETD
Characteristic Retention 20 — — Year If no other specifications are violated
D136 T
CE
Self-Timed Chip Erase
Time
16.0 17.0 18.0 ms
Note 1: Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
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TABLE 26-12: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
TABLE 26-13: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS
Operating Conditions: 2.0V V
DD
3.6V, -40°C T
A
+85°C (unless otherwise stated)
Param
No. Symbol Characteristics Min Typ
(1)
Max Units Comments
DVR10 V
BG
Band Gap Reference Voltage —1.2 — V
DVR20 V
RGOUT
Regulator Output Voltage —1.8 — V V
DD
> 1.9V
DVR21 C
EFC
External Filter Capacitor Value 4.7 10 —µF Series Resistance < 3
recommended; < 5 required
DVR30 V
LVR
Low-Voltage Regulator
Output Voltage
0.9 —1.2 VRETEN = 1,
RETVR (FPOR<2>) = 0
Note 1: Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
Operating Conditions: 2.0V V
DD
3.6V, -40°C T
A
+85°C (unless otherwise stated)
Param
No. Symbol Characteristic Min Typ
(2)
Max Units
DC18 V
HLVD(1)
HLVD Voltage on V
DD
Transition
HLVDL<3:0> = 0101 3.25 —3.63 V
HLVDL<3:0> = 0110 2.95 —3.30 V
HLVDL<3:0> = 0111 2.75 —3.09 V
HLVDL<3:0> = 1000 2.65 —2.98 V
HLVDL<3:0> = 1001 2.45 —2.80 V
HLVDL<3:0> = 1010 2.35 —2.69 V
HLVDL<3:0> = 1011 2.25 —2.55 V
HLVDL<3:0> = 1100 2.15 —2.44 V
HLVDL<3:0> = 1101 2.08 —2.33 V
HLVDL<3:0> = 1110 2.00 —2.22 V
DC101 V
THL
HLVD Voltage on
LVDIN Pin Transition
HLVDL<3:0> = 1111 —1.2 — V
Note 1: Trip points for values of HLVD<3:0>, from ‘0000’ to ‘0100’, are not implemented.
2: Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
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TABLE 26-14: COMPARATOR SPECIFICATIONS
TABLE 26-15: VOLTAGE REFERENCE SPECIFICATIONS
Operating Condit ions : 2.0V < V
DD
< 3.6V, -40°C < T
A
< +85°C (unless otherwise stated)
Param
No. Symbol Characteristic Min Typ
(2)
Max Units
D300 V
IOFF
Input Offset Voltage -20 — 20 mV
D301 V
ICM
Input Common-Mode Voltage AV
SS
– 0.3V — AV
DD
+ 0.3V V
D307 T
RESP(1)
Response Time — 150 — ns
Note 1: Measured with one input at V
DD
/2 and the other transitioning from V
SS
to V
DD
.
2: Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
Operating Condit ions : 2.0V < V
DD
< 3.6V, -40°C < T
A
< +85°C (unless otherwise stated)
Param
No. Symbol Characteristic Min Typ
(2)
Max Units
VRD310 T
SET
Settling Time
(1)
——10µs
VRD311 VR
A
Accuracy -1 — 1 LSb
VRD312 VR
UR
Unit Resistor Value (R) —4.5—k
Note 1: Measures the interval while VRDAT<4:0> transitions from ‘11111’ to ‘00000’.
2: Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
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26.2 AC Characteristics and Timing Parameter s
FIGURE 26-2: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
TABLE 26-16: CAPACITIVE LOADING CONDITIONS ON OUTPUT PINS
Param
No. Symbol Characteristic Min Max Units Conditions
DO50 C
OSCO
OSC2/CLKO Pin —15 pF In XT and HS modes when
external clock is used to drive
OSC1/CLKI
DO56 C
IO
All I/O Pins and OSC2 —50 pF EC mode
V
DD
/2
C
L
R
L
Pin
Pin
V
SS
V
SS
C
L
R
L
=464
C
L
= 50 pF for all pins except OSC2/CLKO
15 pF for OSC2/CLKO output
Load Condition 1 – for all pins except OSC2/CLKO Load Condition 2 – for OSC2/CLKO
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FIGURE 26-3: EXTERN AL CLOCK TIMING
TABLE 26-17: EXTERNAL CLOCK TIMING REQUIREMENTS
Operating Conditions: 2.0V V
DD
3.6V, -40°C T
A
+85°C (unless otherwise stated)
Param
No. Symbol Characteristic Min Typ
(1)
Max Units Conditions
OS10 F
OSC
External CLKI Frequency DC
2
—
—
25
12.5
MHz
MHz
EC
ECPLL
(2)
Oscillator Frequency 3.5
3.5
10
10
31
—
—
—
—
—
10
10
25
25
50
MHz
MHz
MHz
MHz
kHz
XT
XTPLL
(2)
HS
HSPLL
(2)
SOSC
OS30 To sL ,
To s H
External Clock in (OSC1)
High or Low Time
0.45 x T
OSC
—0.55 x T
OSC
ns EC
OS31 To sR ,
To s F
External Clock in (OSC1)
Rise or Fall Time
— — 20 ns EC
OS40 Tc kR CLKO Rise Time
(3)
—15 20 ns
OS41 Tc kF CLKO Fall Time
(3)
—15 20 ns
Note 1: Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
2: PLL dividers and postscalers must be configured so that the system clock frequency does not exceed the
maximum operating frequency.
3: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin.
OSCI
CLKO
OS10 OS30 OS30
OS40 OS41
OS31OS31
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TABLE 26-18: PLL CLOCK TIMING SPECIFICATIONS
Operating Conditions: 2.0V V
DD
3.6V, -40°C T
A
+85°C (unless otherwise stated)
Param
No. Symbol Characteristic Min Max Units
OS50 F
PLLI
PLL Input Frequency Range
(1)
224MHz
OS54 F
PLLO
PLL Output Frequency Range
(1)
16 96 MHz
OS52 T
LOCK
PLL Start-up Time (Lock Time) — 24 µs
OS53 D
CLK
CLKO Stability (Jitter) -0.12 0.12 %
Note 1: These parameters are characterized but not tested in manufacturing.
TABLE 26-19: INTERNAL OSCILLATOR ACCURACY
(1)
Operating Conditions: 2.0V V
DD
3.6V, -40°C T
A
+85°C (unless otherwise stated)
Param No. Characteristic Min Typ
(2)
Max Units
F20 FRC Accuracy @ 8 MHz -3 — 3 %
F21 LPRC @ 32 kHz -20 —20 %
F22 FRC Tune Step-Size (in OSCTUN register) —0.05 —%/Bit
Note 1: To achieve this accuracy, physical stress applied to the microcontroller package (ex., by flexing the PCB)
must be kept to a minimum.
2: Data in the “Typ” column is 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
TABLE 26-20: INTERNAL OSCILLATOR START-UP TIME
Operating Conditions: 2.0V V
DD
3.6V, -40°C T
A
+85°C (unless otherwise stated)
Param
No. Symbol Characteristic Max Units
FR0 T
FRC
FRC Oscillator Start-up Time 2µs
FR1 T
LPRC
Low-Power RC Oscillator Start-up Time 70 µs
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FIGURE 26-4: CLKO AND I/O TIMING CHARACTERISTICS
TABLE 26-21: CLKO AND I/O TIMING REQUIREMENTS
Operating Conditions: 2.0V V
DD
3.6V, -40°C T
A
+85°C (unless otherwise stated)
Param
No. Symbol Characteristic Min Typ
(1)
Max Units
DO31 T
IO
RPort Output Rise Time —10 25 ns
DO32 T
IO
FPort Output Fall Time —10 25 ns
DI35 T
INP
INTx Input Pin High or Low
Time
10 — — ns
DI40 T
RBP
CNx Input Pin High or Low Time 10 — — ns
Note 1: Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
Note: Refer to Figure 26-2 for load conditions.
I/O Pin
(Input)
I/O Pin
(Output)
DI35
Old Value New Value
DI40
DO31
DO32
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TABLE 26-22: RESET, BROWN-OUT RESET AND SLEEP MODES TIMING SPECIFICATIONS
Operating Conditions: 2.0V V
DD
3.6V, -40°C T
A
+85°C (unless otherwise stated)
Param
No. Symbol Characteristic Min Typ
(1)
Max Units Conditions
SY10 T
MCL
MCLR Pulse Width (Low) 2 — — µs
SY13 T
IOZ
I/O High-Impedance from
MCLR Low
—1—µs
SY25 T
BOR
Brown-out Reset Pulse
Width
1——µsV
DD
V
BOR
SY45 T
RST
Reset State Time — 25 — µs
SY71 T
WAKE(2)
Wake-up Time with Main
Voltage Regulator
— 22 — µs Sleep wake-up with
VREGS = 0, RETEN = 0,
RETVR = 1
— 3.8 — µs Sleep wake-up with
VREGS = 1, RETEN = 0,
RETVR = 1
SY72 T
WAKELVR(2)
Wake-up Time with
Retention Low-Voltage
Regulator
— 163 — µs Sleep wake-up with
VREGS = 0, RETEN = 1,
RETVR = 0
— 23 — µs Sleep wake-up with
VREGS = 1, RETEN = 1,
RETVR = 0
Note 1: Data in the “Typ.” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
2: The parameters are measured with the external clock source (EC). To get the full wake-up time, the
oscillator start-up time must be added.
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FIGURE 26-5: TIMER1 EXTERNAL CLOCK TIMING CHARACTERISTICS
T1CK
TMR1
TA10 TA11
TA15 TA20
TABLE 26-23: MCCP/SCCP TIMER1 EXTERNAL CLOCK TIMING CHARACTERISTICS
Operating Conditions: 2.0V V
DD
3.6V, -40°C T
A
+85°C (unless otherwise stated)
Param.
No. Symbol Characteristics
(1)
Min Max Units Conditions
TA10 T
CKH
T1CK High Time Synchronous 1—T
PBCLK
Must also meet Parameter TA15
Asynchronous 10 —ns
TA11 T
CKL
T1CK Low Time Synchronous 1—T
PBCLK
Must also meet Parameter TA15
Asynchronous 10 —ns
TA15 T
CKP
T1CK Input
Period
Synchronous 2—T
PBCLK
Asynchronous 20 —ns
TA20 T
CKEXTMRL
Delay from External T1CK Clock
Edge to Timer Increment
—3T
PBCLK
Synchronous mode
Note 1: These parameters are characterized but not tested in manufacturing.
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FIGURE 26-6: MCCP/SCCP TIMERx EXTERNAL CLOCK TIMING REQUIREMENTS
TCKIx
CCPxTMR
TMR10 TMR11
TMR15 TMR20
TABLE 26-24: MCCP/SCCP TIMING REQUIREMENTS
Operating Conditions: 2.0V V
DD
3.6V, -40°C T
A
+85°C (unless otherwise stated)
Param.
No. Symbol Characteristics
(1)
Min Max Units Conditions
TMR10 T
CKH
TCKIx High Time Synchronous 1—T
PBCLK
Must also meet
Parameter TMR15
Asynchronous 10 —ns
TMR11 T
CKL
TCKIx Low Time Synchronous 1—T
PBCLK
Must also meet
Parameter TMR15
Asynchronous 10 —ns
TMR15 T
CKP
TCKIx Input Period Synchronous 2—T
PBCLK
Asynchronous 20 —ns
TMR20 T
CKEXTMRL
Delay from External TCKIx Clock Edge
to Timer Increment
—1T
PBCLK
Note 1: These parameters are characterized but not tested in manufacturing.
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FIGURE 26-7: MCCP AND SCCP INPUT CAPTURE x MODE TIMING CHARACTERISTICS
FIGURE 26-8: MCCP AND SCCP OUTPUT COMPARE x MODE TIMING CHARACTERISTICS
TABLE 26-26: MCCP AND SCCP OUTPUT COMPARE x MODE TIMING REQUIREMENTS
ICMx
IC10 IC11
IC15
TABLE 26-25: MCCP AND SCCP INPUT CAPTURE x MODE TIMING REQUIREMENTS
Operating Conditions: 2.0V V
DD
3.6V, -40°C T
A
+85°C (unless otherwise stated)
Param.
No. Symbol Characteristics
(1)
Min Max Units Conditions
IC10 T
ICL
ICMx Input Low Time 25 —nsMust also meet Parameter IC15
IC11 T
ICH
ICMx Input High Time 25 —nsMust also meet Parameter IC15
IC15 T
ICP
ICMx Input Period 50 —ns
Note 1: These parameters are characterized but not tested in manufacturing.
Operating Conditions: 2.0V V
DD
3.6V, -40°C T
A
+85°C (unless otherwise stated)
Param.
No. Symbol Characteristics
(1)
Min Typ Max Units
OC10 T
OCF
OCMx Output Fall Time —10 25 ns
OC11 T
OCR
OCMx Output Rise Time —10 25 ns
Note 1: These parameters are characterized but not tested in manufacturing.
OCMx
OC11 OC10
Note: Refer to Figure 26-2 for load conditions.
2015-2016 Microchip Technology Inc. DS60001324B-page 225
PIC32MM0064GPL036 FAMILY
FIGURE 26-9: MCCP AND SCCP PWMx MODE TIMING CHARACTERISTICS
OCFA/OCFB
OCMx OCMx is Tri-Stated
OC20
OC15
TABLE 26-27: MCCP AND SCCP PWM MODE TIMING REQUIREMENTS
Operating Conditions: 2.0V V
DD
3.6V, -40°C T
A
+85°C (unless otherwise stated)
Param
No. Symbol Characteristics
(1)
Min Max Units
OC15 T
FD
Fault Input to PWM I/O Change —30 ns
OC20 T
FLT
Fault Input Pulse Width 10 —ns
Note 1: These parameters are characterized but not tested in manufacturing.
PIC32MM0064GPL036 FAMILY
DS60001324B-page 226 2015-2016 Microchip Technology Inc.
FIGURE 26-10: SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS
FIGURE 26-11: SP Ix MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS
SCKx
(CKP =
0
)
SCKx
(CKP =
1
)
SDOx
SDIx
SP10 SP10
SP40 SP41
SP35
MSb LSb
LSb InMSb In
SCKx
(CKP =
0
)
SCKx
(CKP =
1
)
SDOx
SDIx
SP36
SP35
LSb In
LSb
SP10 SP10
SP40 SP41
MSb In
MSb
2015-2016 Microchip Technology Inc. DS60001324B-page 227
PIC32MM0064GPL036 FAMILY
FIGURE 26-12: SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS
TABLE 26-28: SPIx MO DUL E MAS TER MODE TIMING REQUIREMENTS
Operating Conditions: 2.0V V
DD
3.6V, -40°C T
A
+85°C (unless otherwise stated)
Param.
No. Symbol Characteristics
(1)
Min Max Units
SP10 T
SC
L, T
SC
H SCKx Output Low or High Time 10 — ns
SP35 T
SC
H2
DO
V,
T
SC
L2
DO
V
SDOx Data Output Valid after SCKx Edge — 7 ns
SP36 T
DO
V2
SC
,
T
DO
V2
SC
L
SDOx Data Output Setup to First SCKx Edge 7 — ns
SP40 T
DI
V2
SC
H,
T
DI
V2
SC
L
Setup Time of SDIx Data Input to SCKx Edge 7 — ns
SP41 T
SC
H2
DI
L,
T
SC
L2
DI
L
Hold Time of SDIx Data Input to SCKx Edge 7 — ns
Note 1: These parameters are characterized but not tested in manufacturing.
SSx
SCKx
(CKP =
0
)
SCKx
(CKP =
1
)
SDOx
SP50
SP40 SP41
SP51
SP35
MSb LSb
LSb In
SP52
SP71 SP70
SDIx MSb In
PIC32MM0064GPL036 FAMILY
DS60001324B-page 228 2015-2016 Microchip Technology Inc.
FIGURE 26-13: SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS
SSx
SCKx
(CKP =
0
)
SCKx
(CKP =
1
)
SDOx
SDIx
SP60
MSb LSb
SP51
LSb In
SP52
SP71
SP40 SP41
SP50
SP70
SP35
MSb In
TA BL E 26-29: SPIx MODULE SL AV E MODE TIMING REQUIREMENTS
Operating Conditions: 2.0V V
DD
3.6V, -40°C T
A
+85°C (unless otherwise stated)
Param.No. Symbol Characteristics
(1)
Min Max Units
SP70 T
SC
LSCKx Input Low Time 10 —ns
SP71 T
SC
HSCKx Input High Time 10 —ns
SP35 T
SC
H2
DO
V,
T
SC
L2
DO
V
SDOx Data Output Valid after SCKx Edge —10 ns
SP40 T
DI
V2
SC
H,
T
DI
V2
SC
L
Setup Time of SDIx Data Input to SCKx Edge 0 — ns
SP41 T
SC
H2
DI
L,
T
SC
L2
DI
L
Hold Time of SDIx Data Input to SCKx Edge 7 — ns
SP50 T
SS
L2
SC
H,
T
SS
L2
SC
L
SSx to SCKx or SCKx Input 40 —ns
SP51 T
SS
H2
DO
ZSSx to SDOx Output High-Impedance 2.5 12 ns
SP52 T
SC
H2
SS
H
T
SC
L2
SS
H
SSx after SCKx Edge 10 —ns
SP60 T
SS
L2
DO
VSDOx Data Output Valid after SSx Edge —12.5 ns
Note 1: These parameters are characterized but not tested in manufacturing.
2015-2016 Microchip Technology Inc. DS60001324B-page 229
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TABLE 26-30: ADC MODULE INPUTS SPECIFICATIONS
Operating Conditions: 2.0V V
DD
3.6V, -40°C T
A
+85°C (unless otherwise stated)
Param
No. Symbol Characteristic Min Max Units
Reference I npu ts
AD05 V
REFH
Reference Voltage High AV
SS
+ 1.7 AV
DD
V
AD06 V
REFL
Reference Voltage Low AV
SS
AV
DD
– 1.7 V
AD07 V
REF
Absolute Reference
Voltage
AV
SS
– 0.3 AV
DD
+ 0.3 V
Anal og Input s
AD10 V
INH
-V
INL
Full-Scale Input Span V
REFL
V
REFH
V
AD11 V
IN
Absolute Input Voltage AV
SS
– 0.3 AV
DD
+ 0.3 V
AD12 V
INL
Absolute V
INL
Input Voltage AV
SS
– 0.3 AV
DD
+ 0.3 V
AD17 R
IN
Recommended Impedance of Analog
Voltage Source
—2.5K
TABLE 26-31: ADC ACCURACY AND CONVERSION TIMING REQUIREMENTS FOR 12-BIT MODE
(1)
Operating Condit ions : V
DD
= 3.3V, AV
SS
= V
REFL
= 0V, AV
DD
= V
REFH
= 3.3V, -40°C T
A
+85°C
Param
No. Symbol Characteristic Min Typ
(2)
Max Units
ADC Accuracy
AD20B Nr Resolution —12 —bits
AD21B INL Integral Nonlinearity —±2.5 ±3.5 LSb
AD22B DNL Differential Nonlinearity —±0.75 +1.75/-0.95 LSb
AD23B G
ERR
Gain Error –+2 +3 LSb
AD24B E
OFF
Offset Error —+1 +2 LSb
Clock Parameters
AD50B T
AD
ADC Clock Period 280 — — ns
AD61B t
PSS
Sample Start Delay from Setting
Sample bit (SAMP)
2—3T
AD
Conv ersi on Rat e
AD55B t
CONV
Conversion Time —14—T
AD
AD56B F
CNV
Throughput Rate — — 200 ksps
Note 1: Measurements are taken with the external V
REF
+ and V
REF
- used as the ADC voltage reference.
2: Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
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DS60001324B-page 230 2015-2016 Microchip Technology Inc.
TABLE 26-32: ADC ACCURACY AND CONVERSION TIMING REQUIREMENTS FOR 10-BIT MODE
(1)
Operating Condit ions : V
DD
= 3.3V, AV
SS
= V
REFL
= 0V, AV
DD
= V
REFH
= 3.3V, -40°C T
A
+85°C
Param
No. Symbol Characteristic Min Typ
(2)
Max Units
ADC Accuracy
AD20A Nr Resolution —10 —bits
AD21A INL Integral Nonlinearity —±0.5 —LSb
AD22A DNL Differential Nonlinearity —±0.5 —LSb
AD23A G
ERR
Gain Error —+0.75 —LSb
AD24A E
OFF
Offset Error —+0.25 —LSb
Clock Parame ters
AD50A T
AD
ADC Clock Period 200 — — ns
AD61A t
PSS
Sample Start Delay from Setting
Sample bit (SAMP)
2—3T
AD
Conv ersi on Rat e
AD55A t
CONV
Conversion Time —12—T
AD
AD56A F
CNV
Throughput Rate — — 300 ksps
Note 1: Measurements are taken with the external V
REF
+ and V
REF
- used as the ADC voltage reference.
2: Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
2015-2016 Microchip Technology Inc. DS60001324B-page 231
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FIGURE 26-14: EJTAG TIMING CHARACTERISTICS
T
TCKcyc
T
TCKhigh
T
TCKlow
T
rf
T
rf
T
rf
T
rf
T
Tset up
T
Thold
T
TDOout
T
TDOzstate
Defined Undefined
T
TRST*low
T
rf
TCK
TDO
T
RST
*
TDI
TMS
TABLE 26-33: EJTAG TIMING REQUIREMENTS
Operating Conditions: 2.0V V
DD
3.6V, -40°C T
A
+85°C (unless otherwise stated)
Param.
No. Symbol Description
(1)
Min Max Units Conditions
EJ1 T
TCKCYC
TCK Cycle Time 25 —ns
EJ2 T
TCKHIGH
TCK High Time 10 —ns
EJ3 T
TCKLOW
TCK Low Time 10 —ns
EJ4 T
TSETUP
TAP Signals Setup Time before
Rising TCK
5 — ns
EJ5 T
THOLD
TAP Signals Hold Time after
Rising TCK
3 — ns
EJ6 T
TDOOUT
TDO Output Delay Time from
Falling TCK
— 5 ns
EJ7 T
TDOZSTATE
TDO 3-State Delay Time from
Falling TCK
— 5 ns
EJ8 T
TRSTLOW
T
RST
Low Time 25 —ns
EJ9 T
RF
TAP Signals Rise/Fall Time,
All Input and Output
— — ns
Note 1: These parameters are characterized but not tested in manufacturing.
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DS60001324B-page 232 2015-2016 Microchip Technology Inc.
NOTES:
2015-2016 Microchip Technology Inc. DS60001324B-page 233
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27.0 PACKAGING INFORMATION
27.1 Package Marking Information
Legend: XX...X Customer-specific information
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
*All packages are Pb-free
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
28-Lead SPDIP
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
Example
PIC32MM0064GPL028
1610017
XXXXXXXX
20-Lead QFN
XXXXXXXX
YYWWNNN
32MM0016
Example
GPL020
1610017
28-Lead SOIC (7.5 mm)
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
YYWWNNN
Example
PIC32MM0032GPL028
1610017
20-Lead SSOP
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
Example
PIC32MM0016
GPL020
1610017
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DS60001324B-page 234 2015-2016 Microchip Technology Inc.
27.1 Package Marking Information (Continue d)
XXXXXXXX
28-Lead QFN
XXXXXXXX
YYWWNNN
32MM0032
Example
GPL028
1610017
XXXXXXXX
28-Lead UQFN
XXXXXXXX
YYWWNNN
32MM0032
Example
GPL028
1610017
36-Lead VQFN
40-Lead UQFN
XXXXXXXX
XXXXXXXX
YYWWNNN
32MM0064
Example
GPL036
1610017
XXXXXXXX
XXXXXXXX
YYWWNNN
32MM0064
GPL036
1610017
Example
28-Lead SSOP
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
Example
PIC32MM0064
GPL028
1610017
2015-2016 Microchip Technology Inc. DS60001324B-page 235
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27.2 Package Details
The following sections give the technical details of the packages.
!"
#$
#$
φ
L
L1
A2 c
e
b
A1
A
12
NOTE 1
E1
E
D
N
PIC32MM0064GPL036 FAMILY
DS60001324B-page 236 2015-2016 Microchip Technology Inc.
RECOMMENDED LAND PATTERN
Microchip Technology Drawing No. C04-2072B
20-Lead Plastic Shrink Small Outline (SS) - 5.30 mm Body [SSOP]
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
c
G
E
X1
Y1
SILK SCREEN
Dimension Limits
Units
CContact Pad Spacing
Contact Pitch
MILLIMETERS
0.65 BSC
MIN
E
MAX
7.20
Contact Pad Length (X20)
Contact Pad Width (X20)
Y1
X1
1.75
0.45
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
GDistance Between Pads 0.20
NOM
0.45
0.65
2015-2016 Microchip Technology Inc. DS60001324B-page 237
PIC32MM0064GPL036 FAMILY
%&'#()*+*+, !%&#"
#$
#$
D
EXPOSED
PAD
E
E2
2
1
N
TOP VIEW NOTE 1
N
L
K
b
e
D2
2
1
A
A1
A3
BOTTOM VIEW
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DS60001324B-page 238 2015-2016 Microchip Technology Inc.
#$
2015-2016 Microchip Technology Inc. DS60001324B-page 239
PIC32MM0064GPL036 FAMILY
- ./ !./"
#$
#$
NOTE 1
N
12
D
E1
eB
c
E
L
A2
eb
b1
A1
A
3
PIC32MM0064GPL036 FAMILY
DS60001324B-page 240 2015-2016 Microchip Technology Inc.
- !"
#$
#$
L
L1
c
A2
A1
A
E
E1
D
N
12
NOTE 1 b
e
φ
2015-2016 Microchip Technology Inc. DS60001324B-page 241
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Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
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DS60001324B-page 242 2015-2016 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2015-2016 Microchip Technology Inc. DS60001324B-page 243
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Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
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DS60001324B-page 244 2015-2016 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2015-2016 Microchip Technology Inc. DS60001324B-page 245
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DS60001324B-page 246 2015-2016 Microchip Technology Inc.
2015-2016 Microchip Technology Inc. DS60001324B-page 247
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-%&'#()0+0 !%&#"
12(
#$
PIC32MM0064GPL036 FAMILY
DS60001324B-page 248 2015-2016 Microchip Technology Inc.
B
A
0.10 C
0.10 C
0.07 C A B
0.05 C
(DATUM B)
(DATUM A)
C
SEATING
PLANE
NOTE 1
1
2
N
2X
TOP VIEW
SIDE VIEW
BOTTOM VIEW
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
NOTE 1
1
2
N
0.10 C A B
0.10 C A B
0.10 C
0.08 C
Microchip Technology Drawing C04-333-M6 Rev B Sheet 1 of 2
28-Lead Ultra Thin Plastic Quad Flat, No Lead Package (M6) - 4x4x0.6 mm Body [UQFN]
D
E
A
(A3)
28X b
e
e
2
2X
D2
E2
K
L
28X
A1
With Corner Anchors
4x b2
4x b2
4x b1
4x b1
2015-2016 Microchip Technology Inc. DS60001324B-page 249
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Microchip Technology Drawing C04-333-M6 Rev A Sheet 2 of 2
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Number of Pins
Overall Height
Terminal Width
Overall Width
Overall Length
Terminal Length
Exposed Pad Width
Exposed Pad Length
Terminal Thickness
Pitch
Standoff
Units
Dimension Limits
A1
A
b
D
E2
D2
A3
e
L
E
N
0.40 BSC
0.152 REF
1.80
1.80
0.30
-
0.00
4.00 BSC
0.45
1.90
1.90
-
0.02
4.00 BSC
MILLIMETERS
MIN NOM
28
2.00
2.00
0.50
0.60
0.05
MAX
K0.60--
REF: Reference Dimension, usually without tolerance, for information purposes only.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
1.
2.
3.
Notes:
Pin 1 visual index feature may vary, but must be located within the hatched area.
Package is saw singulated
Dimensioning and tolerancing per ASME Y14.5M
Terminal-to-Exposed-Pad
28-Lead Ultra Thin Plastic Quad Flat, No Lead Package (M6) - 4x4x0.6 mm Body [UQFN]
Corner Anchor Pad b1
0.15 0.20 0.25
With Corner Anchors
Corner Pad, Metal Free Zone b2
0.40 0.45 0.50
0.18 0.23 0.28
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DS60001324B-page 250 2015-2016 Microchip Technology Inc.
RECOMMENDED LAND PATTERN
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Dimension Limits
Units
C2
Center Pad Width
Contact Pad Spacing
Center Pad Length
Contact Pitch
Y2
X2
2.00
2.00
MILLIMETERS
0.40 BSC
MIN
E
MAX
Contact Pad Length (X28)
Contact Pad Width (X28)
Y1
X1
0.85
0.20
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
Microchip Technology Drawing C04-2333-M6 Rev B
NOM
28-Lead Ultra Thin Plastic Quad Flat, No Lead Package (M6) - 4x4x0.6 mm Body [UQFN]
SILK SCREEN
1
2
28
C1
C2
E
X1
Y1
Y2
X2
C1Contact Pad Spacing 3.90
Contact Pad to Center Pad (X28) G1 0.52
Thermal Via Diameter V
Thermal Via Pitch EV
0.30
1.00
ØV
EV
EV
G3
G1
X3
Y3
Corner Anchor Length (X4)
Corner Anchor Width (X4)
Y3
X3
0.78
0.78
3.90
With Corner Anchors
Contact Pad to Pad (X24) G2 0.20
G2
Contact Pad to Corner Pad (X8) G3 0.20
2015-2016 Microchip Technology Inc. DS60001324B-page 251
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B
A
0.10 C
0.10 C
0.10 C A B
0.05 C
(DATUM B)
(DATUM A)
C
NOTE 1
1
2
N
2X
TOP VIEW
SIDE VIEW
BOTTOM VIEW
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
NOTE 1
0.10 C A B
0.10 C A B
0.10 C
0.08 C
Microchip Technology Drawing C04-272B-M2 Sheet 1 of 2
2X
36X
D
E
1
2
N
(A3)
A
A1
D2
E2
L36X b
e
K
36-Terminal Very Thin Plastic Quad Flatpack No-Lead (M2) - 6x6x1.0mm Body [VQFN]
SMSC Legacy "Sawn Quad Flatpack No-Lead [SQFN]"
SEATING
PLANE
PIC32MM0064GPL036 FAMILY
DS60001324B-page 252 2015-2016 Microchip Technology Inc.
Microchip Technology Drawing C04-272B-M2 Sheet 2 of 2
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Number of Terminals
Overall Height
Terminal Width
Overall Width
Overall Length
Terminal Length
Exposed Pad Width
Exposed Pad Length
Terminal Thickness
Pitch
Standoff
Units
Dimension Limits
A1
A
b
D
E2
D2
A3
e
L
E
N
0.50 BSC
0.20 REF
3.60
3.60
0.50
0.18
0.80
0.00
0.25
6.00 BSC
0.60
3.70
3.70
0.90
0.02
6.00 BSC
MILLIMETERS
MIN NOM
36
3.80
3.80
0.75
0.30
1.00
0.05
MAX
K0.550.45 -
REF: Reference Dimension, usually without tolerance, for information purposes only.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
1.
2.
3.
Notes:
Pin 1 visual index feature may vary, but must be located within the hatched area.
Package is saw singulated
Dimensioning and tolerancing per ASME Y14.5M
Terminal-to-Exposed-Pad
36-Terminal Very Thin Plastic Quad Flatpack No-Lead (M2) - 6x6x1.0mm Body [VQFN]
SMSC Legacy "Sawn Quad Flatpack No-Lead [SQFN]"
2015-2016 Microchip Technology Inc. DS60001324B-page 253
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RECOMMENDED LAND PATTERN
Dimension Limits
Units
C2
Optional Center Pad Width
Contact Pad Spacing
Optional Center Pad Length
Contact Pitch
Y2
X2
3.80
3.80
MILLIMETERS
0.50 BSC
MIN
E
MAX
5.60
Contact Pad Length (X36)
Contact Pad Width (X36)
Y1
X1
1.10
0.30
Microchip Technology Drawing C04-2272B-M2
NOM
SILK SCREEN
1
2
36
C1Contact Pad Spacing 5.60
Thermal Via Diameter V
Thermal Via Pitch EV
0.30
1.00
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
Dimensioning and tolerancing per ASME Y14.5M
For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
1.
2.
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
EV
EV
C2
C1
X2
Y2
E
X1
Y1
G1
ØV
G2
36-Terminal Very Thin Plastic Quad Flatpack No-Lead (M2) - 6x6x0.9 mm Body [VQFN]
SMSC Legacy "Sawn Quad Flatpack No-Lead [SQFN]"
Contact Pad to Center Pad (X36) G1 0.35
Space Between Contact Pads (X32) G2 0.20
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DS60001324B-page 254 2015-2016 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2015-2016 Microchip Technology Inc. DS60001324B-page 255
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Note: For the most current package drawings, please see the Microchip Packaging Specification located at
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Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2015-2016 Microchip Technology Inc. DS60001324B-page 257
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APPENDIX A: REVISION HISTORY
Revision A (February 2015)
This is the initial version of the document.
Revision B (May 2016)
This revision incorporates the following updates:
•Registers:
- Updates Register 5-1, Register 5-3,
Register 5-6, Register 5-7, Register 6-3,
Register 6-4, Register 7-2, Register 8-2,
Register 8-3, Register 8-5, Register 8-6,
Register 11-1, Register 13-1, Register 14-1,
Register 15-1, Register 15-5, Register 15-6,
Register 16-1, Register 16-2, Register 16-3,
Register 16-5, Register 18-2, Register 19-1,
Register 19-2 and Register 23-7
• Tables:
- Updates Ta b l e 1-1, Table 5-1, Table 6-1,Tabl e 7-2,
Table 7-3, Ta bl e 9-3, Ta b le 9-7, Table 15-1,
Table 16-1, Table 19-1, Ta b l e 22-1, Table 23-4,
Table 23-5 Table 26-2, Table 26-3, Ta b l e 26-4
and Ta b l e 26-6 through Table 26-33
-Adds Tab l e 23-8
•Figures:
- Updates Figure 1-1, Figure 3-1, Figure 8-1,
Figure 10-1, Figure 14-1, Figure 13-1,
Figure 14-1, Figure 14-1, Figure 15-1,
Figure 17-1, Figure 18-1, Figure 18-3,
Figure 26-1, Figure 26-3, Figure 26-4,
Figure 26-9, Figure 26-10, Figure 26-11 and
Figure 26-12
• Updates pin function descriptions in Section 1.0
“Device Overview”
• Updates text in Section 9.6 “Input Change Notifi-
cation (ICN)”, Section 9.8.4 “Input Mapping”,
Section 23.7 “Unique Device Identifier (UDID)”,
Section 22.5 “Low-Power Brown-out Reset”
and Section 27.0 “Packaging Information”
•Adds Section 5.1 “Flash Controller Registers
Wr ite Protecti on” , Section 8.0 “Oscillator Con-
figuration”, Section 23.4 “System Re gisters
Wr ite Protecti on” , reference to Section 22.1
“Sleep Mode”, Section 22 .2 “Id le Mode ” and
Section 23.8 “Reserved Registers”
• Updates the Absolute Maximum Ratings in
Section 26.0 “Electrical Characteristics”
This revision also includes minor typographical and
formatting changes throughout the data sheet text.
PIC32MM0064GPL036 FAMILY
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NOTES:
2015-2016 Microchip Technology Inc. DS60001324B-page 259
PIC32MM0064GPL036 FAMILY
INDEX
A
AC Characteristics
10-Bit ADC Accuracy and Conversion
Requirements ................................................... 230
12-Bit ADC Accuracy and Conversion
Requirements ................................................... 229
ADC Inputs Specifications ........................................ 229
and Timing Parameters............................................. 217
Capacitive Loading on Output Pins........................... 217
CLKO and I/O Timing Requirements ........................ 220
EJTAG Requirements ............................................... 231
External Clock Timing Requirements........................ 218
Internal Oscillator Accuracy ...................................... 219
Internal Oscillator Start-up Time ............................... 219
Load Conditions for Device Timing ........................... 217
MCCP/SCCP Input Capture x Mode
Requirements ................................................... 224
MCCP/SCCP Output Compare x Mode
Requirements ................................................... 224
MCCP/SCCP PWM Mode Requirements ................. 225
MCCP/SCCP Timer1 External Clock Timing ............ 222
MCCP/SCCP Timing Requirements ......................... 223
PLL Clock Timing Specifications............................... 219
Reset, Brown-out Reset and Sleep Modes
Timing Specifications........................................ 221
SPIx Master Mode Requirements ............................. 227
SPIx Module Slave Mode Timing Requirements ...... 228
ADC Converter
Control Registers ...................................................... 134
Introduction ............................................................... 133
Assembler
MPASM Assembler................................................... 200
B
Band Gap Voltage Reference ........................................... 182
Block Diagrams
ADC Module.............................................................. 133
CDAC Module ........................................................... 169
CLCx Input Source Selection.................................... 153
CLCx Logic Function Combinatorial Options ............ 152
CLCx Module ............................................................ 151
CPU Exceptions and Interrupt Controller.................... 51
CRC Module ............................................................. 147
Dual Comparator Module.......................................... 163
High/Low-Voltage Detect (HLVD) ............................. 173
MCCP/SCCP Module.................................................. 96
MCLR Pin Connections............................................... 20
Microprocessor Core................................................... 24
Multiplexing Remappable Output for RP1................... 81
Oscillator Circuit Placement........................................ 21
Oscillator System........................................................ 66
PIC32MM0064GPL036 Family ................................... 13
Recommended Minimum Connection......................... 20
Remappable Input Example for U2RX ........................ 80
Reset System.............................................................. 45
RTCC Module ........................................................... 123
SPI/I
2
S Module ......................................................... 109
Timer1 Module ............................................................ 87
Typical Shared Port Structure..................................... 77
UARTx Module.......................................................... 117
Watchdog Timer (WDT) .............................................. 91
C
C Compilers
MPLAB XC Compilers .............................................. 200
Capture/Compare/PWM/Timer Modules
(MCCP, SCCP)........................................................... 95
CLC
Control Registers...................................................... 154
CLR, SET and INV Registers ............................................. 78
Code Examples
UART2 RX Input Assignment to RP9/RB14 Pin......... 80
UART2 TX Output Assignment to
RP13/RB13 Pin .................................................. 81
Code Execution from RAM ............................................... 181
Comparator....................................................................... 163
Configurable Logic Cell (CLC).......................................... 151
Configurable Logic Cell. See CLC.
Configuration Bits ............................................................. 181
Control Digital-to-Analog Converter (CDAC) .................... 169
Control Digital-to-Analog Converter. See CDAC.
CP0 Register 16, Select 1) ................................................. 30
CP0 Register 16, Select 3) ................................................. 31
CP0 Register 16, Select 5) ................................................. 32
CPU
Architecture Overview ................................................ 25
Coprocessor 0 Registers ............................................ 27
Core Exception Types ................................................ 52
EJTAG Debug Support............................................... 28
Power Management ................................................... 28
CPU Module ....................................................................... 23
Customer Change Notification Service............................. 262
Customer Notification Service .......................................... 262
Customer Support............................................................. 262
Cyclic Redundancy Check. See CRC.
D
DC Characteristics
Comparator Specifications ....................................... 216
High/Low-Voltage Detect .......................................... 215
I/O Pin Input Injection Current Specifications ........... 213
I/O Pin Input Specifications ...................................... 212
I/O Pin Output Specifications.................................... 214
Idle Current (I
IDLE
) .................................................... 209
Incremental Peripheral Current (BOR, WDT,
HLVD, RTCC, ADC, FRC, PLL, DAC,
LPBOR, CMP) .................................................. 211
Internal Voltage Regulator Specifications................. 215
Operating Current (I
DD
) ............................................ 208
Operating Voltage Specifications ............................. 207
Power-Down Current (I
PD
)........................................ 210
Program Flash Memory Specifications..................... 214
Thermal Operating Conditions.................................. 206
Voltage Reference Specifications............................. 216
Demo/Development Boards, Evaluation and
Starter Kits................................................................ 202
Development Support....................................................... 199
Third-Party Tools ...................................................... 202
Device IDs ........................................................................ 181
E
Electrical Characteristics .................................................. 205
Absolute Maximum Ratings...................................... 205
V/F Graph (Industrial) ............................................... 206
Errata.................................................................................. 10
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DS60001324B-page 260 2015-2016 Microchip Technology Inc.
F
Fail-Safe Clock Monitor (FSCM) ......................................... 65
Flash Program Memory....................................................... 37
Write Protection ..........................................................37
G
Getting Started with PIC32 MCUs....................................... 19
Connection Requirements .......................................... 19
Decoupling Capacitors................................................ 19
External Oscillator Pins............................................... 21
ICSP Pins.................................................................... 21
Internal Voltage Regulator Capacitor (V
CAP
) .............. 20
JTAG........................................................................... 21
Master Clear (MCLR) Pin............................................20
Unused I/Os ................................................................ 21
H
High/Low-Voltage Detect (HLVD) ..................................... 173
High/Low-Voltage Detect. See HLVD.
I
I/O Ports..............................................................................77
Analog/Digital Port Pins Configuration........................ 78
Open-Drain Configuration ........................................... 78
Parallel I/O (PIO)......................................................... 78
Pull-up/Pull-Down Pins ...............................................79
Write/Read Timing ...................................................... 78
Input Change Notification (ICN) .......................................... 78
Instruction Set ...................................................................203
Inter-IC Sound. See I
2
S.
Internet Address................................................................ 262
M
MCCP/SCCP
Registers..................................................................... 96
Memory Maps
Devices with 16 Kbytes Program Memory .................. 34
Devices with 32 Kbytes Program Memory .................. 35
Devices with 64 Kbytes Program Memory .................. 36
Memory Organization.......................................................... 33
Alternate Configuration Bits Space .............................33
Microchip Internet Web Site..............................................262
MIPS32® microAptiv™ UC Core Configuration..................28
MPLAB Assembler, Linker, Librarian ................................ 200
MPLAB ICD 3 In-Circuit Debugger.................................... 201
MPLAB PM3 Device Programmer..................................... 201
MPLAB REAL ICE In-Circuit Emulator System................. 201
MPLAB X Integrated Development
Environment Software...............................................199
MPLAB X SIM Software Simulator.................................... 201
MPLIB Object Librarian .....................................................200
MPLINK Object Linker....................................................... 200
Multiply/Divide Unit Latencies and Repeat Rates ............... 25
O
Oscillator Configuration....................................................... 65
P
Package Thermal Resistance ........................................... 206
Packaging ......................................................................... 233
Details ....................................................................... 235
Marking ..................................................................... 233
Peripheral Pin Select (PPS) ................................................ 79
PICkit 3 In-Circuit Debugger/Programmer ........................ 201
Pinout Description ............................................................... 14
Power-Saving Features .................................................... 177
Idle Mode.................................................................. 177
Low-Power Brown-out Reset.................................... 179
On-Chip Voltage Regulator Low-Power Modes........ 179
Regulator Retention.......................................... 179
Regulator Standby............................................ 179
Peripheral Module Disable........................................ 178
Sleep Mode .............................................................. 177
PPS
Available Peripherals.................................................. 79
Available Pins ............................................................. 79
Controlling .................................................................. 79
Controlling Configuration Changes............................. 81
Input Mapping ............................................................. 80
Input Pin Selection...................................................... 80
Output Mapping .......................................................... 81
Output Pin Selection................................................... 81
Programming and Diagnostics.......................................... 182
R
Real-Time Clock and Calendar (RTCC) ........................... 123
Real-Time Clock and Calendar. See RTCC.
Register Map
ADC .......................................................................... 135
Alternate Configuration Words Summary ................. 184
Band Gap ................................................................. 195
CDAC ....................................................................... 170
CLC1 and CLC2 ....................................................... 155
Comparator 1 and 2.................................................. 164
Configurations Words Summary............................... 183
CRC.......................................................................... 148
Flash Controller .......................................................... 38
High/Low Voltage Detect .......................................... 174
Interrupts .................................................................... 56
MCCP/SCCP .............................................................. 97
Oscillator Configuration .............................................. 67
Peripheral Module Disable........................................ 180
Peripheral Pin Select .................................................. 85
PORTA ....................................................................... 82
PORTB ....................................................................... 83
PORTC ....................................................................... 84
RAM Configuration, Device ID and System Lock ..... 192
Reserved Registers .................................................. 197
Resets ........................................................................ 46
RTCC........................................................................ 124
SPI1 and SPI2 .......................................................... 110
Timer1 ........................................................................ 88
UART1 and UART2 .................................................. 118
UDID......................................................................... 197
Watchdog Timer ......................................................... 92
Registers
AD1CHIT (ADC Compare Hit) .................................. 145
AD1CHS (ADC Input Select) .................................... 143
AD1CON1 (ADC Control 1) ...................................... 137
AD1CON2 (ADC Control 2) ...................................... 139
AD1CON3 (ADC Control 3) ...................................... 140
AD1CON5 (ADC Control 5) ...................................... 141
AD1CSS (ADC Input Scan Select) ........................... 144
ALMDATE (Alarm Date) ........................................... 131
ANCFG (Band Gap Control) ..................................... 196
CCPxCON1 (Capture/Compare/PWMx
Control 1)............................................................ 99
CCPxCON2 (Capture/Compare/PWMx
Control 2).......................................................... 102
2015-2016 Microchip Technology Inc. DS60001324B-page 261
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CCPxCON3 (Capture/Compare/PWMx
Control 3) .......................................................... 104
CCPxSTAT (Capture/Compare/PWMx Status)......... 106
CFGCON (Configuration Control)............................. 193
CLCxCON (CLCx Control)........................................ 156
CLCxGLS (CLCx Gate Logic Input Select) ............... 160
CLCxSEL (CLCx Input MUX Select)......................... 158
CLKSTAT (Clock Status) ............................................ 74
CMSTAT (Comparator Status).................................. 165
CMxCON (Comparator x Control)............................. 166
CNCONx (Change Notification Control
for PORTx).......................................................... 86
CONFIG
(CP0 Register 16, Select 0) ................................ 29
CONFIG1
(Configuration Register 1.................................... 30
CONFIG3
(Configuration Register 3.................................... 31
CONFIG5
(Configuration Register 5.................................... 32
CRCCON (CRC Control) .......................................... 149
CRCXOR (CRC XOR) .............................................. 150
DAC1CON (CDAC Control) ...................................... 171
DEVID (Device ID) .................................................... 194
FDEVOPT/AFDEVOPT (Device Options
Configuration) ................................................... 185
FICD/AFICD (ICD/Debug Configuration) .................. 186
FOSCSEL/AFOSCSEL (Oscillator Selection
Configuration) ................................................... 190
FPOR/AFPOR (Power-up Settings
Configuration) ................................................... 187
FSEC/AFSEC (Code-Protect Configuration) ............ 191
FWDT/AFWDT (Watchdog Timer
Configuration) ................................................... 188
HLVDCON (High/Low Voltage Detect Control)......... 175
IECx (Interrupt Enable Control x)................................ 62
IFSx (Interrupt Flag Status x)...................................... 62
INTCON (Interrupt Control)......................................... 58
INTSTAT (Interrupt Status)......................................... 61
IPCx (Interrupt Priority Control x) ................................ 63
IPTMR (Interrupt Proximity Timer) .............................. 61
NVMADDR (NVM Flash Address) .............................. 41
NVMBWP (NVM Boot Flash (Page)
Write-Protect)...................................................... 44
NVMCON (NVM Programming Control) ..................... 39
NVMDATAx (NVM Flash Data x) ................................ 42
NVMKEY (NVM Programming Unlock)....................... 41
NVMPWP (NVM Program Flash Write-Protect).......... 43
NVMSRCADDR (NVM Source Data Address)............ 42
OSCCON (Oscillator Control) ..................................... 68
OSCTUN (FRC Tuning).............................................. 75
PRISS (Priority Shadow Select).................................. 59
PWRCON (Power Control) ......................................... 50
RCON (Reset Control) ................................................ 47
REFO1CON (Reference Oscillator Control) ............... 71
REFO1TRIM (Reference Oscillator Trim) ................... 73
RNMICON (Non-Maskable Interrupt (NMI)
Control) ............................................................... 49
RSWRST (Software Reset) ........................................ 48
RTCCON1 (RTCC Control 1).................................... 125
RTCCON2 (RTCC Control 2).................................... 127
RTCDATE (RTCC Date)........................................... 130
RTCSTAT (RTCC Status Register) .......................... 128
RTCTIME/ALMTIME (RTCC/Alarm Time)................ 129
SPIxCON (SPIx Control) .......................................... 111
SPIxCON2 (SPIx Control 2) ..................................... 114
SPIxSTAT (SPIx Status)........................................... 115
SPLLCON (System PLL Control) ............................... 70
SYSKEY (System Unlock)........................................ 194
T1CON (Timer1 (Type A) Control) ............................. 89
UxMODE (UARTx Mode) ......................................... 119
UxSTA (UARTx Status and Control) ........................ 121
WDTCON (Watchdog Timer Control) ......................... 93
Resets ................................................................................ 45
Brown-out Reset (BOR).............................................. 45
Configuration Mismatch Reset (CMR)........................ 45
Master Clear Reset Pin (MCLR)................................. 45
Power-on Reset (POR)............................................... 45
Software Reset (SWR) ............................................... 45
Watchdog Timer Reset (WDTR)................................. 45
Revision History................................................................ 257
S
Serial Peripheral Interface (SPI) ....................................... 109
Serial Peripheral Interface. See SPI.
Special Features............................................................... 181
T
Timer1 Module.................................................................... 87
Timing Diagrams
CLKO and I/O Characteristics .................................. 220
EJTAG Characteristics ............................................. 231
External Clock .......................................................... 218
MCCP/SCCP Input Capture x Mode ........................ 224
MCCP/SCCP Output Compare x Mode.................... 224
MCCP/SCCP PWMx Mode Characteristics.............. 225
MCCP/SCCP Timerx External Clock Timing............ 223
SPIx Master Mode (CKE = 0) ................................... 226
SPIx Master Mode (CKE = 1) ................................... 226
SPIx Slave Mode (CKE = 0) ..................................... 227
SPIx Slave Mode (CKE = 1) ..................................... 228
Timer1 External Clock Characteristics ..................... 222
U
UART................................................................................ 117
Unique Device Identifier (UDID) ....................................... 182
Universal Asynchronous Receiver Transmitter. See UART.
W
Watchdog Timer (WDT)...................................................... 91
Write Protection
System Registers ..................................................... 181
WWW Address ................................................................. 262
WWW, On-Line Support ..................................................... 10
PIC32MM0064GPL036 FAMILY
DS60001324B-page 262 2015-2016 Microchip Technology Inc.
NOTES:
2015-2016 Microchip Technology Inc. DS60001324B-page 263
PIC32MM0064GPL036 FAMILY
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
•Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
•General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
•Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
CUSTOMER SUPP ORT
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
Customers should contact their distributor,
representative or Field Application Engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical s upport is avail able throug h the web si te
at: http://microchip.com/support
PIC32MM0064GPL036 FAMILY
DS60001324B-page 264 2015-2016 Microchip Technology Inc.
NOTES:
2015-2016 Microchip Technology Inc. DS60001324B-page 265
PIC32MM0064GPL036 FAMILY
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office
.
Architecture MM = MIPS32
®
microAptiv™ UC CPU Core
Flash Memory Size 0016 = 16 Kbytes
0032 = 32 Kbytes
0064 = 64 Kbytes
Family GP = General Purpose Family
Key Feature L = Up to 25 MHz operating frequency with basic peripheral set of 2 UART
and 2 SPI modules
Pin Count 020 = 20-pin
028 = 28-pin
036 = 36/40-pin
Pattern Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise)
ES = Engineering Sample
Example:
PIC32MM0064GPL036-I/M2:
PIC32 General Purpose Device
with MIPS32
®
microAptiv™ UC
Core, 64-Kbyte Program Memory,
36-Pin Package.
Microchip Brand
Architecture
Key Feature Set
PIC32 MM XXXX GP LXXX T - XXX
Flas h Memory Size
Tape and Reel Flag (if applicable)
Pattern
Pin Count
Family
PIC32MM0064GPL036 FAMILY
DS60001324B-page 266 2015-2016 Microchip Technology Inc.
NOTES:
2015-2016 Microchip Technology Inc. DS60001324B-page 267
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate,
dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq,
KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST,
MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo,
RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O
are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company,
ETHERSYNCH, Hyper Speed Control, HyperLight Load,
IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut,
BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, Dynamic Average Matching, DAM, ECAN,
EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip
Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker,
Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2015-2016, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-0653-2
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microch ip rece iv ed ISO/T S -16 94 9:20 09 certifi cat i on for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
®
MCUs and dsPI C
®
DSCs, KEELOQ
®
code hoppi ng
devices, Serial EEPROMs, microperiph erals, nonvolat ile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS60001324B-page 268 2015-2016 Microchip Technology Inc.
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China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
ASIA/PACIFIC
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhu ha i
Tel: 86-756-3210040
Fax: 86-756-3210049
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
India - Pune
Tel: 91-20-3019-1500
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Taiwan - Kaohs iung
Tel: 886-7-213-7828
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Thail a nd - Ba ngk ok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Cop e nha ge n
Tel: 45-4450-2828
Fax: 45-4485-2829
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Dusseldorf
Tel: 49-2129-3766400
Germany - Karlsruhe
Tel: 49-721-625370
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Venice
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Poland - Warsaw
Tel: 48-22-3325737
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Worldwide Sales and Service
07/14/15
