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GENERAL DESCRIPTION
The DS21610 is a multirate, low-jitter clock adapter
that converts E-carrier and T-carrier clocks to
multiple PDH carrier clock rates. Two clock outputs
are available that are frequency-locked to the input
clock. The clock outputs along with an 8kHz frame-
sync output can be phase-aligned to a frame-sync
input. The device is backward compatible with the
LXP610 and operates from either a 3.3V or 5V
supply. All modes of operation include a standard
8kHz output.
PIN CONFIGURATION
FEATURES
§ Direct Replacement for LXP610SE
§ Converts E-Carrier Clock Rates to T-Carrier
Clock Rates
§ Converts T-Carrier Clock Rates to E-Carrier
Clock Rates
§ 3.3V or 5V Supply
§ Low Jitter Output
§ Multiple Output Clocks Synchronized to Input
Clock
§ 8kHz Frequency-Locked Output for all Operation
Modes
§ No External Components Required
§ 16-Pin SO and 28-Pin PLCC
§ Industrial Temperature Range: -40ºC to +85ºC
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE
DS21610SN -40ºC to +85ºC 16 SO
DS21610QN -40ºC to +85ºC 29 PLCC
DS21610
3.3V/5V Clock Rate Adapte
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SO
Dallas
Semiconductor
DS21610
DS21610 3.3V/5V Clock Rate Adapter
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TABLE OF CONTENTS
1. PIN DESCRIPTION ......................................................................................................................3
1.1 COMPATIBILITY WITH LXP610.........................................................................................................................3
2. FUNCTIONAL DESCRIPTION......................................................................................................5
3. OUTPUT JITTER..........................................................................................................................6
3.1 JITTER TRANSFER ..........................................................................................................................................6
4. OPERATING PARAMETERS .......................................................................................................8
5. PACKAGE INFORMATION ........................................................................................................13
6. REVISION HISTORY..................................................................................................................15
LIST OF FIGURES
Figure 1-1. Block Diagram....................................................................................................................4
Figure 3-1. Nominal Jitter Transfer (1.544MHz CLKIN to 2.048MHz CLKOUT1) ..................................6
Figure 3-2. Nominal Jitter Transfer (2.048MHz CLKIN to 1.544MHz CLKOUT1) ..................................7
Figure 4-1. SYNCIN/CLKIN to CLKOUT1/SYNCOUT and CLKOUT2 ................................................10
Figure 4-2. Output Frame-Sync Alignment When CLKOIT2 = 2 x CLKOUT1 .....................................11
Figure 4-3. Output Frame-Sync Alignment When CLKOUT2 = 3 x CLKOUT1....................................11
Figure 4-4. Output Frame-Sync Alignment When CLKOIT2 = 4 x CLKOUT1 .....................................12
Figure 4-5. Output Frame-Sync Alignment When CLKOUT2 = 5 x CLKOUT1....................................12
LIST OF TABLES
Table 1-A. Pin Description....................................................................................................................3
Table 1-B. Pin Name Cross-Reference to LXP610...............................................................................3
Table 2-A. Program Pin Functions (SEL = 0)........................................................................................5
Table 2-B. Program Pin Functions (SEL = 1)........................................................................................5
Table 3-A. Output Jitter Specifications, CLKOUT1 = 1.544MHz ...........................................................6
Table 3-B. Output Jitter Specifications, CLKOUT1 = 2.048MHz ...........................................................6
DS21610 3.3V/5V Clock Rate Adapter
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1. PIN DESCRIPTION
Table 1-A. Pin Description
PIN
PLCC SO NAME TYPE FUNCTION
1 1 P3 Input
Program Pin 3. Used to select the various combinations of
clock and sync outputs.
2 2 SYNCOUT Output
Synchronization Pulse Output. An 8kHz output that can be
synchronized to the clock outputs and SYNCIN (if present).
3–5, 7–9,
11, 12, 17–
19, 21, 23,
25, 26
3, 6, 11 N.C. — No Connect
6 4 CLKOUT2 Output
Clock Output 2. T1 or E1 carrier clock output referenced to
CLKIN.
10 5 CLKIN Input
Clock Input. Reference Clock Input. CLKOUT1 and CLKOUT2
will be referenced to this clock.
13 7 CLKOUT1 Output
Clock Output 1. T1 or E1 carrier clock output referenced to
CLKIN.
14 8 P1 Input
Program Pin 3. Used to select the various combinations of
clock and sync outputs.
15 9 VSS Supply Ground
16 10 P2 Input
Program Pin 2. Used to select the various combinations of
clock and sync outputs.
20 12 SEL Input Clock Mode Select. T-carrier/E-carrier mode select.
22 13 FSP Input
Frame Synchronization Pulse Polarity. Used to change the
polarity of the SYNCOUT output.
24 14 SYNCIN Input
Synchronization Pulse Input. Used to synchronize the clock
outputs and SYNCOUT to CLKIN and SYNCIN. SYNCIN
should be tied high or low when not in use.
27 15 P4 Input
Program Pin 4. Used to select the various combinations of
clock and sync outputs.
28 16 VDD Supply Positive Supply, 3.3V or 5V ±5%
1.1 Compatibility with LXP610
The DS21610 is pin compatible with the LXP610.
Table 1-B. Pin Name Cross-Reference to LXP610
DS21610 LXP610 FUNCTION
P3 P3 Program Pin 3
SYNCOUT FSO Synchronization Pulse Output
CLKOUT2 HFO Clock 2 Output
CLKIN CLKI Clock Input
CLKOUT1 CLKO Clock 1 Output
P1 P1 Program pin 1
VSS GND Ground
P2 P2 Program Pin 2
N.C. N.C. No Connect
DS21610 3.3V/5V Clock Rate Adapter
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Figure 1-1. Block Diagram
ANALOG
PLL
OUTPUT
DIVIDER
FRAME SYNC
GENERATOR
CLKIN
SEL
SYNCIN
CLKOUT2
CLKOUT1
SYNCOUT
FEEDBACK
CIRCUIT
FREQUENCY
PLL
SELECT
LOGIC
P1
P2
P3
P4
FSP
Dallas Semiconductor
DS21610
DS21610 3.3V/5V Clock Rate Adapter
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2. FUNCTIONAL DESCRIPTION
A clock input at CLKIN is converted to various clocks available on CLKOUT1 and CLKOUT2. Additionally, an 8kHz
clock locked to CLKIN and SYNCIN (if present) is always available at the SYNCOUT pin. The pulse width of the
SYNCOUT is selectable. It can be one or one-half the clock period of CLKIN, centered on the rising edge of
CLKIN. Pins P1 to P4 are used to select the various clock rates and operational modes. Table 2-A and Table 2-B
list the various operational modes of the DS21610.
CLKIN, CLKOUT1, and CLCKOUT2 are always frequency-locked. They can all be phase-locked to a system
frame-sync pulse. A frame-sync pulse applied to SYNCIN will cause CLKIN and CLKOUT1 and CLKOUT2 to be
phased-locked to that sync pulse. This causes the clocks to have a fixed alignment at the frame-sync boundaries.
The signal applied to SYNCIN can be 8kHz or some integer subrate such as 1kHz, 2kHz, or 4kHz. Phase
synchronization occurs within a maximum of 50ms when SYNCIN is 8kHz.
Table 2-A. Program Pin Functions (SEL = 0)
P4 P3 P2 P1 CLKIN CLKOUT1 CLKOUT2 SYNCOUT
0 0 0 0 1.544 2.048 6.144 Long
0 0 0 1 3.088 2.048 8.192 Short
0 0 1 0 1.544 2.048 6.144 Long
0 0 1 1 1.544 2.048 8.192 Short
0 1 0 0 1.544 2.560 7.680 Long
0 1 0 1 6.176 4.096 8.192 Long
0 1 1 0 1.544 2.560 7.680 Long
0 1 1 1 6.176 2.048 8.192 Short
1 0 0 0 3.088 2.048 6.144 Long
1 0 0 1 3.088 4.096 8.192 Long
1 0 1 0 3.088 2.048 6.144 Long
1 0 1 1 1.544 4.096 8.192 Long
1 1 0 0 6.176 2.560 7.680 Long
1 1 0 1 6.176 4.096 8.192 Long
1 1 1 0 6.176 2.560 7.680 Long
1 1 1 1 6.176 4.096 8.192 Long
Table 2-B. Program Pin Functions (SEL = 1)
P4 P3 P2 P1 CLKIN CLKOUT1 CLKOUT2 SYNCOUT
0 0 0 0 2.048 3.088 6.176 Long
0 0 0 1 2.048 3.088 6.176 Long
0 0 1 0 2.048 1.544 6.176 Long
0 0 1 1 2.048 1.544 6.176 Long
0 1 0 0 2.560 1.544 7.720 Long
0 1 0 1 8.192 3.088 6.176 Long
0 1 1 0 2.560 1.544 7.720 Long
0 1 1 1 8.192 1.544 6.176 Long
1 0 0 0 2.048 3.088 6.176 Long
1 0 0 1 4.096 3.088 6.176 Long
1 0 1 0 2.048 3.088 6.176 Long
1 0 1 1 4.096 1.544 6.176 Long
1 1 0 0 2.560 1.544 7.720 Long
1 1 0 1 8.192 3.088 6.176 Long
1 1 1 0 2.560 1.544 7.720 Long
1 1 1 1 8.192 1.544 6.176 Long
DS21610 3.3V/5V Clock Rate Adapter
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3. OUTPUT JITTER
Table 3-A shows the output jitter specifications for 2.048MHz (or 4.096MHz) to 1.544MHz conversions (SEL = 1)
and 1.544MHz to 2.048MHz (or 4.096MHz) conversions (SEL = 0).
Table 3-A. Output Jitter Specifications, CLKOUT1 = 1.544MHz
FREQUENCY BAND TR62411
SPECIFICATION TYP MAX UNITS
No bandlimiting TR62411 0.010 0.020 UIP-P
10Hz–40kHz TR62411 0.005 0.010 UIP-P
8kHz–40kHz TR62411 0.006 0.012 UIP-P
Table 3-B. Output Jitter Specifications, CLKOUT1 = 2.048MHz
FREQUENCY BAND G.823 SPECIFICATION TYP MAX UNITS
20Hz–100kHz 1.5 0.018 0.035 UIP-P
18kHz–100kHz 0.2 0.012 0.025 UIP-P
3.1 Jitter Transfer
Figure 3-1 and Figure 3-2 show jitter transfer for 2.048MHz-to-1.544MHz conversions and vice versa.
Figure 3-1. Nominal Jitter Transfer (1.544MHz CLKIN to 2.048MHz CLKOUT1)
NOTE: THE TYPICAL PEAK JITTER GAIN OF THE DS21610 IS ABOUT 1.6 FOR CONVERSION FROM T1 TO E1. THE
TYPICAL PEAK-JITTER GAIN OF THE LEVEL ONE DEVICE IS ABOUT 1.1. HOWEVER, THE JITTER GAIN FOR THE
DS21610 PEAKS IN THE 4kHz TO 8kHz RANGE, WHEREAS THE PEAK JITTER GAIN FOR THE LXP610 SPANS A
GREATER FREQUENCY RANGE (20kHz TO 40kHz).
0.00
0.20
0.40
0.60
0.80
1.00
1.20
1.40
1.60
1.80
2.00
0 5 10 15 20 25 30 35 40
JITTER FREQUENCY (kHz)
JITTER GAIN (ns/ns)
DS21610 3.3V/5V Clock Rate Adapter
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Figure 3-2. Nominal Jitter Transfer (2.048MHz CLKIN to 1.544MHz CLKOUT1)
NOTE: THE TYPICAL PEAK JITTER GAIN OF THE DS2161 IS ABOUT 1.4 FOR CONVERSION FROM T1 TO E1. THE
TYPICAL PEAK-JITTER GAIN OF THE LEVEL ONE DEVICE IS ABOUT 1.1. HOWEVER, THE JITTER GAIN FOR THE
DS21610 PEAKS IN THE 4kHz TO 8kHz RANGE, WHEREAS THE PEAK JITTER GAIN FOR THE LXP610 SPANS A
GREATER FREQUENCY RANGE (20kHz TO 40kHz).
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
0 10 20 30 40 50 60 70 80
JITTER FREQUENCY (kHz)
JITTER GAIN (ns/ns)
DS21610 3.3V/5V Clock Rate Adapter
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4. OPERATING PARAMETERS
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground -1.0V to +6.0V
Operating Temperature Range for DS21610SN -40°C to +85°C
Storage Temperature Range -55°C to +125°C
Soldering Temperature See IPC/JEDEC J-STD-020
Specification
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications
is not implied. Exposure to absolute maximum rating conditions for extended periods can affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA = -40°C to +85°C)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Logic 1 VIH 2.0 5.5 V
Logic 0 VIL -0.3 +0.8 V
3.3V 3.135 3.3 3.465
Supply Voltage VDD 5V 4.75 5 5.25
V
DC CHARACTERISTICS
(VDD = 3.3V/5V ± 5%, TA = -40°C to +85°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Current IDD (Note 1) 14 mA
Input Leakage IIL (Note 2) -10.0 +10.0
mA
Output Leakage ILO mA
Output Current (2.4V) IOH -1.0 mA
Output Current (0.4V) IOL +4.0 mA
Note 1: 100pF load on all outputs.
Note 2: 0V < VIN < VDD.
DS21610 3.3V/5V Clock Rate Adapter
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AC TIMING
(Figure 4-1, Figure 4-2, Figure 4-3, Figure 4-4, and Figure 4-5)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Capture Range on CLKIN (Note 3) ±10,000 ppm
Lock Range on CLKIN (Note 3) ±10,000 ppm
CLKIN Duty Cycle (Note 3) 35 65 %
SYNCIN Setup to CLKIN Rising tSU 46 ns
SYNCIN Hold After CLKIN Rising tHI 30 ns
SYNCIN Pulse Width tPW 76 CLKIN
period ns
3.3V -15 0 +15
CLKOUT1 Delay from CLKIN Rising tD 5V -15 0 +31
ns
CLKOUT1 Duty Cycle CD 49 51 %
SYNCOUT Delay from CLKOUT2 tDF -5 30 ns
SYNCOUT Pulse Width tSPW CLKOUT
1 period ns
CLKOUT1 Delay from CLKOUT2
Rising tDH -15 0 +15 ns
3.3V 60 Rise/Fall Time on CLKIN, SYNCIN
(Note 3) tRF 5V 40
ns
3.3V 60
Rise/Fall Time on CLKOUT,
SYNCOUT, CLKOUT2 (Note 4) tRF 5V 40
ns
Note 3: Guaranteed by design.
Note 4: 100pF load on CLKOUT, SYNCOUT, CLKOUT.
DS21610 3.3V/5V Clock Rate Adapter
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Figure 4-1. SYNCIN/CLKIN to CLKOUT1/SYNCOUT and CLKOUT2
SYNCOUT
CLKOUT1
tDH
CLKOUT1
CLKOUT2
tDH
tD
tPW
tHI tSU
SINCIN
CLKIN
CLKOUT1
tDF tDF
tWO
DS21610 3.3V/5V Clock Rate Adapter
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Figure 4-2. Output Frame-Sync Alignment When CLKOIT2 = 2 x CLKOUT1
Figure 4-3. Output Frame-Sync Alignment When CLKOUT2 = 3 x CLKOUT1
SYNCOUT
CLKOUT2
(8.192MHz)
CLKOUT1
(4.096MHz)
SYNCOUT
CLKOUT2
(
6.176MHz
)
CLKOUT1
(3.088MHz)
CLKOUT2
(7.680MHz or
6.144MHz)
CLKOUT1
(2.56MHz or
2.048MHz)
SYNCOUT
DS21610 3.3V/5V Clock Rate Adapter
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Figure 4-4. Output Frame-Sync Alignment When CLKOIT2 = 4 x CLKOUT1
Figure 4-5. Output Frame-Sync Alignment When CLKOUT2 = 5 x CLKOUT1
CLKOUT2
(6.176MHz or
8.192MHz)
CLKOUT1
(1.544MHz or
2.048MHz)
SYNCOUT
(
short
)
SYNCOUT
(long)
CLKOUT2
(7.720MHz)
CLKOUT1
(1.544MHz)
SYNCOUT
DS21610 3.3V/5V Clock Rate Adapter
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28-PIN PLCC
LTR MIN MAX
A 0.165 0.180
A1 0.090 0.120
A2 0.02 —
B 0.026 0.033
B1 0.013 0.021
C 0.009 0.012
D 0.485 0.495
D1 0.450 0.456
D2 0.390 0.430
E 0.485 0.495
E1 0.450 0.456
E2 0.390 0.430
L1 0.060 —
N 28 —
E1 0.050 BSC
Ch1 0.042 0.048
DS21610 3.3V/5V Clock Rate Adapter
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6. REVISION HISTORY
REVISION DESCRIPTION
090100 Preliminary release
112700 Remove references to 3V operation
120600 Add FSP pin to block diagram
021501 Add mechanical drawings for PLCC package
060601 Added jitter specifications and pinout for all packages
082001 Added timing diagrams
032002 Updated jitter specifications
032803 Added 3.3V operation specifications
113004 Added soldering temperature to Absolute Maximum Ratings section
