Copyright Cirrus Logic, Inc. 2012
(All Rights Reserved)
http://www.cirrus.com
104 dB, 24-Bit, 192 kHz Stereo Audio CODEC
D/A Features
Multi-Bit Delta Sigma Modulator
104 dB Dynamic Range
-90 dB THD+N
Up to 192 kHz Sampling Rates
Single-Ended Analog Architecture
Volume Control with Soft Ramp
– 0.5 dB Step Size
– Zero Crossing, Click-Free Transitions
Popguard® Technology
– Minimizes the Effects of Output Transients
Filtered Line-Level Outputs
Selectable Serial Audio Interface Formats
– Left-Justified up to 24-bit
– I²S up to 24-bit
– Right-Justified 16-, 18-, 20-, and 24-bit
Selectable 50/15 µs De-Emphasis
A/D Features
Multi-Bit Delta Sigma Modulator
104 dB Dynamic Range
-95 dB THD+N
Stereo 2:1 Input Multiplexer
Programmable Gain Amplifier (PGA)
– ± 12 dB Gain, 0.5 dB Step Size
– Zero Crossing, Click-Free Transitions
Pseudo-Differential Stereo Line Inputs
Stereo Microphone Inputs
– +32 dB Gain Stage
– Low-Noise Bias Supply
Up to 192 kHz Sampling Rates
Selectable Serial Audio Interface Formats
– Left-Justified up to 24-bit
– I²S up to 24-bit
High-Pass Filter or DC Offset Calibration
1.8 V to 5 V
Multibit
Modulator
Multibit
Modulator
Low-Latency
Anti-Alias Filter
Interpolation
Filter
Interpolation
Filter
Left DAC Output
Right DAC Output
Switched Capacitor
DAC and Filter
Multibit
Oversampling
ADC
Multibit
Oversampling
ADC
Low-Latency
Anti-Alias Filter
High Pass
Filter
High Pass
Filter
Stereo
Line Input
Serial
Audio
Input
Serial
Audio
Output
3.3 V to 5 V 3.3 V to 5 V
Switched Capacitor
DAC and Filter
MUX
PGA
Volume
Control
Volume
Control
PCM Serial Interface / Loopback
Mute
Control
Level Translator Level Translator
Reset
I2C Control
Data
Mute Control
Mic Input
1 & 2
PGA +32 dB
+32 dB
Internal Voltage
Reference
IEC60958-3 Transmitter
Mic Bias Microphone Bias
Transmitter Output
Register Configuration
AUG '12
DS657F3
CS4265
2DS657F3
CS4265
System Features
Synchronous IEC60958-3 Transmitter
– Up to 192 kHz Sampling Rates
– 75 Drive Capability
Serial Audio Data Input Multiplexer
Internal Digital Loopback
Supports Master or Slave Operation
Mute Output Control
Power-Down Mode
– Available for A/D, D/A, CODEC, Mic
Preamplifier
+3.3 V to +5 V Analog Power Supply
+3.3 V to +5 V Digital Power Supply
Direct Interface with 1.8 V to 5 V Logic Levels
Supports I²C® Control Port Interface
General Description
The CS4265 is a highly integrated stereo audio CO-
DEC. The CS4265 performs stereo analog-to-digital
(A/D) and digital-to-analog (D/A) conversion of up to
24-bit serial values at sample rates up to 192 kHz.
A 2:1 stereo input multiplexer is included for s electing
between line-level or microphone-level inputs. The mi-
crophone input path includes a +32 dB gain stage and
a low noise bias voltage supply. The PGA is availa ble
for line or microphone inputs and provides gain or atten-
uation of 12 dB in 0.5 dB steps.
The output of the PGA is followed by an advanced 5th-
order, multi-bit delta sigma modulator and digital filter-
ing/decimation. Sampled data is transmitted by the
serial audio interface at rates from 4 kHz to 192 kHz in
either Slave or Master Mode.
The D/A converter is based on a 4th-order multi-bit delta
sigma modulator with an ultra-linear low-pass filter and
offers a volume control that operates with a 0.5 dB step
size. It in corporates selectable soft ramp and zero
crossing transition functions to eliminate clicks and
pops.
Standard 50/15 s de-emphasis is availa ble for a
44.1 kHz sample rate for compatibility with digital audio
programs mastered using the 50 /15 s pre-emphasis
technique.
Integrated level translators allow ea sy interfacing be-
tween the CS4265 and other devices operating over a
wide range of logic levels.
The CS4265 is available in a 32-pin QFN package for
both Commercial (-10° to +70° C) and Automotive (-40°
to +105° C) grade. The CDB4265 is also available for
device evaluation and implementation suggestions.
Please refer to “Ordering Information” on page 57 for
complete details.
DS657F3 3
CS4265
TABLE OF CONTENTS
1. PIN DESCRIPTIONS .......................................................................................................................... 7
2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 9
SPECIFIED OPERATING CONDITIONS ............................................................................................. 9
ABSOLUTE MAXIMUM RATINGS .......................................................................................................9
DAC ANALOG CHARACTERISTICS ................................................................................................. 10
DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ............................ 11
ADC ANALOG CHARACTERISTICS ................................................................................................. 13
ADC ANALOG CHARACTERISTICS ................................................................................................. 15
ADC DIGITAL FILTER CHARACTERISTICS ..................................................................................... 16
DC ELECTRICAL CHARACTERISTICS ............................................................................................. 17
DIGITAL INTERFACE CHARACTERISTICS ...................................................................................... 18
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT ............................................................. 19
SWITCHING CHARACTERISTICS - I²C CONTROL PORT ............................................................... 22
3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 23
4. APPLICATIONS ................................................................................................................................... 24
4.1 Recommended Power-Up Sequence ............................................................................................. 24
4.2 System Clocking ............................................................................................................................. 24
4.2.1 Master Clock ......................................................................................................................... 24
4.2.2 Master Mode ......................................................................................................................... 25
4.2.3 Slave Mode ........................................................................................................................... 25
4.3 High-Pass Filter and DC Offset Calibration .................................................................................... 25
4.4 Analog Input Multiplexer, PGA, and Mic Gain ................................................................................27
4.5 Input Connections ........................................................................................................................... 27
4.5.1 Pseudo-Differential Input ....................................................................................................... 27
4.6 Output Connections ........................................................................................................................ 28
4.7 Output Transient Control ................................................................................................................ 28
4.7.1 Power-Up .............................................................................................................................. 28
4.7.2 Power-Down .......................................................................................................................... 28
4.7.3 Serial Interface Clock Changes ............................................................................................. 28
4.8 DAC Serial Data Input Multiplexer .................................................................................................. 29
4.9 De-Emphasis Filter ......................................................................................................................... 29
4.10 Internal Digital Loopback .............................................................................................................. 29
4.11 Mute Control ................................................................................................................................. 30
4.12 AES3 Transmitter ......................................................................................................................... 30
4.12.1 TxOut Driver ........................................................................................................................ 30
4.12.2 Mono Mode Operation ......................................................................................................... 31
4.13 I²C Control Port Description and Timing ....................................................................................... 31
4.14 Status Reporting ........................................................................................................................... 32
4.15 Reset ............................................................................................................................................ 33
4.16 Synchronization of Multiple Devices ............................................................................................. 33
4.17 Grounding and Power Supply Decoupling .................................................................................... 33
4.18 Package Considerations ............................................................................................................... 33
5. REGISTER QUICK REFERENCE ........................................................................................................ 34
6. REGISTER DESCRIPTION .................................................................................................................. 36
6.1 Chip ID - Register 01h .................................................................................................................... 36
6.2 Power Control - Address 02h ......................................................................................................... 36
6.2.1 Freeze (Bit 7) ......................................................................................................................... 36
6.2.2 Power-Down MIC (Bit 3) ........................................................................................................ 36
6.2.3 Power-Down ADC (Bit 2) ....................................................................................................... 36
6.2.4 Power-Down DAC (Bit 1) ....................................................................................................... 37
6.2.5 Power-Down Device (Bit 0) ................................................................................................... 37
6.3 DAC Control - Address 03h ............................................................................................................ 37
4DS657F3
CS4265
6.3.1 DAC Digital Interface Format (Bits 5:4) ................................................................................. 37
6.3.2 Mute DAC (Bit 2) ................................................................................................................... 37
6.3.3 De-Emphasis Control (Bit 1) .................................................................................................. 38
6.4 ADC Control - Address 04h ............................................................................................................ 38
6.4.1 Functional Mode (Bits 7:6) .................................................................................................... 38
6.4.2 ADC Digital Interface Format (Bit 4) ...................................................................................... 38
6.4.3 Mute ADC (Bit 2) ................................................................................................................... 39
6.4.4 ADC High-Pass Filter Freeze (Bit 1) ..................................................................................... 39
6.4.5 Master / Slave Mode (Bit 0) ................................................................................................... 39
6.5 MCLK Frequency - Address 05h .................................................................................................... 39
6.5.1 Master Clock Dividers (Bits 6:4) ............................................................................................ 39
6.6 Signal Selection - Address 06h ...................................................................................................... 40
6.6.1 DAC SDIN Source (Bit 7) ...................................................................................................... 40
6.6.2 Digital Loopback (Bit 1) ......................................................................................................... 40
6.7 Channel B PGA Control - Address 07h .......................................................................................... 40
6.7.1 Channel B PGA Gain (Bits 5:0) ............................................................................................. 40
6.8 Channel A PGA Control - Address 08h .......................................................................................... 40
6.8.1 Channel A PGA Gain (Bits 5:0) ............................................................................................. 40
6.9 ADC Input Control - Address 09h ................................................................................................... 41
6.9.1 PGA Soft Ramp or Zero Cross Enable (Bits 4:3) .................................................................. 41
6.9.2 Analog Input Selection (Bit 0) ................................................................................................ 41
6.10 DAC Channel A Volume Control - Address 0Ah ........................................................................... 41
6.11 DAC Channel B Volume Control - Address 0Bh ........................................................................... 42
6.11.1 Volume Control (Bits 7:0) .................................................................................................... 42
6.12 DAC Control 2 - Address 0Ch ...................................................................................................... 42
6.12.1 DAC Soft Ramp or Zero Cross Enable (Bits 7:6) ................................................................ 42
6.12.2 Invert DAC Output (Bit 5) .................................................................................................... 43
6.13 Status - Address 0Dh ................................................................................................................... 43
6.13.1 E to F C-Buffer Transfer ...................................................................................................... 43
6.13.2 Clock Error (Bit 3) ................................................................................................................ 43
6.13.3 ADC Overflow (Bit 1) ........................................................................................................... 43
6.13.4 ADC Underflow (Bit 0) ......................................................................................................... 43
6.14 Status Mask - Address 0Eh .......................................................................................................... 44
6.15 Status Mode MSB - Address 0Fh ................................................................................................. 44
6.16 Status Mode LSB - Address 10h .................................................................................................. 44
6.17 Transmitter Control 1 - Address 11h ............................................................................................ 44
6.17.1 E to F C-Data Buffer Transfer Inhibit (Bit 6) ........................................................................ 44
6.17.2 C-Data Access Mode (Bit 5) ................................................................................................ 44
6.18 Transmitter Control 2 - Address 12h ............................................................................................ 45
6.18.1 Transmitter Digital Interface Format (Bits 7:6) .................................................................... 45
6.18.2 Transmitter Output Driver Control (Bit 5) ............................................................................. 45
6.18.3 Transmitter Mute Control (Bit 4) .......................................................................................... 45
6.18.4 Transmitted Validity Bit Control (Bit 3) ................................................................................45
6.18.5 Transmitter Mono/Stereo Operation Control (Bit 2) ............................................................. 45
6.18.6 Mono Mode CS Data Source (Bit 1) .................................................................................... 45
6.18.7 Mono Mode Channel Selection (Bit 0) ................................................................................. 46
7. PARAMETER DEFINITIONS ................................................................................................................ 47
8. DAC FILTER PLOTS .................................................................................................................... 48
9. ADC FILTER PLOTS ......................................................................................................................... 50
10. EXTERNAL IEC60958-3 TRANSMITTER COMPONENTS ............................................................... 52
10.1 IEC60958-3 Transmitter External Components ............................................................................ 52
10.2 Isolating Transformer Requirements ............................................................................................ 52
11. CHANNEL STATUS BUFFER MANAGEMENT ................................................................................ 53
11.1 IEC60958-3 Channel Status (C) Bit Management ........................................................................ 53
DS657F3 5
CS4265
11.1.1 Accessing the E Buffer ........................................................................................................ 54
11.2 Serial Copy Management System (SCMS) .................................................................................. 54
11.3 Channel Status Data E Buffer Access .......................................................................................... 54
11.3.1 One-Byte Mode ................................................................................................................... 55
11.3.2 Two-Byte Mode ................................................................................................................... 55
12. PACKAGE DIMENSIONS ........ ... .... ... ... ... ... ................. ... ... ... ................ .... ... ... ................ ... .... ............ 56
13. THERMAL CHARACTERISTICS AND SPECIFICATIONS ............................................................... 56
14. ORDERING INFORMATION ........................................................................................................ 57
15. REVISION HISTORY ...... ................. ... ... ... ................ .... ... ... ................ ... .... ... ... ................ ................... 57
LIST OF FIGURES
Figure 1.DAC Output Test Load ................................................................................................................ 12
Figure 2.Maximum DAC Loading .............................................................................................................. 12
Figure 3.Master Mode Serial Audio Port Timing ....................................................................................... 20
Figure 4.Slave Mode Serial Audio Port Timing ......................................................................................... 20
Figure 5.Format 0, Left-Justified up to 24-Bit Data ................................................................................... 21
Figure 6.Format 1, I²S up to 24-Bit Data ................................................................................................... 21
Figure 7.Format 2, Right-Justified 16-Bit Data.
Format 3, Right-Justified 24-Bit Data. ....................................................................................................... 21
Figure 8.Control Port Timing - I²C Format ................................................................................................. 22
Figure 9.Typical Connection Diagram ....................................................................................................... 23
Figure 10.Master Mode Clocking .............................................................................................................. 25
Figure 11.Analog Input Architecture .......................................................................................................... 27
Figure 12.Pseudo-Differential Input Stage ................................................................................................ 28
Figure 13.De-Emphasis Curve .................................................................................................................. 29
Figure 14.Suggested Active-Low Mute Circuit .......................................................................................... 30
Figure 15.Control Port Timing, I²C Write ................................................................................................... 32
Figure 16.Control Port Timing, I²C Read ................................................................................................... 32
Figure 17.De-Emphasis Curve .................................................................................................................. 38
Figure 18.DAC Single-Speed Stopband Rejection ................................................................................... 48
Figure 19.DAC Single-Speed Transition Band .......................................................................................... 48
Figure 20.DAC Single-Speed Transition Band .......................................................................................... 48
Figure 21.DAC Single-Speed Passband Ripple ........................................................................................ 48
Figure 22.DAC Double-Speed Stopband Rejection ..................................................................................48
Figure 23.DAC Double-Speed Transition Band ........................................................................................ 48
Figure 24.DAC Double-Speed Transition Band ........................................................................................ 49
Figure 25.DAC Double-Speed Passband Ripple ...................................................................................... 49
Figure 26.DAC Quad-Speed Stopband Rejection ..................................................................................... 49
Figure 27.DAC Quad-Speed Transition Band ........................................................................................... 49
Figure 28.DAC Quad-Speed Transition Band ........................................................................................... 49
Figure 29.DAC Quad-Speed Passband Ripple ......................................................................................... 49
Figure 30.ADC Single-Speed Stopband Rejection ................................................................................... 50
Figure 31.ADC Single-Speed Stopband Rejection ................................................................................... 50
Figure 32.ADC Single-Speed Transition Band (Detail) ............................................................................. 50
Figure 33.ADC Single-Speed Passband Ripple ........................................................................................ 50
Figure 34.ADC Double-Speed Stopband Rejection ..................................................................................50
Figure 35.ADC Double-Speed Stopband Rejection ..................................................................................50
Figure 36.ADC Double-Speed Transition Band (Detail) ............................................................................51
Figure 37.ADC Double-Speed Passband Ripple ...................................................................................... 51
Figure 38.ADC Quad-Speed Stopband Rejection ..................................................................................... 51
Figure 39.ADC Quad-Speed Stopband Rejection ..................................................................................... 51
Figure 40.ADC Quad-Speed Transition Band (Detail) ..............................................................................51
Figure 41.ADC Quad-Speed Passband Ripple ......................................................................................... 51
6DS657F3
CS4265
Figure 42.Consumer Output Circuit (VD = 5 V) ........................................................................................ 52
Figure 43.TTL/CMOS Output Circuit ......................................................................................................... 52
Figure 44.Channel Status Data Buffer Structure ....................................................................................... 53
Figure 45.Flowchart for Writing the E Buffer ............................................................................................. 54
LIST OF TABLES
Table 1. Speed Modes .............................................................................................................................. 24
Table 2. Common Clock Frequencies ....................................................................................................... 24
Table 3. MCLK Dividers ............................................................................................................................ 25
Table 4. Slave Mode Serial Bit Clock Ratios ............................................................................................. 25
Table 5. Device Revision .......................................................................................................................... 36
Table 6. Freeze-able Bits .......................................................................................................................... 36
Table 7. DAC Digital Interface Formats .................................................................................................... 37
Table 8. De-Emphasis Control .................................................................................................................. 38
Table 9. Functional Mode Selection .......................................................................................................... 38
Table 10. ADC Digital Interface Formats .................................................................................................. 39
Table 11. MCLK Frequency ...................................................................................................................... 39
Table 12. DAC SDIN Source Selection ..................................................................................................... 40
Table 13. Example Gain and Attenuation Settings ................................................................................... 40
Table 14. PGA Soft Cross or Zero Cross Mode Selection ........................................................................ 41
Table 15. Analog Input Selection .............................................................................................................. 41
Table 16. Digital Volume Control Example Settings ................................................................................. 42
Table 17. DAC Soft Cross or Zero Cross Mode Selection ........................................................................ 43
Table 18. Transmitter Digital Interface Formats ........................................................................................ 45
DS657F3 7
CS4265
1. PIN DESCRIPTIONS
Pin Name # Pin Description
SDA 1 Serial Control Data (Input/Output) - Bidirectional data line for the I²C control port.
SCL 2 Serial Control Port Clock (Input) - Serial clock for the I²C control port.
VLC 3Control Port Power (Input) - Determines the required signal level for the control port interface. Refer to
the Recommended Operating Conditions for appropriate voltages.
RESET 4Reset (Input) - The device enters a low-power mode when this pin is driven low.
VA 5 Analog Power (Input) - Positive power for the internal analog section.
AGND 6 Analog Ground (Input) - Ground reference for the internal analog section.
AINA
AINB
7,
8
Analog Input (Input) - The full-scale level is specified in the ADC Analog Characteristics specification
table.
SGND 9 Signal Ground (Input) - Ground reference for the analog line inputs.
AFILTA
AFILTB
10,
11 Antialias Filter Connection (Output) - Antialias filter connection for the ADC inputs.
VQ 12 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage.
FILT+ 13 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
MICIN1
MICIN2
14,
15
Microphone Input (Input) - The full-scale level is specified in the ADC Analog Characteristics specifica-
tion table.
MICBIAS 16 Microphone Bias (Output) - Low noise bias supply for external microphone. Electrical characteristics
are specified in the DC Electrical Characteristics table.
109
8
7
6
5
4
3
2
1
11 12 13 14 15 16
17
18
19
20
21
22
23
24
25
262728
29
303132
Top-Down (Through Package) View
32-Pin QFN Package
TXOUT
VD
DGND
MCLK
LRCK
SCLK
SDOUT
SDIN1
SGND
AFILTA
AFILTB
VQ
FILT+
MICIN1
MICIN2
MICBIAS
SDA
SCL
VLC
RESET
VA
AGND
AINA
AINB
SDIN2
TXSDIN
VLS
MUTEC
AOUTB
AOUTA
AGND
VA
Thermal Pad
8DS657F3
CS4265
VA 17 Analog Power (Input) - Positive power for the internal analog section.
AGND 18 Analog Ground (Input) - Ground reference for the internal analog section.
AOUTA
AOUTB
19, 20 Analog Audio Output (Output) - The full scale output level is specified in the DAC Analog Characteris-
tics specification table.
MUTEC 21 Mute Control (Output) - This pin is active during power-up initialization, reset, muting, when master
clock left/right clock frequency ratio is incorrect, or power-down.
VLS 22 Serial Audio Interface Power (Input) - Determines the required signal level for the serial audio inter-
face. Refer to the Recommended Operating Conditions for appropriate voltages.
TXSDIN 23 Transmitter Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
SDIN2 24 Serial Audio Data Input 2 (Input) - Input for two’s complement serial audio data.
SDIN1 25 Serial Audio Data Input 1 (Input) - Input for two’s complement serial audio data.
SDOUT 26 Serial Audio Data Output (Output) - Output for two’s complement serial audio data.
SCLK 27 Serial Clock (Input/Output) - Serial clock for the serial audio interface.
LRCK 28 Lef t Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the
serial audio data line.
MCLK 29 Master Clock (Input) - Clock source for the delta-sigma modulators.
DGND 30 Digital Ground (Input) - Ground reference for the internal digital section.
VD 31 Digita l Power (Input) - Positive power for the internal digital section.
TXOUT 32 Transmitter Line Driver Output (Output) - IEC60958-3 driver output.
Thermal Pad - Thermal Pad - Thermal relief pad for optimized heat dissipation.
DS657F3 9
CS4265
2. CHARACTERISTICS AND SPECIFICATIONS
SPECIFIED OPERATING CONDITIONS
AGND = DGND = 0 V; All voltages with respect to ground.
Notes: 1. Maximum of VA+0.25 V or 5.25 V, whichever is less.
ABSOLUTE MAXIMUM RATINGS
AGND = DGND = 0 V All voltages with respect to ground. (Note 2)
2. Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
3. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SCR latch-up.
Parameters Symbol Min Nom Max Units
DC Power Supplies: Analog
Digital
Logic - Serial Port
Logic - Control Port
VA
VD
VLS
VLC
3.13
3.13
1.71
1.71
5.0
3.3
3.3
3.3
5.25
(Note 1)
5.25
5.25
V
V
V
V
Ambient Operating Temperature (Power Applied) TA-10 - +70 C
Parameter Symbol Min Max Units
DC Power Supplies: Analog
Digital
Logic - Serial Port
Logic - Control Port
VA
VD
VLS
VLC
-0.3
-0.3
-0.3
-0.3
+6.0
+6.0
+6.0
+6.0
V
V
V
V
Input Current (Note 3) Iin -10 mA
Analog Input Voltage VINA AGND-0.3 VA+0.3 V
Digital Input Voltage Logic - Serial Port
Logic - Control Port
VIND-S
VIND-C
-0.3
-0.3
VLS+0.3
VLC+0.3
V
V
Ambient Operating Temperature (Power Applied) TA-50 +125 C
Storage Temperature Tstg -65 +150 C
10 DS657F3
CS4265
DAC ANALOG CHARACTERISTICS
Test Conditions (unless otherwise specified): AGND = DGND = 0 V; VA = 3.13 V to 5.25 V; VD = 3.13 V to 5.25 V
or VA + 0.25 V, whichever is less; VLS = VLC = 1.71 V to 5.25 V; TA = -10° to +70° C for Commercial or -40° to
+85° C for Automotive; Output test signal: 997 Hz full-scale sine wave; Test load RL = 3 k, CL = 10 pF (see
Figure 1), Fs = 48/96/192 kHz. Measurement Bandwidth 10 Hz to 20 kHz; All Connections as shown in Figure 9 on
page 23.
4. One-half LSB of triangular PDF dither added to data.
5. Guaranteed by design. The DC current draw represents the allowed current draw from the AOUT pin
due to typical leakage through the electrolytic DC blocking capacitors.
Parameter
Commercial Grade Automotive Grade
Symbol Min Typ Max Min Typ Max Unit
Dynamic Performance for VA = 4.75 V to 5.25 V
Dynamic Range (Note 4)
18 to 24-Bit A-Weighted
unweighted
16-Bit A-Weighted
unweighted
98
95
90
87
104
101
96
93
-
-
-
-
96
93
88
85
104
101
96
93
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise (Note 4)
18 to 24-Bit 0 dB
-20 dB
-60 dB
16-Bit 0 dB
-20 dB
-60 dB
THD+N
-
-
-
-
-
-
-90
-81
-41
-93
-73
-33
-84
-
-
-87
-
-
-
-
-
-
-
-
-90
-81
-41
-93
-73
-33
-82
-
-
-85
-
-
dB
dB
dB
dB
dB
dB
Dynamic Performance for VA = 3.13 V to 3.46 V
Dynamic Range (Note 4)
18 to 24-Bit A-Weighted
unweighted
16-Bit A-Weighted
unweighted
95
92
88
85
101
98
93
90
-
-
-
-
93
90
86
83
101
98
93
90
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise (Note 4)
18 to 24-Bit 0 dB
-20 dB
-60 dB
16-Bit 0 dB
-20 dB
-60 dB
THD+N
-
-
-
-
-
-
-87
-78
-38
-90
-70
-30
-79
-
-
-82
-
-
-
-
-
-
-
-
-87
-78
-38
-90
-70
-30
-77
-
-
-80
-
-
dB
dB
dB
dB
dB
dB
Interchannel Isolation (1 kHz) - 100 - - 100 - dB
DC Accuracy
Interchannel Gain Mismatch - 0.1 0.25 - 0.1 0.25 dB
Gain Drift - 100 - - 100 - ppm/°C
Analog Output
Full Scale Output Voltage 0.60*VA 0.65*VA 0.70*VA 0.60*VA 0.65*VA 0.70*VA Vpp
DC Current draw from an AOUT pin (Note 5) IOUT --10--10A
AC-Load Resistance (Note 6) RL3--3- -k
Load Capacitance (Note 6) CL- - 100 - - 100 pF
Output Impedance ZOUT -150- -150-
DS657F3 11
CS4265
6. Guaranteed by design. See Figure 2. RL and CL reflect the recommended minimum resistance and
maximum capacitance required for the internal op-amp’s stability. CL affects the dominant pole of the
internal output amp; increasing CL beyond 100 pF can cause the internal op-amp to become unstable.
DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
7. Filter response is guaranteed by design.
8. For Single-Speed Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs.
For Double-Speed Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs.
For Quad-Speed Mode, the Measurement Bandwidth is 0.7 Fs to 1 Fs.
9. De-emphasis is available only in Single-Speed Mode.
10. Response is clock dependent and will scale with Fs. Note that the amplitude vs. frequency plots of this
data (Figures 18 to 27) have been normalized to Fs and can be de-normalized by multiplying the X-axis
scale by Fs.
Parameter (Note 7,10)Symbol Min Typ Max Unit
Combined Digital and On-chip Analog Filter Response Single-Speed Mode
Passband (Note 7) to -0.1 dB corner
to -3 dB corner
0
0
-
-
0.35
0.4992
Fs
Fs
Frequency Response 10 Hz to 20 kHz -0.175 - +0.01 dB
StopBand 0.5465 - - Fs
StopBand Attenuation (Note 8) 50 - - dB
Group Delay tgd - 10/Fs - s
De-emphasis Error (Note 9) Fs = 44.1 kHz - - +0.05/-0.25 dB
Combined Digital and On-chip Analog Filter Response Double-Speed Mode
Passband (Note 7) to -0.1 dB corner
to -3 dB corner
0
0
-
-
0.22
0.501
Fs
Fs
Frequency Response 10 Hz to 20 kHz -0.15 - +0.15 dB
StopBand 0.5770 - - Fs
StopBand Attenuation (Note 8) 55 - - dB
Group Delay tgd - 5/Fs - s
Combined Digital and On-chip Analog Filter Response Quad-Speed Mode
Passband (Note 7) to -0.1 dB corner
to -3 dB corner
0
0
-
-
0.110
0.469
Fs
Fs
Frequency Response 10 Hz to 20 kHz -0.12 - 0 dB
StopBand 0.7 - - Fs
StopBand Attenuation (Note 8) 51 - - dB
Group Delay tgd - 2.5/Fs - s
DS657F3 13
CS4265
ADC ANALOG CHARACTERISTICS
Test conditions (unless otherwise specified): AGND = DGND = 0 V; VA = 3.13 V to 5.25 V; VD = 3.13 V to 5.25 V
or VA + 0.25 V, whichever is less; VLS = VLC = 1.71 V to 5.25 V; TA = -10° to +70° C for Commercial or -40° to
+85° C for Automotive; Input test signal: 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz;
Fs = 48/96/192 kHz.; All connections as shown in Figure 9 on page 23.
Line-Level Inputs
Parameter Symbol Min Typ Max Unit
Dynamic Performance for VA = 4.75 V to 5.25 V
Dynamic Range
PGA Setting: -12 dB to +6 dB
A-weighted
unweighted
(Note 13) 40 kHz bandwidth unweighted
PGA Setting: +12 dB Gain
A-weighted
unweighted
(Note 13) 40 kHz bandwidth unweighted
98
95
-
92
89
-
104
101
98
98
95
92
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
Total Harmonic Distortion + Noise (Note 12)
PGA Setting: -12 dB to +6 dB
-1 dB
-20 dB
-60 dB
(Note 13) 40 kHz bandwidth -1 dB
PGA Setting: +12 dB Gain
-1 dB
-20 dB
-60 dB
(Note 13) 40 kHz bandwidth -1 dB
THD+N
-
-
-
-
-
-
-
-
-95
-81
-41
-92
-92
-75
-35
-89
-89
-
-
-
-86
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
Dynamic Performance for VA = 3.13 V to 3.46 V
Dynamic Range
PGA Setting: -12 dB to +6 dB
A-weighted
unweighted
(Note 13) 40 kHz bandwidth unweighted
PGA Setting: +12 dB Gain
A-weighted
unweighted
(Note 13) 40 kHz bandwidth unweighted
93
90
-
89
86
-
101
98
95
95
92
89
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
Total Harmonic Distortion + Noise (Note 12)
PGA Setting: -12 dB to +6 dB
-1 dB
-20 dB
-60 dB
(Note 13) 40 kHz bandwidth -1 dB
PGA Setting: +12 dB Gain
-1 dB
-20 dB
-60 dB
(Note 13) 40 kHz bandwidth -1 dB
THD+N
-
-
-
-
-
-
-
-
-92
-78
-38
-84
-89
-72
-32
-81
-86
-
-
-
-83
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
Line-Level Inputs
Parameter Symbol Commercial Grade UnitMin Typ Max
Interchannel Isolation - 90 - dB
14 DS657F3
CS4265
11. Valid when the line-level inputs are selected.
DC Accuracy
Gain Error --10 %
Gain Drift -100 - ppm/°C
Line-Level Input Characteristics
Full-scale Input Voltage 0.51*VA 0.57*VA 0.63*VA Vpp
Input Impedance (Note 11) 6.12 6.8 7.48 k
Maximum Interchannel Input Impedance
Mismatch -5-%
Line-Level and Microphone-Level Inputs
Parameter Symbol Commercial Grade UnitMin Typ Max
DC Accuracy
Interchannel Gain Mismatch - 0.1 - dB
Programmable Gain Characteristics
Gain Step Size - 0.5 - dB
Absolute Gain Step Error - - 0.4 dB
DS657F3 15
CS4265
ADC ANALOG CHARACTERISTICS
(Continued)
12. Referred to the typical line-level full-scale input voltage
13. Valid for Double- and Quad-Speed Modes only.
14. Valid when the microphone-level inputs are selected.
Microphone-Level Inputs
Parameter Symbol Min Typ Max Unit
Dynamic Performance for VA = 4.75 V to 5.25 V
Dynamic Range
PGA Setting: -12 dB to 0 dB
A-weighted
unweighted
PGA Setting: +12 dB
A-weighted
unweighted
77
74
65
62
83
80
71
68
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise (Note 12)
PGA Setting: -12 dB to 0 dB
-1 dB
-20 dB
-60 dB
PGA Setting: +12 dB
-1 dB
THD+N
-
-
-
-
-80
-60
-20
-68
-74
-
-
-
dB
dB
dB
dB
Dynamic Performance for VA = 3.13 V to 3.46 V
Dynamic Range
PGA Setting: -12 dB to 0 dB
A-weighted
unweighted
PGA Setting: +12 dB
A-weighted
unweighted
77
74
65
62
83
80
71
68
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise (Note 12)
PGA Setting: -12 dB to 0 dB
-1 dB
-20 dB
-60 dB
PGA Setting: +12 dB
-1 dB
THD+N
-
-
-
-
-80
-60
-20
-68
-74
-
-
-
dB
dB
dB
dB
Interchannel Isolation - 80 - dB
DC Accuracy
Gain Error - 5-%
Gain Drift - 300 - ppm/°C
Microphone-Level Input Characteristics
Full-scale Input Voltage 0.013*VA 0.017*VA 0.021*VA Vpp
Input Impedance (Note 14) -60-k
16 DS657F3
CS4265
ADC DIGITAL FILTER CHARACTERISTICS
15. Filter response is guaranteed by design.
16. Response shown is for Fs = 48 kHz.
17. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 30 to 41) are
normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
Parameter (Notes 15, 17) Symbol Min Typ Max Unit
Single-Speed Mode
Passband (-0.1 dB) 0 - 0.4896 Fs
Passband Ripple - - 0.035 dB
Stopband 0.5688 - - Fs
Stopband Attenuation 70 - - dB
Total Group Delay (Fs = Output Sample Rate) tgd -12/Fs - s
Double-Speed Mode
Passband (-0.1 dB) 0 - 0.4896 Fs
Passband Ripple - - 0.025 dB
Stopband 0.5604 - - Fs
Stopband Attenuation 69 - - dB
Total Group Delay (Fs = Output Sample Rate) tgd -9/Fs - s
Quad-Speed Mode
Passband (-0.1 dB) 0 - 0.2604 Fs
Passband Ripple - - 0.025 dB
Stopband 0.5000 - - Fs
Stopband Attenuation 60 - - dB
Total Group Delay (Fs = Output Sample Rate) tgd -5/Fs - s
High-Pass Filter Characteristics
Frequency Response -3.0 dB
-0.13 dB (Note 16)
-1
20
-
-
Hz
Hz
Phase Deviation @ 20 Hz (Note 16) -10 -Deg
Passband Ripple -- 0dB
Filter Settling Time 105/Fs s
DS657F3 17
CS4265
DC ELECTRICAL CHARACTERISTICS
AGND = DGND = 0 V, all voltages with respect to ground. MCLK=12.288 MHz; Fs=48 kHz; Master Mode.
18. Power-Down Mode is defines as RESET = Low with all clock and data lines held static and no analog
input.
19. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection
Diagram.
20. Guaranteed by design. The DC current draw represents the allowed current draw due to typical leakage
through the electrolytic de-coupling capacitors.
Parameter Symbol Min Typ Max Unit
Power Supply Current VA = 5 V
(Normal Operation) VA = 3.3 V
VD, VLS, VLC = 5 V
VD, VLS, VLC = 3.3 V
IA
IA
ID
ID
-
-
-
-
41
37
39
23
50
45
47
28
mA
mA
mA
mA
Power Supply Current VA = 5 V
(Power-Down Mode) (Note 18) VLS, VLC, VD=5 V
IA
ID
-
-
0.50
0.54
-
-
mA
mA
Power Consumption
(Normal Operation) VA, VD, VLS, VLC = 5 V
VA, VD, VLS, VLC = 3.3 V
(Power-Down Mode) VA, VD, VLS, VLC = 5 V
-
-
-
-
-
-
400
198
4.2
485
241
-
mW
mW
mW
Power Supply Rejection Ratio (1 kHz) (Note 19) PSRR - 55 - dB
VQ Characteristics
Quiescent Voltage VQ - 0.5 x VA - VDC
DC Current from VQ (Note 20) IQ-- 1A
VQ Output Impedance ZQ-4.5 -k
FILT+ Nominal Voltage FILT+ - VA - VDC
Microphone Bias Voltage MICBIAS - 0.8 x VA - VDC
Current from MICBIAS IMB -- 2mA
18 DS657F3
CS4265
DIGITAL INTERFACE CHARACTERISTICS
Test conditions (unless otherwise specified): AGND = DGND = 0 V; VLS = VLC = 1.71 V to 5.25 V.
21. Serial Port signals include: MCLK, SCLK, LRCK, SDIN1, SDIN2, TXSDIN, SDOUT.
Control Port signals include: SCL, SDA, RESET.
22. Guaranteed by design.
Parameters (Note 21) Symbol Min Typ Max Units
High-Level Input Voltage
VL = 1.71 V Serial Port
Control Port
VL > 2.0 V Serial Port
Control Port
VIH
VIH
VIH
VIH
0.8xVLS
0.8xVLC
0.7xVLS
0.7xVLC
-
-
-
-
-
-
-
-
V
V
V
V
Low-Level Input Voltage Serial Port
Control Port
VIL
VIL
-
-
-
-
0.2xVLS
0.2xVLC
V
V
High-Level Output Voltage at Io= 2 mA Serial Port
Control Port
MUTEC
TXOUT
VOH
VOH
VOH
VOH
VLS-1.0
VLC-1.0
VA-1.0
VD-1.0
-
-
-
-
-
-
-
-
V
V
V
V
Low-Level Output Voltage at Io= 2 mA Serial Port
Control Port
MUTEC
TXOUT
VOL
VOL
VOL
VOL
-
-
-
-
-
-
-
-
0.4
0.4
0.4
0.4
V
V
V
V
Input Leakage Current Iin --±10A
Input Capacitance (Note 22) --1pF
Maximum MUTEC Drive Current - 3 - mA
DS657F3 19
CS4265
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT
Logic ‘0’ = DGND = AGND = 0 V; Logic ‘1’ = VL, CL = 20 pF. (Note 23)
23. See Figures 3 and 4 on page 20.
Parameter Symbol Min Typ Max Unit
Sample Rate Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
Fs
Fs
Fs
4
50
100
-
-
-
50
100
200
kHz
kHz
kHz
MCLK Specifications
MCLK Frequency fmclk 1.024 - 51.200 MHz
MCLK Input Pulse Width High/Low tclkhl 8--ns
MCLK Output Duty Cycle 45 50 55 %
Master Mode
LRCK Duty Cycle - 50 - %
SCLK Duty Cycle - 50 - %
SCLK falling to LRCK edge tslr -10 - 10 ns
SCLK falling to SDOUT valid tsdo 0 - 36 ns
SDIN valid to SCLK rising setup time tsdis 16 - - ns
SCLK rising to SDIN hold time tsdih 20 - - ns
Slave Mode
LRCK Duty Cycle 405060%
SCLK Period
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
tsclkw
tsclkw
tsclkw
-
-
-
-
-
-
ns
ns
ns
SCLK Pulse Width High tsclkh 30 - - ns
SCLK Pulse Width Low tsclkl 48 - - ns
SCLK falling to LRCK edge tslr -10 - 10 ns
SCLK falling to SDOUT valid tsdo 0 - 36 ns
SDIN valid to SCLK rising setup time tsdis 16 - - ns
SCLK rising to SDIN hold time tsdih 20 - - ns
109
128Fs
---------------------
109
64Fs
------------------
109
64Fs
------------------
DS657F3 21
CS4265
Figure 5. Format 0, Left-Justified up to 24-Bit Data
LRCK
SCLK
SDATA +3 +2 +1+5 +4
-1 -2 -3 -4 -5 +3 +2 +1+5 +4
MSB -1 -2 -3 -4
Channel A - Left Channel B - Right
LSBLSBMSB
Figure 6. Format 1, I²S up to 24-Bit Data
LRCK
SCLK
SDATA +3 +2 +1+5 +4
MSB -1 -2 -3 -4 -5 +3 +2 +1+5 +4
-1 -2 -3 -4
Channel A - Left Channel B - Right
LSB MSB LSB
LRCK
SCLK
SDATA +5 +4 +3 +2 +1-1 -2 -3 -4 -5 +5 +4 +3 +2 +1-1 -2 -3 -4 -5+6-6 +6-6
Channel A - Left Channel B - Right
MSB LSB MSB LSBLSB
Figure 7. Format 2, Right-Justified 16-Bit Data.
Format 3, Right-Justified 24-Bit Data.
22 DS657F3
CS4265
SWITCHING CHARACTERISTICS - I²C CONTROL PORT
Inputs: Logic 0 = DGND = AGND = 0 V, Logic 1 = VLC, CL=30pF.
24. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
25. Guaranteed by design.
Parameter Symbol Min Max Unit
SCL Clock Frequency fscl - 100 kHz
RESET Rising Edge to Start tirs 500 - ns
Bus Free Time Between Transmissions tbuf 4.7 - µs
Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs
Clock Low time tlow 4.7 - µs
Clock High Time thigh 4.0 - µs
Setup Time for Repeated Start Condition tsust 4.7 - µs
SDA Hold Time from SCL Falling (Note 24) thdd 0-µs
SDA Setup time to SCL Rising tsud 250 - ns
Rise Time of SCL and SDA (Note 25) trc, trd -1µs
Fall Time SCL and SDA (Note 25) tfc, tfd - 300 ns
Setup Time for Stop Condition tsusp 4.7 - µs
Acknowledge Delay from SCL Falling tack 300 1000 ns
tbuf thdst
tlow thdd
thigh
tsud
Stop Sta rt
SDA
SCL
tirs
RST
thdst
trc
tfc
tsust
tsusp
Start Stop
Repeated
trd tfd
tack
Figure 8. Control Port Timing - I²C Format
DS657F3 23
CS4265
3. TYPICAL CONNECTION DIAGRAM
VLS
10 µF
+3.3V to +5V
47 µF
VQ
FILT+
0.1 µF
10 µF
0.1 µF
10 µF
0.1 µF
+1.8V
to +5V
DGND
VLC
0.1 µF
+1.8V
to +5V
SCL
SDA
RST
2 k
Note 1
LRCK
SDIN1
AGND
Digital Audio
Processor
Micro-
Controller
MCLK
SCLK
0.1 µF
VAVD
* Capacitors must be C0G or equivalent
Digital Audio
Output
2.2nF
AFILTA
AFILTB
MICIN1
MICIN2
Microphone Input 1
Microphone Input 2
2.2nF
SDIN2
TXOUT
TXSDIN
SDOUT
CS4265
2 k
0.1 µF 10 µF
MICBIAS
**
+3.3V to +5V
SGND Signal Ground
MUTEC Mute
Drive
AOUTA
AOUTB
470
470
3.3 µF
COptional
Analog
Muting
3.3 µF
10 k
10 kCRext
Rext
See Note 2
*
*
AIN1A Left Analog Input 1
10 µF
10 µF
1800 pF
1800 pF
100 k
100 k
100
100
AIN1B Right Analog Input 1
*
*
10 µF
10 µF
10 µF
Note 1: Resistors are required for I²C control
port operation
For best response to Fs/2 :
4704470
ext
ext
RFs
R
C
This circuitry is intended for applications where the CS4265
connects directly to an unbalanced output of the design . For internal
routing applications please see the DAC Analog Output
Characteristics section for loading limitations.
Note 2 :
RLRL
Note 3
Note 3: The value of RL is dictated by the
microphone carteridge.
VA
0.1 µF
AGND
47 k
Note 4: Sets the LSB of the 7-bit chip address.
See the I²C Control Port Description and
Timing section.
Note 4
Figure 9. Typical Connection Diagram
24 DS657F3
CS4265
4. APPLICATIONS
4.1 Recommended Power-Up Sequence
1. Hold RESET low until the power supply, MCLK, and LRCK are stable. In this state, the Control Port is
reset to its default settings.
2. Bring RESET high. The device will remain in a low power state with the PDN bit set by default. The con-
trol port will be accessible.
3. The desired register settings can be loaded while the PDN bit remains set.
4. Clear the PDN bit to initiate the power-up sequence.
4.2 System Clocking
The CS4265 will operate at sampling frequencies from 4 kHz to 200 kHz. This range is divided into three
speed modes as shown in Table 1.
4.2.1 Master Clock
MCLK/LRCK must maintain an integer ratio as shown in Table 2. The LRCK frequency is equal to Fs, the
frequency at which audio samples for each channel are clocked into or out of the device. The FM bits (See
“Functional Mode (Bits 7:6)” on page 38.) and the MCLK Freq bits (See “MCLK Frequency - Address 05h”
on page 39.) configure the device to generate the proper clocks in Master Mode, and receive the proper
clocks in Slave Mode. Table 2 illustrates several standard audio sample rates and the required MCLK and
LRCK frequencies.
Mode Sampling Frequency
Single-Speed 4-50 kHz
Double-Speed 50-100 kHz
Quad-Speed 100-200 kHz
Table 1. Speed Modes
LRCK
(kHz) MCLK (MHz)
64x 96x 128x 192x 256x 384x 512x 768x 1024x
32 ----8.1920 12.2880 16.3840 24.5760 32.7680
44.1 ----11.2896 16.9344 22.5792 33.8680 45.1584
48 ----12.2880 18.4320 24.5760 36.8640 49.1520
64 -- 8.1920 12.2880 16.3840 24.5760 32.7680 - -
88.2 -- 11.2896 16.9344 22.5792 33.8680 45.1584 - -
96 -- 12.2880 18.4320 24.5760 36.8640 49.1520 - -
128 8.1920 12.2880 16.3840 24.5760 32.7680 - - - -
176.4 11.2896 16.9344 22.5792 33.8680 45.1584 - - - -
192 12.2880 18.4320 24.5760 36.8640 49.1520 - - - -
Mode QSM DSM SSM
Table 2. Common Clock Frequencies
DS657F3 25
CS4265
In both Master and Slave Modes, the external MCLK must be divided down based on the MCLK/LRCK
ratio to achieve a post-divider MCLK/LRCK ratio of 256x for SSM, 128x for DSM, or 64x for QSM. Table 3
lists the appropriate dividers.
4.2.2 Master Mode
As a clock master, LRCK and SCLK will operate as outputs. LRCK and SCLK are internally derived from
MCLK with LRCK equal to Fs and SCLK equal to 64 x Fs as shown in Figure 10.
4.2.3 Slave Mode
In Slave Mode, SCLK and LRCK operate as inputs. The Left/Right clock signal must be equal to the sam-
ple rate, Fs, and must be synchronously derived from the supplied master clock, MCLK.
The serial bit clock, SCLK, must be synchronously derived from the master clock, MCLK, and be equal to
128x, 64x, 48x or 32x Fs, depending on the desired speed mode. Refer to Table 4 for required clock ra-
tios.
4.3 High-Pass Filter and DC Offset Calibration
When using operational amplifiers in the input circuitry driving the CS4265, a small DC offset may be driven
into the A/D converter. The CS4265 includes a high-pass filter after the decimator to remove any DC offset
MCLK/LRCK Ratio MCLK Dividers
64x --÷1
96x --÷1.5
128x -÷1÷2
192x -÷1.5÷3
256x ÷1 ÷2 ÷4
384x ÷1.5 ÷3 -
512x ÷2 ÷4 -
768x ÷3 - -
1024x ÷4 - -
Mode SSM DSM QSM
Table 3. MCLK Dividers
Single-Speed Double-Speed Quad-Speed
SCLK/LRCK Ratio 32x, 48x, 64x, 128x 32x, 48x, 64x 32x, 48x, 64x
Table 4. Slave Mode Serial Bit Clock Ratios
÷256
÷128
÷64
÷4
÷2
÷1
00
01
10
00
01
10
LRCK
SCLK
000
001
010
÷1
÷1.5
÷2
011
100
÷3
÷4
MCLK FM Bits
MCLK Freq Bits
Figure 10. Master Mode Clocking
26 DS657F3
CS4265
which could result in recording a DC level, possibly yielding clicks when switching between devices in a mul-
tichannel system.
The high-pass filter continuously subtracts a measure of the DC offset fro m the output of the decimation
filter. If the HPFFreeze bit (See “ADC High-Pass Filter Freeze (Bit 1)” on page 39.) is set during normal op-
eration, the current value of the DC offset for the each channel is frozen and this DC offset will continue to
be subtracted from the conversion result. This feature makes it possible to perform a system DC offset cal-
ibration by:
1. Running the CS4265 with the high-pass filter enabled until the filter settles. See the ADC Digital Filter
Characteristics section for filter settling time.
2. Disabling the high-pass filter and freezing the stored DC offset.
A system calibration performed in this way will eliminate offsets anywhere in the signal path between the
calibration point and the CS4265.
DS657F3 27
CS4265
4.4 Analog Input Multiplexer, PGA, and Mic Gain
The CS4265 contains a stereo 2-to-1 analog input multiplexer followed by a programmable gain amplifier
(PGA). The input multiplexer is able to select either a line-level input source, or a mic-level input source, and
route it to the PGA. The mic-level input passes through a +32 dB gain stage prior to the input multiplexer,
allowing it to be used for microphone-level signals without the need for any external gain. The PGA stage
provides 12 dB of gain or attenuation in 0.5 dB steps. Figure 11 shows the architecture of the input multi-
plexer, PGA, and mic gain stages.
The “Analog Input Selection (Bit 0)” on page 41 outlines the bit settings necessary to control the input mul-
tiplexer and mic gain. “Channel B PGA Control - Address 07h” on page 40 and “Channel A PGA Control -
Address 08h” on page 40 outline the register settings necessary to control the PGA. By default, the line-
level input is selected by the input multiplexer, and the PGA is set to 0 dB.
4.5 Input Connections
The analog modulator samples the input at 6.144 MHz (MCLK=12.288 MHz). The digital filter will reject sig-
nals within the stopband of the filter. However, there is no rejection for input signals which are
(n 6.144 MHz) the digital passband frequency, where n=0,1,2,... Refer to the Typical Connection Diagram
for the recommended analog input circuit that will attenuate noise energy at 6.144 MHz. The use of capac-
itors which have a lar ge voltage coefficient (such as ge neral-purpose ceramics) must be avoided since
these can degrade signal linearity. Any unused analog input pairs should be left unconnected.
4.5.1 Pseudo-Differential Input
The CS4265 implements a pseudo-differential input stage. The SGND input is intended to be used as a
pseudo-differential reference signal. This feature allows for common mode noise rejection with single-
ended signals. Figure 12 shows a basic diagram outlining the internal implementation of the pseudo-dif-
ferential input stage. The Typical Connection Diagram shows the recommended pseudo-differential input
PGA
MUX
+32 dB
AINA
MICIN1
Channel B
PGA Gain Bits
Out to ADC
Channel A
Out to ADC
Channel B
MUX
+32 dB
AINB
MICIN2
PGA
Analog Input
Selection Bits
Channel A
PGA Gain Bits
Figure 11. Analog In put Architecture
28 DS657F3
CS4265
topology. If pseudo-differential input functionality is not required, simply connect the SGND pin to AGND
through the parallel combination of a 10 µF and a 0.1 µF capacitor.
4.6 Output Connections
The CS4265 DACs implement a switched-capacitor filter, followed by a continuous time low-pass filter. Its
response, combined with tha t of the digital interpolator, is sh own in Section 8. “DAC Filter Plots” on
page 48”. The recommended external analog circuitry is shown in the Typical Connection Diagram.
The CS4265 DAC does not include phase or amplitude compensation for an external filter. Therefore, the
DAC system phase and amplitude response is dependent on the external analog circuitry.
4.7 Output Transient Control
The CS4265 uses Popguard® technology to minimize the effects of output transients during power-up and
power-down. This technique eliminates the audio transients commonly produced by single-ended, single-
supply converters when it is implemented with external DC-blocking capacitors connected in series with the
audio outputs. To make best use of this feature, it is necessary to understand its operation.
4.7.1 Power-Up
When the device is initially powered-up, the DAC outputs AOUTA and AOUTB are clamped to VQ, which
is initially low. After the PDN bit is released (set to ‘0’), the outputs begin to ramp with VQ towards the
nominal quiescent voltage. This ramp takes approximately 200 ms to complete. The gradual voltage
ramping allows time for the external DC-blocking capacitors to charge to VQ, effectively blocking the qui-
escent DC voltage. Audio output will begin after approximately 2000 sample periods.
4.7.2 Power-Down
To prevent audio transients at power-down, the DC-blocking capacitors must fully discharge before turn-
ing off the power. In order to do this, either the PDN should be set or the device should be reset about
250 ms before removing power. During this time, the voltage on VQ and the DAC outputs will gradually
discharge to GND. If power is removed before this 250 ms time period has passed, a transient will occur
when the VA supply drops below that of VQ. There is no minimum time for a power cycle; power may be
re-applied at any time.
4.7.3 Serial Interface Clock Changes
When changing the clock ratio or sample rate, it is recommended that zero data (or near zero data) be
present on the selected SDIN pin for at least 10 LRCK samples before the change is made. During the
+
-
VA
+
-
AINA
AINB
SGND
In to PG A
In to PG A
10 µF
0.1 µF
Note: If pseudo-differential input functionality is not required, the
connections shown with dashed line should be added.
Figure 12. Pseudo-Differential Input Stage
CS4265
DS657F3 29
CS4265
clocking change, the DAC outputs will always be in a zero-data state. If non-zero serial audio input is
present at the time of switching, a slight click or pop may be heard as the DAC output automatically goes
to its zero-data state.
4.8 DAC Serial Data Input Multiplexer
The CS4265 contains a 2-to-1 serial data input multiplexer. This allows two se parate data sources to be
input into the DAC without the use of any external multiplexing components. “Section 6.6.1 “DAC SDIN
Source (Bit 7)” on page 40” describes the control port settings necessary to control the multiplexer.
4.9 De-Emphasis Filter
The CS4265 includes on-chip digital de-emphasis optimized for a sample rate of 44.1 kHz. The filter re-
sponse is shown in Figure 13. The frequency response of the de-emphasis curve scales proportionally with
changes in sample rate, Fs. Please see Section 6.3.3 “De-Emphasis Control (Bit 1)” on page 38 for de-em-
phasis control.
The de-emphasis feature is included to accommodate audio recordings that utilize 50/15 s pre-emphasis
equalization as a means of noise reduction.
De-emphasis is only available in Single-Speed Mode.
4.10 Internal Digital Loopback
The CS4265 supports an internal digital loopback mode in which the output of the ADC is routed to the input
of the DAC. This mode may be activated by setting the LOOP bit in the Signal Selection register (See “Signal
Selection - Address 06h” section on page 40).
When this bit is set, the status of the DAC_DIF[1:0] bits in register 03h will be disregarded by the CS4265.
Any changes made to the DAC_DIF[1:0] bits while the LOOP bit is set will have no impact on operation until
the LOOP bit is cleared, at which time the Digital Interface Format of the DAC will operate according to the
format selected by the DAC_DIF[1:0] bits. While the LOOP bit is set, data will be present on the SDOUT pin
in the format selected by the ADC_DIF bit in register 04h.
Gain
dB
-10dB
0dB
Frequency
T2 = 15 µs
T1=50 µs
F1 F2
3.183 kHz 10.61 kHz
Figure 13. De-Emphasis Curve
30 DS657F3
CS4265
4.11 Mute Control
The MUTEC pin becomes active during power-up initialization, reset, muting, if the MCLK to LRCK ratio is
incorrect, and during power-down. The MUTEC pin is intended to be used as control for an external mute
circuit in order to add off-chip mute capability.
Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute min-
imum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer
to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit. The
MUTEC pin is an active-low CMOS driver. See Figure 14 for a suggested active-low mute circuit.
4.12 AES3 Transmitter
The CS4265 includes an IEC60958-3 digital audio transmitter. A comprehensive buffering scheme provides
write access to the channel status data. This buffering scheme is described in the “Channel Status Buffer
Management” section on page 53.
The IEC60958-3 transmitter encodes and transmits audio and digital data according to the IEC60958-3
(S/PDIF) interface standard. The transmitter receives audio data from the input pin TXSDIN and control
clocks from the PCM Serial Interface. Audio and control data are multiplexed together and bi-phase mark
encoded. The resulting bit stream is driven from the output pin TXOUT to an output connector either directly
or through a transformer. The transmitter is clocked from the clock input pin MCLK.
The channel status (C) bits in the transmitted data stream are taken from storage areas within the CS4265.
The user can manually access the internal storage of the CS4265 to configure the transmitted channel sta-
tus data. The “Channel Status Buffer M anagement” section describes the method of manually accessing
the storage areas. The CS4265 transmits all zeros in the user (U) data fields.
4.12.1 TxOut Driver
The line driver is a low skew, low impedance, single-ended output capable of driving cables directly. The
driver is set to ground during reset (RESET = LOW), when no transmit clock is provided, and optionally
LPF
+VEE
-VEE
560
Audio
Out
2 k
10 k
-VEE
+VA
MMUN2111LT1
AOUT
MUTEC
AC
Couple
47 k
Figure 14. Suggested Active-Low Mute Circuit
CS4265
DS657F3 31
CS4265
under the control of a register bit. The CS4265 also allows immediate muting of the IEC60958-3 transmit-
ter audio data through a control register bit.
External components are used to terminate and isolate the external cable from the CS4265. These com-
ponents are detailed in the “External IEC60958-3 Transmitter Components” section on page 52.
4.12.2 Mono Mode Operation
An IEC60958-3 stream may be used in more than one way to transmit 192 kHz sample rate data. One
method is to double the frame rate of the current format. This results is a stereo signal with a sample rate
of 192 kHz. An alternate method is implemented using the two sub-frames in a 96 kHz frame rate
IEC60958-3 signal to carry consecutive samples of a mono signal, resulting in a 192 kHz sample rate
stream. This allows older equipment, whose IEC60958-3 transmitters and receivers are not rated for
192 kHz frame rate operation, to handle 192 kHz sample rate information. In this “mono mode”, two ca-
bles are needed for stereo data transfer. The CS4265 offers Mono Mode operation. The CS4265 is placed
into and out of Mono Mode with the MMT control bit.
In Mono Mode, the input port will run at the audio sample rate (Fs), while the IEC60958-3 transmitter
frame rate will be at Fs/2. Consecutive left or right channel serial audio data samples may be selected for
transmission on the A and B sub-frames, and the channel status block transmitted is also selectable.
Using Mono Mode is only necessary if the incoming audio sample rate is already at 192 kHz and contains
both left and right audio data words. The “Mono Mode” IEC60958-3 output stream may also be achieved
by keeping the CS4265 in normal stereo mode and placing consecutive audio samples in the left and right
positions in an incoming 96 kHz word-rate data stream.
4.13 I²C Control Port Description and Timing
The control port is used to access the registers, allowing the CS4265 to be configured for the desired oper-
ational modes and formats. The operation of the control port may be completely asynchronous with respect
to the audio sample rates. However, to avoid potential interference problems, the control port pins should
remain static if no operation is required.
SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. A 47 k pull-up
or pull-down on the SDOUT pin will set AD0, the least significant bit of the chip address. A pull-up to VLS
will set AD0 to ‘1’ and a pull-down to DGND will set AD0 to ‘0’. The state of the SDOUT pin is sensed and
AD0 is set upon the release of RESET.
The signal timings for a read and write cycle are shown in Figure 15 and Figure 16. A Start condition is de-
fined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the
clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS4265 after
a Start condition consists of a 7-bit chip address field and an R/W bit (high for a read, low for a write). The
upper 6 bits of the 7-bit address field are fixed at 100111. To communicate with a CS4265, the chip address
field, which is the first byte sent to the CS4265, should match 100111 followed by the setting of AD0. The
eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the Memory Address Point-
er (MAP), which selects the register to be read or written. If the operation is a read, the contents of the reg-
ister pointed to by the MAP will be output. Following each data byte, the memory address pointer will
automatically increment to facilitate block reads and writes of successive registers. Each byte is separated
by an acknowledge bit. The ACK bit is output from the CS4265 after each input byte is read, and is input to
the CS4265 from the microcontroller after each transmitted byte.
32 DS657F3
CS4265
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown
in Figure 16, the write operation is aborted after the acknowledge for the MAP byte by sending a stop con-
dition. The following pseudocode illustrates an aborted write operation followed by a read operation.
Send start condition.
Send 100111x0 (chip address & write operation).
Receive acknowledge bit.
Send MAP byte.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 100111x1(chip address & read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
4.14 Status Reporting
The CS4265 has comprehensive status reporting capabilities. Many conditions can be reported in the status
register, as listed in the status register descriptions. See “Status - Address 0Dh” on page 43. Each source
may be masked off through mask register bits. In addition, each source may be set to ris ing edge, falling
edge, or level sensitive. Combined with the option of level-sensitive or edge-sensitive modes within the mi-
crocontroller, many different configurations are possible, depending on the needs of the equipment design-
er.
4 5 6 7 24 25
SCL
CHIP ADDRESS (WRITE) MAP BYTE DATA DATA +1
START
ACK
STOP
ACKACKACK
1 0 0 1 1 1 AD0 0
SDA 7 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0
0 1 2 3 8 9 12 16 17 18 19 10 11 13 14 15 27 28
26
DATA +n
Figure 15. Control Port Timing, I²C Write
SCL
CHIP ADDRESS (WRITE) MAP BYTE DATA DATA +1
START
ACK
STOP
ACK
ACK
ACK
1 0 0 1 1 1 AD0 0
SDA 1 0 0 1 1 1 AD0 1
CHIP ADDRESS (READ)
START
7 6 5 4 3 2 1 0 7 0 7 0 7 0
NO
16 8 9 12 13 14 15 4 5 6 7 0 1 20 21 22 23 24 26 27 28
2 3 10 11 17 18 19 25
ACK
DATA + n
STOP
Figure 16. Control Port Timing, I²C Read
DS657F3 33
CS4265
4.15 Reset
When RESET is low, the CS4265 enters a low-power mode and all internal states are reset, including the
control port and registers, the outputs are muted. When RESET is high, the control port becomes operation-
al, and the desired settings should be loaded into the control registers. Writing a 0 to the PDN bit in the Pow-
er Control register will then cause the part to leave the low-power state and begin operation.
The delta-sigma modulators settle in a matter of microseconds after the analog section is powered, either
through the application of power or by setting the RESET pin high. However, the voltage reference will take
much longer to reach a final value due to the presence of external capacitance on the FILT+ pin. During this
voltage reference ramp delay, both SDOUT and DAC outputs will be automatically muted.
It is recommended that RESET be activated if the analog or digital supplies drop below the recommended
operating condition to prevent power-glitch-related issues.
4.16 Synchronization of Multiple Devices
In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To
ensure synchronous sampling, the master clocks a nd left/right clocks mu st be the same for all o f the
CS4265s in the system. If only one master clock source is needed, one solution is to place one CS4265 in
Master Mode, and slave all of the other CS4265s to the one master. If multiple master clock sources are
needed, a possible solution would be to supply all clocks from the same external source and time the
CS4265 reset with the inactive edge of master clock. This will ensure that all converters begin sampling on
the same clock edge.
4.17 Grounding and Power Supply Decoupling
As with any high-resolution converter, the CS4265 requires careful attention to power supply and grounding
arrangements if its po tential performance is to b e realized. Figure 9 shows the recommended power ar-
rangements, with VA connected to a clean supply. VD, which powers the digital filter, may be run from the
system logic supply (VLS or VLC) or may be powered from the analog supply (VA) via a resistor. In this
case, no additional devices should be powered from VD. Power supply decoupling capacitors should be as
near to the CS4265 as possible, with the low value ceramic capacitor being the nearest. All signals, espe-
cially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the
modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to mini-
mize the electrical path from FILT+ and AGND. The CS4265 evaluation board demonstrates the optimum
layout and power supply arrangements. To minimize digital noise, connect the CS4265 digital outputs only
to CMOS inputs.
4.18 Package Considerations
The CS4265 is available in the compact QFN package. The under side of the QFN package reveals a large
metal pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with
an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of
vias should be used to connect this copper pad to one or more larger ground planes on other PCB layers.
In split ground systems, it is recommended that this thermal pad be connected to AGND for best perfor-
mance. The CS4265 evaluation board demonstrates the optimum thermal pad and via configuration.
34 DS657F3
CS4265
5. REGISTER QUICK REFERENCE
This table shows the register names and their associated default values.
Addr Function 7 6 5 4 3 2 1 0
01h Chip ID PART3 PART2 PART1 PART0 REV3 REV2 REV1 REV0
11010001
02h Power Control Freeze Reserved Reserved Reserved PDN_MIC PDN_ADC PDN_DAC PDN
00000001
03h DAC Control 1 Reserved Reserved DAC_DIF1 DAC_DIF0 Reserved MuteDAC DeEmph Reserved
00001000
04h ADC Control FM1 FM0 Reserved ADC_DIF Reserved MuteADC HPFFreeze M/S
00000000
05h MCLK
Frequency
Reserved MCLK
Freq2
MCLK
Freq1
MCLK
Freq0
Reserved Reserved Reserved Reserved
00000000
06h Signal Selec-
tion
SDINSel Reserved Reserved Reserved Reserved Reserved LOOP Reserved
01000000
07h PGA Ch B
Gain Control
Reserved Reserved Gain5 Gain4 Gain3 Gain2 Gain1 Gain0
00000000
08h PGA Ch A
Gain Control
Reserved Reserved Gain5 Gain4 Gain3 Gain2 Gain1 Gain0
00000000
09h Analog Input
Control
Reserved Reserved Reserved PGASoft PGAZero Reserved Reserved Select
00011001
0Ah DAC Ch A Vol-
ume Control
Vol7 Vol6 Vol5 Vol4 Vol3 Vol2 Vol1 Vol0
00000000
0Bh DAC Ch B Vol-
ume Control
Vol7 Vol6 Vol5 Vol4 Vol3 Vol2 Vol1 Vol0
00000000
0Ch DAC Control 2 DACSoft DACZero InvertDAC Reserved Reserved Reserved Reserved Reserved
11000000
0Dh Status Reserved Reserved Reserved EFTC ClkErr Reserved ADCOvfl ADCUndrfl
00000000
0Eh Status Mask Reserved Reserved Reserved EFTCM ClkErrM Reserved ADCOvflM ADCUndrflM
00000000
0Fh Status Mode
MSB
Reserved Reserved Reserved EFTC1 ClkErr1 Reserved ADCOvfl1 ADCUndrfl1
00000000
10h Status Mode
LSB
Reserved Reserved Reserved EFTC0 ClkErr0 Reserved ADCOvfl0 ADCUndrfl0
00000000
36 DS657F3
CS4265
6. REGISTER DESCRIPTION
6.1 Chip ID - Register 01h
Function:
This register is Read-Only. Bits 7 through 4 are the part number ID, which is 1101b (0Dh), and the remaining
bits (3 through 0) indicate the device revision as shown in Table 5 below.
6.2 Power Control - Address 02h
6.2.1 Freeze (Bit 7)
Function:
This function allows modifications to be made to certain control port bits without the changes taking effect
until the Freeze bit is disabled. To make multiple changes to these bits take effect simultaneously, set the
Freeze bit, make all changes, then clear the Freeze bit. The bits affected by the Freeze function are listed
in Table 6.
6.2.2 Power-Down MIC (Bit 3)
Function:
The microphone preamplifier block will enter a low-power state whenever this bit is set.
6.2.3 Power-Down ADC (Bit 2)
Function:
The ADC pair will remain in a reset state whenever this bit is set.
76543210
PART3 PART2 PART1 PART0 REV3 REV2 REV1 REV0
REV[2:0] Revision
001 A
010 B, C0
011 C1
Table 5. Devic e Revision
76543210
Freeze Reserved Reserved Reserved PDN_MIC PDN_ADC PDN_DAC PDN
Name Register Bit(s)
MuteDAC 03h 2
MuteADC 04h 2
Gain[5:0] 07h 5:0
Gain[5:0] 08h 5:0
Vol[7:0] 0Ah 7:0
Vol[7:0] 0Bh 7:0
TxMute 0Eh 4
Table 6. Freeze-able Bits
DS657F3 37
CS4265
6.2.4 Power-Down DAC (Bit 1)
Function:
The DAC pair will remain in a reset state whenever this bit is set.
6.2.5 Power-Down Device (Bit 0)
Function:
The device will enter a low-power state whenever this bit is set. The power-down bit is set by default and
must be cleared before normal operation can occur. The contents of the control registers are retained
when the device is in power-down.
6.3 DAC Control - Address 03h
6.3.1 DAC Digital Interface Format (Bits 5:4)
Function:
The required relationship between LRCK, SCLK and SDIN for the DAC is defined by the DAC Digital In-
terface Format and the options are detailed in Table 7 and Figures 5-7.
6.3.2 Mute DAC (Bit 2)
Function:
The DAC outputs will mute and the MUTEC pin will become active when this bit is set. Though this bit is
active high, it should be noted that the MUTEC pin is active low. The common mode voltage on the outputs
will be retained when this bit is set. The muting function is effected, similar to attenuation changes, by the
DACSoft and DACZero bits in the DAC Control 2 register.
76543210
Reserved Reserved DAC_DIF1 DAC_DIF0 Reserved MuteDAC DeEmph Reserved
DAC_DIF1 DAC_DIF0 Description Format Figure
0 0 Left Justified, up to 24-bit data (default) 0 5
0 1 I²S, up to 24-bit data 1 6
1 0 Right-Justified, 16-bit Data 2 7
1 1 Right-Justified, 24-bit Data 3 7
Table 7. DAC Digital Interface Formats
38 DS657F3
CS4265
6.3.3 De-Emphasis Control (Bit 1)
Function:
The standard 50/15 s digital de-emphasis filter response, Figure 17, may be implemented for a sample
rate of 44.1 kHz when the DeEmph bit is configured as shown in Table 8. NOTE: De-emphasis is available
only in Single-Speed Mode.
6.4 ADC Control - Address 04h
6.4.1 Functional Mode (Bits 7:6)
Function:
Selects the required range of sample rates.
6.4.2 ADC Digital Interface Format (Bit 4)
Function:
The required relationship between LRCK, SCLK and SDOUT is defined by the ADC Digital Interface For-
mat bit. The options are detailed in Table 10 and may be seen in Figure 5 and Figure 6.
DeEmph Description
0 Disabled (default)
1 44.1 kHz de-emphasis
Table 8. De-Empha sis Control
76543210
FM1 FM0 Reserved ADC_DIF Reserved MuteADC HPFFreeze M/S
FM1 FM0 Mode
0 0 Single-Speed Mode: 4 to 50 kHz sample rates
0 1 Double-Speed Mode: 50 to 100 kHz sample rates
1 0 Quad-Speed Mode: 100 to 200 kHz sample rates
11Reserved
Table 9. Functional Mode Selection
Gain
dB
-10dB
0dB
Frequency
T2 = 15 µs
T1=50 µs
F1 F2
3.183 kHz 10.61 kHz
Figure 17. De-Emphas is Curve
DS657F3 39
CS4265
6.4.3 Mute ADC (Bit 2)
Function:
When this bit is set, the serial audio output of the both ADC channels is muted.
6.4.4 ADC High-Pass Filter Freeze (Bit 1)
Function:
When this bit is set, the internal high-pass filter is disabled. The current DC offset value will be frozen and
continue to be subtracted from the conversion result. See “High-Pass Filter and DC Offset Calibration” on
page 25.
6.4.5 Master / Slave Mode (Bit 0)
Function:
This bit selects either master or slave operation for the serial audio port. Setting this bit selects Master
Mode, while clearing this bit selects Slave Mode.
6.5 MCLK Frequency - Address 05h
6.5.1 Master Clock Dividers (Bits 6:4)
Function:
Sets the frequency of the supplied MCLK signal. See Table 11 for the appropriate settings.
ADC_DIF Description Format Figure
0 Left-Justified, up to 24-bit data (default) 0 5
1 I²S, up to 24-bit data 1 6
Table 10. ADC Digital Interface Formats
76543210
Reserved MCLK
Freq2
MCLK
Freq1
MCLK
Freq0 Reserved Reserved Reserved Reserved
MCLK Divider MCLK Freq2 MCLK Freq1 MCLK Freq0
÷1 000
÷1.5 001
÷2 010
÷3 011
÷4 100
Reserved 101
Reserved 11x
Tab le 11. MCLK Frequency
40 DS657F3
CS4265
6.6 Signal Selection - Address 06h
6.6.1 DAC SDIN Source (Bit 7)
Function:
This bit is used to select the serial audio data source for the DAC as shown in Table 12.
6.6.2 Digital Loopback (Bit 1)
Function:
When this bit is set, an internal digital loopback from the ADC to the DAC will be enabled. Please refer to
“Internal Digital Loopback” on page 29.
6.7 Channel B PGA Control - Address 07h
6.7.1 Channel B PGA Gain (Bits 5:0)
Function:
See “Channel A PGA Gain (Bits 5:0)” on page 40.
6.8 Channel A PGA Control - Address 08h
6.8.1 Channel A PGA Gain (Bits 5:0)
Function:
Sets the gain or attenuation for the ADC input PGA stage. The gain may be adjusted from -12 dB to
+12 dB in 0.5 dB steps. The gain bits are in two’s complement with the Gain0 bit set for a 0.5 dB step.
Register settings outside of the ±12 dB range are reserved and must not be used. See Table 13 for ex-
ample settings.
76543210
SDINSel Reserved Reserved Reserved Reserved Reserved LOOP Reserved
SDINSel Setting DAC Data Source
0 SDIN1
1 SDIN2
Table 12. DAC SDIN Source Selection
76543210
Reserved Reserved Gain5 Gain4 Gain3 Gain2 Gain1 Gain0
76543210
Reserved Reserved Gain5 Gain4 Gain3 Gain2 Gain1 Gain0
Gain[5:0] Setting
101000 -12 dB
000000 0 dB
011000 +12 dB
Table 13. Example Gain and Attenuation Settin gs
DS657F3 41
CS4265
6.9 ADC Input Control - Address 09h
6.9.1 PGA Soft Ramp or Zero Cross Enable (Bits 4:3)
Function:
Soft Ramp Enable
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramp-
ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
See Table 14.
Zero Cross Enable
Zero Cross Enable dictates that signal-level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a time-
out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal
does not encounter a zero crossing. The zero cross function is independently monitored and implemented
for each channel. See Table 14.
Soft Ramp and Zero Cross Enable
Soft Ramp and Zero Cross Enable dictate that signal-level changes, either by attenuation changes or mut-
ing, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will
occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sam-
ple rate) if the signal does not encounter a zero crossing. The zero cross function is independently mon-
itored and implemented for each channel. See Table 14.
6.9.2 Analog Input Selection (Bit 0)
Function:
These bits are used to select the input source for the PGA and ADC. Please see Table 15.
6.10 DAC Channel A Volume Control - Address 0Ah
See 6.11 DAC Channel B Volume Control - Address 0Bh.
76543210
Reserved Reserved Reserved PGASoft PGAZero Reserved Reserved Select
PGASoft PGAZeroCross Mode
0 0 Changes to affect immediately
0 1 Zero Cross enabled
1 0 Soft Ramp enabled
1 1 Soft Ramp and Zero Cross enabled (default)
Table 14. PGA Soft Cross or Zero Cross Mode Selection
Select PGA/ADC Input
0 Microphone-Level Input
1 Line-Level Input
Table 15. Analog Input Selection
42 DS657F3
CS4265
6.11 DAC Channel B Volume Control - Address 0Bh
6.11.1 Volume Control (Bits 7:0)
Function:
The digital volume control allows the user to attenuate the signal in 0.5 dB increments from 0 to -127 dB.
The Vol0 bit activates a 0.5 dB attenuation when set, and no attenuation when cleared. The Vol[7:1] bits
activate attenuation equal to their decimal equivalent (in dB). Example volume settings are decoded as
shown in Table 16. The volume changes are implemented as dictated by the DACSoft and DACZero-
Cross bits in the DAC Control 2 register (see Section 6.12.1).
6.12 DAC Control 2 - Address 0Ch
6.12.1 DAC Soft Ramp or Zero Cross Enable (Bits 7:6)
Function:
Soft Ramp Enable
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramp-
ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
See Table 17.
Zero Cross Enable
Zero Cross Enable dictates that signal-level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a time-
out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal
does not encounter a zero crossing. The zero cross function is independently monitored and implemented
for each channel. See Table 17.
Soft Ramp and Zero Cross Enable
Soft Ramp and Zero Cross Enable dictate that signal-level changes, either by attenuation changes or mut-
ing, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will
occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sam-
76543210
Vol7 Vol6 Vol5 Vol4 Vol3 Vol2 Vol1 Vol0
Binary Code Volume Setting
00000000 0 dB
00000001 -0.5 dB
00101000 -20 dB
00101001 -20.5 dB
11111110 -127 dB
11111111 -127.5 dB
Table 16. Digital Volume Control Example Settings
76543210
DACSoft DACZero InvertDAC Reserved Reserved Reserved Reserved Reserved
DS657F3 43
CS4265
ple rate) if the signal does not encounter a zero crossing. The zero cross function is independently mon-
itored and implemented for each channel. See Table 17.
6.12.2 Invert DAC Output (Bit 5)
Function:
When this bit is set, the output of the DAC is inverted.
6.13 Status - Address 0Dh
For all bits in this register, a ‘1’ means the associated condition has occurred at least once since the register
was last read. A ‘0’ means the associated condition has NOT occurred since the last reading of the register.
Status bits that are masked off in the associated mask register will always be ‘0’ in this register. This register
defaults to 00h.
6.13.1 E to F C-Buff er Transfer
Function:
Indicates the completion of an E to F C-buffer transfer. See “Channel Status Buffer Management” on
page 53 for more information.
6.13.2 Clock Error (Bit 3)
Function:
Indicates the occurrence of a clock error condition.
6.13.3 ADC Overflow (Bit 1)
Function:
Indicates the occurrence of an ADC overflow condition.
6.13.4 ADC Underflow (Bit 0)
Function:
Indicates the occurrence of an ADC underflow condition.
DACSoft DACZeroCross Mode
0 0 Changes to affect immediately
0 1 Zero Cross enabled
1 0 Soft Ramp enabled
1 1 Soft Ramp and Zero Cross enabled (default)
Table 17. DAC Soft Cross or Zero Cross Mode Selection
76543210
Reserved Reserved Reserved EFTC ClkErr Reserved ADCOvfl ADCUndrfl
44 DS657F3
CS4265
6.14 Status Mask - Address 0Eh
Function:
The bits of this register serve as a mask for the Status sources found in the register “Status - Address 0Dh”
on page 43. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect the status
register. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not affect the status
register. The bit positions align with the corresponding bits in the Status register.
6.15 Status Mode MSB - Address 0Fh
6.16 Status Mode LSB - Address 10h
Function:
The two Status Mode registers form a 2-bit code for each Status register function. There are three ways to
update the Status register in accordance with the status condition. In the Rising-Edge Active Mode, the sta-
tus bit becomes active on the arriva l of the c ondition. In the Falling-Ed ge Active Mode, the status bit be-
comes active on the removal of the condition. In Level-Active Mode, the status bit is ac tive during the
condition.
00 - Rising edge active
01 - Falling edge active
10 - Level active
11 - Reserved
6.17 Transmitter Control 1 - Address 11h
6.17.1 E to F C-Data Buffer Transfer Inhibit (Bit 6)
Function:
When cleared, C-data E to F buffer transfers are allowed. When set, C-data E to F buffer transfers are
inhibited. See “IEC60958-3 Channel Status (C) Bit Management” on page 53.
6.17.2 C-Data Access Mode (Bit 5)
Function:
When cleared, the C-data buffer will operate in One-byte control port access mode. When set, the C-data
buffer will operate in Two-byte control port access mode. See “IEC60958-3 Channel Status (C) Bit Man-
agement” on page 53.
76543210
Reserved Reserved Reserved EFTCM ClkErrM Reserved ADCOvflM ADCUndrflM
76543210
Reserved Reserved Reserved EFTC1 ClkErr1 Reserved ADCOvfl1 ADCUndrfl1
Reserved Reserved Reserved EFTC0 ClkErr0 Reserved ADCOvfl0 ADCUndrfl0
76543210
Reserved EFTCI CAM Reserved Reserved Reserved Reserved Reserved
DS657F3 45
CS4265
6.18 Transmitter Control 2 - Address 12h
6.18.1 Transmitter Digital Interface Format (Bits 7:6)
Function:
The required relationship between LRCK, SCLK and SDIN for the transmitter is defined by the Transmitter
Digital Interface Format and the options are detailed in Table 18 and Figures 5-7.
6.18.2 Transmitter Output Driver Control (Bit 5)
Function:
When this bit is cleared, the transmitter output pin driver will be in the normal operational mode. When
set, the transmitter output pin driver will drive to a constant 0 V.
6.18.3 Transmitter Mute Control (Bit 4)
Function:
When this bit is cleared, the transmitter data will be in the normal operational mode. When set, the trans-
mitter will output all zero data.
6.18.4 Transmitted Validity Bit Control (Bit 3)
Function:
This bit sets the transmitted Validity bit level.
When this bit is cleared, valid linear PCM audio data is indicated. When this bit is set, invalid or non-linear
PCM audio data is indicated.
6.18.5 Transmitter Mono/Stereo Operation Control (Bit 2)
Function:
When this bit is cleared, the transmitter will operate in stereo mode. When set, the transmitter will operate
in Mono Mode with one input channel’s data output in both A and B subframes (see “IEC60958-3 Channel
Status (C) Bit Management” on page 53) and the CS data defined by the MMTCS bit (see Section 6.18.6).
6.18.6 Mono Mode CS Data Source (Bit 1)
Function:
When this bit is cleared, the transmitter will transmit the channel A CS data in the A subframe and the
channel B CS data in the B subframe.
When this bit is set, the transmitter will transmit the CS data defined for the channel selected by the
MMTLR bit in both the A and B subframes.
76543210
Tx_DIF1 Tx_DIF0 TxOff TxMute V MMT MMTCS MMTLR
Tx_DIF1 Tx_DIF0 Description Format Figure
0 0 Left Justified, up to 24-bit data (default) 0 5
0 1 I²S, up to 24-bit data 1 6
1 0 Right-Justified, 16-bit Data 2 7
1 1 Right-Justified, 24-bit Data 3 7
Table 18. Transmitter Digital Interface Formats
DS657F3 47
CS4265
7. PARAMETER DEFINITIONS
Dynamic Range
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with
a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full scale. This
technique ensures that the distortion components are below the noise level and do not affect the measure-
ment. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991,
and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.
Tota l Harmonic Distortion + Noise
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured
at -1 and -20 dBFS as suggested in AES17-1991 Annex A.
Frequency Response
A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at
1 kHz. Units in decibels.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with no signal to the input under test and a full-scale signal applied to the other channel. Units in deci-
bels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
48 DS657F3
CS4265
8. DAC FILTER PLOTS
Figure 18. DAC Single-Speed Stopband Rejection Figure 19. DAC Single-Speed Transition Band
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
-0.25
-0. 2
-0.15
-0. 1
-0.05
0
0.05
Frequency (normalized to Fs)
Amplitude dB
Figure 20. DAC Single-Speed Transition Band Figure 21. DAC Single-Speed Passband Ripple
0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
Frequency (normalized to Fs)
Amplitude dB
Figure 22. DAC Double-Speed Stopband Rejection Figure 23. DAC Double-Speed Transition Band
DS657F3 49
CS4265
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
-0. 2
-0. 1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Frequency (normalized to Fs)
Amplitude dB
0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
Frequency (normalized to Fs)
Amplitude dB
Figure 24. DAC Double-Speed Transition Band Figure 25. DAC Double-Speed Passband Ripple
Figure 26. DAC Quad-Speed Stopband Rejection Figure 27. DAC Quad-Speed Transition Band
0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75
-60
-50
-40
-30
-20
-10
0
Amplitude (dB)
Frequency(normalized to Fs)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
Amplitude (dB)
Frequency(normalized to Fs)
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
-1. 5
-1
-0. 5
0
Frequency (normalized to Fs)
Amplitude dB
Figure 28. DAC Quad-Speed Transition Band Figure 29. DAC Quad-Speed Passband Ripple
0.4 0.45 0.5 0.55 0.6 0.65 0.7
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
Amplitude (dB)
Frequency(normalized to Fs)
50 DS657F3
CS4265
9. ADC FILTER PLOTS
Figure 30. ADC Single -Speed Stopband Rejectio n Figure 31. ADC Single-Speed Stopband Rejection
Figure 32. ADC Single-Speed Transition Band (Detail) Figure 33. ADC Single-Speed Passband Ripple
Figure 34. ADC Double-Speed Stopband Rejection Figure 35. ADC Double-Speed Stopband Rejection
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.0 0.1 0 .2 0 .3 0.4 0.5 0.6 0.7 0 .8 0.9 1.0
Frequency (normali zed to Fs)
Amplitude (dB)
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60
Frequency (normalized to Fs)
Amplitude (dB)
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55
Frequency (normalized to Fs)
Amplitude (dB)
-0.10
-0.08
-0.06
-0.04
-0.02
0.00
0.02
0.04
0.06
0.08
0.10
0 0 .05 0.1 0.15 0.2 0.2 5 0.3 0.35 0.4 0.45 0.5
Frequency (normalized to Fs)
Amplitude (dB)
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.0 0.1 0 .2 0 .3 0.4 0.5 0.6 0.7 0 .8 0.9 1.0
Frequency (normali zed to Fs)
Amplitude (dB)
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60
Frequency (normalized to Fs)
Amplitude (dB)
DS657F3 51
CS4265
Figure 36. ADC Double-Speed Transition Band (Detail) Figure 37 . ADC Double-Speed Passband Ripple
Figure 38. ADC Quad-Speed Stopband Rejection Figure 39. ADC Quad-Speed Stopband Rejection
Figure 40. ADC Quad-Speed Transition Band (Detail) Figure 41. ADC Quad-Speed Passband Ripple
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
0.46 0.47 0.48 0.49 0.50 0.51 0.52
Frequency (normalized to Fs)
Amplitude (dB)
-0.10
-0.08
-0.06
-0.04
-0.02
0.00
0.02
0.04
0.06
0.08
0.10
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Frequency (normalized to Fs)
Amplitude (dB)
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.0 0.1 0 .2 0 .3 0.4 0.5 0.6 0.7 0 .8 0.9 1.0
Frequency (normali zed to Fs)
Amplitude (dB)
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85
Frequency (normali zed to Fs)
Amplitude (dB)
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Frequency (normalized to Fs)
Amplitude (dB)
-0.10
-0.08
-0.06
-0.04
-0.02
0.00
0.02
0.04
0.06
0.08
0.10
0.00 0.03 0.05 0.08 0.10 0.13 0.15 0.18 0.20 0.23 0.25 0.28
Frequency (norma li zed to Fs)
Amplitude (dB)
52 DS657F3
CS4265
10.EXTERNAL IEC60958-3 TRANSMITTER COMPONENTS
This section details the external components required to interface the IEC60958-3 transmitter to cables and fiber-
optic components.
10.1 IEC60958-3 Transmitter External Compon ents
The IEC60958-3 specifications call for an unbalanced drive circuit with an output impedance of 75
and an output drive level of 0.5 volts peak-to-peak ±20% when measured across a 75 load using no cable.
The circuit shown in Figure 42 provides the proper output impedance and drive level using standard 1% re-
sistors. If VD is driven from +3.3 V, use resistor values of 243 in place of the 374 resistor and a 107
resistor in place of the 90.9 resistor. The standard connector for a consumer application is an RCA phono
socket.
The TXOUT pin may be used to drive TTL or CMOS gates as shown in Figure 43. This circuit may be used
for optical connectors for digital audio as they typically implement TTL or CMOS compatible inputs. This cir-
cuit is also useful when driving multiple digital audio outputs as RS422 line drivers typically implement TTL
compatible inputs.
10.2 Isolating Transformer Requirements
Please refer to Cirrus application note AN134: AES and SPDIF Recommended Transformers for resources
on transformer selection.
374-RTXP
90.9
TXOUT
RCA
Phono
Figure 42. Consumer Output Circui t (VD = 5 V)
CS4265
TXOUT
TTL or
CMOS Gate
Figure 43. TTL/CMOS Output Circuit
CS4265
DS657F3 53
CS4265
11.CHANNEL STATUS BUFFER MANAGEMENT
The CS4265 has a comprehensive channel status (C) data buffering scheme which allows the user to manage the
C data through the control port.
11.1 IEC60958-3 Channel Status (C) Bit Management
The CS4265 contains sufficient RAM to store a full block of C data for both A and B channels (192x2 = 384
bits). The user may read from, or write to, these RAM buffers through the control port.
The CS4265 manages the flow of channel status data at the block level, meaning that entire blocks of chan-
nel status information are buffered at the input, synchronized to the output time base, and then transmitted.
The buffering scheme involves a cascade of two block-sized buffers, named E and F, as shown in Figure 44.
The MSB of each byte represents the first bit in the serial C data stream. For example, the MSB of byte 0
(which is at control port address 13h) is the consumer/professional bit for channel status block A.
The E buffer is accessible from the control port, allowing read and writing of the C data. The F buffer is used
as the source of C data for the IEC60958-3 transmitter. The F buffer accepts block transfers from the E buff-
er.
Control Port
To
AES3
Transmitter
E
24
words
8-bits 8-bits
AB
F
Transmit
Data
Buffer
Figure 44. Channel Status Data Buffer Structu re
54 DS657F3
CS4265
11.1.1 Accessing the E Buffer
The user can monitor the data being transferred by reading the E buffer, which is mapped into the register
space of the CS4265, through the control port. The user can modify the data to be transmitted by writing
to the E buffer.
The E buffer is only accessible when an MCLK signal is applied to the CS4265 and the device is out of
the power-down state (the PDN bit in register 02h is cleared). If either of these conditions is not met, the
values stored in the E buffer will not change when written via the control port.
The user can configure the status register such that EFTC bit is set whenever an E to F transfer com-
pletes. With this configuration in place, periodic polling of the status register allows determination of the
time periods acceptable for E buffer interaction.
Also provided is an “E to F” inhibit bit. The “E to F” buffer transfer is disabled whenever the user sets this
bit. This may be used whenever “long” control port interactions are occurring.
A flowchart for reading and writing to the E buffer is shown in Figure 45. For writing, the sequence starts
after an E to F transfer, which is based on the output time base.
11.2 Serial Copy Management System (SCMS)
The CS4265 allows read/modify/write access to all the channel status bits. For consumer mode SCMS com-
pliance, the host microcontroller needs to manipulate the Category Code, Copy bit and L bit appropriately.
11.3 Channel Status Data E Buffer Access
The E buffer is organized as 24 x 16 -bit words. For each word, the most significant byte is the A channel
data, and the least significant byte is the B channel data (see Figure 44).
There are two methods of accessing this memory, known as One-Byte Mode and Two-Byte Mode. The de-
sired mode is selected through a control register bit.
Read the Status Register
(Reg 0Dh)
If set, clear E to F inhibit
Write E data
Optionally set E to F inhibit
Is the EFTC bit set?
Configure the EFTC status bit as
Rising Edge active.
Begin
Yes
No
Figure 45. Flowchart for Writing the E Buffer
DS657F3 55
CS4265
11.3.1 One-Byte Mo de
In many applications, the channel status blocks for the A and B channels will be identical. In this situation,
if the user reads a byte from one of the channel's blocks, the corresponding byte for the other channel will
be the same. Similarly, if the user wrote a byte to one channel's block, it would be necessary to write the
same byte to the other block. One-Byte Mode takes advantage of the often identical nature of A and B
channel status data.
When reading data in One-Byte Mode, a single byte is returned, which can be from channel A or B data,
depending on a register control bit. If a write is being done, the CS4265 expects a single byte to be input
to its control port. This byte will be written to both the A and B locations in the addressed word.
One-Byte Mode saves the user substantial control port access time, as it effectively accesses two byte’s
worth of information in 1 byte's worth of access time. If the control port's auto increment addressing is used
in combination with this mode, multi-byte accesses such as full-block reads or writes can be done espe-
cially efficiently.
11.3.2 Two-Byte Mode
There are those applications in which the A and B channel status blocks will not be the same, and the
user is interested in accessing both blocks. In these situations, Two-Byte Mode should be used to access
the E buffer.
In this mode, a read will cause the CS4265 to output two bytes from its control port. The first byte out rep-
resents the A channel status data, and the second byte represents the B channel status data. Writing is
similar, in that two bytes must now be input to the CS4265's control port. The A channel status data is
first; B channel status data is second.
56 DS657F3
CS4265
12.PACKAGE DIMENSIONS
Notes:
1. Dimensioning and tolerance per ASME Y 14.5M-1995.
2. Dimensioning lead width applies to the plated terminal and is measured between 0.20 mm and 0.25 mm
from the terminal tip.
13.THERMAL CHARACTERISTICS AND SPECIFICATIONS
INCHES MILLIMETERS NOTE
DIM MIN NOM MAX MIN NOM MAX
A----0.0394----1.001
A1 0.0000 -- 0.0020 0.00 -- 0.05 1
b 0.0071 0.0091 0.0110 0.18 0.23 0.28 1,2
D 0.1969 BSC 5.00 BSC 1
D2 0.1280 0.1299 0.1319 3.25 3.30 3.35 1
E 0.1969 BSC 5.00 BSC 1
E2 0.1280 0.1299 0.1319 3.25 3.30 3.35 1
e 0.0197 BSC 0.50 BSC 1
L 0.0118 0.0157 0.0197 0.30 0.40 0.50 1
JEDEC #: MO-220
Controlling Dimension is Millimeters.
Parameters Symbol Min Typ Max Units
Package Thermal Resistance 2 Layer Board
4 Layer Board JA
-
-
52
38
-
-
°C/Watt
°C/Watt
Allowable Junction Temperature --125
C
Side View
A1
Bottom View
Top View
A
Pin #1 Corner
D
E
D2
L
be Pin #1 Corner
E2
32L QFN (5 X 5 mm BODY) PACKAGE DRAWING
DS657F3 57
CS4265
14.ORDERING INFORMATION
15.REVISION HISTORY
Product Description Package Pb-Free Grade Temp Range Container Order #
CS4265 24-bit, 192 kHz
Stereo Audio CODEC 32-QFN Yes Commercial -10° to +70° C Tube CS4265-CNZ
Tape & Reel CS4265-CNZR
CS4265 24-bit, 192 kHz
Stereo Audio CODEC 32-QFN Yes Automotive -40° to +105° C Tube CS4265-DNZ
Tape & Reel CS4265-DNZR
CDB4265 CS4265 Evaluation Board No - - - CDB4265
Release Changes
F1
– Removed the MAP auto-increment functional description from the I²C Control Port Description and Timing
section beginning on page 31.
– Added device revision information to the Chip ID - Register 01h description on page 36.
– Updated the VQ Output Impedance specification in the DC Electrical Characteristics table on page 17.
– Updated the Microphone Interchannel Isolation specification in the ADC Analog Characteristics table on page 15.
F2
– Added Automotive Grade
– Updated the DAC Analog Characteristics table on page 10.
– Updated the ADC Analog Characteristics table on page 13.
– Updated the DC Electrical Characteristics table on page 17.
– Updated the Digital Interface Characteristics table on page 18.
– Updated the Switching Characteristics - Serial Audio Port table on page 19.
– Updated the Typical Connection Diagram on page 23.
– Switched Channel B PGA Control - Address 07h on page 40 and Channel A PGA Control - Address 08h on
page 40.
F3 – Added Table 3.
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find the one nearest you, go to www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con-
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does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP-
ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE-
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TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED
IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICA-
TIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER
AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH
THESE USES.
Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be
trademarks or service marks of their respective owners.
I²C is a registered trademark of Philips Semiconductor.
