PIC18F2682T-I/SO - Microchip Technology, Inc.

PIC16F610/16HV610

PIC16F616/16HV616

Data Sheet

14-Pin, Flash-Based 8-Bit

CMOS Microcontrollers

Information contained in this publication regarding device

applications a nd the like is p ro vid ed only f or yo ur c o n ve nience

and may be supers eded by updates. It is y our res po nsibilit y to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,

PICmic ro, PI C START, PRO MATE, PowerSm art , rfPIC, and

SmartShunt are registered trademark s of Microchip

Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Linear Active Thermistor, Migratable

Memory, MXDEV, MXLAB, PS logo, SEEV AL, SmartSensor

and The Embedded Control Solutions Company are

registered trademarks of Microchip Technology Incorporated

in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,

MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

PowerInf o, PowerMate, PowerTool, REAL ICE , rfLAB,

rfPICDEM, Select Mode, Smart Serial, SmartTel, Total

Endurance, UNI/O, WiperLock and ZENA are trademarks of

Microchip Technology Incorporat ed in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrit y of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violat ion of the Digital Millennium Copyright Act. If suc h ac t s

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

T empe, Arizona, Gresham, Oregon and Mountain View , California. The

Company’s quality system processes and procedures are for its PIC®

MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial

EEPROMs, microperipherals, nonvolatile memory and analog

products. In addition, Microchip’s quality system for the design and

manufacture of development systems is ISO 9001:2000 certified.

PIC16F610/616/16HV610/616

High-Performance RISC CPU:

• Only 35 instructions to learn:

- All single-cycle instructions except branches

• Operati ng spe ed:

- DC – 20 MHz oscillator/c lock input

- DC – 200 ns instruction cycle

• Interrupt capability

• 8-level deep hardware stack

• Direct, Indirect and Relative Addressing modes

Special Microcontroller Features:

• Precision Internal Oscillator:

- Factory calibrated to ±1%, typical

- User selectable frequency: 4 MHz or 8 MHz

• Power-Saving Sleep mode

• Volta ge rang e:

- PIC16F610/616: 2.0V to 5.5V

- PIC16HV610/616: 2.0V to user defined

maximum (see note)

• Industri al and Extended Tempe ratu r e range

• Power-on Reset (POR)

• Power-up Ti mer (PWRT) and Oscillator Start-up

Timer (OST)

• Brown-out Reset (BOR)

• Watchdog Timer (WDT) with independent

oscilla tor for reliable operation

• Multiplexed Master Clear with pull-up/input pin

• Programmable code protection

• High Endurance Flash:

- 100,000 writ e Flash endurance

- Flash retention: > 40 years

Low-Power Features:

• Standby Current:

- 50 nA @ 2.0V, typical

• Operati ng Curren t:

-20μA @ 32 kH z, 2.0V, typical

-220μA @ 4 MHz, 2.0V, typical

• Watchdog Timer Current:

-1μA @ 2.0V, typical

Note: Voltage across internal shunt regulator

cannot exc ee d 5V.

Peripheral Feat ures:

• Shunt Voltage Regulator (PIC16HV610/616 only):

- 5 volt regulation

- 4 mA to 50 mA shunt range

• 11 I/O pins and 1 input only

- High current source/sink for direct LED drive

- Interrupt-on-Change pins

- Individually programmable weak pull-ups

• Analog Compar ator module with:

- Two analog comparators

- Programmable on-chip voltage reference

(CVREF) module (% of VDD)

- Fixed Voltage Reference

- Comparator inputs and outputs externally

accessible

-SR Latch

- Built-In Hysteresis (user selectable)

• Timer0: 8-bit timer/counter with 8-bit

progra mmab le pres caler

• Enhanced Timer1:

- 16-bit timer/counter with prescaler

- External Timer1 Ga te (c ou nt enab le)

- Option to use OSC1 and OSC2 in LP mode

as Timer1 oscillator if INTOSC mode

selected

- Timer1 oscillator

• In-Circuit Serial ProgrammingTM (ICSPTM) via two

pins

PIC16F616/16HV616 only:

• A/D Converter:

- 10-bit resolution

- 8 external input channels

- 2 internal reference channels

• Timer2: 8-bit timer/counter with 8-bit period

• Enhanced Capture, Compare, PWM module:

- 16-bit Capture, max. resolution 12.5 ns

- 16-bit Compare, max. resolution 200 ns

- 10-bit PWM with 1, 2 or 4 output channels,

programmable “dead time”, max. frequency

20 kHz

14-Pin Flash-Based, 8-Bit CMOS Microcontrollers

PIC16F610/616/16HV610/616

PIC16F610/16HV610 14-Pin Diagram (PDIP, SOIC, TSSOP)

TABLE 1: PIC16F610/16HV610 14-PIN SUMMARY

Device Program Memory Data Memory I/O 10- bit A/D

(ch) Comparators Timers

8/16-bit Voltage Range

Flash

(words) SRAM (bytes)

PIC16F610 1024 64 11 — 2 1/1 2.0-5.5V

PIC16HV610 1024 64 11 — 2 1/1 2.0-user defined

PIC16F616 2048 128 11 8 2 2/1 2.0-5.5V

PIC16HV616 2048 128 11 8 2 2/1 2.0-user defined

I/O Pin Comparators Timer Interrupts Pull-ups Basic

RA0 13 C1IN+ —IOC YICSPDAT

RA1 12 C12IN0- — IOC Y ICSPCLK

RA2 11 C1OUT T0CKI INT/IOC Y —

RA3(1) 4— —IOCY

(2) MCLR/VPP

RA4 3 — T1G IOC YOSC2/CLKOUT

RA5 2 — T1CKI IOC Y OSC1/CLKIN

RC0 10 C2IN+ — — — —

RC1 9 C12IN1- — — — —

RC2 8C12IN2- — — — —

RC3 7 C12IN3- — — — —

RC4 6C2OUT — — — —

RC5 5 — — — — —

— 1 — — — — VDD

—14 — — — — VSS

Note 1: Input only.

2: Only when pin is configured fo r external MCLR.

VDD

RA5/T1CKI/OSC1/CLKIN

RA4/T1G/OSC2/CLKOUT

RA3/MCLR/VPP

RC5

RC4/C2OUT

RC3/C12IN3-

VSS

RA0/C1IN+/ICSPDAT

RA1/C12IN0-/ICSPCLK

RA2/T0CKI/INT/C1OUT

RC0/C2IN+

RC1/C12IN1-

RC2/C12IN2-

PIC16F610/16HV610

PIC16F610/616/16HV610/616

PIC16F616/16HV616 14-Pin Diagram (PDIP, SOIC, TSSOP)

TABLE 2: PIC16F616/16HV616 14-PIN SUMMARY

I/O Pin Analog Comparators Timer CCP Interrupts Pull-ups Basic

RA0 13 AN0 C1IN+ — — IOC YICSPDAT

RA1 12 AN1/VREF C12IN0- — — IOC Y ICSPCLK

RA2 11 AN2 C1OUT T0CKI —INT/IOC Y —

RA3(1) 4— — — — IOCY

(2) MCLR/VPP

RA4 3AN3 —T1G —IOC YOSC2/CLKOUT

RA5 2 — — T1CKI — IOC Y OSC1/CLKIN

RC0 10 AN4 C2IN+ — — — — —

RC1 9 AN5 C12IN1- — — — — —

RC2 8AN6 C12IN2- —P1D — — —

RC3 7 AN7 C12IN3- — P1C — — —

RC4 6 — C2OUT —P1B — — —

RC5 5 — — — CCP1/P1A — — —

— 1 — — — — — — VDD

—14 — — — — — — VSS

Note 1: Input only.

2: Only when pin is configured fo r external MCLR.

VDD

RA5/T1CKI/OSC1/CLKIN

RA4/AN3/T1G/OSC2/CLKOUT

RA3/MCLR/VPP

RC5/CCP1/P1A

RC4/C2OUT/P1B

RC3/AN7/C12IN3-/P1C

VSS

RA0/AN0/C1IN+/ICSPDAT

RA1/AN1/C12IN0-/VREF/ICSPCLK

RA2/AN2/T0CKI/INT/C1OUT

RC0/AN4/C2IN+

RC1/AN5/C12IN1-

RC2/AN6/C12IN2-/P1D

PIC16F616/16HV616

PIC16F610/616/16HV610/616

PIC16F610/16HV610 16-Pin Diagram (QFN)

TABLE 3: PIC16F610/16HV610 16-PIN SUMMARY

I/O Pin Comparators Timers Interrupts Pull-ups Basic

RA0 12 C1IN+ —IOC YICSPDAT

RA1 11 C12IN0- — IOC Y ICSPCLK

RA2 10 C1OUT T0CKI INT/IOC Y —

RA3(1) 3— —IOCY

(2) MCLR/VPP

RA4 2 — T1G IOC YOSC2/CLKOUT

RA5 1 — T1CKI IOC Y OSC1/CLKIN

RC0 9C2IN+ — — — —

RC1 8 C12IN1- — — — —

RC2 7C12IN2- — — — —

RC3 6 C12IN3- — — — —

RC4 5C2OUT — — — —

RC5 4 — — — — —

—16 — — — — VDD

—13 — — — — VSS

Note 1: Input only.

2: Only when pin is configured fo r external MCLR.

PIC16F610/

PIC16HV610

RA5/T1CKI/OSC1/CLKIN

RA4/T1G/OSC2/CLKOUT

RA3/MCLR/VPP

RC5

VDD

VSS

RA0/C1IN+/ICSPDAT

RA1/C12IN0-/ICSPCLK

RA2/T0CKI/INT/C1OUT

RC0/C2IN1+

RC4/C2OUT

RC3/C12IN3-

RC2/C12IN2-

RC1/C12IN1-

PIC16F610/616/16HV610/616

PIC16F616/16HV616 16-Pin Diagram (QFN)

TABLE 4: PIC16F616/16HV616 16-PIN SUMMARY

I/O Pin Analog Comparators Timers CCP Interrupts Pull-ups Basic

RA0 12 AN0 C1IN+ — — IOC YICSPDAT

RA1 11 AN1/VREF C12IN0- — — IOC Y ICSPCLK

RA2 10 AN2 C1OUT T0CKI —INT/IOC Y —

RA3(1) 3— — — — IOCY

(2) MCLR/VPP

RA4 2AN3 —T1G —IOC YOSC2/CLKOUT

RA5 1 — — T1CKI — IOC Y OSC1/CLKIN

RC0 9AN4 C2IN+ — — — — —

RC1 8 AN5 C12IN1- — — — — —

RC2 7AN6 C12IN2- —P1D — — —

RC3 6 AN7 C12IN3- — P1C — — —

RC4 5 — C2OUT —P1B — — —

RC5 4 — — — CCP1/P1A — — —

—16 — — — — — — VDD

—13 — — — — — — VSS

Note 1: Input only.

2: Only when pin is configured fo r external MCLR.

PIC16F616/

PIC16HV616

RA5/T1CKI/OSC1/CLKIN

RA4/AN3/T1G/OSC2/CLKOUT

RA3/MCLR/VPP

RC5/CCP/P1A

VDD

VSS

RA0/AN0/C1IN+/ICSPDAT

RA1/AN1/C12IN0-/VREF/ICSPCLK

RA2/AN2/T0CKI/INT/C1OUT

RC0/AN4/C2IN1+

RC4/C2OUT/P1B

RC3/AN7/C12IN3-/P1C

RC2/AN6/C12IN2-/P1D

RC1/AN5/C12IN1-

PIC16F610/616/16HV610/616

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 7

2.0 Memory O rganization................................................................................................................................................................. 11

3.0 Oscillator Module ........................................................................................................................................................................ 25

4.0 I/O Ports ....... ....................... ....................... ....................... ....................... .................................................................................. 31

5.0 Timer0 Module ........................................................................................................................................................................... 43

6.0 Timer1 Module with Gate Control............................................................................................................................................... 47

7.0 Timer2 Module ........................................................................................................................................................................... 53

8.0 Comparator Module..................... ......... .. .... .... .. ......... .. .... .... .. ......... .... .. .... .... ....... .... .. .... .... ......................................................... 55

9.0 Analog-to-Digital Converter (AD C) Module ................................................................................................................................ 71

10.0 Enhanc ed Capture/Com pare/PW M (With Auto-Shutdown and Dead Band) Module................................................................. 83

11.0 Voltage Regulator................ .. .... .. .. ..... .. .. .. .. .... .. .. ..... .. .. .. .. .. .... .. ..... .. .. .. .. .. .. .... ..... .. .. .. .. .. .. ........................................................... 105

12.0 Specia l Features of the CPU...................... ................... ............................. ................... ........................................................... 106

13.0 Instruction Set Summary.......................................................................................................................................................... 125

14.0 Development Support............................................................................................................................................................... 135

15.0 Electrical Specifications ............................................................................................................................................................ 139

16.0 DC and AC Characteristics Graphs and Tables..................................... .... .. ......... .... .... .. ......... .... .... ........................................ 161

17.0 Packagin g In fo r mation........... ................... ................... ............................. ................... ............................................................. 163

Appendix A: Data Sheet Revision History..................................... .... ......... .... .... .... ......... .... .... .... ....................................................... 169

Appendix B: Migrating from other PIC® Devices................. ............................. ................... ................... ................... ......................... 169

Index .................................................................................................................................................................................................. 171

The Micro chip Web Site................ .................................. ....................... ....................... ..................................................................... 175

Customer Change Notification Service . .. ............... ...... ............. ...... ............... ...... ............... .... ........................................................... 175

Customer Support.......... ............. ...... .... ............. ...... .... ............. ...... ............. ...... .... ............................................................................ 175

Reader Response.............................................................................................................................................................................. 176

Product Identification System............................................................................................................................................................. 177

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers wit h the best docum entation possible to ensure s uccessful use of y our M icrochip

products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and

enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via

E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We

welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web sit e at:

http://www.microchip.com

You can det ermine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operati onal differences from the data sheet and recommended workarounds, may exist for current

devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revisi on of

silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page)

When contacting a sales office, please sp ecify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Noti fic atio n Syst em

PIC16F610/616/16HV610/616

1.0 DEVICE OVERVIEW

The PIC16F610/616/16HV610/616 is covered by this

data sheet. It is available in 14-pin PDIP, SOIC, TSSO P

and 16-pin QFN packages.

Block Diagrams and pinout descriptions of the devices

are as follows:

• PIC16F610/16HV610 (Figure 1-1, Table 1-1)

• PIC16F616/16HV616 (Figure 1-2, Table 1-2)

FIGURE 1-1: PIC16F610/16HV 610 BLOC K DIAGRAM

Flash

Program

Memory

13 Data Bus 8

Program

Bus

Instruction Reg

Progra m Counter

RAM

File

Registers

Direct Addr 7

RAM Addr 9

Addr MU X

Indirect

Addr

FSR Reg

STATUS Reg

MUX

ALU

W Reg

Instruction

Decode and

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

PORTA

8-Level Stack 64 Bytes

1K X 14

(13-Bit)

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

MCLR VSS

Brown-out

Reset

Timer0

Timer1

RA0

RA1

RA2

RA3

RA4

RA5

2 Analog Comparators

T0CKI

INT

T1CKI

Configuration

Internal

Oscillator

T1G

PORTC

VDD

Block Shunt Regulator

(PIC16HV610 only)

RC0

RC1

RC2

RC3

RC4

RC5

C1IN+

C12IN0-

C12IN1-

C12IN2-

C12IN3-

C1OUT

C2IN+

C2OUT

Comparator Voltage Reference

Fixed Voltage Referenc e

PIC16F610/616/16HV610/616

FIGURE 1-2: PIC16F616/1 6HV616 BLOCK DIAGRAM

Flash

Program

Memory

13 Data Bus 8

Program

Bus

Instruction Reg

Progra m Counter

RAM

File

Registers

Direct Addr 7

RAM Addr 9

Addr MU X

Indirect

Addr

FSR Reg

STATUS Reg

MUX

ALU

W Reg

Instruction

Decode and

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

PORTA

8-Level Stack 128 Bytes

2K X 14

(13-Bit)

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

MCLR VSS

Brown-out

Reset

Timer0

Timer1

RA0

RA1

RA2

RA3

RA4

RA5

2 Analog Comparators

T0CKI

INT

T1CKI

Configuration

Internal

Oscillator

VREF

T1G

PORTC

VDD

Timer2

Block Shunt Regulator

(PIC16HV616 only)

Analog-T o-Digital Converter

RC0

RC1

RC2

RC3

RC4

RC5

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

C1IN+

C12IN0-

C12IN1-

C12IN2-

C12IN3-

C1OUT

C2IN+

C2OUT

ECCP

CCP1/P1A

P1B

P1C

P1D

Comparator Voltage Reference

Fixed Voltage Referenc e

PIC16F610/616/16HV610/616

TABLE 1-1: PIC16F610/16HV610 PINOUT DESCRIPTION

Name Function Input

Type Output

Type Description

RA0/C1IN+/ICSPDAT RA0 TTL CMOS PORTA I/O with prog. pull-up and interrupt-on-change

C1IN+ AN — Comparator C1 non-inverting input

ICSPDAT ST CMOS Se rial Programming Data I/O

RA1/C12IN0-/ICSPCLK RA1 TTL CMOS PORTA I/O with prog. pull-up and interrupt-on-change

C12IN0- AN —Comparat ors C1 and C2 inverting inpu t

ICSPCLK ST — Serial Programming Clock

RA2/T0CKI/INT/C1OUT RA2 ST CMOS PORTA I/O with prog. pull-up and interrupt-on-change

T0CKI ST — Timer0 clock input

INT ST — Ex ter nal Inte rru pt

C1OUT — CMOS Comparator C1 output

RA3/MCLR/VPP RA3 TTL — PORTA input with interrupt-on-change

MCLR ST — Master Clear w/internal pull-up

VPP HV — Programming voltage

RA4/T1G/OSC2/CLKOUT RA4 TTL CMOS PORTA I/O with prog. pull-up and interrupt-on-change

T1G ST — Timer1 gate (count enable)

OSC2 — XTAL Crystal/Resonator

CLKOUT — CMOS FOSC/4 output

RA5/T1CKI/OSC1/CLKIN RA5 TTL CMOS PORTA I/O with prog. pull-up and interrupt-on-change

T1CKI ST — Timer1 clock input

OSC1 XTAL — Crystal/Resonator

CLKIN ST — External clock input/RC oscillator connection

RC0/C2IN+ RC0 TTL CMOS POR TC I/O

C2IN+ AN — Comparator C2 non-inverting input

RC1/C12IN1- RC1 TTL CMOS PORTC I/O

C12IN1- AN —Comparat ors C1 and C2 inverting inpu t

RC2/C12IN2- RC2 TTL CMOS PORTC I/O

C12IN2- AN —Comparat ors C1 and C2 inverting inpu t

RC3/C12IN3- RC3 TTL CMOS PORTC I/O

C12IN3- AN —Comparat ors C1 and C2 inverting inpu t

RC4/C2OUT RC4 TTL CMOS POR TC I/O

C2OUT — CMOS Comparator C2 output

RC5 RC5 TTL CMOS PORTC I/O

VDD VDD Power — Positive supply

VSS VSS Power — Ground reference

Legend: AN = Analog input or output CMOS = CMOS compatible input or output HV = High Voltage

ST = Schmitt Trig ger input with CMOS levels TTL = TTL compatible input XTAL = Crystal

PIC16F610/616/16HV610/616

TABLE 1-2: PIC16F616/16HV616 PINOUT DESCRIPTION

Name Function Input

Type Output

Type Description

RA0/AN0/C1IN+/ICSPDAT RA0 TTL CMOS PORTA I/O with prog. pull-up and interrupt-on-change

AN0 AN — A/D Channel 0 input

C1IN+ AN — Comparator C1 non-inverting input

ICSPDAT ST CMOS Se rial Programming Data I/O

RA1/AN1/C12IN0-/VREF/ICSPCLK RA1 TTL CMOS PORTA I/O with prog. pull-up and interrupt-on-change

AN1 AN — A/D Channel 1 input

C12IN0- AN —Comparat ors C1 and C2 inverting inpu t

VREF AN — External Voltage Reference for A/D

ICSPCLK ST — Serial Programming Clock

RA2/AN2/T0CKI/INT/C1OUT RA2 ST CMOS PORTA I/O with prog. pull-up and interrupt-on-change

AN2 AN — A/D Channel 2 input

T0CKI ST — Timer0 clock input

INT ST — Ex ter nal Inte rru pt

C1OUT — CMOS Comparator C1 output

RA3/MCLR/VPP RA3 TTL — PORTA input with interrupt-on-change

MCLR ST — Master Clear w/internal pull-up

VPP HV — Programming voltage

RA4/AN3/T1G/OSC2/CLKOUT RA4 TTL CMOS PORTA I/O with prog. pull-up and interrupt-on-change

AN3 AN — A/D Channel 3 input

T1G ST — Timer1 gate (count enable)

OSC2 — XTAL Crystal/Resonator

CLKOUT — CMOS FOSC/4 output

RA5/T1CKI/OSC1/CLKIN RA5 TTL CMOS PORTA I/O with prog. pull-up and interrupt-on-change

T1CKI ST — Timer1 clock input

OSC1 XTAL — Crystal/Resonator

CLKIN ST — External clock input/RC oscillator connection

RC0/AN4/C2IN+ RC0 TTL CMOS PORTC I/O

AN4 AN — A/D Channel 4 input

C2IN+ AN — Comparator C2 non-inverting input

RC1/AN5/C12IN1- RC1 TTL CMOS PORTC I/O

AN5 AN — A/D Channel 5 input

C12IN1- AN —Comparat ors C1 and C2 inverting inpu t

RC2/AN6/C12IN2-/P1D RC2 TTL CMOS PORTC I/O

AN6 AN — A/D Channel 6 input

C12IN2- AN —Comparat ors C1 and C2 inverting inpu t

P1D — CMOS PWM output

RC3/AN7/C12IN3-/P1C RC3 TTL CMOS PORTC I/O

AN7 AN — A/D Channel 7 input

C12IN3- AN —Comparat ors C1 and C2 inverting inpu t

P1C — CMOS PWM output

RC4/C2OUT/P1B RC4 TTL CMOS PORTC I/O

C2OUT — CMOS Comparator C2 output

P1B — CMOS PWM output

RC5/CCP1/P1A RC5 TTL CMOS PORTC I/O

CCP1 ST CMOS Capture input/Compare output

P1A — CMOS PWM output

VDD VDD Power — Positive supply

VSS VSS Power — Ground reference

Legend: AN = Analog input or output CMOS = CMOS compatible input or output HV = High Voltage

ST = Schmitt Trig ger input with CMOS levels TTL = TTL compatible input XTAL = Crystal

PIC16F610/616/16HV610/616

2.0 MEMORY ORGANIZATION

2.1 Program Memory Organization

The PIC16F610/616/16HV610/616 has a 13-bit pro-

gram counter capable of addressing an 8k x 14 pro-

gram memory space. Only the first 1K x 14

(0000h-3FF) for the PIC16F610/16HV610 and the first

2K x 14 (0000h-07F Fh) for the PIC16F61 6/16HV616 is

physically implemented. Accessing a location above

these boundaries will cause a wraparound within the

first 1K x 14 sp ac e (PIC 16F610 /16HV610) and 2K x 1 4

space (PIC16F616/16HV616). The Reset vector is at

0000h and the interrupt vector is at 0004h (see

Figure 2-1).

FIGURE 2-1: PROGRAM MEMORY MAP

AND STACK FOR THE

PIC16F610/16HV610

FIGURE 2-2: PROGRAM MEMORY MAP

AND STACK FOR THE

PIC16F616/16HV616

PC<12:0>

0000h

0004h

0005h

03FFh

0400h

1FFFh

Stack Level 1

Stack Level 8

Reset V ector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN

RETFIE, RETLW

Stack Level 2

PC<12:0>

0000h

0004h

0005h

07FFh

0800h

1FFFh

Stack Level 1

Stack Level 8

Reset V ector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN

RETFIE, RETLW

Stack Level 2

PIC16F610/616/16HV610/616

2.2 Data Memory Organization

The data memory (see Figure 2-4) is partitioned into

two banks, which contain the General Purpose

Registers (GPR) and the Special Function Registers

(SFR). The Special Function Registers are located in

the first 32 locations of each bank.

PIC16F610/16HV610 Register locations 40h-7Fh in

Bank 0 are General Purpose Registers, implemented

as static RAM. PIC16F616/16HV616 Register

locations 20h-7Fh in Bank 0 and A0h-BFh in Bank 1

are General Purpose Registers, implemented as static

RAM. Register locations F0h-FFh in Bank 1 point to

addresses 70h-7Fh in Bank 0. All other RAM is

unimpl emented and returns ‘0’ when read. Th e RP0 b it

of the STATU S register is the bank select bit .

RP0

0→Bank 0 is selected

1→Bank 1 is selected

2.2. 1 GENERAL PU RPOSE REGISTER

FILE

The register file is organized as 64 x 8 in the

PIC16F610/16HV610 and 128 x 8 in the

PIC16F616/16HV616. Each register is accessed,

either d irectly or i ndirec tly, through th e File Selec t Reg-

ister (FSR) (see Section 2.4 “Indirect Addressing,

INDF and FSR Registers”).

2.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by

the CPU and peripheral functions for controlling the

desired operation of the device (see Table 2-1). These

registers are static RAM.

The special registers can be classified into two sets:

core and peripheral. The Special Function Registers

associated with the “core” are described in this section.

Those related to the operation of the peripheral features

are described in the section of th at peripheral feature.

Note: The IRP and RP1 bits of the STATUS

maintained as ‘0’s.

PIC16F610/616/16HV610/616

FIGURE 2-3: DATA MEMORY MAP OF

THE PIC16F 61 0/16 HV6 10 FIGURE 2-4: DATA MEMORY MAP OF

THE PIC16F 61 6/16 HV6 16

Indirect Addr.(1)

TMR0

PCL

STATUS

FSR

PORTA

PCLATH

INTCON

PIR1

TMR1L

TMR1H

T1CON

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

7Fh

Bank 0

Unimplemented data memory locations, read as ‘0’.

Note 1: Not a physical register .

CM1CON0 SRCON0

General

Purpose

Registers

64 Bytes

SRCON1

File

Address File

Address

WPUA

IOCA

Indirect Addr.(1)

OPTION_REG

PCL

STATUS

FSR

TRISA

PCLATH

INTCON

PIE1

PCON

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

A0h

FFh

Bank 1

ANSEL

TRISC

PORTC

Accesses 70h-7Fh F0h

VRCON

CM2CON0

OSCTUNE

CM2CON1

3Fh

40h

Indirect Addr.(1)

TMR0

PCL

STATUS

FSR

PORTA

PCLATH

INTCON

PIR1

TMR1L

TMR1H

T1CON

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

7Fh

Bank 0

Unimplemented data memory locations, read as ‘0’.

Note 1: Not a physical register .

CM1CON0 SRCON0

General

Purpose

Registers

96 Bytes

SRCON1

File

Address File

Address

WPUA

IOCA

Indirect Addr.(1)

OPTION_REG

PCL

STATUS

FSR

TRISA

PCLATH

INTCON

PIE1

PCON

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

A0h

FFh

Bank 1

ADRESH

ADCON0

ADRESL

ADCON1

ANSEL

TRISC

PORTC

BFh

General

Purpose

Registers

32 Bytes

Accesses 70h-7Fh F0h

TMR2

T2CON

CCPR1L

CCPR1H

CCP1CON

PWM1CON

ECCPAS

VRCON

CM2CON0

OSCTUNE

PR2

70h

6Fh

CM2CON1

C0h

PIC16F610/616/16HV610/616
DS41288C-page 14 Preliminary © 2007 Microchip Technology Inc.
TABLE 2-1: PIC16F610/616/16HV610/616 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0 
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2  Bit 1 Bit 0 Value on 
POR, BOR Page
Bank 0
00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 22, 113
01h TMR0 Timer0 Module’s Register xxxx xxxx 43, 113
02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 22, 113
03h STATUS IRP(1) RP1(1) RP0 TO PD ZDCC0001 1xxx 16, 113
04h FSR Indirect Data Memory Address Pointer xxxx xxxx 22, 113
05h PORTA —— RA5 RA4 RA3 RA2 RA1 RA0 --x0 x000 31, 113
06h —Unimplemented — —
07h PORTC —— RC5 RC4 RC3 RC2 RC1 RC0 --xx 00xx 40, 113
08h —Unimplemented — —
09h —Unimplemented — —
0Ah PCLATH — — — Write Buffer for upper 5 bits of Program Counter ---0 0000 22, 113
0Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 18, 113
0Ch PIR1 —ADIF
(2) CCP1IF(2) C2IF C1IF —TMR2IF
(2) TMR1IF -000 0-00 20, 113
0Dh —Unimplemented — —
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 47, 113
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 47, 113
10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 50, 113
11h TMR2(2) Timer2 Module Register 0000 0000 53, 113
12h T2CON(2) — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 54, 113
13h CCPR1L(2) Capture/Co mpare /P W M Register 1 Low Byte XXXX XXXX 84, 113
14h CCPR1H(2) Captur e/C o mpare /P WM R egist er 1 High  Byte XXXX XXXX 84, 113
15h CCP1CON(2) P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 83, 113
16h PWM1CON(2) PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 83, 113
17h ECCPAS(2) ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 100, 113
18h —Unimplemented — —
19h VRCON C1VREN C2VREN VRR FVREN VR3 VR2 VR1 VR0 0000 0000 70, 113
1Ah CM1CON0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 0000 -000 60, 113
1Bh CM2CON0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 0000 -000 61, 113
1Ch CM2CON1 MC1OUT MC2OUT — T1ACS C1HYS C2HYS T1GSS C2SYNC 00-0 0010 63, 113
1Dh —Unimplemented — —
1Eh ADRESH(2) Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result  xxxx xxxx 78, 113
1Fh ADCON0(2) ADFM VCFG CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 76, 113
Legend: – = Unimpl em ent ed locat io ns rea d as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: IRP and RP1 bits are reserved, always maintain these bits clear.
2: PIC16F6 16/16HV6 16 onl y.

© 2007 Microchip Technology Inc. Preliminary DS41288C-page 15
PIC16F610/616/16HV610/616
TABLE 2-2: PIC16F610/616/16HV610/616 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2  Bit 1 Bit 0 Value  on 
POR, BOR Page
Bank 1
80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 22, 113
81h OPTION_REG RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 17, 113
82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 22, 113
83h STATUS IRP(1) RP1(1) RP0 TO PD ZDCC0001 1xxx 16, 113
84h FSR Indi rect Data Me mory Address Pointer xxxx xxxx 22, 113
85h TRISA —— TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 31, 113
86h —Unimplemented — —
87h TRISC —— TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 40, 113
88h —Unimplemented — —
89h —Unimplemented — —
8Ah PCLATH — — — Write Buffer for upper 5 bits of Program Counter ---0 0000 22, 113
8Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 18, 113
8Ch PIE1 —ADIE
(3) CCP1IE(3) C2IE C1IE —TMR2IE
(3) TMR1IE -000 0-00 19, 113
8Dh —Unimplemented — —
8Eh PCON — — — — — —PORBOR ---- --qq 21, 113
8Fh —Unimplemented — —
90h OSCTUNE — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 29, 113
91h ANSEL ANS7 ANS6 ANS5 ANS4 ANS3(3) ANS2(3) ANS1 ANS0 1111 1111 32, 114
92h PR2(3) Timer2 Module Period Register 1111 1111 53, 114
93h —Unimplemented — —
94h —Unimplemented — —
95h WPUA —— WPUA5 WPUA4 — WPUA2 WPUA1 WPUA0 --11 -111 33, 114
96h IOCA —— IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 33, 114
97h —Unimplemented — —
98h —Unimplemented — —
99h SRCON0 SR1 SR0 C1SEN C2REN PULSS PULSR — SRCLKEN 0000 00-0 67, 114
9Ah SRCON1 SRCS1 SRCS0 — — — — — — 00-- ---- 67, 114
9Bh —Unimplemented — —
9Ch —Unimplemented — —
9Dh —Unimplemented — —
9Eh ADRESL(3) Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result xxxx xxxx 78, 114
9Fh ADCON1(3) — ADCS2 ADCS1 ADCS0 ————-000 ---- 77, 114
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: IRP and RP1 bits are reserved, always maintain these bits clear.
2: RA3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register.
3: PIC16F616/16HV616 only.

PIC16F610/616/16HV610/616

2.2.2.1 STATUS Register

The S TATUS regi ste r, sho wn i n R e gis ter 2-1, contains:

• the arithm etic status of the ALU

• the Reset status

• the bank select bits for data memory (RAM)

The STATUS register can be the destination for any

instruction, like any other register. If the STATUS

the Z, DC or C bits, then the write to these three bits is

disabl ed. These bit s are set or clea red according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

For exam ple, CLRF STATUS, will clea r the upper three

bits and set the Z bit. This leaves the STATUS register

as ‘000u u1uu’ (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

STATUS register, because these instructions do not

affect any Status bits. For other instructions not affect-

ing any Status bits, see the Section 13.0 “Instruction

Set Summary”.

Note 1: Bits IRP and RP1 of the STATUS register

are not used by the

PIC16F610/616/16HV610/616 and

should be maintained as clear. Use of

these b its is n ot reco mmen ded, s ince this

may affect upward compatibility with

future products.

2: The C and DC bits operate as a Borrow

and Digit Borrow out bit, respectively, in

subtraction. See the SUBLW and SUBWF

instructions for examples.

Reserved Reserved R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD ZDCC

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IRP: T his bit is reserved and should be maintained as ‘0’

bit 6 RP1: This bit is reserved and should be maintained as ‘0’

bit 5 RP0: Register Bank Select bit (used for direct addressing)

1 = Bank 1 (80h – FFh)

0 = Bank 0 (00h – 7Fh)

bit 4 TO: Time-out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction

0 = A WDT time-out occurred

bit 3 PD: Power-down bit

1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions), For Borrow , the polarity is reversed.

1 = A carry-out from the 4th low-order bit of the result occurred

0 = No carry-out from the 4th low-order bit of the result

bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)

1 = A carry-out from the Most Significant bit of the result occurred

0 = No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow , t he polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand.

For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.

PIC16F610/616/16HV610/616

2.2.2.2 OPTION Register

The OPTION register is a readable and writable regis-

ter, which contains various control bits to configure:

• Timer0/WDT prescaler

• External R A2/INT int errupt

•Timer0

• Weak pull-ups on PORTA

Note: To achieve a 1:1 prescaler assignment for

Timer0, assign the prescaler to the WDT

by setting PSA bit to ‘1’ of the OPTION

Programmable Prescaler”.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 RAPU: PORTA Pull-up Enable bit

1 = PORTA pu ll-ups are disabled

0 = PORTA pull-ups are enabled by individual PORT latch values

bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RA2/INT pin

0 = Interrupt on falling edge of RA2/INT pin

bit 5 T0CS: Timer0 Clock Sou rce Select bit

1 = Transit ion on RA2/T0CKI pin

0 = Internal instruction cycle clock (FOSC/4)

bit 4 T0SE: Timer0 Source Edge Select bit

1 = Increment on high-to-low transition on RA2/T0CKI pin

0 = Increment on low-to-high transition on RA2/T0CKI pin

bit 3 PSA: Prescaler Assignme nt bit

1 = Prescaler is assigned to the WDT

0 = Prescaler is assigned to the Timer0 module

bit 2-0 PS<2:0>: Prescaler Rate Select bits

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

BIT VALUE TI MER0 RATE WD T RATE

PIC16F610/616/16HV610/616

2.2.2.3 INTCON Register

The INTCON register is a readable and writable

for TMR0 register overflow, PORTA change and

external RA2/INT pin interrupts.

Note: Interru pt flag bi ts are set when an interrupt

conditi on occ urs, regar dless o f the s tate of

its corresponding enable bit or the global

enable bit, GIE of the INTCON register.

User software should ensure the

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

GIE PEIE T0IE INTE RAIE T0IF INTF RAIF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all unmasked interrupts

0 = Disables all interrupts

bit 6 PEIE: Peripheral Interrupt Enable bit

1 = Enables all unmasked peripheral interrupts

0 = Disables all peripheral interrupts

bit 5 T0IE: Timer0 Overflow Interrupt E nab le bit

1 = Enables the Timer0 interrupt

0 = Disables the Timer0 interrupt

bit 4 INTE: RA2/INT External Interrupt Enable bit

1 = Enables the RA2/INT external interrupt

0 = Disables the RA2/INT external interrupt

bit 3 RAIE: PORTA Change Interrupt Enable bit(1)

1 = Enables the PORTA change interrupt

0 = Disables the PORTA change interrupt

bit 2 T0IF: Timer0 Overflow Interrupt Flag bit(2)

1 = Timer0 register has overflowed (must be cleared in software)

0 = Timer0 register did not overflow

bit 1 INTF: RA2/INT External Interrupt Flag bit

1 = The RA2/INT external interrupt occurred (must be cleared in software)

0 = The RA2/INT external interrupt did not occur

bit 0 RAIF: PORTA Change Interrupt Flag bit

1 = When at least one of the PORTA <5:0> pins changed state (must be cleared in software)

0 = None of the PORTA <5:0> pins have changed state

Note 1: IOCA register must also be enabled.

2: T0IF bit is set when TMR0 rolls over. TMR0 is unchanged on Reset and should be initialized before

clearing T0IF bit.

PIC16F610/616/16HV610/616

2.2.2.4 PIE1 Regist er

The PIE1 register contains the peripheral interrupt

enable bits, as shown in Register 2-4.

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0

—ADIE

(1) CCP1IE(1) C2IE C1IE —TMR2IE

(1) TMR1IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Re ad as ‘0’

bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit(1)

1 = Enables the ADC interrupt

0 = Disables the ADC interrupt

bit 5 CCP1IE: CCP1 Interrupt Enable bit(1)

1 = Enables the CCP1 interrupt

0 = Disables the CCP1 interru pt

bit 4 C2IE: Comparator C2 Interrupt Enable bit

1 = Enables the Comparator C2 interrupt

0 = Disables the Comparator C2 interrupt

bit 3 C1IE: Comparator C1 Interrupt Enable bit

1 = Enables the Comparator C1 interrupt

0 = Disables the Comparator C1 interrupt

bit 2 Unimplemented: Re ad as ‘0’

bit 1 TMR2IE: Timer2 to PR2 Match Interrupt Enable bit(1)

1 = Enables the Timer2 to PR2 match interrupt

0 = Disables the Timer2 to PR2 match interrupt

bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit

1 = Enables the Timer1 overflow interrupt

0 = Disables the Timer1 overflow interrupt

Note 1: PIC16F616/16HV616 only. PIC16F610/16HV610 unimplemented, read as ‘0’.

PIC16F610/616/16HV610/616

2.2.2.5 PIR1 Register

The PIR1 register contains the peripheral interrupt flag

bits, as shown in Register 2-5.

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE of the INTCON register . User

software should ensure the appropriate

interru pt flag bits are clear prior t o enabling

an interrupt.

U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0

—ADIF

(1) CCP1IF(1) C2IF C1IF —TMR2IF

(1) TMR1IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Re ad as ‘0’

bit 6 ADIF: A/D Interrupt Flag bit(1)

1 = A/D conversion complete

0 = A/D conversion has not completed or has not been started

bit 5 CCP1IF: CCP1 Interrupt Flag bit(1)

Capture mode:

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register captu re occurred

Compare mode:

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM mode:

Unused in this mode

bit 4 C2IF: Comparator C2 Interrupt Flag bit

1 = Comparator C2 output has changed (must be cleared in software)

0 = Comparator C2 output has not changed

bit 3 C1IF: Comparator C1 Interrupt Flag bit

1 = Comparator C1 output has changed (must be cleared in software)

0 = Comparator C1 output has not changed

bit 2 Unimplemented: Re ad as ‘0’

bit 1 TMR2IF: Timer2 to PR2 Match Interrupt Flag bit(1)

1 = Timer2 to PR2 match occurred (must be cleared in software)

0 = Timer2 to PR2 match has not occurred

bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit

1 = Timer1 register overflowed (must be cleared in software)

0 = Timer1 has not overflowed

Note 1: PIC16F616/16HV616 only. PIC16F610/16HV610 unimplemented, read as ‘0’.

PIC16F610/616/16HV610/616

2.2.2.6 PCON Register

The Power Control (PCON) register (see Table 12-2)

cont ains flag bit s to differentiate between a:

• Power-on Reset (POR)

• Brown-out Reset (BOR)

• Watchdog Timer Reset (WDT)

• External MCLR Reset

The PCON register also controls the software en able of

the BOR.

The PCON register bits are shown in Register 2-6.

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0(1)

— — — — — —PORBOR

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-2 Unimplemented: Read as ‘0’

bit 1 POR: Power-on Reset Status bit

1 = No Power-on Reset occurred

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0 BOR: Brown-out Reset Status bit

1 = No Brown-out Reset occurred

0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

Note 1: Reads as ‘0’ if Brown-out Reset is disabled.

PIC16F610/616/16HV610/616

2.3 PCL and PCLATH

The Program Counter (PC) is 13 bi ts wide . The low byte

comes from the PCL register, which is a readable and

writable register . The high byte (PC<12:8>) is not directly

readable or writable and comes from PCLATH. On any

Reset, the PC is cleared. Figure 2-5 shows the two

situations for the loading of the PC. The upper example

in Figure 2-5 shows how the PC is loaded on a write to

PCL (PCLATH<4:0> → PCH). The lower example in

Figure 2-5 show s how the PC is loaded during a CALL or

GOTO instru ctio n (P CLATH<4:3> → PCH).

FIGURE 2-5: LOADING OF PC IN

DIFFERENT SITUATIONS

2.3.1 MODIFYING PCL

Executing any instruction with the PCL register as the

destination simultaneously causes the Program

Counter PC<12:8> bits (PCH) to be replaced by the

content s of the PCLATH register. This al lows the e ntire

contents of the program counter to be changed by

writing the desired upp er 5 bits to the PCL A TH re gister.

When the lower 8 bits are written to the PCL register , all

13 bits of the program counter will change to the values

contained in the PCLATH register and those being

written to the PCL register.

A computed GOTO i s ac co mp li shed by ad ding an offset

to the program counter (ADDWF PCL). Care should be

exercised when jumping into a look-up table or

program branch table (computed GOTO) by modifying

the PCL register. Assuming that PCLATH is set to the

table start address, if the table length is greater than

255 instructions or if the lower 8 bits of the memory

address rolls over from 0xFF to 0x00 in the middle of

the table, then PCLATH must be incremented for each

address rollover that occurs between the table

beginning and the target location within the table.

For more information refer to Application Note AN556,

“Implementing a Table Read” (DS00556).

2.3.2 STACK

The PIC16F610/616/16HV610/616 Family has an

8-level x 13-bit wide hardware stack (see Figure 2-1).

The stack space is not part of either program or data

spac e and the S t ack Pointe r is not readable or writ able.

The PC is PUSHed onto the stack when a CALL

instruction is executed or an interrupt causes a branch.

The st ack is POP ed in the event o f a RETURN, RETLW

or a RETFIE instruction execution. PCLATH is not

affected by a PUSH or POP operation.

The stack operates as a circular buf fer . This means tha t

after the st ack has be en PUSHed eigh t times, the ninth

push ove rwrites the val ue that wa s stored from the first

push. The ten th pu sh overw rit es the second push (and

so on).

2.4 Indirect Addressing, INDF and

FSR Registers

The INDF re gister is not a physical register . Ad dressing

the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF

actually accesses data pointed to by the File Select

produce 00h. Writing to the INDF register indirectly

results in a no operation (although Status bits may be

affected). An effective 9-bit address is obtained by

concatenating the 8-bit FSR and the IRP bit of the

STATUS register, as shown in Figure 2-7.

A simpl e prog ram to c lear RAM location 40h-4 Fh using

indirect addressing is shown in Example 2-1.

EXAMPLE 2-1: INDIRECT ADDRESSING

12 8 7 0

5PCLATH<4:0>

PCLATH

Instruction wit

ALU Result

GOTO, CALL

OPCODE <10:0

12 11 10 0

PCLATH<4:3>

PCH PCL

PCLATH

PCH PCL

PCL a

Destinatio

Note 1: There are no Status bits to indicate stack

overflow or stack underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of the

CALL, RETURN, RETLW and RETFIE

instructions or the vectoring to an

interrupt address.

MOVLW 0x40 ;initialize pointer

MOVWF FSR ;to RAM

NEXT CLRF INDF ;clear INDF register

INCF FSR, F ;inc pointer

BTFSS FSR,4 ;all done?

GOTO NEXT ;no clear next

CONTINUE ;yes continue

PIC16F610/616/16HV610/616

FIGURE 2-6: DIRECT/INDIRECT ADDRESSING PIC16F610/16HV610

FIGURE 2-7: DIRECT/INDIRECT ADDRESSING PIC16F616/16HV616

Data

Memory

Indirect AddressingDirect Addressing

Bank Select Location Select

RP1(1) RP0 6 0

From Opcode IRP(1) File Select Register

Bank Select Location Select

00 01 10 11 180h

1FFh

00h

7Fh Bank 0 Bank 1 Bank 2 Bank 3

NOT USED(2)

For memory map detail, see Figure 2 -3.

70h

40h

Unimplemented data memory locations, read as ‘0’.

Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear .

2: Accesses in Bank 2 and Bank 3 are mirrored back into Bank 0 and Bank 1, respectively.

20h

Data

Memory

Indirect AddressingDirect Addressing

Bank Select Location Select

RP1(1) RP0 6 0

From Opcode IRP(1) File Select Register

Bank Select Location Select

00 01 10 11 180h

1FFh

00h

7Fh

Bank 0 Bank 1 Bank 2 Bank 3

NOT USED(2)

For memory map detail, see Figure 2 -4.

70h

40h

Unimplemented data memory locations, read as ‘0’.

Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear .

2: Accesses in Bank 2 and Bank 3 are mirrored back into Bank 0 and Bank 1, respectively.

PIC16F610/616/16HV610/616

NOTES:

PIC16F610/616/16HV610/616

3.0 OSCILLATOR MODULE

3.1 Overview

The Oscillator module has a wide variety of clock

sources and selection features that allow it to be used

in a wide range of applic ations while maximizing perfor-

mance and minimizing power consumption. Figure 3-1

illustrates a block diagram of the Oscillator module.

Clock sources can be configured from external

oscilla tors, quartz crystal resonators , ceramic resonators

and Resistor-Capacitor (RC) circuits. In addition, the

system clock source can be configured with a choice of

two selectable speeds: internal or external system clock

source.

The Os cillator mod ule can be c onfigured in one of eig ht

clock modes.

1. EC – External clock with I/O on O SC2/CLKOUT.

2. LP – 32 kHz Low-Power Crystal mode.

3. XT – Medium Gain Crystal or Ceramic Resonator

Oscillator mode.

4. HS – High Gain Crystal or Ceramic Resonator

mode.

5. RC – External Resistor-Capacitor (RC) with

FOSC/4 output on OSC2/CLKOUT.

6. RCIO – External Resistor-Capacitor (RC) with

I/O on OSC2/CLKOUT.

7. INTOSC – Internal oscillator with FOSC/4 output

on OSC2 and I/O on OSC1/CLKIN.

8. INTOSCIO – Internal oscillator with I/O on

OSC1/CLKIN and OSC2/CLKOUT.

Clock Source modes are configured by the FOSC<2:0>

bits in the Configuration Word register (CONFIG). The

Internal Oscillator module provides a selectable system

clock mode of either 4 MHz (Postscaler) or 8 MHz

(INTOSC).

FIGURE 3-1: PIC® MCU CLOCK SOURCE BLOCK DIAGRAM

(CPU and Peripherals)

OSC1

OSC2

Sleep

External Oscillator

LP, XT, HS, RC, RCIO, EC

System Clock

MUX

FOSC<2:0>

(Configuration Word Register)

Internal Oscillator

INTOSC

8 MHz

Postscaler

4 MHz

INTOSC

IOSCFS

PIC16F610/616/16HV610/616

3.2 Clock Source Modes

Clock Source modes can be classified as external or

internal.

• External Clock mod es rely on e xternal circui try fo r

the clock source. Examples are: Oscillator mod-

ules (EC mode), quartz crystal resonators or

ceramic resonators (LP, XT and HS modes) and

Resistor-Capacitor (R C) mode circuits.

• Internal clock sources are contained internally

within the Oscillator module. The Oscillator

module has two selectable clock frequencies:

4 MHz and 8 MHz

The syste m cl oc k ca n be selected between ex tern al or

internal clock sources via the FOSC<2:0> bits of the

Configuration Word register.

3.3 External Clock Modes

3.3.1 EC MODE

The External Clock (EC) mode allows an externally

generated logic level as the system clock source. When

operating in this mode, an external clock source is

connected to the OSC1 input and the OSC2 is available

for general purpose I/O. Figure 3-2 shows the pin

connections for EC mode.

The Oscillator Start-up Timer (OST) is disabled when

EC mode is selected. Therefore, there is no delay in

operation after a Power-on Reset (POR) or wake-up

from Sleep. Because the PIC® MCU design is fully

static, stopping the external clock input will have the

effect of halting the device while leaving all data intact.

Upon restarting the external clock, the device will

resume operation as if no time had elapsed.

FIGURE 3-2: EXTERNAL CLOCK (EC)

MODE OPERATION

3.3.2 OSCILLATOR START-UP TIMER

(OST)

If the Oscillator module is configured for LP, XT or HS

modes, the Oscillator Start-up Timer (OST) counts

1024 oscillations from OSC1. This occurs following a

Power-on Reset (POR) and when the Power-up Timer

(PWRT) has expired (if configured), or a wake-up from

Sleep. During this time, the program counter does not

increment and program execution is suspended. The

OST ensures that the oscillator circuit, using a quartz

cryst al res onator o r ce ramic res onator, has st arted an d

is providing a stable system clock to the Oscillator

module. When switching between clock sources, a

delay is required to allow the new clock to stabilize.

These oscillator delays are shown in Table 3-1.

TABLE 3-1: OSCILLATOR DELAY EXAMPLES

OSC1/CLKIN

OSC2/CLKOUT(1)

I/O

Clock from

Ext. System PIC® MCU

Note 1: Alt ernat e pin functions are listed in the

Section 1.0 “Device Overview”.

Switch From Switch To Frequency Oscillator Delay

Sleep/POR INTOSC 4 MHz to 8 MHz Oscillator Warm-Up Delay (TWARM)

Sleep/POR EC, RC DC – 20 MHz 2 Instruction Cycles

Sleep/POR LP, XT, HS 32 kHz to 20 MHz 1024 Clock Cycles (OST)

PIC16F610/616/16HV610/616

3.3.3 LP, XT, HS MODES

The LP, XT and HS modes support the use of quartz

crystal resonators or ceramic resonators connected to

OSC1 a nd OSC2 (Figur e 3-3). The mod e selects a low ,

medium or high gain setting of the internal inverter-

amplifi er to support vari ous resonator typ es and spee d.

LP Oscillator mode selects the lowest gain setting of

the internal inverter-amplifier. LP mode current

consum ption is the least of the three modes. This mode

is designed to drive only 32.768 kHz tuning-fork type

crystals (watch crystals).

XT Oscillator mode selects the intermediate gain

setting of the internal inverter-amplifier. XT mode

current c onsumption is the medium of the three mo des.

This mode is best suited to drive resonators with a

medium drive level specification.

HS Oscillator mode selects the highest gain setting of

the internal inverter-amplifier. HS mode current

consumption is the highest of the three modes. This

mode is best suited for resonators that require a high

drive setting.

Figure 3-3 and Figure 3-4 show typical circuits for

quartz crystal and ceramic resonators, respectively.

FIGURE 3-3: QUARTZ CRYSTAL

OPERATION (LP, XT OR

HS MODE)

FIGURE 3-4: CERAMIC RESONATOR

OPERATION

(XT OR HS MODE)

Note 1: A series resistor (RS) may be required for

quartz crystals with low drive level.

2: The value of RF varies with the Oscillator mode

selected (typically between 2 MΩ to 10 MΩ).

Quartz

RS(1)

OSC1/CLKIN

RF(2) Sleep

To Internal

Logic

PIC® MCU

Crystal

OSC2/CLKOUT

Note 1: Quartz crystal characteristics vary according

to type, package and manufacturer. The

user should consult the manufacturer data

sheet s for sp ecifi catio ns an d reco mmen ded

application.

2: Always veri fy os ci lla tor performance over

the VDD and temperature range that is

expected for the application.

3: For oscillator de sign assistance, refer ence

the following Microchip Applications Notes:

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC® and PIC®

Devices” (DS00826)

• AN849, “Basic PIC® Oscillator Design”

(DS00849)

• AN943, “Practical PIC® Oscillator

Analysis and Design” (DS00943)

• AN949, “Making Your Oscillator Work”

(DS00949)

Note 1: A series resistor (RS) may be required for

ceramic resonators with low drive level.

2: The value of RF varies with the Oscillator mode

selected (typically between 2 MΩ to 10 M Ω).

3: An additional parallel feedback resistor (RP)

may be required for proper ceramic resonator

operation.

C2 Ceramic RS(1)

OSC1/CLKIN

RF(2) Sleep

To Internal

Logic

PIC® MCU

RP(3)

Resonator OSC2/CLKOUT

PIC16F610/616/16HV610/616

3.3.4 EXT ERNAL RC MODES

The external Resistor-Capacitor (RC) modes support

the use of an external RC circuit. This allows the

designer maximum flexibility in frequency choice while

keeping costs to a minimum when clock accuracy is not

required. There are two modes: RC and RCIO.

In RC mode, the RC circuit connects to OSC1. OSC2/

CLKOUT outputs the RC oscillator frequency divided

by 4. This signal may be used to provide a clock for

external circuitry, synchronization, calibration, test or

other application requirements. Figure 3-5 shows the

external RC mode connections.

FIGURE 3-5: EXTERNAL RC MODES

In RCIO mode, the RC circuit is connected to OSC1.

OSC2 becomes an additional general purpose I/O pin.

The RC oscillator frequency is a function of the supply

voltage, the resis tor (REXT) and cap acito r (CEXT) values

and the operating temperature. Other factors affecting

the oscillator frequency are:

• threshold voltage variation

• component tolerances

• pack aging var iations in capacitanc e

The user also needs to take into account variation due

to tolerance of external RC components used.

3.4 Internal Clock Modes

The Oscillator module provides a selectable system

clock source of either 4 MHz or 8 MHz. The selectable

frequency is configured through the IOSCFS bit of the

Configuration Word.

The frequency of the internal oscillator can be can be

user-adjusted via software using the OSCTUNE

3.4.1 INTOSC AND INTOSCIO MODES

The INTOSC and INTOSCIO modes configure the

internal oscillators as the system clock source when

the devi ce is pr ogrammed using the o scillato r selectio n

or the FOSC<2:0> bits in the Configuration Word

Features of the CPU” for more information.

In INTOSC mode , OSC1/CLKIN i s availab le for genera l

purpose I/O. OSC2/CLKOUT outputs the selected

internal oscillator fre quency divide d by 4. The CLKO UT

signal may be used to provide a clock for external

circuitry, synchronization, calibration, test or other

application requirements.

In INTOSCIO mode, OSC1/CLKIN and OSC2/CLKOUT

are available for general purpose I/O.

OSC2/CLKOUT(1)

CEXT

REXT

PIC® MCU

OSC1/CLKIN

FOSC/4 o r

Internal

Clock

VDD

VSS

Recommended values: 10 kΩ ≤ REXT ≤ 100 kΩ, <3V

3 kΩ ≤ REXT ≤ 100 kΩ, 3-5V

CEXT > 20 pF, 2-5V

Note 1: Alternate pin functions are listed in

Section 1.0 “Device Overview”.

2: Output depen ds upon RC or RC I O Clock

mode.

I/O(2)

PIC16F610/616/16HV610/616

3.4.1.1 OSCTUNE Register

The oscillator is factory calibrated but can be adjusted

in software by writing to the OSCTUNE register

(Register 3-1).

The default value of the OSCTUNE register is ‘0’. The

value is a 5-bit two’s complement number.

When the OSCTUNE register is modified, the frequenc y

will begin shifting to the new frequency. Code execution

continues during this shift. There is no indicatio n that the

shift has occurred.

TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — TUN4 TUN3 TUN2 TUN1 TUN0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 TUN<4:0>: Frequency Tuning bits

01111 = Maximu m frequency

01110 =

•

00001 =

00000 = Oscillator module is running at the manufacturer calibrated frequency.

11111 =

•

10000 = Minimum fre quenc y

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

Resets(1)

CONFIG(2) IOSCFS CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — —

OSCTUNE — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---u uuuu

Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.

Note 1: O ther (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

2: See Configuration Word register (Register 12-1) for operation of all register bits.

PIC16F610/616/16HV610/616

NOTES:

PIC16F610/616/16HV610/616

4.0 I/O PORTS

There are as many as eleven general purpose I/O pins

and an input pin available. Depending on which

peripherals are enabled, some or all of the pins may not

be available as general purpose I/O. In general, when a

peripheral is enabled, the associated pin may not be

used as a genera l purpose I/O pin.

4.1 PORTA and the TRISA Registers

PORTA is a 6-bit wide, bidirectional port. The

corresponding data direction register is TRISA

(Register 4-2). Setting a TRISA bit (= 1) will make the

corresponding PORTA pin an input (i.e., disable the

output driver). Clearing a TRISA bit (= 0) will make the

corresponding POR T A pin an output (i.e., enables output

driver and puts the contents of the output latch on the

selected pin). The exception is RA3, which is input only

and its TRIS bit will always read as ‘1’. Example 4-1

shows how to ini tial ize PO R TA.

Reading the PORTA register (Register 4-1) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then

written to the PORT data latch. RA3 reads ‘0’ when

MCLRE = 1.

The TRISA register controls the direction of the

PORTA pins, even when they are being used as analog

inputs. The user must ensure the bits in the TRISA

input s. I/O pin s co nfigure d as analo g inpu t alw ays rea d

‘0’.

EXAMPLE 4-1: INITIALIZING PORTA

Note: The ANSEL register must be initialized to

configure an analog channel as a digital

input. Pi ns configu red as analo g inputs will

read ‘0’ and cannot generate an interrupt.

BCF STATUS,RP0 ;Bank 0

CLRF PORTA ;Init PORTA

BSF STATUS,RP0 ;Bank 1

CLRF ANSEL ;digital I/O

MOVLW 0Ch ;Set RA<3:2> as inputs

MOVWF TRISA ;and set RA<5:4,1:0>

;as outputs

BCF STATUS,RP0 ;Bank 0

U-0 U-0 R/W-x R/W-0 R-x R/W-0 R/W-0 R/W-0

—— RA5 RA4 RA3 RA2 RA1 RA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 RA<5:0>: PO RTA I/ O Pin bit

1 = PORTA pin is > VIH

0 = PORTA pin is < VIL

U-0 U-0 R/W-1 R/W-1 R-1 R/W-1 R/W-1 R/W-1

—— TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 TRISA<5:0>: PORTA Tri-State Control bit

1 = PORTA pin configured as an input (tri-stated)

0 = PORTA pin configured as an output

Note 1: T RISA<3> always reads ‘1’.

2: TRISA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.

PIC16F610/616/16HV610/616

4.2 Additional Pin Functions

Every PORTA pin on the PIC16F610/616/16HV610/

616 has an interrupt-on-change option and a weak pull-

up option. The next three sections describe these

functions.

4.2.1 ANSEL REGISTER

The ANSEL register is used to configure the Input

mode of an I/O pin to analog. Setting the appropriate

ANSEL bit hi gh wil l ca us e all digi t al read s on the pi n to

be rea d as ‘0’ and allow analog functions on the pin to

operate correctly.

The state of the ANSEL bits has no affect on digital

output functions. A pin with TRIS clear and ANSEL set

will still operate as a digital output, but the Input mode

will be analog. This can cause unexpected behavior

when executing read-modify-write instructions on the

affec ted port.

4.2.2 WEAK PULL-UPS

Each of the PORTA pins, except RA3, has an

individually configurable internal weak pull-up. Control

bits WPUAx enable or disable each pull-up. Refer to

Re gi st er 4-4. Eac h weak pu ll-up is aut omatically turned

off when the port pin is configured as an output. The

pull-ups are disabled on a Power-on Reset by the

RAPU bit of the OPTION register). A weak pull-up is

automatically enabled for RA3 when configured as

MCLR and disabled when RA3 is an I/O. There is no

software control of the MCLR pul l-up .

4.2.3 INTERRUPT-ON-CHANGE

Each PORTA pin is individually configurable as an

interrupt-on-change pin. Control bits IOCAx enable or

disable the interrupt function for each pin. Refer to

Power-on Reset.

For enabled interrupt-on-change pins, the values are

comp ared with the old val ue latch ed on the la st read of

PORTA. The ‘mismatch’ outputs of the last read are

OR’d tog ether to set the PO RTA Change I nterrupt Flag

bit (RAIF) in the INTCON register (Register 2-3).

This interrupt can wake the device from Sleep. The

user, in the Interrupt Service Routine, clears the

interrupt by :

a) Any read or write of PORTA. This will end the

mismatch condition, then,

b) Clear the flag bit RAIF.

A mism at c h c ond it i on wi ll co nti n ue to s et f lag bi t RA IF.

Reading PORTA will end the mismatch condition and

allow flag bit RAIF to be cleared. The latch holding the

last read value is not affected by a MCLR nor BOR

Reset. After the se rese ts , the RAIF flag wil l continue to

be set if a mismatch is present.

Note: If a change on the I/O pin should occur

when any PORTA operation is being

execute d, then the RAIF i nterrupt flag ma y

not get set.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 ANS<7:0>: Analog Select bits

Analog select between analog or digital function on pins AN<7:0>, respectively.

1 = Analog input. Pin is assigned as analog input(1).

0 = Digital I/O. Pin is assigned to port or special function.

Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and

interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow

external control of the voltage on the pin.

PIC16F610/616/16HV610/616

U-0 U-0 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1

—— WPUA5 WPUA4 — WPUA2 WPUA1 WPUA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 WPUA<5:4>: Weak Pull-up Control bits

1 = Pull-up enabled

0 = Pull-up disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 WPUA<2:0>: Weak Pull-up Control bits

1 = Pull-up enabled

0 = Pull-up disabled

Note 1: Global RAPU must be enabled for individual pull-ups to be enabled.

2: The weak pull-up device is automatically disabled if the pin is in Output mode (TRISA = 0).

3: The RA3 pull-up is enabled when configured as MCLR and disabled as an input in the Configuration

Word.

4: WPUA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 IOCA<5:0>: Interrupt-on-change PORTA Control bit

1 = Interrupt-on-change enabled

0 = Interrupt-on-change disabled

Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized.

2: IOCA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.

PIC16F610/616/16HV610/616

4.2.4 PIN DESCRIPTIONS AND

DIAGRAMS

Each PORTA pin is multiplexed with other functions.

The pins and their combined functions are briefly

described here. For specific information about

individual functions such as the Comparator or the

ADC, refer to the appro priate sect ion in this data s heet.

4.2.4.1 RA0/AN0(1)/C1IN+/ICSPDAT

Figure 4-1 show s the di agram for this pi n. The RA 0 pin

is configurable to function as one of the following:

• a general pu rpose I/ O

• an analog input for the ADC(1)

• an analog non-inverting input to the comparator

• In-Circuit Se rial Programming data

4.2.4.2 RA1/AN1(1)/C12IN0-/VREF(1)/

ICSPCLK

Figur e 4-1 shows the di agram fo r this pin. Th e RA1 pi n

is configurable to function as one of the following:

• a general purpo se I/O

• an analog input for the ADC(1)

• an analog inverting input to the comparator

• a voltage reference input for the ADC(1)

• In-Circuit Serial Programming clock

FIGURE 4-1: BLOCK DIAGRAM OF RA<1:0>

Note 1: PIC16F616/16HV616 only.

VDD

VSS

VDD

Weak

RD PORTA

IOCA

Interrupt-on-

To Comparator

Analog(1)

Input Mode

RAPU

Analog(1)

Input Mode

Change

WPUA

Data Bus

WPUA

PORTA

TRISA

PORTA

Note 1: Comparator mode and ANSEL determi nes Analog Input mo de.

2: Set has priority over Reset.

3: PIC16F6 16/16HV6 16 onl y.

To A/D Converter(3)

I/O Pin

S(2)

From other

RA<5:1> pins (RA0)

Write ‘0’ to RAIF RA<5:2, 0> pins (RA1)

PIC16F610/616/16HV610/616

4.2.4.3 RA2/AN2(1)/T0CKI/INT/C1OUT

Figure 4-2 sh ows the di agram f or thi s pin. The R A2 pin

is configurable to function as one of the following:

• a general pu rpose I/ O

• an analog input for the ADC(1)

• the clock input for TM R0

• an external edge triggered interrupt

• a digital output from Comparator C1

FIGURE 4-2: BLOCK DIAGRAM OF RA2

Note 1: PIC16F616/16HV616 only.

VDD

VSS

VDD

Weak

RD PORTA

IOAC

Interrupt-on-

To INT

Analog(1)

Input Mode

RAPU

Analog(1)

Input Mode

Change

WPUA

Data Bus

WPUA

PORTA

TRISA

PORTA

Note 1: Comparator mode and ANSEL determines Analog Input mode.

2: Set has priority over Reset.

3: PIC16F6 16/16HV6 16 onl y.

To A/D Converter(3)

I/O Pin

S(2)

From other

RA<5:3, 1:0> pins

Write ‘0’ to RAIF

C1OE

Enable

To Timer0

PIC16F610/616/16HV610/616

4.2.4.4 RA3/MCLR/VPP

Figure 4-3 show s the di agram for this pi n. The RA 3 pin

is configurable to function as one of the following:

• a general pu rpose input

• as Master Clear Reset with weak pull-up

FIGURE 4-3: BLOCK DIAGRAM OF RA3

VSS

Data Bus

RD PO RTA

PORTA

IOCA

Reset MCLRE

TRISA VSS

MCLRE

VDD

Weak

MCLRE

Input

Interrupt-on-

Change

S(1)

From other

Write ‘0’ to RAIF

Note 1: Set has priority over Reset

RA<5:4, 2:0> pins

PIC16F610/616/16HV610/616

4.2.4.5 RA4/AN3(1)/T1G/OSC2/CLKOUT

Figure 4-4 sh ows the di agram f or thi s pin. The R A4 pin

is configurable to function as one of the following:

• a general pu rpose I/ O

• an analog input for the ADC(1)

• a Timer1 gat e (coun t enabl e)

• a cryst al/ reso nator connectio n

• a clock output

FIGURE 4-4: BLOCK DIAGRAM OF RA4

Note 1: PIC16F616/16HV616 only.

VDD

VSS

VDD

Weak

Analog

Input Mode

Data Bus

WPUA

PORTA

TRISA

IOCA

FOSC/4

To A/D Converter(5)

Oscillator

Circuit

OSC1

CLKOUT

Enable

Analog(3)

Input Mode

RAPU

RD PORTA

To T1G

INTOSC/

RC/EC(2)

CLK(1)

Modes

CLKOUT

Enable

Note 1: CLK modes are XT, HS, LP, TMR1 LP and CLKOUT Enable.

2: With CLKOUT option.

3: Analog Input mode comes from ANSEL.

4: Set has priority over Reset.

5: PIC16F616/16HV616 only.

I/O Pin

Interrupt-on-

Change

S(4)

From other

Write ‘0’ to RAIF

RA<5, 3:0> pins

PIC16F610/616/16HV610/616

4.2.4.6 RA5/T1CKI/OSC1/CLKIN

Figure 4-5 show s the di agram for this pi n. The RA 5 pin

is configurable to function as one of the following:

• a general purpo se I/O

• a Timer1 clock input

• a cryst al/ reso nator connectio n

• a cloc k inpu t

FIGURE 4-5: BLOCK DIAGRAM OF RA5

VDD

VSS

VDD

Weak

Data Bus

WPUA

PORTA

TRISA

IOCA

To Timer1

INTOSC

Mode

RD PORTA

INTOSC

Mode

RAPU

OSC2

Note 1: Timer1 LP Oscillator enabled.

2: Set has pri o rity over Reset.

TMR1LPEN(1)

Oscillator

Circuit

I/O Pin

Interrupt-on-

Change

S(2)

From other

RA<4:0> pins

Write ‘0’ to RAIF

PIC16F610/616/16HV610/616

TABLE 4-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Va lue on

POR, BOR

Value on

all other

Resets

ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111

CM1CON0 C1ON C1OUT C1OE C1POL —C1R C1CH1 C1CH0 0000 -000 0000 -000

CM2CON0 C2ON C2OUT C2OE C2POL —C2R C2CH1 C2CH0 0000 -000 0000 -000

INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000

IOCA —— IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 --00 0000

OPTION_REG RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

PORTA —— RA5 RA4 RA3 RA2 RA1 RA0 --x0 x000 --u0 u000

TRISA —— TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111

WPUA ——WPUA5WPUA4— WPUA2 WPUA1 WPUA0 --11 -111 --11 -111

Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.

PIC16F610/616/16HV610/616

4.3 PORTC and the TRISC Registers

PORTC is a general purpose I/O port consisting of 6

bidirec tional pins . The pins c an b e con figured for e ither

digital I/O or analog input to A/D Converter (ADC) or

Comparator. For specific information about individual

functio ns such a s the Enhan ced CCP or t he ADC , refer

to the appropriate section in this data sheet.

EXAMPLE 4- 2: INITIALI ZING PORTC

Note: The ANSEL register must be initialized to

configure an analog channel as a digital

input. Pi ns configu red as analo g inputs will

read ‘0’ and canno t gene rate an inte rrup t .

BCF STATUS,RP0 ;Bank 0

CLRF PORTC ;Init PORTC

BSF STATUS,RP0 ;Bank 1

CLRF ANSEL ;digital I/O

MOVLW 0Ch ;Set RC<3:2> as inputs

MOVWF TRISC ;and set RC<5:4,1:0>

;as outputs

BCF STATUS,RP0 ;Bank 0

U-0 U-0 R/W-x R/W-x R/W-0 R/W-0 R/W-x R/W-x

—— RC5 RC4 RC3 RC2 RC1 RC0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 RC<5:0>: PORTC I/O Pin bit

1 = PORTC pin is > VIH

0 = PORTC pin is < VIL

U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

—— TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 TRISC<5:0>: PORTC Tri-State Control bit

1 = PORTC pin configured as an input (tri-stated)

0 = PORTC pin configured as an output

PIC16F610/616/16HV610/616

4.3.1 RC0/AN4(1)/C2IN+

The RC0 is configurable to function as one of the

following:

• a general pu rpose I/ O

• an analog input for the ADC(1)

• an analog non-inverting input to Comparator C2

4.3.2 RC1/AN5(1)/C12IN1-

The RC1 is configurable to function as one of the

following:

• a general pu rpose I/ O

• an analog input for the ADC(1)

• an analog inverting input to the comparator

FIGURE 4-6: BLOCK DIAGRAM OF RC0

AND RC1

4.3.3 RC2/AN6(1)/C12IN2-/P1D(1)

The RC2 is configurable to function as one of the

following:

• a general purpo se I/O

• an analog input for the ADC(1)

• an analog input to Comparators C1 and C2

• a digita l outp ut from the Enha nc ed CCP(1)

4.3.4 RC3/AN7(1)/C12IN3-/P1C(1)

The RC3 is configurable to function as one of the

following:

• a general purpo se I/O

• an analog input for the ADC(1)

• an analog inverting input to Comparators C1 and C2

• a digita l outp ut from the Enha nc ed CCP(1)

FIGURE 4-7: BLOCK DIAGRAM OF RC2

AND RC3

Note 1: PIC16F616/16HV616 only.

I/O Pi

VDD

VSS

Data Bus

PORTC

TRISC

To A/D Converter

PORTC

Analog Input

Mode(1)

To Comparators

Note 1: Analog Input mode comes from ANSEL or

Comparator mode.

Note 1: PIC16F616/16HV616 only.

I/O Pin

VDD

VSS

Data Bus

PORTC

TRISC

To A/D Converter

PORTC

Analog Input

Mode(1)

CCPOUT

CCPOUT(2)

Enable

Note 1: Analog Input mode comes from ANSEL.

2: PIC16F616/16HV616 only.

PIC16F610/616/16HV610/616

4.3.5 RC4/C2OUT/P1B(1)

The RC4 is configurable to function as one of the

following:

• a general pu rpose I/ O

• a digital output from Comparator C2

• a digital output from the Enhanced CCP(1)

FIGURE 4-8: BLOCK DIAGRAM OF RC4

4.3.6 RC5/CCP1(1)/P1A(1)

The RC5 is configurable to function as one of the

following:

• a general purpo se I/O

• a digital input/output for the Enhanced CCP(1)

FIGURE 4-9: BLOCK DIAGRAM OF RC5

TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Note 1: PIC16F616/16HV616 only.

2: Enabling both C2OUT and P1B will cause

a conflict on RC4 and create unpredict able

results. Therefore, if C2OUT is enabled,

the ECCP can not be used in Half-Bridge

or Full-Bridge mode and vice-versa.

I/O Pin

VDD

VSS

Data Bus

PORTC

TRISC

PORTC

Note 1: Port/Peripheral Select signals selects between

PORT data and peripheral output.

C2OE

CCP1M<3:0>

C2OE

C2OUT

CCP1M<3:0>

CCPOUT/P1B

Note 1: PIC16F616/16HV616 only.

I/O Pin

VDD

VSS

Data bus

PORTC

TRISC

To Enhanced CCP

PORTC

CCP1OUT(1)/

CCP1OUT(1)

Enable

P1A

Note 1: PIC16F616/16HV616 only.

Name B i t 7 B it 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

Resets

ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111

CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000

CM1CON0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 0000 -000 0000 -000

CM2CON0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 0000 -000 0000 -000

PORTC —— RC5 RC4 RC3 RC2 RC1 RC0 --xx 00xx --uu 00uu

TRISC —— TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111

Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.

PIC16F610/616/16HV610/616

5.0 TIMER0 MODULE

The Timer0 module is an 8-bit timer/counter with the

following features:

• 8-bit timer/counter register (TMR0)

• 8-bit prescaler (shared with Watchdog Timer)

• Programmable internal or external clock source

• Programmable external clock edge selection

• Inter rupt on ov erflow

Figure 5-1 is a block diagram of the Timer0 module.

5.1 Timer0 Operation

When use d as a tim er, the Timer0 modul e can be used

as either an 8-bit timer or an 8-bit counter.

5.1.1 8-BIT TIMER MODE

When used as a timer, the Timer0 module will

increment every instruction cycle (without prescaler).

Timer mode is selected by clearing the T0CS bit of the

OPTION register to ‘0’.

When TMR0 is written, the increment is inhibited for

two instruction cycles immediately following the write.

5.1.2 8-BIT COUNTER MODE

When used as a counter, the Timer0 module will

increment on every rising or falling edge of the T0CKI

pin. The incrementing edge is determined by the T0SE

bit of the OPTION register . Counter mode is selected by

setting the T0CS bit of the OPTION register to ‘1’.

FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

Note: The value writ ten to the T MR0 register can

be adju sted, in order to ac count for th e two

instruction cycle delay when TMR0 is

written.

T0CKI

T0SE

TMR0

Watchdog

Timer

WDT

Time-out

PS<2:0>

WDTE

Data Bus

Set Flag bi t T0 IF

on Overflow

T0CS

Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register.

2: WDTE bit is in the Configuration Word register.

Sync

2 Tcy

8-bit

Prescaler

FOSC/4

PSA

PIC16F610/616/16HV610/616

5.1.3 SOFTWARE PROGRAMMABLE

PRESCALER

A single software programmable prescaler is available

for use with either Timer0 or the Watchdog Timer

(WDT), but not both simultaneously. The prescaler

assignme nt is control led by the PSA bit o f the OPTI ON

must be cleared to a ‘0’.

There are 8 prescaler options for the Timer0 module

ranging from 1:2 to 1:256. The prescale values are

select able via the PS<2:0> bit s of the OPTIO N register .

In order to have a 1:1 prescaler value for the Timer0

module, the prescaler must be assigned to the WDT

module.

The prescaler is not readable or writable. When

assigned to the T im er0 module, all instructions writing to

the TMR0 register will clear the prescaler.

When the prescaler is assigned to WDT, a CLRWDT

instruction will clear the prescaler along with the WDT.

5.1.3.1 Switching Prescaler Between

Timer0 and WDT Modules

As a result of having the prescaler assigned to either

Timer0 or the WDT, it is possible to generate an

unintended device Reset when switching prescaler

values . When chan gin g th e presca le r ass ig nme nt from

Timer0 to the WDT module, the instruction sequence

shown in Example 5-1 must be executed.

EXAMPLE 5-1: CHANGING PRESCALER

(TIMER0 →WDT)

When changing the prescaler assignment from the

WDT to the Timer0 module, the following instruction

sequence must be executed (see Example 5-2).

EXAMPLE 5-2: CHANGING PRESCALER

(WDT →TIMER0)

5.1.4 TIMER0 INTERRUPT

Timer0 will generate an interrupt when the TMR0

flag bit of the INTCON register is set every time the

TMR0 register overflows, regardless of whether or not

the Timer0 interrupt is enabled. The T0IF bit must be

cleared in software. The Timer0 interrupt enable is the

T0IE bit of the INTCON register.

5.1.5 USING TIMER0 WITH AN

EXTERNAL CLOCK

When Timer0 is in Count er mode , the syn chronization

of the T0CKI input and the Timer0 register is

accomplished by samp ling the prescaler ou tput on the

Q2 and Q4 cycles of the internal phase clocks.

Therefore, the high and low periods of the external

clock source must meet the timing requirements as

shown in Section 15.0 “Electrical Specifications”.

BANKSEL TMR0 ;

CLRWDT ;Clear WDT

CLRF TMR0 ;Clear TMR0 and

;prescaler

BANKSEL OPTION_REG ;

BSF OPTION_REG,PSA ;Select WDT

CLRWDT ;

;

MOVLW b’11111000’ ;Mask prescaler

ANDWF OPTION_REG,W ;bits

IORLW b’00000101’ ;Set WDT prescaler

MOVWF OPTION_REG ;to 1:32

Note: The Timer0 interrupt cannot wake the

processor from Sleep since the timer is

frozen during Sleep.

CLRWDT ;Clear WDT and

;prescaler

BANKSEL OPTION_REG ;

MOVLW b’11110000’ ;Mask TMR0 select and

ANDWF OPTION_REG,W ;prescaler bits

IORLW b’00000011’ ;Set prescale to 1:16

MOVWF OPTION_REG ;

PIC16F610/616/16HV610/616

TABLE 5-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 RAPU: POR TA Pull-up Enable bit

1 = PORTA pu ll-ups are disabled

0 = PORTA pull-ups are enabled by individual PORT latch values

bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of INT pin

0 = Interrupt on falling edge of INT pin

bit 5 T0CS: TMR0 Clock Source Select bit

1 = Transit ion on T0CKI pin

0 = Internal instruction cycle clock (FOSC/4)

bit 4 T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on T0CKI pin

0 = Increment on low-to-high transition on T0 CKI pin

bit 3 PSA: Prescaler Assignme nt bit

1 = Prescaler is assigned to the WDT

0 = Prescaler is assigned to the Timer0 module

bit 2-0 PS<2:0>: Prescaler Rate Select bits

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

BIT VA LUE TMR 0 RA TE WDT RAT E

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

Resets

TMR0 Timer0 Modules Register xxxx xxxx uuuu uuuu

INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000

OPTION_REG RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111

Legend: – = Un im pl emented loc ati ons , re ad as ‘ 0’, u = unchanged, x = un kn ow n. Shad ed cells a r e no t u sed by th e

Timer0 module.

PIC16F610/616/16HV610/616

NOTES:

PIC16F610/616/16HV610/616

6.0 TIMER1 MODULE WITH GATE

CONTROL

The Timer1 module is a 16-bit timer/counter with the

following features:

• 16-bit tim er/coun ter register p air (TMR 1H:TMR 1L)

• Programmable internal or external clock source

• 3-bit prescaler

• Op tional LP oscillator

• Synchronous or asynchronous operation

• Timer1 gate (count enable) via comparator or

T1G pin

• Inter rupt on ov erflow

• Wake-up on overflow (external cloc k,

Asynchronous mode only)

• Time base for the Capture/Compare function

• Specia l Event Trigger (with ECCP)

• Comparator output synchronization to Timer1

clock

Figure 6-1 is a block diagram of the Timer1 module.

6.1 Timer1 Operation

The Timer1 module is a 16-bit incrementing counter

which is acces sed through the TMR 1H:TMR1L reg ister

pair. Writes to TMR1H or TMR1L directly update the

counter.

When us ed with an interna l clock so urce, the module i s

a time r. W hen used with an ext ernal cl ock so urce, the

module can be used as either a timer or counter.

6.2 Clock Source Selection

The TMR1CS bit of the T1CON register is used to select

the clock source. When TMR1CS = 0, the clock source

is FOSC/4. When TMR1CS = 1, the clock source is

supplied exte rnally.

FIGURE 6-1: TIMER1 BLOCK DIAGRAM

Clock Source TMR1CS T1ACS

FOSC/4 00

FOSC 01

T1CKI pin 1x

TMR1H TMR1L

Oscillator T1SYNC

T1CKPS<1:0>

FOSC/4

Internal

Clock

Prescaler

1, 2, 4, 8

Synchronized

clock input

Set flag bit

TMR1IF on

Overflow TMR1(2)

TMR1GE

TMR1ON

T1OSCEN

C2OUT

T1GSS

T1GINV

To C2 Comparator Module

Timer1 Clock

TMR1CS

OSC2/T1G

OSC1/T1CKI

Note 1: ST Buffer is low power type when using LP osc, or high speed type when using T1CKI.

2: Timer1 register increments on rising edge.

3: Synchronize does not operate while in Sleep.

(1)

INTOSC

Without CLKOUT 1

T1ACS

FOSC

Synchronize(3)

det

PIC16F610/616/16HV610/616

6.2.1 INTERNAL CLOCK SOURCE

When the internal clock source is selected the

TMR1H:TMR1L register pair will increment on multiples

of TCY as determined by the Timer1 prescaler.

6.2.2 EXT ERNAL CLOCK SOURCE

When the external clock sour ce is selected, the Timer1

module may wo rk as a timer or a cou nter.

When counting, Timer1 is incremented on the rising

edge of the external clock input T1CKI. In addition, the

Counter mode clock can be synchronized to the

microcontroller system clock or run async hronously.

If an external clock oscillator is needed (and the

microc ontroller is using the INTOS C withou t CLKOUT),

Timer1 can use the LP oscillator as a clock source.

6.3 Timer1 Prescaler

Timer1 has four prescaler options allowing 1, 2, 4 or 8

divisions of the clock input. The T1CKPS bits of the

T1CON register control the prescale counter. The

prescale counter is not directly readable or writable;

however , the prescaler counter is cleared upon a write to

TMR1H or TMR1L.

6.4 Timer1 Oscillator

A low-power 32.768 kHz crystal oscillator is built-in

between pins OSC1 (input) and OSC2 (output). The

oscillator is enabled by setting the T1OSCEN control

bit of th e T1CON register. The oscillat or will con tinue to

run during Sleep.

The Timer1 oscillator is shared with the system LP

oscillator. Thus, Timer1 can use this mode only when

the primary system clock is derived from the internal

oscillator or when the oscillator is in the LP Oscillator

mode. The us er must provi de a so ftwar e time dela y to

ens ure pr oper oscilla tor start- up.

TRISA5 and TRISA4 bits are set when the Timer1

oscill ato r is enabled. RA 5 an d R A4 b its read as ‘0’ an d

TRIS A5 and TRISA4 bits read as ‘1’.

6.5 Timer1 Operation in

Asynchronous Counter Mode

If control bit T1SYNC of the T1CON register is set, the

external clock input is not synchronized. The timer

continues to increment asynchronous to the internal

phase clocks. The timer will continue to run during

Sleep and can generate an interrupt on overflow,

which will wake-up the processor. However, special

precautions in software are needed to read/write the

timer (see Section 6.5.1 “Reading and Writing

Timer1 in Asynchronous C ounter Mode”).

6.5.1 READING AND WRITING T IMER1 IN

ASYNCHRONOUS COUNTER

MODE

Reading TMR1H or TMR1L while the timer is running

from an e xternal asyn chronous cl ock will ens ure a valid

read (taken care of in hardware). However, the user

should keep i n mind that rea ding t he 16-bi t time r in tw o

8-bit values itself, poses certain problems, since the

timer may overflow between the reads.

For writes , it is re commend ed that th e user s imply sto p

the timer and write the desired values. A write

conte ntion may occ ur by writin g to th e time r regi sters,

while the register is incrementing. This may pro duce an

unpredictable value in the TMR1H:TMR1L register pair .

6.6 Timer1 Gate

Timer1 gate source is software configurable to be the

T1G pin or the output of Comparator C2. This allows the

device to directly time external events using T1G or

analog events using Comparator C2. See the

CM2CON1 register (Register 8-3) for selecting the

Timer1 gate source. This feature can simplify the

software for a Delta-Sigma A/D converter and many

other applications. For more informatio n on Delta-Sigma

A/D converters, see the Microchip web site

(www.microchip.com).

Timer1 gate can be inverted using the T1GINV bit of

the T1CON register, whether it orig inates from the T1G

pin or Comparator C2 output. This configures Timer1 to

measure either the active-high or active-low time

between events.

Note: In Counter mode, a falling edge must be

registered by the counter prior to the first

incr em enti ng ris ing edge.

Note: The oscillator requires a start-up and

stabilization time before use. Thus,

T1OSCEN should be set and a suitable

delay obs erv ed prio r to enabli ng Timer1.

Note: When switching from synchronous to

asynchronous operation, it is possible to

skip an increment. When switching from

asynchronous to synchronous operation,

it is possible to produce an additional

increment.

Note: TMR1GE bit of the T1CON register must

be set to us e ei ther T1G or C2OUT as the

Timer1 gate source. See the CM2CON1

tion on selecting the Timer1 gate source.

PIC16F610/616/16HV610/616

6.7 Timer1 Interrupt

The Timer1 register pair (TMR1H:TMR1L) increments

to FFFFh and rolls over to 0000h. When Timer1 rolls

over, the T i mer1 in terrupt fl ag bit of th e PIR1 regis ter is

set. To enable the interrupt on rollover, you must set

these bits:

• TMR1IE bit of the PIE1 register

• PEIE bit of the INTCON register

• GIE bit of the INTCON register

• T1SYNC bit of the T1CON register

• TMR1CS bit of the T1CON register

• T1OSCEN bit of the T1CON register (can be set)

The interrupt is cleared by clearing the TMR1IF bit in

the Interrupt Service Routine.

6.8 Timer1 Operation During Sleep

Timer1 can only operate during Sleep when setup in

Asynch ronous Counter mode. In this mode, an external

crystal or clock source can be used to increment the

counter. To set up the timer to wake the device:

• TMR1ON bit of the T1CON register must be set

• TMR1IE bit of the PIE1 register must be set

• PEIE bit of the INTCON register must be set

The device will wake-up on an overflow and execute

the next instruction. If the GIE bit of the INTCON

Routine (0004h).

6.9 ECCP Capture/Compare Time Base

(PIC16F616/16HV616 Only)

The ECCP module uses the TMR1H:TMR1L register

pair as the time base when operating in Capture or

Compare mode.

In Capture mode, the value in the TMR1H:TMR1L

In Compare mo de, an event is triggered when the value

CCPR1H:CCPR1L register pair matches the value in

the TMR1H:TMR1L register pair. This event can be a

Special E vent Trigger.

For more information, see Section 10.0 “Enhanced

Capture/Compare/PWM (With Auto-Shutdown and

Dead Band) Module (PIC16F616/16HV616 Only)”.

6.10 ECCP Special Event Trigger

(PIC16F616/16HV616 Only)

When the ECCP is configured to trigger a special

event, the trigger will clear the TMR1H:TMR1L register

pair. This special event does not cause a Timer1 inter-

rupt. The EC CP mo dule ma y stil l be con figured to gen-

erate a ECCP interrupt.

In this mode of operation, the CCP R1H:CCPR1L reg ister

pair effectively becomes the period register for Timer1.

T imer1 should be synchronized to the FOSC to utilize the

Special Event Trigger. Asynchronous operation of

T imer1 can cause a Special Event Tr igger to be missed.

In the eve nt that a wri te to TMR1H or TM R1L coinci des

with a Special Event Trigger from the ECCP, the write

will take precedence.

For more information, see Section 10.2.4 “Special

Event Trigger”.

6.11 Comparator Synchronization

The same clock us ed to increment Timer1 can also be

used to synchronize the comparator output. This

feature is enabled in the Comparator module.

When using the comparator for Timer1 gate, the

comparator output should be synchronized to Timer1.

This ensures Timer1 does not miss an increment if the

comp ara tor changes.

For more information, see Section 8.8.2

“Synchron izing Comparator C2 Output to Timer1”.

FIGURE 6-2: TIMER1 INCREMENTING EDGE

Note: The T MR1H:TTMR1L register p air and the

TMR1IF bit should be cleared before

enabling interrupts.

T1CKI = 1

when TMR1

Enabled

T1CKI = 0

when TMR1

Enabled

Note 1: Arrows indicate counter incremen ts.

2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock

PIC16F610/616/16HV610/616

6.12 Timer1 Control Register

The Timer1 Control register (T1CON), shown in

various features of the Timer1 module.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

T1GINV(1) TMR1GE(2) T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 T1GINV: Timer1 Gate Invert bit(1)

1 = Timer1 gate is active-high (Timer1 counts when gate is high)

0 = Timer1 gate is active-low (Timer1 counts when gate is low)

bit 6 TMR1GE: Timer1 Gate Enable bit(2)

If TMR1ON = 0:

This bit is ignored

If TMR1ON = 1:

1 = Timer1 counting is controlled by the Timer1 Gate function

0 = Timer1 is always counting

bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits

11 = 1:8 Prescale Value

10 = 1:4 Prescale Value

01 = 1:2 Prescale Value

00 = 1:1 Prescale Value

bit 3 T1OSCEN: LP Osci lla tor Enab le C ontro l bit

If INTOSC without CLKOUT oscillator is active:

1 = LP oscillator is enabled for Timer1 clock

0 = LP oscillator is off

Else:

This bit is ignored

bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit

TMR1 CS = 1:

1 = Do not synchroniz e exte rnal cloc k inp ut

0 = Synchronize external clock input

TMR1 CS = 0:

This bit is ignored. Timer1 uses the internal clock

bit 1 TMR1CS: Timer1 Clock Sourc e Sele ct bit

1 = External clock from T1CKI pin (on the rising edge)

0 = Internal clock

If TMR1ACS = 0:

FOSC/4

If TMR1ACS = 1:

FOSC

bit 0 TMR1ON: Timer1 On bit

1 = Enables Timer1

0 = Stops Timer1

Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source.

2: TMR1GE b it mu st be set to us e eithe r T1G pin or C2OUT, as selec ted b y the T1GSS b it of th e CM2CO N1

PIC16F610/616/16HV610/616

TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

Resets

CM2CON0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 0000 -000 0000 -000

CM2CON1 MC1OUT MC2OUT —T1ACSC1HYS C2HYS T1GSS C2SYNC 00-0 0010 00-0 0010

INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000

PIE1 —ADIE(1) CCP1IE(1) C2IE C1IE — TMR2IE(1) TMR1IE -000 0-00 -000 0-00

PIR1 —ADIF(1) CCP1IF(1) C2IF C1IF — TMR2IF(1) TMR1IF -000 0-00 -000 0-00

TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu

Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.

Note 1: PIC16 F6 16/ 16H V6 16 onl y.

PIC16F610/616/16HV610/616

NOTES:

PIC16F610/616/16HV610/616

7.0 TIMER2 MODULE

(PIC16F616/16HV616 ONLY)

The Timer2 module is an 8-bit timer with the following

features:

• 8-bit timer register (TMR2)

• 8-bit period register (PR2)

• Interrupt on TMR2 match with PR2

• Software programmable prescaler (1:1, 1:4, 1:16)

• Software programmable postscaler (1:1 to 1:16)

See Figure 7-1 for a block diagram of Timer2.

7.1 Timer2 Operation

The clock input to the Timer2 module is the system

instruction clock (FOSC/4). The clock is fed into the

Timer2 prescaler, which has prescale options of 1:1,

1:4 or 1:16. The output of the prescaler is then use d to

increm ent the TM R2 regis ter.

The val ues of T MR2 and PR2 are co nstan tly com pared

to determine when they match. TMR2 will increment

from 00h until it matches the value in PR2. When a

match occurs, two things happen:

• TMR2 is reset to 00h on the next increment cycle.

• The Timer2 postscaler is incremented

The match output of the Timer2/PR2 comparator is

then fed into th e T i mer2 post sca ler. The post sca ler ha s

post scal e options of 1 :1 to 1: 16 inclus ive. The output of

the Timer2 postscaler is used to set the TMR2IF

interrupt flag bit in the PIR1 register.

The TMR2 and PR2 registers are both fully readable

and w rita ble. O n any Rese t, the TMR2 regis ter is set to

00h and the PR2 register is set to FFh.

Timer2 is turned on by setting the TMR2ON bit in the

T2CON register to a ‘1’. Timer2 is turned off by setting

the TMR2ON bit to a ‘0’.

The Timer2 prescaler is contro lle d by the T2CKPS bits

in the T2CON register. The Timer2 postscaler is

controlled by the TOUTPS bits in the T2CON register.

The prescaler and postscaler counters are cleared

when:

• A write to TMR2 occurs.

• A write to T2CON occurs.

• Any device Reset occurs (Power-on Rese t, MCLR

Reset, Watchdog Timer Reset, or Brown-out

Reset).

FIGURE 7-1: TIMER2 BLOCK DIAGRAM

Note: TMR2 is not cleared when T2CON is

written.

Comparator

TMR2 Sets Flag

TMR2

Output

Reset

Postscaler

Prescaler

PR2

FOSC/4

1:1 to 1:16

1:1, 1:4, 1:16

bit TMR2IF

TOUTPS<3:0>

T2CKPS<1:0>

PIC16F610/616/16HV610/616

TABLE 7-1: SUMMARY OF ASSOCIATED TIMER2 REGISTERS

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits

0000 = 1:1 Postscaler

0001 = 1:2 Postscaler

0010 = 1:3 Postscaler

0011 = 1:4 Postscaler

0100 = 1:5 Postscaler

0101 = 1:6 Postscaler

0110 = 1:7 Postscaler

0111 = 1:8 Postscaler

1000 = 1:9 Postscaler

1001 = 1:10 Postscaler

1010 = 1:11 Postscale r

1011 = 1:12 Postscaler

1100 = 1:13 Postscaler

1101 = 1:14 Postscaler

1110 = 1:15 Postscaler

1111 = 1:16 Postscaler

bit 2 TMR2ON: Timer2 On bit

1 = Timer2 is on

0 = Timer2 is off

bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits

00 = Prescaler is 1

01 = Prescaler is 4

1x = Prescaler is 16

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

Resets

INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000

PIE1 —ADIE(1) CCP1IE(1) C2IE C1IE —TMR2IE

(1) TMR1IE -000 0-00 -000 0-00

PIR1 —ADIF(1) CCP1IF(1) C2IF C1IF —TMR2IF

(1) TMR1IF -000 0-00 -000 0-00

PR2 Timer2 Module Period Register 1111 1111 1111 1111

TMR2 Holding Register for the 8-bit TMR2 Register 0000 0000 0000 0000

T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

Legend: x = unknown, u = unchanged, – = unimplemente d read as ‘0’. Shaded cells are not used for Timer2 module.

Note 1: PIC16F616/16HV616 only.

PIC16F610/616/16HV610/616

8.0 COMPARATOR MODULE

Comparators are used to interface analog circuits to a

digital circuit by comparing two analog voltages and

providing a digital indication of their relative magnitudes.

The comparators are very useful mixed signal building

blocks because they provide analog functionality

independent of the device. The Analog Comparator

module includes the following features:

• Independent comparator control

• Programmable input selection

• Comparator ou tput is avail able internall y/externally

• Programmable output polarity

• Interrupt-on-change

• Wake-up from Sleep

•PWM shutdown

• Timer1 gate (count enable )

• Output synchronization to Timer1 clock input

•SR Latch

• Programmable and fixed voltage reference

• User-e nab le Comparator Hysteresis

8.1 Comparator Overview

A single comparator is shown in Figure 8-1 along with

the relationship between the analog input levels and

the digital output. When the analog voltage at VIN+ is

less than the analog voltage at VIN-, the output of the

comparator is a digital low level. When the analog

voltage at VIN+ is greater than the analog voltage at

VIN-, the outp ut of the comp arator is a digita l high le vel.

FIGURE 8-1: SINGLE COMP ARATOR

Note: Only Comparator C2 can be linked to

Timer1.

–

VIN+

VIN-Output

Output

VIN+

VIN-

Note: The black areas of the output of the

comparator represents the uncertainty

due to input offsets and response time.

PIC16F610/616/16HV610/616

FIGURE 8-2: COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM

FIGURE 8-3: COMPARATOR C2 SIMPLIFIED BLOCK DIAGRAM

Note 1: When C1ON = 0, the C1 comparator will produce a ‘0’ output to th e XO R Gate.

2: Output shown for reference only. See I/O port pin block diagram for more detail.

C1POL

C1OUT

To PWM Logic

C1OE

RD_CM1CON0

Set C 1IF

Q1 Data Bus

C1POL

Q3*RD_CM1CON0

Reset

C1OUT pin(2)

MUX

C1ON(1)

C1CH<1:0> 2

C1R

C1VREF MUX

C1VIN-

C1VIN+

C12IN0-

C12IN1-

C12IN2-

C12IN3-

C1IN+ +

MUX C2

C2POL

C2OUT To other peripherals

C2ON(1)

C2CH<1:0> 2

C2R

From Timer1

Clock

Note 1: W hen C2ON = 0, the C2 comparator will produce a ‘0’ output to the XOR Gate.

2: Output shown for reference only. See I/O port pin block diagram for more detail.

C2OE

C2VREF MUX

RD_CM2CON0

Q3*RD_CM2CON0

Set C2IF

Reset

C2VIN-

C2VIN+

C2OUT pin(2)

C2IN+

C12IN0-

C12IN1-

C2IN2-

C2IN3-

C2SYNC

C2POL Data Bus

MUX

SYNCC2OUT

To Timer1 Gate

To SR Latch

PIC16F610/616/16HV610/616

8.2 Comparator Control

Each comparator has a separate control and

Configuration register: CM1CON0 for Comparator C1

and CM2CON0 for Comparator C2. In addition,

Comparator C2 has a second control register,

CM2CON1, for controlling the interaction with Timer1 and

simultaneous reading of both comparator outputs.

The CM1CON0 and CM2CON0 registers (see Registers

8-1 and 8-2, respectively) contain the control and Status

bits for the following:

• Enable

• Input selection

• Reference selection

•Output selection

• Output pol arit y

8.2.1 COMPARATOR ENABLE

Setting the CxON bit of the CMxCON0 register enables

the comparator for operation. Clearing the CxON bit

disables the comparator for minimum current

consumption.

8.2.2 COMPARATOR INPUT SELECTION

The CxCH<1:0> bits of the CMxCON0 register direct

one of four analog input pins to the comparator

inverting input.

8.2.3 COMPARATOR REFERENCE

SELECTION

Setting the CxR bit of the CMxCON0 register directs an

internal voltage reference or an analog input pin to the

non-inverting input of the comp arator. See Section 8.11

“Compa rator V o ltage Reference ” for more information

on the internal voltage reference module.

8.2.4 COMPARATOR OUTPUT SELECTION

The output of the comparator can be monitored by

reading either the CxOUT bit of the CMxCON0 register

or the MCxOUT bit of the CM2CON1 register. In order

to make the output available for an external connection,

the following conditions must be true:

• CxOE bit of the CMxCON0 register must be set

• Corresponding TRIS bit must be cleared

• CxON bit of the CMxCON0 register must be set.

8.2.5 COMPA RATOR OUTPUT POLARITY

Inverting the output of the comparator is functionally

equivalent to swapping the comparator inputs. The

polarity of the comparator output can be inverted by

setting the CxPOL bit of the CMxCON0 register.

Clearing the CxPOL bit results in a non-inverted output.

Table 8-1 shows the output state versus input

conditions, including polarity control.

8.3 Comparator Response Time

The comparator output is indeterminate for a period of

time afte r the change of an i nput source or the selection

of a new refe rence volta ge. This period is refer red to as

the response time. The response time of the

comparator differs from the settling time of the voltage

reference. Therefore, both of these times must be

considered when determining the total response time

to a comparator input change. See the Comparator and

Voltage Reference Specifications in Section 15.0

“Electrical Specifications” for more details.

Note: To use CxIN+ and CxIN- pins as analog

inputs , the appropriate bits must be set in

the ANSEL register and the corresponding

TRIS bits must also be set to disable the

output dr ivers.

Note 1: The CxOE bit overrides the PORT data

latch. Setting the CxON has no impact on

the port overrid e.

2: The internal output of the comparator is

latched with each instruction cycle.

Unless otherwise specified, external

outputs are not latched.

TABLE 8-1: COMPARATOR OUTPUT

STATE VS. INPUT

CONDITIONS

Input Condition CxPOL CxOUT

CxVIN- > CxVIN+00

CxVIN- < CxVIN+01

CxVIN- > CxVIN+11

CxVIN- < CxVIN+10

PIC16F610/616/16HV610/616

8.4 Comparator Interrupt Operation

The comparator interrupt flag can be set whenever

there is a chang e in the o utput val ue of the compa rator.

Changes are recognized by means of a mismatch

circuit which consists of two latches and an

exclus ive-or gate (se e Figur e 8-2 and Figure 8-3). One

latch is updated with the comparator output level when

the CMxCON0 register is read. This latch retains the

value until the next read of the CMxCON0 register or

the occurrence of a Reset. The other latch of the

mismatch circuit is up dated on every Q1 system clock.

A mismatch condition will occur when a comparator

output change is clocked through the second latch on

the Q1 clock cycle. At this point the two mismatch

latches have opposite output levels which is detected

by the exclusive-or gate and fed to the interrupt

circuitry. The mismatch condition persists until either

the CMxCON0 register is read or the comparator

output returns to the previous state.

The comparator interrupt is set by the mismatch edge

and not the mismatch level. This means that the inter-

rupt flag can be reset without the additional step of

reading or writing the CMxCON0 register to clear the

mismatch registers. When the mismatch registers are

cleared, an interrupt will occur upon the comparator ’s

return to the previous state, otherwise no interrupt will

be generated.

Software will need to maintain information about the

status of the comparator output, as read from the

CMxCON0 register, or CM2CON1 register , to determine

the actual change that has occ urred.

The CxIF bit of the PIR1 register is the comparator

interrupt flag. This bit must be reset in software by

clearing it to ‘0’. Since i t is a lso po ssib le t o writ e a ‘1’ to

this register, an interrupt can be generated.

The CxIE bi t of the PIE1 re gister and the PEIE and G IE

bits of the INTCON register must all be set to enable

comparator interrupts. If any of these bits are cleared,

the interru pt is not en abled, alt hough the Cx IF bit of the

PIR1 register will still be set if an interrupt condition

occurs.

FIGURE 8-4: COMPARATOR

INTERRUPT TIMING W/O

CMxCON0 READ

FIGURE 8-5: COMPARATOR

INTERRUPT TIMING WITH

CMxCON0 READ

Note 1: A write operation to the CMxCON0

condition because all writes include a read

operation at the beginning of the write

cycle.

2: Comparator interrupts will operate correctly

regardless of the state of CxOE.

Note 1: If a change in the CMxCON0 register

(CxOUT ) should occu r when a read op er-

ation is being executed (start of the Q2

cycle), then the CxIF of the PIR1 register

interrupt flag may not get set.

2: When either comparator is first enabled,

bias circuitry in the comparator module

may cause an invalid output from the

comparator until the bias circuitry is stable.

Allow about 1 μs for bias settling then clear

the mismatch condition and interrupt flags

before enabling comparator interrupts.

CxIN+

CxOUT

Set CxIF (edge)

CxIF

TRT

reset by software

CxIN+

CxOUT

Set CxIF (edge)

CxIF

TRT

reset by software

cleared by CMxCON0 read

PIC16F610/616/16HV610/616

8.5 Operation During Sleep

The compa rator , if enabled b efore entering Sleep mode,

remains active during Sleep. The additional current

consumed by the comparator is shown separately in

Section 15.0 “Electrical Specifications”. If the

comparator is not used to wake the device, power

consumption can be minimized while in Sleep mode by

turning off the comp arator. Each comparator is turned off

by clearing the CxON bit of the CMxCON0 register.

A change to the comparator output can wake-up the

device from Sleep. To enable the comparator to wake

the devic e from Sle ep, the CxIE bit of the PIE1 reg ister

and the PEIE bit of the INTCON register must be set.

The instruction following the Sleep instruction always

executes following a wake from Sleep. If the GIE bit of

the INTCON register is also set, the device will then

execute the interrupt service routine.

8.6 Effects of a Reset

A device Reset forces the CMxCON0 and CM2CON1

registers to their Reset states. This forces both

comparators and the voltage references to their OFF

states.

PIC16F610/616/16HV610/616

R/W-0 R-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0

C1ON C1OUT C1OE C1POL —C1R C1CH1 C1CH0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 C1ON: Comparator C1 Enable bit

1 = Comparator C1 is enabled

0 = Comparator C1 is disabled

bit 6 C1OUT: Comparator C1 Output bit

If C1POL = 1 (inverted polarity):

C1OUT = 0 when C1VIN+ > C1VIN-

C1OUT = 1 when C1VIN+ < C1VIN-

If C1POL = 0 (non-inverted polarity):

C1OUT = 1 when C1VIN+ > C1VIN-

C1OUT = 0 when C1VIN+ < C1VIN-

bit 5 C1OE: Comparator C1 Output Enable bit

1 = C1OUT is present on the C1OUT pin(1)

0 = C1OUT is internal only

bit 4 C1POL: Comparator C1 Output Polarity Select bit

1 = C1OUT logic is inverted

0 = C1OUT logic is not inverted

bit 3 Unimplemented: Read as ‘0’

bit 2 C1R: Comparator C1 Reference Select bit ( non-inverting input)

1 = C1VIN+ connects to C1VREF output

0 = C1VIN+ connects to C1IN+ pin

bit 1-0 C1CH<1:0>: Comparator C1 Channel Select bit

00 = C12IN0- pin of C1 connects to C1VIN-

01 = C12IN1- pin of C1 connects to C1 VIN-

10 = C12IN2- pin of C1 connects to C1VIN-

11 = C12IN3- pin of C1 connects to C1VIN-

Note 1: Comparator output requires the following three conditions: C1OE = 1, C1ON = 1 and corresponding port

TRIS bit = 0.

PIC16F610/616/16HV610/616

R/W-0 R-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0

C2ON C2OUT C2OE C2POL —C2R C2CH1 C2CH0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 C2ON: Comparator C2 Enable bit

1 = Compar ator C2 is enab led

0 = Comparator C2 is disabled

bit 6 C2OUT: Comparator C2 Output bit

If C2POL = 1 (inverted polarity):

C2OUT = 0 when C2VIN+ > C2VIN-

C2OUT = 1 when C2VIN+ < C2VIN-

If C2POL = 0 (non-inverted polarity):

C2OUT = 1 when C2VIN+ > C2VIN-

C2OUT = 0 when C2VIN+ < C2VIN-

bit 5 C2OE: Comparator C2 Output Enable bit

1 = C2OUT is present on C2OUT pin(1)

0 = C2OUT is internal only

bit 4 C2POL: Comparator C2 Output Polarity Select bit

1 = C2OUT logic is inverted

0 = C2OUT logic is not inverted

bit 3 Unimplemented: Read as ‘0’

bit 2 C2R: Comparator C2 Reference Select bits (non-inverting input)

1 = C2VIN+ connects to C2VREF

0 = C2VIN+ connects to C2IN+ pin

bit 1-0 C2CH<1:0>: Comparator C2 Channel Select bits

00 = C2VIN- pin of C2 c onnects to C12IN 0-

01 = C2VIN- pin of C2 c onnects to C12IN 1-

10 = C2VIN- pin of C2 c onnects to C12IN 2-

11 = C2VIN- pin of C2 c onnects to C12IN 3-

Note 1: Comparator output requires the following three conditions: C2OE = 1, C2ON = 1 and corresponding port

TRIS bit = 0.

PIC16F610/616/16HV610/616

8.7 Comparator Analog Input

Connection Considerations

A simplified circuit for an analog input is shown in

Figure 8-6. Sinc e the analo g input pi ns share t heir con-

nection with a digital input, they have reverse biased

ESD protection diodes to VDD and VSS. The analog

input, therefore, must be between VSS and VDD. If the

input voltage deviates from this range by more than

0.6V in either direction, one of the diodes is forward

biased and a latch-up may occur.

A maximum source impedance of 10 kΩ is recommended

for the analog sources. Also, any external component

connected to an anal og inpu t pin, such as a capacitor or

a Zener diode, should h ave very little leakage curr ent to

minimize inaccuracies introduced.

FIGURE 8-6: ANALOG INPUT MODEL

Note 1: When reading a PORT register, all pins

configu red a s anal og inp uts will read as a

‘0’. Pins configured as digital inputs will

convert as an analog input, according to

the input specification.

2: Analog levels on any pin defined as a

digit al input, may ca use the input buff er to

consume more current than is specified.

Rs < 10K

CPIN

5 pF

VDD

VT ≈ 0.6V

RIC

ILEAKAGE

±500 nA

Vss

AIN

Legend: CPIN = Input Capacitanc e

ILEAKAGE = Leakage Current at the pin due to various junctions

RIC = Interconne ct Resista nce

RS= Source I mpedance

VA= Analog Voltage

VT= Threshold Voltage

To ADC Input

PIC16F610/616/16HV610/616

8.8 Additional Comparator Features

There are three additional comparator features:

• Timer1 count enable (gate)

• Synchronizing output with Timer1

• Simultaneous read of comparator outputs

8.8.1 COMPARATOR C2 GATING TIMER1

This feat ure can be used to time the d uration or interva l

of analog events. Clearing the T1GSS bit of the

CM2CON1 register will enable Timer1 to increment

based on the output of Comparator C2. This requires

that Timer1 is on and gating is enabled. See

Section 6.0 “Timer1 Module with Gate Control” for

details.

It is recommended to synchronize the comparator with

Timer1 by setting the C2SYNC bit when the comparator

is us ed as t he T imer1 gate sou rce. Thi s ensur es T imer1

does not miss a n incr eme nt if the compara tor ch an ges

during an increment.

8.8.2 SYNCHRONIZING COMPARATOR

C2 OUTPUT TO TIMER1

The Comparator C2 output can be synchronized with

Timer1 by setting the C2SYNC bit of the CM2CON1

falling edge of the Timer1 clock source. If a prescaler is

used with Timer1, the comparator output is latched after

the prescaling function. To prevent a race condition, the

comparator o utput is latch ed on the falling e dge of th e

Timer1 clock source and Timer1 increments on the

rising edge of its clock source. See the Comparator

Block Diagram (Figure 8-3) and the Timer1 Block

Diagram (Figure 6-1) for more information.

8.8.3 SIMULTANEOUS COMPARATOR

OUTPUT READ

The MC1OUT and MC2OUT bits of the CM2CON1

The ability to read both outputs simultaneously from a

single register eliminates the timing skew of reading

separate registers.

Note 1: Obtaining the status of C1OUT or C2OUT

by readi ng C M2CON 1 do es not af fect th e

comparator interrupt mism atch r egisters.

R-0 R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0

MC1OUT MC2OUT —T1ACS C1HYS C2HYS T1GSS C2SYNC

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 MC1OUT: M irror Copy of C1OUT bit

bit 6 MC2OUT: M irror Copy of C2OUT bit

bit 5 Unimplemented: Read as ‘0’

bit 4 T1ACS: Timer1 Alternate Clock Select bit

1 = Timer1 clock source is the system clock (FOSC)

0 = Timer1 clock source is the internal clock FOSC/4)

bit 3 C1HYS: Comparator C1 Hysteresis Enable bit

1 = Comparator C1 Hysteresis enabled

0 = Comparator C1 Hysteresis disabled

bit 2 C2HYS: Comparator C2 Hysteresis Enable bit

1 = Comparator C2 Hysteresis enabled

0 = Comparator C2 Hysteresis disabled

bit 1 T1GSS: Timer1 Gate Sour ce Select bi t

1 = Timer1 gate source is T1G

0 = Timer1 gate source is SYNCC2OUT.

bit 0 C2SYNC: Comparator C2 Output Synchronization bit

1 = C2 Output is synchronous to falling edge of Timer1 clock

0 = C2 Output is asynchronous

PIC16F610/616/16HV610/616

8.9 Comparator Hysteresis

Each comparator has built-in hysteresis that is user

enabled by setting the C1HYS or C2HYS bits of the

CM2CON1 register. The hysteresis feature can help

filter noise and reduce multiple comparator output

transitions when the output is changing state.

Figure 8-9 shows the relationship between the analog

input levels and digital output of a comp a r ato r w ith an d

without hysteresis. The output of the comparator

changes from a low state to a high state only w hen the

analog voltage at VIN+ rises above the uppe r hysteresis

threshol d (VH+). The output of th e compara tor changes

from a high state to a low state only when the analog

voltage at VIN+ falls below the lower hysteresis

threshold (VH-).

FIGURE 8-7: COMPARATOR HYSTERESIS

–

VIN+

VIN-Output

Note: The black areas of the comparator output represents the uncertainty due to input offsets and response time

VH-

VH+

VIN-

V+

VIN+

Output

(Without Hysteresis)

Output

(With Hysteresis)

PIC16F610/616/16HV610/616

T ABLE 8-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE COMPARATOR AND VOLTAGE

REFERENCE MODULES

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Va lue on

POR, BOR

Value on

all other

Resets

ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111

CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH1 C1CH0 0000 0000 0000 0000

CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH1 C2CH0 0000 0000 0000 0000

CM2CON1 MC1OUT MC2OUT —T1ACS C1HYS C2HYS T1GSS C2SYNC 00-0 0010 00-0 0010

INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 000x 0000 000x

PIE1 —ADIE(1) CCP1IE(1) C2IE C1IE —TMR2IE(1) TMR1IE -000 0-00 -000 0-00

PIR1 —ADIF(1) CCP1IF(1) C2IF C1IF —TMR2IF(1) TMR1IF -000 0-00 -000 0-00

PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --x0 x000 --x0 x000

PORTC — — RC5 RC4 RC3 RC2 RC1 RC0 --xx 00xx --uu 00uu

SRCON0 SR1 SR0 C1SEN C2REN PULSS PULSR — SRCLKEN 0000 00-0 0000 00-0

SRCON1 SRCS1 SRCS0 — — — — — — 00-- ---- 00-- ----

TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111

TRISC TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

VRCON C1VREN C2VREN VRR FVREN VR3 VR2 VR1 VR0 0000 0000 0000 0000

Legend: x = unknown , u = un changed, – = unimplemented, read as ‘0’. Shaded cells are not used for comparator.

Note 1: PIC16F616/16HV616 only.

PIC16F610/616/16HV610/616

8.10 Comparator SR Latch

The SR latch module provides additional control of the

comparator outputs. The module consists of a single

SR latch and output multiplexers. The SR latch can be

set, reset or toggled by the comparator outputs. The SR

latch may also be set or reset, independent of

comparator output, by control bits in the SRCON0

control register. The SR latch output multiplexers select

whether the latch output s or the comparator outputs are

directed to the I/O port log ic for ev entual outpu t to a pin.

The SR latch also has a variable clock, which is con-

nected to the set input of the latch. The SRCLKEN bit

of SRCON0 enables the SR latch set clock. The clock

will period ically p ulse the set input of the lat ch. Cont rol

over t he frequenc y of the SR latc h set clock is provide d

by the SRCS<1:0> bits of SRCON1 register.

8.10.1 LATCH OPERATION

The latch is a Set-Reset latch that does not depend o n a

clock source. Each of the Set and Reset inputs are

active-high. Each latch input is connected to a

comparator output and a software controlled pulse

generator . The latch can be set by C1OUT or the PULSS

bit of the SRCON0 register. The latch can be reset by

C2OUT or the PULSR bit of the SRCON0 register. The

latch is reset-dominant, therefore, if both Set and Reset

inputs are high the latch will go to the Reset state. Both

the PULSS and PULSR bits are self resetting which

means that a single write to either of the bits is all that is

necessary to comple te a latch Set or Reset operation.

8.10.2 LATCH OUTPUT

The SR<1:0> bits of the SRCON0 register control the

latch output multiplexers and determine four possible

output configurations. In these four configurations, the

CxOUT I/O port logic is connected to:

• C1 OUT and C2OUT

• C1OUT and SR latch Q

• C2OUT and SR latch Q

• SR latch Q and Q

After any Reset, the default output configuration is the

unlatched C1OUT and C2OUT mode. This maintains

compatibility with devices that do not have the SR latch

feature.

The applicable TRIS bits of the corresponding ports

must be cleared to enable the port pin output drivers.

Additionally, the CxOE comparator output enable bits of

the CMxCON0 registers must be set in order to make the

comparator or latch output s available on the output pins.

The latch configuration enable states are completely

independent of the enable states for the comparators.

FIGURE 8-8: SR LATCH SIMPLIFIED BLOCK DIAGRAM

C1SEN

SR0

PULSS

C2REN

PULSR SR1

Note 1: If R = 1 and S = 1 simultaneously, Q = 0, Q =1

2: Pulse generator causes a 1 TOSC pulse width.

3: Output shown for reference only. See I/O port pin block diagram for more detail.

Pulse

Gen(2)

Pulse

Gen(2)

SYNCC2OUT (from comparator)

C1OUT (from comparator)

C2OE

C2OUT pin(3)

C1OE

C1OUT pin(3)

MUX

Latch(1)

SRCLKEN

SRCLK

PIC16F610/616/16HV610/616

R/W-0 R/W-0 R/W-0 R/W-0 R/S-0 R/S-0 U-0 R/W-0

SR1(2) SR0(2) C1SEN C2REN PULSS PULSR — SRCLKEN

bit 7 bit 0

Legend: S = Bit is set only -

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SR1: SR Latch Configuration bit(2)

1 = C 2OU T pin is the latch Q output

0 = C 2OU T pin is the C2 comparator output

bit 6 SR0: SR Latch Configuration bits(2)

1 = C 1OU T pin is the latch Q output

0 = C 1OU T pin is the C1 Comparator output

bit 5 C1SEN: C1 Set Enable bit

1 = C1 comparator output sets SR latch

0 = C1 comparator output has no effect on SR latch

bit 4 C2REN: C2 Reset Enable bit

1 = C2 comparator output resets SR latch

0 = C2 comparator output has no effect on SR latch

bit 3 PULSS: Pulse the SET Input of the SR Latch bit

1 = Triggers pulse generator to set SR latch. Bit is immediately reset by hardware.

0 = Does not trigger pulse generator

bit 2 PULSR: Pulse the Reset Input of the SR Latch bit

1 = T riggers pulse generator to reset SR latch. Bit is immediately reset by hardware.

0 = Does not trigger pulse generator

bit 1 Unimplemented: Read as ‘0’

bit 0 SRCLKEN: SR Latch Set Clock Enable bit

1 = Set input of SR latch is pulsed with SRCLK

0 = Set input of SR latch is not pulsed with the SRCLK

Note 1: The C1OUT and C2OUT bits in the CMxCON0 register will always reflect the actual comparator output (not the level on

the pin), regardless of the SR latch operation.

2: To enable an SR Latch output to the pin, the appropriate CxOE, and TRIS bits must be properly configured.

R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0

SRCS1 SRCS0 — — — — — —

bit 7 bit 0

Legend: S = Bit is set only -

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 SRCS<1:0>: SR Latch Clock Prescale bits

00 = F

OSC/16

01 = F

OSC/32

10 = F

OSC/64

11 = F

OSC/128

bit 5-0 Unimplemented: Read as ‘0’

PIC16F610/616/16HV610/616

8.11 Comparator Voltage Reference

The comparator voltage reference module pr ovides an

internally generated voltage reference for the compara-

tors. The following features are available:

• Independent from Comparator operation

• Two 16-level voltage ranges

• Output clamped to VSS

• Ratiometric with VDD

• Fixed Refe rence (0.6V)

The VRCON register (Register 8-6) controls the

voltage reference module shown in Figure 8-9.

8.11.1 INDEPENDENT OPERATION

The comparator voltage reference is independent of

the comp arat or con figurat ion. Setti ng the FVREN bit of

the VRCON register will enable the voltage reference.

8.11.2 OUTPUT VOLTAGE SELECTION

The CVREF voltage reference has 2 ranges with 16

voltage levels in each range. Range selection is

controlled by the VRR bit of the VRCON register. The

16 levels are set with the VR<3:0> bits of the VRCON

The CVREF output voltage is determined by the following

equations:

EQUATION 8-1: CVREF OUTPUT VOLTAGE

The full range of VSS to VDD cannot be realized due to

the construction of the module. See Figure 8-9.

8.11.3 OUTPUT CLAMPED TO VSS

The fixed voltage reference output voltage can be set

to Vss with no power consumption by clearing the

FVREN bit of the VRCON register (FVREN = 0). This

allows the comparator to detect a zero-crossing while

not consuming additional module current.

8.11.4 OUTPUT RATIOMETRIC TO VDD

The comparator voltage reference is VDD derived and

therefore, the CVREF output changes with fluctuations in

VDD. The tested absolute accuracy of the Comparator

Voltage Reference can be found in Section 15.0

“Electrical Specifications”.

VRR 1 (low range):=

VRR 0 (high range):=

CVREF (VDD/4) + =

CVREF (VR<3:0>/24) VDD×=

(VR<3:0> VDD/32)×

PIC16F610/616/16HV610/616

8.11.5 FIXED VOLTAGE REFERENCE

The fixe d volta ge reference is ind ependent of V DD, with

a nomina l output volt age of 0.6V. This referen ce can be

enabled by setting the FVREN bit of the VRCON

the HFINTOSC oscillator is active.

8.11.6 FIXED VOLTAGE REFERENCE

STABILIZATION PERIOD

When the f ixed vol tage refe ren ce mo dule is enab led, it

will require some time for the reference and its amplifier

circuits to stabilize. The user program must include a

small delay routine to allow the module to settle. See

the electrical specifications section for the minimum

delay requirement.

8.11.7 VOLTAGE REFERENCE

SELECTION

Multiplexers on the output of the voltage reference

module enable selection of either the CVREF or fixed

voltage reference for use by the comparators.

Setting the C1VREN bit of the VRCON register enables

current to flow in the CV REF volt a ge div ider an d sele ct s

the CV REF voltage for use by C1. Clearing the C1VREN

bit selects the fixed voltage for use by C1.

Setting the C2VREN bit of the VRCON register enables

current to flow in the CV REF volt a ge div ider an d sele ct s

the CV REF voltage for use by C2. Clearing the C2VREN

bit selects the fixed voltage for use by C2.

When bo th the C1VREN and C2VREN b its are cle ared,

current flow in the CVREF voltage divider is disabled

minimizing the power drain of the voltage reference

peripheral.

FIGURE 8-9: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM

VRR

VR<3:0>(1)

Analog

8RRR RR

16 Stages

VDD

MUX

Fixed Voltage

C2VREN

C1VREN

CVREF

Reference

FVREN

0.6V

Fixed Ref

To Comparators

and ADC Module

To Comparators

and ADC Module

Note 1: Care should be taken to ensure VREF remains

within the comparator common mode input range.

See Section 15.0 “Electrical Specifications” for

more detail.

1.2V

To ADC Module

PIC16F610/616/16HV610/616

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

C1VREN C2VREN VRR FVREN VR3 VR2 VR1 VR0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 C1VREN: Comparator 1 Voltage Reference Enable bit

1 = CVREF circuit powered on and routed to C1VREF input of Comparator C1

0 = 0.6 Volt constant reference routed to C1VREF input of Comparator C1

bit 6 C2VREN: Comparator 2 Voltage Reference Enable bit

1 = CVREF circuit powered on and routed to C2VREF input of Comparator C2

0 = 0.6 Volt constant reference routed to C2VREF input of Comparator C2

bit 5 VRR: CVREF Range Selection bit

1 = Low range

0 = High range

bit 4 FVREN: Fixed Voltage Reference (0.6V) Enable bit

1 = Enabled

0 = Disabled

bit 3-0 VR<3:0>: Comparator Voltage Reference CVREF Value Selection bits (0 ≤ VR<3:0> ≤ 15)

When VRR = 1: CV REF = (VR<3:0>/24) * VDD

When VRR = 0: CV REF = VDD/4 + (VR<3 :0> /32) * VDD

PIC16F610/616/16HV610/616

9.0 ANALOG-TO-DIGITAL

CONVERTER (ADC) MODULE

(PIC16F616/16HV616 ONLY)

The Analog-to-Digital Converter (ADC) allows

conversion of an analog input signal to a 10-bit binary

representation of that signal. This device uses analog

inputs, which are multiplexed into a single sample and

hold circuit. The output of the sample and hold is

connected to the input of the converter. The converter

generates a 10-bit binary result via successive

approximation and stores the conversion result into the

ADC result registers (ADRESL and ADRESH).

The ADC voltage reference is software selectable to

either VDD or a v olt age applied to the ex ternal reference

pins.

The ADC can generate an interrupt upon completion of

a conversion. This interrupt ca n be used to wake-up the

device from Sleep.

Figure 9-1 shows the block diagram of the ADC.

FIGURE 9-1: ADC BLOCK DIAGRAM

ADC

VDD

VREF

ADON

GO/DONE

VCFG = 1

VCFG = 0

CHS <3:0> VSS

RA0/AN0

RA1/AN1/VREF

RA2/AN2

RA4/AN3

RC0/AN4

RC1/AN5

RC2/AN6

RC3/AN7

CVREF

0.6V Reference

1.2V Reference

ADRESH ADRESL

ADFM 0 = Left Justify

1 = Right Justify

PIC16F610/616/16HV610/616

9.1 ADC Configuration

When configuring and using the ADC, the following

functio ns must be consi dere d:

• Port configuration

• Channel selection

• ADC voltage reference selection

• ADC co nversion clock source

• Interrupt control

• Results formatti ng

9.1.1 PORT CONFIGURATION

The ADC can be used to convert both analog and digital

signals. When converting analog signals, the I/O pin

should be configured for analog by setting the associated

TRIS and ANSEL bits. See the corresponding Port

section for more information.

9.1.2 CHANNEL SELECTION

The CHS bi ts of the ADCON0 r egister det ermine whic h

channel is connected to the sample and hold circuit.

When changing channels, a delay is required before

starting the next conversion. Refer to Section 9.2

“ADC Operation” for more information.

9.1.3 ADC VOLTAGE REFERENCE

The VCFG bit of the ADCON0 register provides contro l

of the positive voltage reference. The positive voltage

reference can be either VDD or an external voltage

source. The negative voltage reference is always

connec ted to the ground refe renc e.

9.1.4 CONVERSION CLOCK

The so urce of th e conver sion cloc k is sof tware sele ct-

able via the ADCS bits of the ADCON1 register. There

are seven possible clock options:

•F

OSC/2

•FOSC/4

•FOSC/8

•F

OSC/16

•FOSC/32

•FOSC/64

•F

RC (dedicated internal oscillator)

The time to complete one bit conversion is defined as

TAD. One ful l 1 0-b it c on ve r si on requ ire s 11 TAD period s

as shown in Figure 9-3.

For correct conversion, the appropriate TAD specification

must be met. See A/D conversion requirements in

Section 15.0 “Electrical Specifications” for more

information. Table 9-1 gives examples of appropriate

ADC clock selections.

TABLE 9-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V)

Note: Analog voltages on any pin that is defined

as a digital input may cause the input

buffer to conduct excess current.

Note: Unless using the FRC, any changes in the

system clock frequency will change the

ADC clock frequency, which may

adversely affect the ADC result.

ADC Clock Period (TAD) Device Freque ncy (FOSC)

ADC Clock Source ADCS<2:0> 20 MHz 8 MHz 4 MHz 1 MHz

FOSC/2 000 100 ns(2) 250 ns(2) 500 ns(2) 2.0 μs

FOSC/4 100 200 ns(2) 500 ns(2) 1.0 μs(2) 4.0 μs

FOSC/8 001 400 ns(2) 1.0 μs(2) 2.0 μs8.0 μs(3)

FOSC/16 101 800 ns(2) 2.0 μs4.0 μs16.0 μs(3)

FOSC/32 010 1.6 μs4.0 μs8.0 μs(3) 32.0 μs(3)

FOSC/64 110 3.2 μs8.0 μs(3) 16.0 μs(3) 64.0 μs(3)

FRC x11 2-6 μs(1,4) 2-6 μs(1,4) 2-6 μs(1,4) 2-6 μs(1,4)

Legend: Shaded cells are outside of recommended range.

Note 1: The FRC source has a typical TAD time of 4 μs for VDD > 3.0V.

2: These values violate the minimum required TAD time.

3: For faster conversion times, the selection of another clock source is recommended.

4: When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the

conversion will be perform ed during Sleep.

PIC16F610/616/16HV610/616

FIGURE 9-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES

9.1.5 INTERRUPTS

The ADC module allows for the ability to generate an

interrupt upon completion of an analog-to-digital

conversion. The ADC interrupt flag is the ADIF bit in the

PIR1 reg ister. The AD C inte rrupt en able i s the ADIE bit

in the PIE1 register. The ADIF bit must be cleared in

software.

This interrupt can be generated while the device is

operatin g or while in Sle ep. If the device is in Sle ep, the

interrupt will wake-up the device. Upon waking from

Sleep, the next instruction following the SLEEP

instruc tio n is al w ays executed. If the use r i s att em ptin g

to wake-up from Sleep and resume in-line code

execution, the global interrupt must be disabled. If the

global interrupt is enabled, execution will switch to the

inter rupt se rvi ce rout ine .

Please see Section 9.1.5 “Interrupts” for more

information.

9.1.6 RESUL T FORMATTING

The 10- bit A/D conversion resu lt can be suppli ed in two

formats, left justified or right justified. The ADFM bit of

the ADCON0 register controls the output format.

Figure 9-4 shows the two output formats.

FIGURE 9-3: 10-BIT A/D CONVERSION RESULT FORMAT

TAD1TAD2 TAD3TAD4TAD5 TAD6 TAD7 TAD8 TAD9

Set GO/DONE bit

Holding Capacitor is Disconnected from Analog Input (typically 100 ns)

b9 b8 b7 b6 b5 b4 b3 b2

TAD10 TAD11

b1 b0

TCY to TAD

Conversion S tarts

ADRESH and ADRESL registers are loaded,

GO bit is cleared,

ADIF bit is set,

Holding capacitor is connected to analog input

Note: The ADIF bit is set at the completion of

every conversion, regardless of whether

or not the ADC interrupt is enabled.

ADRESH ADRESL

(ADFM = 0)MSB LSB

bit 7 bit 0 bit 7 bit 0

10-bit A/D Result Unimplemented: Read as ‘0’

(ADFM = 1)MSB LSB

bit 7 bit 0 bit 7 bit 0

Unimplemented: Read as ‘0’ 10-bit A/D Result

PIC16F610/616/16HV610/616

9.2 ADC Operation

9.2.1 STARTING A CONVERSION

To enable the ADC module, the ADON bit of the

ADCON0 register must be set to a ‘1’. Setting the GO/

DONE bit of the ADCON0 register to a ‘1’ will start the

analog-to-digital co nve rsion.

9.2.2 COMPLETION OF A CONVE RSION

When the conv ersion is complete, the ADC module will:

• Clear the GO/DONE bit

• Set the ADIF flag bit

• Update the ADRESH:A DRESL regis ters with new

conversion result

9.2.3 TERMINATING A CONVERSION

If a co nver sion must b e term ina ted be fore comp leti on,

the GO/DONE bit can be cleared in software. The

ADRESH:ADRESL registers will not be updated with

the partially complete analog-to-digital conversion

sample. Instead, the ADRESH:ADRESL register pair

will retain the value of the previous conversion. Addi-

tionall y, a 2 TAD delay is requir ed before anothe r acqui-

sition can be initiated. Following this delay, an input

acquisition is automatically started on the selected

channel.

9.2.4 ADC OPERATION DURING SLEEP

The ADC module can operate during Sleep. This

requires the ADC clock source to be set to the FRC

option. When the FRC clock source is selected, the

ADC wa its on e additio nal instru ction bef ore sta rting th e

conversion. This allows the SLEEP instruction to be

executed, which can reduce system noise during the

conversion. If the ADC interrupt is enabled, the device

will wake-up from Sleep when the conversion

completes. If the ADC interrupt is disabled, the ADC

module is turned off after the conversion completes,

although the ADON bit remains set.

When the ADC clock source is something other than

FRC, a SLEEP instruction causes the present conver-

sion to be aborted and the ADC module is turned off,

although the ADON bit remains set.

9.2.5 SPECIAL E VENT TRIGGER

The ECCP Special Event Trigger allows periodic ADC

measurements without software intervention. When

this trigger occurs, the GO/DONE bit is set by hardware

and the Timer1 counter resets to zero.

Using the Special Event Trigger does not ensure

proper ADC timing. It is the user’s responsibility to

ensure that the ADC timing requirements are met.

See Section 10.0 “Enhanced Capture/Compare/

PWM (With Auto-Shutdown and Dead Band) Mod-

ule (PIC16F616/16HV616 Only)” for more informa-

tion.

9.2.6 A/D CONVERSION PROCEDURE

This is an example procedure for using the ADC to

perform an analog-to-digital c onversion:

1. Configure Port:

• Disable pin output driver (See TRIS register)

• Configure pin as analog

2. Configure the ADC module:

• Select ADC co nversion clock

• Config ure vo lt ag e refere nc e

• Select ADC input channel

• Select result format

• Turn on ADC module

3. Configure ADC interrupt (optional):

• Clear ADC interrupt flag

• Enable ADC interrupt

• Enable peripheral interrupt

• Enable global interrupt(1)

4. Wait the required acquisition time(2).

5. Start conversion by setting the GO/DONE bit.

6. Wait for ADC conversion to complete by one of

the following:

• Polli ng the GO /DO N E bit

• Waiting for the ADC interrupt (interrupts

enabled)

7. Read ADC Result

8. Clear the ADC interrup t flag (requi red if interrupt

is enabled).

Note: The GO/DONE bit shou ld not be set in th e

same instruction that turns on the ADC.

Refer to Section 9.2.6 “A/D Conversion

Procedure”.

Note: A device Reset forces all registers to their

Reset state. Thus, the ADC module is

turned off and any pending conversion is

terminated.

Note 1: The global interrupt may be disabled if the

user is attem pti ng to wak e-up from Sleep

and resume in-line code execution.

2: See Section 9.3 “A/D Acquisition

Requirements”.

PIC16F610/616/16HV610/616

EXAMPLE 9-1: A/D CONVERSION

;This code block configures the ADC

;for polling, Vdd reference, Frc clock

;and AN0 input.

;

;Conversion start & polling for completion

; are included.

;

BANKSEL ADCON1 ;

MOVLW B’01110000’ ;ADC Frc clock

MOVWF ADCON1 ;

BANKSEL TRISA ;

BSF TRISA,0 ;Set RA0 to input

BANKSEL ANSEL ;

BSF ANSEL,0 ;Set RA0 to analog

BANKSEL ADCON0 ;

MOVLW B’10000001’ ;Right justify,

MOVWF ADCON0 ;Vdd Vref, AN0, On

CALL SampleTime ;Acquisiton delay

BSF ADCON0,GO ;Start conversion

BTFSC ADCON0,GO ;Is conversion done?

GOTO $-1 ;No, test again

BANKSEL ADRESH ;

MOVF ADRESH,W ;Read upper 2 bits

MOVWF RESULTHI ;store in GPR space

BANKSEL ADRESL ;

MOVF ADRESL,W ;Read lower 8 bits

MOVWF RESULTLO ;Store in GPR space

PIC16F610/616/16HV610/616

9.2.7 ADC REGISTER DEFINITIONS

The following registers are used to control the operation of the ADC.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADFM VCFG CHS3 CHS2 CHS1 CHS0 GO/DONE ADON

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ADFM: A/D Conversion Result Format Select bit

1 = Right justified

0 = Left justified

bit 6 VCFG: Volt age Reference bit

1 = VREF pin

0 = VDD

bit 5-2 CHS<3:0>: Analog Channel Select bits

0000 = Channel 00 (AN 0)

0001 = Channel 01 (AN 1)

0010 = Channel 02 (AN 2)

0011 = Channel 03 (AN 3)

0100 = Channel 04 (AN 4)

0101 = Channel 05 (AN 5)

0110 = Channel 06 (AN 6)

0111 = Channel 07 (AN 7)

1000 = Reserved – do not use

1001 = Reserved – do not use

1010 = Reserved – do not use

1011 = Reserved – do not use

1100 =CV

REF

1101 = 0.6V Fixed Voltage Reference(1)

1110 = 1.2V Fixed Voltage Reference(1)

1111 = Reserved – do not use

bit 1 GO/DONE: A/D Conversion Status bit

1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.

This bit is automatically cleared by hardware when the A/D conversion has completed.

0 = A/D conversion completed/not in progress

bit 0 ADON: ADC Enable bit

1 = ADC is enabled

0 = ADC is disabled and consumes no operating current

Note 1: When the CHS<3:0> bits change to select the 1.2V or 0.6V Fixed Voltage Reference, the reference output voltage will

have a transient. If the Comparator module uses this VP6 reference voltage, the comparator output may momentarily

change state due to the transient.

PIC16F610/616/16HV610/616

U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— ADCS2 ADCS1 ADCS0 — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits

000 = FOSC/2

001 = FOSC/8

010 = FOSC/32

x11 = FRC (clock derived from a dedicated internal oscillator = 500 kHz max)

100 = FOSC/4

101 = FOSC/16

110 = FOSC/64

bit 3-0 Unimplemented: Read as ‘0’

PIC16F610/616/16HV610/616

R-x R-x R-x R-x R-x R-x R-x R-x

ADRES9 ADRES8 ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 ADRES<9:2>: ADC Result Register bits

Upper 8 bits of 10-bit conversion result

R-x R-x U-0 U-0 U-0 U-0 U-0 U-0

ADRES1 ADRES0 — — — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 ADRES<1:0>: ADC Result Register bits

Lower 2 bits of 10-bit conversion result

bit 5-0 Reserved: Do not use.

U-0 U-0 U-0 U-0 U-0 U-0 R-x R-x

— — — — — — ADRES9 ADRES8

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-2 Reserved: Do not use.

bit 1-0 ADRES<9:8>: ADC Result Register bits

Upper 2 bits of 10-bit conversion result

R-x R-x R-x R-x R-x R-x R-x R-x

ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 ADRES<7:0>: ADC Result Register bits

Lower 8 bits of 10-bit conversion result

PIC16F610/616/16HV610/616

9.3 A/D Acquisition Requirements

For the A DC t o meet i ts specified accuracy, the char ge

holding capacitor (CHOLD) must be allowed to fully

charge to the input channel voltage level. The Analog

Input model is shown in Figure 9-4. The source

impedance (RS) and the internal sampling switch (RSS)

impedance directly affect the time required to charge the

capacitor CHOLD. The sampling switch (RSS) impedance

varies over the device voltage (VDD), see Figure 9-4.

The maximum recommended impedance for analog

sources is 10 kΩ. As the source impedance is

decreased, the acquisition time may be decreased.

After the analog input channel is selected (or changed),

an A/D acquisition must be done before t he conversion

can be started. To calculate the minimum acquisition

time, Equation 9-1 may be used. This equation

assumes that 1/2 LSb error is used (1024 steps for the

ADC). The 1/2 LSb error is the maximum error allowed

for the ADC to meet its specified resolution.

EQUATION 9-1: ACQUISITION TIME EXAMPLE

TACQ Amplifier Settling Time Hold Capacitor Charging Time Temperature Coefficient++=

TAMP TCTCOFF++=

5µs TCTemperature - 25°C()0.05µs/°C()[]++=

TCCHOLD RIC RSS RS++() ln(1/2047)–=

10pF 1k

10k

++()– ln(0.0004885)=

1.37=µs

TACQ 5µS1.37µS50°C- 25°C()0.05µS/°C()[]++=

7.67µS=

VAPPLIED 1e

Tc–

---------

–

⎝⎠

⎜⎟

⎛⎞

VAPPLIED 11

2047

------------

–

⎝⎠

⎛⎞

VAPPLIED 11

2047

------------

–

⎝⎠

⎛⎞

VCHOLD=

VAPPLIED 1e

TC–

----------

–

⎝⎠

⎜⎟

⎛⎞

VCHOLD=

;[1] VCHOLD charged to with in 1/2 lsb

;[2] VCHOLD charge response to VAPPLIED

;combining [1] and [2]

The value for TC can be approxima ted with the following equations:

Solving for TC:

Therefore:

Temperature 50°C and external impedance of 10k

5.0 V VDD=

Assumptions:

Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.

2: The charge holding capacitor (CHOLD) is not discharged after each conversion.

3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin

leakage specification.

PIC16F610/616/16HV610/616

FIGURE 9-4: ANALOG INPUT MODEL

FIGURE 9-5: ADC TRANSFER FUNCTION

CPIN

Rs ANx

5 pF

VDD

VT = 0.6V

VT = 0.6V I LEAKAGE

RIC ≤ 1k

Sampling

Switch

SS Rss

CHOLD = 10 pF

VSS/VREF-

Sampling Switch

567891011

(kΩ)

VDD

± 500 nA

Legend: CPIN

I LEAKAGE

RIC

CHOLD

= Input Capacitance

= Threshold Voltage

= Leakage current at the pin due to

= Interconnect Resistance

= Sampling Switch

= Sample/Hold Capacitance

various junctions

RSS

3FFh

3FEh

ADC Output Code

3FDh

3FCh

004h

003h

002h

001h

000h

Full-Scale

3FBh

1 LSB ideal

VSS/VREF-Zero-Scale

Transition VDD/VREF+

Transition

1 LSB ideal

Full-Scale Range

Analog Input Voltage

PIC16F610/616/16HV610/616

TABLE 9-2: SUMMARY OF ASSOCIATED ADC REGISTERS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

Resets

ADCON0(1) ADFM VCFG CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 0000 0000

ADCON1(1) — ADCS2 ADCS1 ADCS0 — — — — -000 ---- -000 ----

ANSEL ANS ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111

ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu

ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu

INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000

PIE1 —ADIE

(1) CCP1IE(1) C2IE C1IE — TMR2IE(1) TMR1IE -000 0-00 -000 0-00

PIR1 —ADIF

(1) CCP1IF(1) C2IF C1IF — TMR2IF(1) TMR1IF -000 0-00 -000 0-00

PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --x0 x000 --u0 u000

PORTC — — RC5 RC4 RC3 RC2 RC1 RC0 --xx 00xx --uu 00uu

TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111

TRISC — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111

Legend: x = unknown, u = unchanged, – = unimplemented read as ‘0’. Shaded cells are not used for ADC module.

Note 1: PIC16 F6 16/ 16H V6 16 onl y.

PIC16F610/616/16HV610/616

NOTES:

PIC16F610/616/16HV610/616

10.0 ENHANCED CAPTURE/

COMPARE/PWM (WITH AUTO-

SHUTDOWN AND DEAD BAND)

MODULE

(PIC16F616/16HV616 ONLY)

The Enhanced Capture/Compare/PWM module is a

peripheral which allows the user to time and control

different events. In Capture mode, the peripheral

allows the timing of the duration of an event. The

Compare mode allows the user to trigger an external

event when a predetermined amount of time has

expired. The PWM mode can generate a Pulse-Width

Modulated signal of varying frequency and duty cycle.

Table 10-1 shows the timer resources required by the

ECCP module.

TABLE 10-1: ECCP MODE – TIMER

RESOURCES REQUIRED

ECCP Mode Timer Resource

Capture Timer1

Compare Timer1

PWM Timer2

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 P1M<1:0>: PW M Ou tp ut Co nf igu rat ion bits

If CCP1M<3:2> = 00, 01, 10:

xx = P1A assigned as Capture/Compare input; P1B, P1C, P1D assigned as port pins

If CCP1M<3:2> = 11:

00 = Single output; P1A modulated; P1B, P1C, P1D assigned as port pins

01 = Full-Bridge output forward; P1D modulated; P1A active; P1B, P1C inactive

10 = Half-Bridge output; P1A, P1B modulated with dead-time control; P1C, P1D assigned as port pins

11 = Full-Bridge output reverse; P1B modulated; P1C active; P1A, P1D inactive

bit 5-4 DC1B<1:0>: PWM Duty Cycle Least Significant bits

Capture mode:

Unused.

Compare mode:

Unused.

PWM mode:

These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L.

bit 3-0 CCP1M<3:0>: ECCP Mode Select bits

0000 = Capture/Compare/PWM off (resets ECCP module)

0001 = Unused (reserved)

0010 = Compare mode, toggle output on match (CCP1IF bit is set)

0011 = Unused (reserved)

0100 = Capture mode, every falling edge

0101 = Capture mode, every rising edge

0110 = Capture mode, every 4th rising edge

0111 = Capture mode, every 16th rising edge

1000 = Compare mode, set output on match (CCP1IF bit is set)

1001 = Compare mode, clear output on match (CCP1IF bit is set)

1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected)

1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1 and starts an A/D

conversion, if the ADC module is enabled)

1100 = PWM mode; P1A, P1C active-high; P1B, P1D active-high

1101 = PWM mode; P1A, P1C active-high; P1B, P1D active-low

1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high

1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low

PIC16F610/616/16HV610/616

10.1 Capture Mode

In Capture mode, CCPR1H:CCPR1L captures the

16-bit val ue of the TMR1 register when an event occurs

on pin CCP1. An event is defined as one of the

following and is configured by the CCP1M<3:0> bits of

the CCP1CON register:

• Every falling edge

• Every rising edge

• Every 4th rising edge

• Every 16th rising edge

When a cap ture i s m ade, the I nterrupt Re quest Flag bit

CCP1IF of the PIR1 register is set. The interrupt flag

must be cleared in software. If another capture occurs

before the value in the CCPR1H, CCPR1L register pair

is read, the old captured value is overwritten by the new

captured value (see Figure 10-1).

10.1.1 CCP1 PIN CONFIGURATION

In Capture mode, the CCP1 pin should be configured

as an input by setting the associated TRIS control bit.

FIGURE 10-1: CAPTURE MODE

OPERATION BLOCK

DIAGRAM

10.1.2 TIMER1 MODE SELECTION

T imer1 must be running in T imer mode or Synchroni zed

Counter mode for the CCP module to use the capture

feature. In Asynchronous Counter mode, the capture

operation may not work.

10.1.3 SOFTWARE INTERRUPT

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep the

CCP1IE i nterrupt en able bit of the PIE1 regis ter clear to

avoid false interrupts. Additionally, the user should

clear the CCP1IF interrupt flag bit of the PIR1 register

following any change in operating mode.

10.1.4 CCP PRESCALER

There are four prescaler settings specified by the

CCP1M<3:0> bits of the CCP1CON register.

Whenever the CCP module is turned off, or the CCP

module is not in Capture mode, the prescaler counter

is cleared. Any Reset will clear the prescal er counter.

Switching from one capture prescaler to another does not

clear the prescaler and may generate a false interrupt. To

avoid this unexpected operation, turn the module off by

clearing the CCP1CON register before changing the

prescaler (see Example 10-1).

EXAMPLE 10-1: CHANGIN G BETWEEN

CAPTURE PRESCALERS

Note: If the C CP1 pin is con figured as an output ,

a write to the port can cause a capture

condition.

CCPR1H CCPR1L

TMR1H TMR1L

Set Flag bit CCP1IF

(PIR1 register )

Capture

Enable

CCP1CON<3:0>

Prescaler

÷ 1, 4, 16

and

Edge Detect

CCP1

System Clock (FOSC)

BANKSEL CCP1CON ;Set Bank bits to point

;to CCP1CON

CLRF CCP1CON ;Turn CCP module off

MOVLW NEW_CAPT_PS ;Load the W reg with

; the new prescaler

; move value and CCP ON

MOVWF CCP1CON ;Load CCP1CON with this

; value

PIC16F610/616/16HV610/616

TABLE 10-2: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE

Name Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

Value on

POR, BOR

Value on

all other

Resets

CCP1CON(1) P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000

CCPR1L(1) Captur e/Comp are/PWM Register 1 Low Byte xxxx xxxx uuuu uuuu

CCPR1H(1) Capture/Compare/PWM Register 1 High Byte xxxx xxxx uuuu uuuu

INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000

PIE1 —ADIE(1) CCP1IE(1) C2IE C1IE — TMR2IE(1) TMR1IE -000 0-00 0000 0-00

PIR1 —ADIF(1) CCP1IF(1) C2IF C1IF — TMR2IF(1) TMR1IF -000 0-00 0000 0-00

T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu

TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111

TRISC ——TRISC5TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111

Legend: – = Unimple mented locat ions, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Capture, Compare and PWM.

Note 1: PIC16F616/16HV616 only.

PIC16F610/616/16HV610/616

10.2 Comp are Mode

In C ompare mo de, t he 16- bit CC PR1 re gist er va lue is

constantly compared against the TMR1 register pair

value. When a match occurs, the CCP1 module may:

• Toggle the CCP1 output

• Set the CCP1 output

• Clear the CCP1 output

• Generate a Special Event Trigger

• Generate a Software Interrupt

The action on the pin is based on the value of the

CCP1M<3:0> control bits of the CCP1CON register.

All Compare modes can generate an interrupt.

FIGUR E 1 0-2: COM PARE MODE

OPERATION BLOCK

DIAGRAM

10.2.1 CCP1 PIN CONFIGURATION

The user m us t co nfi gure the C CP 1 pin a s an out put b y

clearing the associated TRIS bit.

10.2.2 TIMER1 MODE SELECTION

In Compare mode, Timer1 must be running in either

Timer mode or Synchronized Counter mode. The

compare operation may not work in Asynchronous

Counter mode.

10.2.3 SOFTWARE INTERRUPT MODE

When Generate Software Interrupt mode is chosen

(CCP1M<3:0> = 1010), the CCP1 module does not

assert control of the CCP1 pin (see the CCP1CON

10.2.4 SPECIAL EVENT TRIGGER

When Special Event Trigger mode is chosen

(CCP1M<3:0> = 1011), the CCP1 module does the

following:

• Resets Timer1

• Starts an ADC conversion if ADC is enabled

The CCP 1 module do es not assert co ntrol of the CC P1

pin in this mode (see the CCP1CON register).

The Special Event Trigger output of the CCP occurs

immediately upon a match between the TMR1H,

TMR1L register pair and the CCPR1H, CCPR1L

reset until th e next r ising ed ge of the T imer1 clock. This

allows the CCPR1H, CCPR1L register pair to

effectively provide a 16-bit programmable period

Note: Clearing the CCP1CON register will force

the CCP1 compare output latch to the

default lo w level. This is not the PO R T I/O

data l atch.

CCPR1H CCPR1L

TMR1H TMR1L

Comparator

ROutput

Logic

Specia l Event Trigger

Set CCP1IF Interrupt Flag

(PIR1)

Match

TRIS

CCP1CON<3:0>

Mode Select

Output Enable

Special Event Trigger will:

• Clear TMR1H and TMR1L registers.

• NOT set interrupt flag bit TMR1IF of the PIR1 register.

• Set the GO/DONE bit to start the ADC conversion.

CCP1 4

Note 1: The Special Event Trigger from the CCP

module does not set interrupt flag bit

TMR1IF of the PIR1 registe r.

2: Removing the match condition by

changing the contents of the CCPR1H

and CCPR1L register pair, between the

clock edge that generates the Special

Event Trigger and the clock edge that

generate s the T imer1 Reset, w ill preclud e

the Reset from occurring.

PIC16F610/616/16HV610/616

TABLE 10-3: SUMMARY OF REGISTERS ASSOCIATED WITH COMP ARE