CS44130-DNZR - Cirrus Logic, Inc.

http://www.cirrus.com

Advance Product Information This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.

60 W Quad Half-Bridge Digital Amplifier Power Stage

Features

Configurable Outputs (10% THD+N)

– 2 x 30 W into 8 Ω, Full-Bridge

– 1 x 60 W into 4 Ω, Parallel Full-Bridge

– 4 x 15 W into 4 Ω, Half-Bridge

– 2 x 15 W into 4 Ω, Half-Bridge + 1 x 30 W

into 8 Ω, Full-Bridge

Space-Efficient, Thermally-Enhanced QFN

Package

PWM Popguard® Technology for Quiet Startup

> 100 dB Dynamic Range - System Level

< 0.12% THD+N @ 1 W - System Level

Built-In Protection with Error Reporting

– Over-Current

– Thermal Warning

– Thermal Fault

– Under-Voltage

Single (+10.8 V to +21 V) High

Voltage Supply

High Efficiency (90%)

Low RDS(ON)

Low Quiescent Current

Low Power Standby Mode

Common Applications

Digital Televisions

MP3 Docking Stations

Mini Shelf Systems

Networked Audio/POE Systems

Desktop Speakers

Automotive Audio Systems

M[3:1] RST1/2LVDOCREF RAMP

Protection and Error Reporting

(Open Drain with Internal Pull-ups)

Contr ol Logic

ERROC3/4 ERRUVTE TWR

OUT[4:1]

PGND

Gate

Drivers

Level Shifters Non-Overlap

Time Insertion

IN[4:1]

GND

RST3/4 ERROC1/2

APRIL '06

DS690A2

CS44130

2DS690A2

CS44130

General Description

The CS44130 is a high-efficiency power stage for digital Class-D amplifiers designed to input PWM signals from a

modulator such as th e CS44800/6 00. The power stag e outputs ca n be configured a s four half-bridge channels, two

half-bridge channels and one full-bridge channel, two full-bridge channels, or one parallel full-bridge channel.

The CS44130 integrates on-chip over-current, under-voltage, over-temperature protection and error reporting as

well as a thermal warning indicator. The low RDS(ON) of the outputs allows the part to operate at up to 90% efficiency.

This efficiency provides for a smaller device package, no heat sink requirements, and smaller power supplies.

The CS44130 is available in a 48-pin QFN package for both Commercial grades(-10° to +70° C) and Automotive

grades (-40° to +85° C). The CRD44130-FB is also availa ble for device evaluation and implementatio n suggestions.

Please refer to “Ordering Information” on page 24 for complete ordering information.

DS690A2 3
CS44130
TABLE OF CONTENTS
1.  PIN DESCRIPTION  ............................................................................................................................... 4
1.1 I/O Pin Characteristics  ................................................................................................................... 6
2.  CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 7
SPECIFIED OPERATING CONDITIONS.............................................................................................. 7
ABSOLUTE MAXIMUM RATINGS........................................................................................................7
DC ELECTRICAL CHARACTERISTICS ...... .... ... ... ... .... ... ... ................... .................... ................... ........ 8
PWM OUTPUT CHARACTERISTICS................................................................................................... 9
DIGITAL INTERFACE CHARACTERISTICS ........................................................................................ 9
3.  TYPICAL CONNECTION DIAGRAMS   ..............................................................................................10
4.  APPLICATIONS  .................................................................................................................................. 14
4.1 Overview ................ ................ .... ... ... ... ... .... ... ................ ... .... ... ... ... ... ............................................. 14
4.2 Feature Set Summary  .................................................................................................................. 14
4.3 Output Mode Configuration  .......................................................................................................... 15
4.4 Output Filter .................. ... ... ................................................................................. ... ...................... 16
4.4.1 Half-Bridge Output Filter .................................................................................................. 16
4.4.2 Full-Bridge Output Filter (Stereo or Parallel) ........... ............ ............. ............. ............. ...... 17
4.5 Protection and Error Reporting ..................................................................................................... 18
4.5.1 Over-Current Protection ... ... ... ... .... ... ... .................... ... ................... ... .................... ... ... ...... 18
4.5.2 Under-Voltage and Thermal Protection  ........... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ......... 18
5.  RESET AND POWER-UP .................................................................................................................... 19
5.1 PWM Popguard Transient Control ... ... ... .... ... ... ... .................... ... ... ... .... ... ... ... .... ... ................... ...... 19
5.2 Recommended Power-Up Sequence ........................................................................................... 19
5.3 Recommended Power-Down Sequence ....................................................................................... 19
6.  POWER SUPPLY, GROUNDING, AND PCB LAYOUT ...................................................................... 20
7.  PARAMETER DEFINITIONS ............................................................................................................... 20
8.  PACKAGE DIMENSIONS    ................................................................................................................. 21
9.  THERMAL CHARACTERISTICS  ........................................................................................................ 22
9.1 Thermal Flag  ... ... ................ ... .... ... ... ... ... .... ... ................................................................................ 22
10.  ORDERING INFORMATION  ............................................................................................................. 24
11.  REFERENCES .. .... ... ... ... .... ... ... ... .................... ................... .................................... ............................ 24
12.  REVISION HISTORY ......................................................................................................................... 24
LIST OF FIGURES
Figure 1. Typical Connection Diagram - Stereo Full-Bridge.......................................................................10
Figure 2. Typical Connection Diagram - 2.1 Channels (2 x Half-Bridge + 1 x Full-Bridge)........................ 11
Figure 3. Typical Connection Diagram - 4-Channel Half-Bridge................................................................ 12
Figure 4. Typical Connection Diagram - Mono Parallel Full-Bridge ........................................................... 13
Figure 5. Output Filter - Half-Bridge........................................................................................................... 16
Figure 6. Output Filter - Full-Bridge............................................................................................................ 17
Figure 7. System qJA vs. Bottom-Side Thermal Flag Area........................................................................ 23
Figure 8. Maximum Power Output vs. Ambient Temperature.................................................................... 23
LIST OF TABLES
Table 1. Output Mode Configuration Options............................................................................................. 15
Table 2. Low-Pass Filter Components - Half-Bridge. ................................................................................. 16
Table 3. DC-Blocking Capacitors Values - Half-Bridge.............................................................................. 16
Table 4. Low-Pass Filter Components - Full-Bridge .. ... ... .... ................... ... ... .................... ... ...................... 17
Table 5. Over-Current Error Conditions..................................................................................................... 18
Table 6. Thermal and Under-Voltage Error Conditions.............................................................................. 18

4DS690A2

CS44130

1. PIN DESCRIPTION

Pin Name Pin # Pin Description

High Voltage Output Power (Input) - High voltage power supply for the individual output power

half-bridge devices.

PGND

3, 6

7, 10

13, 14

15, 16

43,45

46, 47,

Power Ground (Input) - Ground for the individual output power half-bridge devices. These pins

should be connected to the common system ground.

Thermal Pad

1413

15 16 17 18 19 20

424344

464748 37

3940

21 22 23 24

PGND

RST1/2

ERROC1/2

PGND

TWR

ERRUVTE

OCREF

OUT1

PGND

OUT2

PGND

OUT3

GND

IN1

GND

IN2

LVD

IN3

PGND

OUT4

GND

IN4

GND

ERROC3/4

RST3/4

RAMP

DS690A2 5
CS44130
VD 20, 25
28, 32
35 Core Logic Power (Input) - Low voltage power supply for internal logic.
VL 37 Control Interface and PWM Inpu t Power (Input) - Supply for the I/O.
GND
21
27
33
36
Ground (Input) - Ground for the internal logic and I/O.  These pins should be connected to the 
common system ground.
OUT1
OUT2
OUT3
OUT4
2
5
8
11
PWM Output (Output) - Amplified PWM power half-bridge outputs.
IN1
IN2
IN3
IN4
34
31
29
26
PWM Input (Input) - Inputs from a PWM modulator . These pins should not be left floating.
RST1/2
RST3/4 42
23 Reset Input (Input) - Reset inputs for channel 1, 2, 3, and 4; active low . These pins should not be 
left floating .
ERROC1/2
ERROC3/4 41
22 Over-Current Error Output (Output) - Over-current error flag for OUTx. Open drai n wi th  inte rnal  
pull-up, active low. See Protection and Error Reporting on page 18 for details.
ERRUVTE 18 Thermal and Under-Volt age Error Output (Output) - Error flag for thermal shutdown and under-
voltage. Open drain with internal pul l-up, active low. See Pro tec tio n an d Err or  Rep ortin g on  
page 18 for details.
TWR 17 Thermal W arning Output (Output) - Thermal warning output. Open drain with internal pull-up, 
active low. See Protection and Error Reporting on page 18 for details.
LVD 30 Input Voltage Level Select (Output) - Input voltage indicator of VD. A high level indicates VD is 
set to 5.0 V. A low level indicates VD is set to 3.3 V. This pins should not be left floating.
M1
M2
M3
40
39
38
Mode Select (Input) - Used to set the operating mode. See Output Mode Configuration on 
page 15 for details. These pins should not be left floating.
OCREF 19 Over-Current Reference (Input) - Over-current trip level setting. This pin should be connected 
through a 60 kΩ resistor to GND. See Protection and Erro r Reporting  on pa ge 1 8 for  de tails. 
This pins should not be left floating.
RAMP 24
Ramp-Up/Down Select (Input) - When set high, ramping is enabled. When set low , ramping is 
disabled. See PWM Popguard Transient Control on page 19 for details. This pin should not 
be left floating. Ramp should on ly be used in half bridge mode or in full bridge configuration 
modes 010 and 011.
Pin Name Pin # Pin Description

6DS690A2

CS44130

1.1 I/O Pin Characteristics

Signal Name Power Rail I/O Driver Receiver

OUT1 VP Output 10.8 V-21.0 V Power MOSFET -

OUT2 VP Output 10.8 V-21.0 V Power MOSFET -

OUT3 VP Output 10.8 V-21.0 V Power MOSFET -

OUT4 VP Output 10.8 V-21.0 V Power MOSFET -

IN1 VL Input - 2.5 V to 5.0 V Compatible.

IN2 VL Input - 2.5 V to 5.0 V Compatible.

IN3 VL Input - 2.5 V to 5.0 V Compatible.

IN4 VL Input - 2.5 V to 5.0 V Compatible.

RST1/2 VL Input - 2.5 V to 5.0 V Compatible.

RST3/4 VL Input - 2.5 V to 5.0 V Compatible.

ERROC1/2 VL Output Open Drain, Internal pull-up -

ERROC3/4 VL Output Open Drain, Internal pull-up -

ERRUVTE VL Output Open Drain, Internal pull-up -

TWR VL Output Open Drain, Internal pull-up -

LVD VL Input - 2.5 V to 5.0 V Compatible.

RAMP VL Input - 2.5 V to 5.0 V Compatible.

M1 VL Input - 2.5 V to 5.0 V Compatible.

M2 VL Input - 2.5 V to 5.0 V Compatible.

M3 VL Input - 2.5 V to 5.0 V Compatible.

All input pins should be connected and not left floating.

DS690A2 7

CS44130

2. CHARACTERISTICS AND SPECIFICATIONS

(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical

performance characteristics and specifications are derived from measurements taken at nominal supply voltages

and TA = 25°C.)

SPECIFIED OPERATING CONDITIONS

(GND/PGND = 0 V, all voltages with respect to ground, unless otherwise specified)

ABSOLUTE MAXIMUM RATINGS

WARNING:Operatio n at or beyond these limits may result in permanent damage to the device. Normal operation

is not guaranteed at these extremes.

(GND/PGND = 0 V; all voltages with respect to ground.)

Notes:

1. Any pin except supplies. Transient currents of up to ±100 mA on the input pins will not cause SCR latch-up.

2. The maximum over/under-voltage is limited by the input current.

Parameter Symbol Min Typ Max Units

DC Power Supply

PWM Outputs Power Stage Supply VP 10.8 - 21.0 V

Core Logic 3.3 V

5.0 V VD 3.14

4.75 3.3

5.0 3.47

5.25 V

Control Interface and PWM Inputs 2.5 V

3.3 V

5.0 V VL 2.37

3.14

4.75

2.5

3.3

5.0

2.63

3.47

5.25

Ambient Operating Temperature

Commercial -CNZ

Automotive -DNZ TA-10

-40 -

-+70

+85 °C

°C

Junction Temperature TJ-+150°C

Parameters Symbol Min Max Units

DC Power Supply PWM Outputs

Core Logic

Control Interface and PWM Inputs

-0.3

23.0

7.0

Input Current (Note 1) Iin -±10mA

Digital Input Voltage (Note 2) VIN -0.4 VL+0.4 V

Ambient Operating Temperature Commercial

(power applied) Automotive TA-20

-50 +85

+95 °C

°C

Storage Temperature Tstg -65 +150 °C

8DS690A2

CS44130

DC ELECTRICAL CHARACTERISTICS

(GND/PGND = 0 V, all voltages with respect to ground; PWM Switch Rate = 384 kHz unless otherwise specified.)

3. Normal operation is defined with RSTx/y = HI.

4. Current consumption increases with increasing PWM switch rates.

5. Power-Down Mode is defined as RSTx/y = LOW with all input lines held static.

Parameter Symbol Min Typ Max Units

Normal Operation (Note 3)

Power Supply Current (Note 4) VL = 2.5 V

VL = 3.3 V

VL = 5.0 V

VD = 3.3 V

VD = 5.0 V

4.0

5.28

264

400

Power Dissipation (Ptotal = Pdl + Pdd)VL = 2.5 V

VL = 3.3 V

VL = 5.0 V

VD = 3.3 V

VD = 5.0 V

Pdl

Pdd

17.42

.87

Power-Down Mode (Note 5)

Power Supply Current VL = 2.5 V

VL = 3.3 V

VL = 5.0 V

VD = 3.3 V

VD = 5.0 V

.75

.99

1.5

46.2

DS690A2 9

CS44130

PWM OUTPUT CHARACTERISTICS

(Unless otherwise noted: GND/PGND = 0 V, all voltages with respect to ground, VP = 21 V, RL = 8 Ω in Full-Bridge

Mode, RL = 4 Ω in Half-Bridge Mode, PWM Switch Rate = 384 kHz, Modulation Index = 0.88; Measurement band-

width is 10 Hz to 20 kHz; Performance measurements taken with a full scale 997 Hz and AES17 filter.)

DIGITAL INTERFACE CHARACTERISTICS

(GND/PGND = 0 V, all voltages with respect to ground)

Parameters Symbol Conditions Min Typ Max Units

Power Output per Channel Half-Bridge

Full-Bridge

Parallel Full-Bridge

THD+N =10%, RL = 4 Ω

THD+N =1%, RL = 4 Ω

THD+N = 10%, RL = 8 Ω

THD+N = 1%, RL = 8 Ω

THD+N = 10%, RL = 4 Ω

THD+N = 1%, RL = 4 Ω

Total Harmonic Distortion + Noise

Half-Bridge

Full-Bridge

Parallel Full-Bridge

THD+N

PO = 1 W

PO =7.8 W (0 dBFS)

PO = 1 W

PO = 15.9 W (0 dBFS)

PO = 1 W

PO = 30.8 W (0 dBFS)

.20

.35

.12

.19

.14

.29

Dynamic Range Half-Bridge

Full-Bridge

Parallel Full-Bridge DR

PO = -60 dBFS, A-Weighted

PO = -60 dBFS, Unweighted

PO = -60 dBFS, A-Weighted

PO = -60 dBFS, Unweighted

PO = -60 dBFS, A-Weighted

PO = -60 dBFS, Unweighted

102

107

105

102

MOSFET On Resistance RDS(ON) Id = 0.5 A - 350 450 mΩ

Efficiency (Full Bridge) h0dBFS P

O = 2 x 24 W - 90 - %

Minimum Output Pulse Width PWmin No Load - 60 - ns

Rise Time of OUTx trResistive Load - 20 - ns

Fall Time of OUTx tfResistive Load - 20 - ns

Junction Therm al Warning Trip Point TTW -125-°C

Junction Over te mpe r at ur e Trip Point TOT -150-°C

VP Under-voltage Tr ip Point VUV TA = 25°C-6-V

Ramp Up Time (Half-Bridge Mode) TRU DC Blocking Cap = 1000 µF - 1.5 - s

Ramp Down Time (Half-Bridge Mode) TRD DC Blocking Cap = 1000 µF - 50 - s

Parameters Symbol Min Typ Max Units

High-Level Input Voltage ( % of VL) VIH 70% - - V

Low-Level Input Voltage (% of VL) VIL --30%V

Low-Level Output Voltage at Io=2 mA (% of VL) VOL --20%V

Input Leakage Current Iin --±10µA

Input Capacitance --8pF

10 DS690A2

CS44130

3. TYPICAL CONNECTION DIAGRAMS

VD VP

0.1 µF

OUT1

PGND

OUT2

PGND

0.1 µF470 µF

OUT3

PGND

OUT4

PGND

0.1 µF470 µF

VD VD VDVD

GND GND GND GND GND

0.1 µF

Output

Filter

Output

Filter

Output

Filter

Output

Filter

VD (+3.3 V or +5.0 V)

VL (+2.5 V, +3.3 V, or +5.0 V)

0.1 µF (X5)

0.1 µF

47 µF

IN1

IN2

IN3

ERROC1/2

60K

RST3/4

RST1/2

IN4

ERROC3/4

ERRUVTE

LVD

RAMP

OCREF

Hardware

Control

Settings

System

Control

Logic

TWR

PWM1+

PWM3+

PWM2+

PWM4+

Figure 1. Typical Connection Diagram - Stereo Full-Bridge

CS44130

VP (+10.8 V to +21 V)

DS690A2 11

CS44130

VD VP

IN1

IN2

IN3

ERROC1/2

VD (+3.3 V or +5.0 V)

0.1 µF

RST3/4

RST1/2

IN4

ERROC3/4

ERRUVTE

LVD

RAMP

OCREF

OUT1

PGND

470 µF

Output

Filter

OUT2

PGND

470 µF

Output

Filter

OUT3

PGND

OUT4

PGND

VL (+2.5 V, +3.3 V, or +5.0 V)

VD VD VD

Hardware

Control

Settings

System

Control

Logic

0.1 µF (X5)

0.1 µF

GND GND GND GND GND

47 µF

TWR

PWM1+

PWM3+

PWM2+

PWM4+

0.1 µF

0.1 µF470 µF

0.1 µF

Output

Filter

Output

Filter

60K

Figure 2. Typical Connection Diag ram - 2.1 Channels (2 x Half-Bridge + 1 x Full-Bridge )

CS44130

VP (+10.8 V to +21 V)

12 DS690A2

CS44130

VD VP

IN1

IN2

IN3

ERROC1/2

VD (+3.3 V or +5.0 V)

0.1 µF

RST3/4

RST1/2

IN4

ERROC3/4

ERRUVTE

LVD

RAMP

OCREF

OUT1

PGND

470 µF

Output

Filter

OUT2

PGND

470 µF

Output

Filter

OUT3

PGND

470 µF

Output

Filter

OUT4

PGND

470 µF

Output

Filter

VL (+2.5 V, +3.3 V, or +5.0 V)

VD VD VD

Hardware

Control

Settings

System

Control

Logic

0.1 µF (X5)

0.1 µF

GND GND GND GND GND

47 µF

TWR

PWM1+

PWM3+

PWM2+

PWM4+

0.1 µF

60K

Figure 3. Typical Connection Diagram - 4-Channel Half-Bridge

CS44130

VP (+10.8 V to +21 V)

DS690A2 13

CS44130

VD VP

OUT1

PGND

OUT2

PGND

0.1 µF470 µF

OUT3

PGND

OUT4

PGND

0.1 µF

VD VD VDVD

GND GND GND GND GND

0.1 µF

Output

Filter

Output

Filter

VD (+3.3 V or +5.0 V)

0.1 µF

VL (+2.5 V, +3.3 V, or +5.0 V)

0.1 µF (X5)

0.1 µF

47 µF

IN1

IN2

IN3

ERROC1/2

60K

RST3/4

RST1/2

IN4

ERROC3/4

ERRUVTE

LVD

RAMP

OCREF

Hardware

Control

Settings

System

Control

Logic

TWR

PWM1+

PWM3+

PWM2+

PWM4+

Figure 4. Typical Connection Diagram - Mono Parallel Full-Bridge

CS44130

VP (+10.8 V to +21 V)

14 DS690A2

CS44130

4. APPLICATIONS

4.1 Overview

The CS44130 is a high-e fficiency power stage for digital Class-D amplifiers. It has been desig ned to be con-

figured as four half-bridge channels, two half-bridge channels and one full-bridge channel, two full-bridge

channels, or one parallel full-bridge channel.

The CS44130 integr ates on-chip over-current, under-voltage , and over-temperature protection an d error re-

porting as well as a therma l warning indicator.The low RDS(ON) of the outputs allows the part to operate at

up to 90% efficiency. This efficie ncy provides for a smaller device package, no heat sink req uirements, and

smaller power supplies.

The CS44130 is ideal for digital audio systems requiring space-efficient, high quality audio, such as Digital

Televisions, MP3 Docking Stations, Mini Shelf Systems, Desktop Speakers, Automotive Audio Systems.

4.2 Feature Set Summary

• VD voltage pins for internal core logic levels between 3.3 V and 5.0 V.

• VL voltage pin for PWM input, mode configuration, and error reporting logic levels between 2.5 V and

5.0 V.

• VP voltage pin for PWM output levels between +10.8 V and +21 V.

• Over-curr ent (progra mmable trip po int), Un der-vol tage, and Thermal Overload Protection an d Error Re-

porting.

• PWM Popguard for Quiet Startup. (Valid for Half Bridge configurations only.)

DS690A2 15

CS44130

4.3 Output Mode Configuration

The CS44130 can be configured for several modes of operation. Table 1 shows the setting of the M[3:1]

inputs and the cor responding mode of operat ion. These pins should remain static during operation (RSTx/y

set high).

M3 M2 M1 Output Mode Description

0 0 0 Auto-Reset When an error cond ition o ccurs on a channe l, tha t chann el is auto -r eset until

the error condition is removed.

IN1 must be inverted from IN2 for full-bridge operation.

IN3 must be inverted from IN4 for full-bridge operation.

0 0 1 Latched Shutdown When an error condition occurs on a channel, that channel is shutdown until

the error condition is removed and the channel reset is toggled.

IN1 must be inverted from IN2 for full-bridge operation.

IN3 must be inverted from IN4 for full-bridge operation.

0 1 0 Auto-Reset with

Inversion This mode should only be used for full-bridge applications.

When an error condition o ccurs on a chan ne l, tha t channel is au to -reset un til

the error condition is removed.

IN2 is internally inverted for the seco nd half-bridge.1

IN4 is internally inverted for the seco nd half-bridge.1

1. In modes 010 and 011, IN1 should be connected to IN2 (external to the chip) an d driven with a single

PWM signal. Likewise, in these same modes, IN3 should be connected to IN4 (external to the chip) and

driven with a single PWM signal.

0 1 1 Latched Shutdown

with Inversion This mode should only be used for full-bridge applications.

When an error condition occurs on a channel, that channel is shutdown until

the error condition is removed and the channel reset is toggled.

IN2 is internally inverted for the seco nd half-bridge.1

IN4 is internally inverted for the seco nd half-bridge.1

1 x x Reserved This setting is reserved and should not be used.

Table 1. Output Mode Configuration Options

16 DS690A2

CS44130

4.4 Output Filter

The RC filter placed after the PWM outputs can greatly affect the output performance. The filter not only

reduces radiated EMI (snubber filter) but also filters high-frequency content from the switching output before

going to the speake r (lo w-p a ss filte r) .

4.4.1 Half-Bridge Output Filter

Figure 5 shows the output filter for a half-bridge configuration. The transient-voltage suppression circuit,

(snubber circuit) is comprised of a r esistor (5.6 Ω, 1/8 W) and capacitor (560 pF) and should be placed as

close as possible to the corresponding PWM output pin. This will greatly reduce radiated EMI.

The inductor, L1, and ca pacitor, C1, com prise the lo w-pass filter . Along with the no minal load impedance

of the speaker, these values set the cutoff frequency o f the filter. Table 2 shows the component va lues for

L1 and C1 based on nominal speaker (load) impedance for a corner frequency (-3 dB point) of approxi-

mately 35 kHz.

C2 is the DC-blocking capacitor. Table 3 shows the component values for C2 based corner frequency (-

3 dB point) and a nominal spea ker (load) impedance of 4 Ω. This capacitor should also be ch osen to have

a ripple current rating above the amount of current that will pass through it.

Load L1 C1

4Ω22 µH 1.0 µF

6Ω33 µH 0.68 µF

8Ω47 µH 0.47 µF

Table 2. Low-Pass Filter Components - Half-Bridge

Corner Frequency C2

36 Hz 1000 µF

54 Hz 680 µF

110 Hz 330 µF

Table 3. DC-B locking Capacitors Values - Half-Bridge

Figure 5. Ou tput Filter - Half-Bridge

PWM

Output

560 pF C1

5.6 Ω

L1 C2

*Diode is Zetex

ZHC S400 or

equivalent

DS690A2 17

CS44130

4.4.2 Full-Bridge Output Filter (Stereo or Parallel)

Figure 6 shows the output filter for a full-bridge configuration. The snubber resistor (20 Ω, 1/10 W) and

capacitor (330 pF), as well as the diodes, should be placed as close as possible to the corresponding

PWM output pins. This will greatly reduce radiated EMI. The inductors, L1 and L2, and capacitor, C1, com-

prise the low-pass filter. Along with the nominal load impedance of the speaker, these values set the cutoff

frequency of the filte r. Table 4 shows the component va lues based on nominal speaker ( load) impedance

for a corner frequency (-3 dB point) of approximately 35 kHz.

Load L1 & L2 C1

4Ω10 µH 1.0 µF

6Ω15 µH 0.47 µF

8Ω22 µH 0.47 µF

Table 4. Low-Pass Filter Components - Full-Bridge

Figure 6. Output Filter - Full-Bridge

330 pF

20 Ω

*Diode is Zetex

ZHCS400 or

equivalent

+ PWM

Output

- PWM

Output

18 DS690A2

CS44130

4.5 Protection and Error Reporting

The CS44130 has built-i n protection circuitry for over-c urrent, under-vo ltage, and thermal warn ing/overload

conditions. All error outputs are open -drai n, active l ow, and ca n safely be tie d together in any comb ination.

These pins also have internal pull- up resistors, alleviating the need for external resistors.

4.5.1 Over-Current Protection

Over-current errors are reported on the ERROCx/y pins (example: ov er -c ur re nt err or on OUT 1 wou ld be

reported on ERROC1/2). The over-current error is designe d to go low for conditions that could potentially

damage the part. In order for ERROCx /y to go low only under conditions that could damage the par t, it is

recommended that a 60 kΩ resistor be connected from the OCREF pin to ground. If the part has been

configured for latched shutdown, as specified in Table 1 on page 15, the channel which is reporting the

over-current condition will be shut down (OUTx set to HI-Z) until the error condition has been removed

and the RSTx/y for that channel has been cycled from low to high.

If the part has been configured for auto-reset, as specified in Table 1 on page 15, the channel which is

reporting the over-current condition will be shut down (OUTx set to HI-Z). After approximately 85 millisec-

onds, the part will try to re-enable the outputs. If the fault has been cleared, the unit will return to normal

operation. If the fault is still present, the outputs will remain disabled and the part will try again in approx-

imately 85 milliseconds. After 5 unsuccessful attempts, the outputs will latch in the off (OUTx set to HI-Z)

condition and wait for RSTx/y to be reset.

4.5.2 Under-Voltage and Thermal Protection

Table 6 shows the behavior of the TWR and ERRUVTE pins. When the junction temperature exceeds the

Junction Thermal Warning Trip Point (TTW, as specified in the “PWM Output Characteristics” on pag e 9),

the TWR pin will be set low. If the junction temperature continues to increase beyond the Junction Over-

temperature Trip Point (TOT, as specified in the “P WM Output Characteristics” on p age 9), the ERRUVTE

pin will be set low. If the voltage on VP falls below the VP Under-voltage Trip Point (VUV, as specified in

the “PWM Output Characteristics” on page 9), ERRUVTE will be set low.

If the part has been configured for auto-reset, as specified in Table 1 on page 15, the channel which is

reporting the over-current condition will be shut down (OUTx set to HI-Z). After approximately 85 millisec-

onds, the part will try to re-enable the outputs. If the fault has been cleared, the unit will return to normal

operation. If the fault is still present, the outputs will remain disabled and the part will try again in approx-

imately 85 milliseconds. After 5 unsuccessful attempts, the outputs will latch in the off (OUTx set to HI-Z)

condition and wait for RSTx/y to be reset.

ERROCx/y Error Condition

0Over-current error on channel x or channel y

1Normal operation

Table 5. Over-Current Error Conditions

TWR ERRUVTE Error Condition

0 0 Thermal warning and thermal error and/or under-voltage error.

0 1 Thermal warning only.

1 0 Un de r- vo ltage erro r.

1 1 Normal operation.

Table 6. Thermal and Under-Voltage Error Conditions

DS690A2 19

CS44130

5. RESET AND POWER-UP

Reliable power- up can be accomplished by keeping the device in reset until the power supplies, clocks, and

configuration pins ar e stable. It is also recommended that the RSTx/y pin be activated if the voltage supplies

drop below the recommended operating condition to prevent power-glitch- related issues.

When RSTx/y is low, the corresponding channels of the CS44130 enter a low-power mode and all internal

states are reset and the outputs are set to HI-Z. When RSTx/y is high, the desired mode settings will be

loaded and the outputs will begin normal operation.

5.1 PWM Popguard Transient Control

The CS44130 uses Popguard® technology to minimize the effects of output transients during power-up

and power-down for half-bridge configurations. This technique reduces the audio transients commonly

produced by half-bridge, single-supply amplifiers when implemented with external DC-blocking capacitors

connected in series with the audio outputs.

When the device is configured for ramping (RAMP set high) and RSTx/y is set high and the inputs are

pulsed, the OUTx output will ramp-up to the bias point (VP/2). This gradual voltage ramping allows time

for the external DC-blocking capacitor to charge to the quiescent voltage, minimizing the power-up tran-

sient. The OUTx output will not begin normal operation until the ramp has reached the bias point. The INx

input must begin switching before the ramp cycle begins.

When the device is configured for ramping (RAMP set high) and RSTx/y is set low, the OUTx output will

begin to slowly ramp d own from the bias point to PGND, allowing the DC-blocking capacitor to discharge.

It is not necessary to complete a ramp up/down sequence before ramping up/down again. PWM Popguard

should only be used in Half Bridge configurations.

5.2 Recommended Power-Up Sequence

1. Turn on the system power.

2. Hold RSTx/y low until the power supply and system clocks are stable. In this state, all associated

outputs are HI-Z.

3. Start the PWM modulator output.

4. Once the PWM modulator output is valid, release RSTx/y high. If the CS44130 is configured for

ramping, the outputs will ramp to the bias point and then begin switching normally. If the CS44130 is

not configured for ramping, the outputs will immediately begin switching normally.

5.3 Recommended Power-Down Sequence

1. Set RSTx/y low. If the CS44130 is configured for ramping, the outputs will ramp down to PGND and

then become HI-Z. If the CS44130 is not configured for ramping, the outputs will immediately become

HI-Z.

2. Power-d o wn th e re ma in de r of the system.

3. Turn off the system power.

20 DS690A2

CS44130

6. POWER SUPPLY, GROUNDING, AND PCB LAYOUT

The CS44130 require s a 3.3 V or 5.0 V digital power supply for the core logic. In orde r to support a number of PWM

backend solutions, a separate VL po wer pin is pr ovided to cond ition the interface signals to su pport up to 5.0 V lev-

els. The VL power pins control the voltage levels fo r all PWM input, mode, and error reporting signals.

Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling capac-

itors are recommended. It is necessary to decouple the power supply by placing capacitors directly between the

power and ground of the CS44130. The recommended procedure is to place a 0.1 µF capacitor as close as physi-

cally possible to each power pin. Decoupling capacitors should be as near to the pins of the CS44130 as possible,

with the low value ceramic capacitor being the nearest and should be mounted on the same side of the board as the

CS44130 to minimize inductance effects

7. PARAMETER DEFINITIONS

Dynamic Range (DR)

The ratio of the rm s value of the sig nal to the rms sum of all other spectral components over the specified

bandwidth, typically 20 Hz to 20 kHz. Dynamic Range is a signal-to-noise ratio measurement over the spec-

ified band w idth made with a - 60 dBFS s ignal. 60 dB is then a dded to the resu lting measurement to refer

the measurement to full-scale, with units in dBFS. These measurement can be made “weighted” or “un-

weighted”. The weigh ting that was used du ring for the test is usually indicated by a letter following the units.

For instance, “dBFS A” would indicate that an A-weighted filter was used during testing.

This technique ensures th at the distortion co mponents are below the noise level and do not effect the mea-

surement. This measurement technique has been accepted by the Audio Engineering Society, AES17-

1991, and the Electronic Industries Association of Japan, EIAJ CP-307.

Frequency Response (FR)

FR is the deviation in sign al level ver sus frequ enc y. The 0 dB re fere nce po int is 1 kHz. The amplit ude cor-

ner, Ac, lists the maximum deviation in amplitude above and below the 1 kHz reference point. The listed

minimum and maximum frequencies are guaranteed to be within the AC from minimum frequency to maxi-

mum frequency inclusive.

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the converter's

output with no signal to the input under test and a full-scale signal applied to the other channel. Units in deci-

bels.

FFT

Fast Fourier Transform.

Sampling Frequency.

Signal to Noise Ratio (SNR)

SNR, similar to DR, is the ratio of an arbitrary sinusoidal input signal to the RMS sum of the noise floor, in

the presence of a signal. It is measured over a 20 Hz to 20 kHz bandwidth with units in dB.

Total Harmonic Distortion + Noise (THD+N)

The ratio of the rms va lue of the signa l to the rms sum of all other spectral components over the specified

band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in %.

DS690A2 21

CS44130

8. PACKAGE DIMENSIONS

Notes: 1. Dimensioning and tolerance per ASME Y4.5M - 1994.

2. Dimensioning lead width applies to the plated terminal and is measured between 0.20 mm and 0.25 mm

from the terminal tip.

INCHES MILLIMETERS NOT

DIM MIN NOM MAX MIN NOM MAX

A -- -- 0.0354 -- -- 0.90 1

A1 0.0000 -- 0.0020 0.00 -- 0.05 1

b 0.0118 0.0138 0.0157 0.30 0.35 0.40 1,2

D 0.3543 BSC 9.00 BSC 1

D2 0.2618 0.2677 0.2736 6.65 6.80 6.95 1

E 0.3543 BSC 9.00 BSC 1

E2 0.2618 0.2677 0.2736 6.65 6.80 6.95 1

e 0.0256 BSC 0.65 BSC 1

L 0.0177 0.0217 0.0276 0.45 0.55 0.70 1

JEDEC #: MO-220

Controlling Dimension is Millimeters.

Side View

Bottom View

Top View

Pin #1 ID

bePin #1 ID

48L QFN (9 × 9 MM BODY) PACKAGE DRAWING

22 DS690A2

CS44130

9. THERMAL CHARACTERISTICS

1. θJA is stated for a system with a thermal flag as described in Section 9.1 below.

9.1 Thermal Flag

This device is designed to have th e metal flag on the bottom of the device soldered directly to a metal plane on the

PCB. To enhance the thermal dissipation capabilities of the system, this metal plane should be coupled with vias to

a large metal plane on the backside (and inner ground layer, if applicable) of the PCB.

In either case, it is beneficial to use copper fill in any unused regions inside the PCB layout, especially those imme-

diately surrounding the CS44130. In addition to the electrical performance gains that this practice provides, it also

aids in heat dissipation.

With a top-side metal flag of 7 x 7 mm, and a bottom side metal flag centered under the part connected to the top-

side flag through vias with a diameter of 0.3 mm in a 5 x 5 mm array spaced 1.2 mm center-to-center; the system’s

θJA for a 2-layer board (2 oz copper) and a 4-layer board (2 oz copper top and bottom layers,1 oz copper interior

layers) are shown in Figure 7.

The heat dissipation capability required of the metal plane for a given output power can be calculated as follows:

TCA = [(TJ(MAX) - TA) / PD] - θJC

where,

TCA = Thermal resistance of the metal plane in °C/Watt

TJ(MAX) = Maximum rated operating junction temperature in °C, eq ual to 150 °C

TA = Ambient temperature in °C

PD = RMS power dissipati on of the device, equal to 0.10*PRMS (assuming 90% efficiency)

θJC = Junction-to-case thermal resistance of the device in °C/Watt

For the recommended configuration as described for Figure 7, the maximum power output is shown as a function

of maximum ambient temperature, TA(MAX) in Figure 8 for a 2-layer board with a θJA = 20 °C/W, and a 4-layer

board with a θJA =18.5°C/W.

For both Figure 7 and Figure 8, the simulations that were used to model the system estimated a 20% trace/pour

coverage in the ar ea imm edi at ely surr ou n ding th e CS4 4 130. Thermal performance will increase noticeably if

higher trace/pour coverage can be achieved.

Parameter Symbol Min Typ Max Units

Junction to Case Thermal Impedance θJC -1-°C/Watt

Junction to Ambient Thermal Impedance (Note 1) 2-Layer PCB

4-Layer PCB θJA -

-20

18.5 -

-°C/Watt

DS690A2 23

CS44130

18.0

19.0

20.0

21.0

22.0

23.0

24.0

25.0

25.0 20.3 15.2 10.2 5.3 2.6

Flag Area [cm2]

4ja [°C/W]

2 Layer PCB

4 Layer PCB

Figure 7. System θJA vs. Bottom-Side Thermal Flag Area

15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90

Ta, Ambient Temp [°C]

Max Power Out [W

rms

]

4 Layer PCB

= 18.5 [°C/W])

2 Layer PCB

= 20 [°C/W])

Figure 8. Maximum Power Output vs. Ambient Temperature

24 DS690A2
CS44130
10.ORDERING INFORMATION
11.REFERENCES
1. Cirrus Logic, AN018: Layout and Design Rules for Data Converters and Other Mixed Signal Devices,
Version 6.0, February 1998.
12.REVISION HISTORY
Product Description Package Pb-
Free Grade Temp 
Range Container Order#
CS44130 Quad Half-Bridge 
Digital Amplifier 
Power Stage 48-QFN Yes
Commercial -10° to 
+70°C
Rail CS44130-CNZ
Tape and 
Reel CS44130-CNZR
Automotive -40° to 
+85°C
Rail CS44130-DNZ
Tape and 
Reel CS44130-DNZR
CRD44130-FB 20 W x 2 + 40 W x 1 
Reference Design - - - - - CRD44130-FB
Release Date Changes
A1 September 2005 Initial Advance Release
A2 April 2006
2nd Advance Release
-Updated “Features” on page 1
-Updated “Specified Operating Conditions” on page 7
-Updated “Absolute Maximum Ratings” on page 7
-Updated “PWM Output Characteristics” on page 9
-Updated “Protection and Error Reporting” on page 18
-Updated “Thermal Characteristics” on page 22

DS690A2 25

CS44130

Contacting Cirrus Logic Support

For all product questions and inquiries, contact a Cirrus Logic Sales Representative.

To find one nearest you, go to www.cirrus.com.

IMPORTANT NOTICE

"Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidia ries (" Cirrus" )

believe that the inform ation co ntained in this docu ment is accura te and reliable. Ho wever, the informa tion is subje ct to chan ge without notice an d is provided "AS IS"

without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that

information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment,

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