1White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
HI-RELIABILITY PRODUCT
WEDPF2M64-XBX3
2Mx64 3.3V Simultaneous Operation Multi-Chip Package
*Preliminary
FEATURES
■Access Times of 100, 120, 150ns
■Packaging
• 119 ball stacked TSOP BGA
■1,000,000 Erase/Program Cycles
■Sector Architecture
• One 16KByte, two 8KBytes, one 32KByte, and fifteen
64kBytes in byte mode
• Any combination of sectors can be concurrently erased.
Also supports full chip erase
■Organized as 2Mx64
■Commercial, Industrial and Military Temperature Ranges
■3.3 Volt for Read and Write Operations
■Simultaneous Read/Write Operation
• Data can be continuously read from one bank while
executing erase/program functions in other banks
■Embedded Erase and Program Algorithms
■Erase Suspend/Resume
• Supports reading data from or programing data to a
sector not being erased
■Data Polling and Toggle Bits
• Provides a software method of detecting the status of
program or erase cycles
■Unlock Bypass Program command
• Reduces overall programming time when issuing multiple
program command sequences
■Ready/Busy output (RY/BY)
• Hardware method for detecting program or erase cycle
completion
■Hardware reset pin (RESET)
• Hardware method of resetting the internal state machine
to the read mode
■WP/ACC input pin
• Write protect (WP#) function allows protection of two
outermost boot sectors, regardless of sector protect
status
•Acceleration (ACC) function accelerates program timing
■Sector Protection
• Hardware method of locking a sector, either in-system or
using programming equipment, to prevent any program or
erase operation within that sector
• Temporary Sector Unprotect allows changing data in
protected sectors in-system
Note: For programming information refer to Flash Programming
WEDPF2M64-XXX3 Application Note.
* Preliminary data sheet. This data sheet describes a product that
is not fully qualified or characterized and is subject to change
without notice.
February 2001 Rev. 0
Note: This data sheet describes a product that is not fully qualified or
characterized and is subject to change without notice.
2
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WEDPF2M64-XBX3
PIN CONFIGURATION FOR WF1M32B-XG2TX3
PIN DESCRIPTION
I/O0-31 Data Inputs/Outputs
A0-19 Address Inputs
WE1-4 Write Enables
CS1-4 Chip Selects
OE Output Enable
RESET Reset/Powerdown
VCC Power Supply
GND Ground
BLOCK DIAGRAM
2M x 16
I/O
0-15
1
2M x 16
I/O
16-31
2
2M x 16
I/O
32-47
3
2M x 16
I/O
48-63
CS
4
A
0
-
20
OE
RESET
RY/BY
1
CS
WE
CS
WE
2
CS
WE
3
WE
4
V
CC
WP/ACC
BYTE BYTE BYTE BYTE
123456789101112131415
A
B
C
D
E
F
G
H
A
2
A
1
DQ
57
DQ
48
DQ
35
DQ
34
DQ
4
DQ
32
DQ
19
DQ
18
DQ
24
CE
4
CE
2
A
A
5
A
4
A
3
DQ
5
DQ
56
DQ
43
DQ
42
DQ
41
DQ
33
DQ
27
DQ
26
DQ
17
CE
3
CE
1
OE
A
18
A
17
A
7
A
6
DQ
49
V
CC
V
CC
V
CC
V
CC
V
CC
DQ
25
DQ
16
DQ DQ
8
DQ
1
A
21
RESET WE
1
RY/BY WP/AC V
CC
V
CC
V
CC
V
CC
V
CC
DQ
09
DQ
2
DQ
1
DQ
3
DQ
11
A
19
A
20
A
08
A
09
DQ
61
V
SS
V
SS
V
SS
V
SS
V
SS
DQ
47
DQ
12
DQ
05
DQ
13
DQ
04
A
11
A
10
A
13
WE
4
DQ
53
V
SS
V
SS
V
SS
V
SS
V
SS
DQ
39
DQ
21
DQ
30
DQ
14
DQ
06
A
12
A
15
WE
2
DQ
51
DQ
52
DQ
62
DQ
63
DQ
44
DQ
37
DQ
38
DQ
20
DQ
29
DQ
23
DQ
15
DQ
07
A
14
WE
3
DQ
58
DQ
59
DQ
60
DQ
54
DQ
55
DQ
36
DQ
45
DQ
46
DQ
28
DQ
22
DQ
31
A
16
NC
TOP VIEW
3White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WEDPF2M64-XBX3
ABSOLUTE MAXIMUM RATINGS
NOTES:
1. Stresses above the absolute maximum rating may cause permanent damage
to the device. Extended operation at the maximum levels may degrade
performance and affect reliability.
Parameter Unit
Operating Temperature -55 to +125 °C
Supply Voltage Range (VCC) -0.5 to +4.0 V
Signal Voltage Range -0.5 to Vcc +0.5 V
Storage Temperature Range -65 to +150 °C
Lead Temperature (soldering, 10 seconds) +300 °C
Endurance (write/erase cycles) 1,000,000 min. cycles
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Max Unit
Supply Voltage VCC 3.0 3.6 V
Input High Voltage VIH 0.7 x Vcc VCC + 0.3 V
Input Low Voltage VIL -0.5 +0.8 V
Operating Temp. (Mil.) TA-55 +125 °C
Operating Temp. (Ind.) TA-40 +85 °C
CAPACITANCE
(TA = +25°C)
Parameter
Symbol
Conditions Max Unit
OE capacitance COE
V
IN
= 0 V, f = 1.0 MHz
50 pF
WE1-4 capacitance CWE
V
IN
= 0 V, f = 1.0 MHz
20 pF
CS1-4 capacitance CCS
V
IN
= 0 V, f = 1.0 MHz
20 pF
Data I/O capacitance CI/O
V
I/O
= 0 V, f = 1.0 MHz
20 pF
Address input capacitance CAD
V
IN
= 0 V, f = 1.0 MHz
50 pF
This parameter is guaranteed by design but not tested.
Parameter Symbol Conditions Min Typ Max Unit
Input Leakage Current ILI VCC = 3.6, VIN = GND or VCC 10 µA
Output Leakage Current ILOx32 VCC = 3.6, VIN = GND or VCC 10 µA
VCC Active Current for Read (1) ICC1 CS = VIL, OE = VIH, f = 5MHz 65 mA
VCC Active Current for Program or Erase (2) ICC2 CS = VIL, OE = VIH 120 mA
VCC Standby Current ICC3 VCC = 3.6, CS = VIH, f = 5MHz 20 mA
VCC Reset Current (2) ICC4 RESET = VSS ± 0.3V 1 20 mA
Automatic Sleep Mode (2,4) ICC5 VIH = VCC ± 0.3 V;
VIL = VSS ± 0.3 V 1 20 mA
VCC Active Read-While-Program ICC6
Current (1,2) CE = VIL, OE = VIH Word 86 180 mA
VCC Active Program-While-Erase ICC7
Current (1,2) CE = VIL, OE = VIH Word 85 180 mA
VCC Active Program-While-Erase-Suspended ICC8 ACC Pin
Current (2,5) CE = VIL, OE = VIH 70 140 mA
ACC Accelerated Program Current IACC
CE = VIL, OE = VIH 60 120 mA
Output Low Voltage VOLIOL = 5.8 mA, VCC = 3.0 0.45 V
Output High Voltage VOH1 IOH = -2.0 mA, VCC = 3.0 0.85 X VCC V
Low VCC Lock-Out Voltage (4) VLKO 2.3 2.5 V
DC CHARACTERISTICS - CMOS COMPATIBLE
(VCC = 3.3V, VSS = 0V, TA = -55°C to +125°C)
NOTES:
1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 5 MHz). The frequency component typically
is less than 8 mA/MHz, with OE at VIH.
2. ICC active while Embedded Algorithm (program or erase) is in progress.
3. DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V
4. Guaranteed by design, but not tested.
DATA RETENTION
Parameter Test Conditions Min Unit
Minimum Pattern Data 150°C 10 Years
Retention Time 125°C 20 Years
4
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WEDPF2M64-XBX3
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS,CS CONTROLLED
(VCC = 3.3V, VSS = 0V, TA = -55°C to +125°C)
Parameter Symbol -100 -120 -150 Unit
Min Max Min Max Min Max
Write Cycle Time tAVAV tWC 100 120 150 ns
Write Enable Setup Time tWLEL tWS 000ns
Chip Select Pulse Width tELEH tCP 45 50 50 ns
Address Setup Time tAVEL tAS 000ns
Data Setup Time tDVEH tDS 45 50 50 ns
Data Hold Time tEHDX tDH 000ns
Address Hold Time tELAX tAH 45 50 50 ns
Chip Select Pulse Width High tEHEL tCPH 20 20 20 ns
Duration of Byte Programming Operation (1) tWHWH1 300 300 300 µs
Sector Erase Time tWHWH2 15 15 15 sec
Read Recovery Time (2) tGHEL 000µs
Chip Programming Time 50 50 50 sec
1. Typical value for tWHWH1 is 9µs.
2. Guaranteed by design, but not tested.
AC TEST CIRCUIT AC TEST CONDITIONS
NOTES:
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75 Ω.
VZ is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
Parameter Typ Unit
Input Pulse Levels
VIL = 0, VIH = 2.5
V
Input Rise and Fall 5 ns
Input and Output Reference Level 1.5 V
Output Timing Reference Level 1.5 V
I
Current Source
D.U.T.
C = 50 pf
eff
I
OL
V
≈
1.5V
(Bipolar Supply)
Z
Current Source
OH
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WEDPF2M64-XBX3
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS - WE CONTROLLED
(VCC = 3.3V, TA = -55°C to +125°C)
Parameter Symbol -100 -120 -150 Unit
Min Max Min Max Min Max
Write Cycle Time tAVAV tWC 100 120 150 ns
Chip Select Setup Time tELWL tCS 000 ns
Write Enable Pulse Width tWLWH tWP 50 50 65 ns
Address Setup Time tAVWL tAS 000 ns
Data Setup Time tDVWH tDS 50 50 65 ns
Data Hold Time tWHDX tDH 000 ns
Address Hold Time tWLAX tAH 50 50 65 ns
Write Enable Pulse Width High tWHWL tWPH 30 30 35 ns
Duration of Byte Programming Operation (1) tWHWH1 300 300 300 µs
Sector Erase tWHWH2 15 15 15 sec
Read Recovery Time before Write (3) tGH
W
L000µs
VCC Setup Time tVCS 50 50 50 µs
Chip Programming Time 50 50 50 sec
Output Enable Setup Time tOES 000 ns
Output Enable Hold Time (2) tOEH 10 10 10 ns
Address Setup Time to OE# low during toggle bit polling tASO 715ns
Address Hold Time From CE# or OE# high
during toggle tAHT 000ns
Output Enable High during toggle bit polling tOEPH 20 20 20 ns
Latency Between Read and Write Operations tTS/W 000ns
Accelerated Programming Operation tWHWH1 444µs
Write Recovery Time from RY/BY# tRB 000ns
Program/Erase Valis to RY.BY# tBUSY 90 90 90 ns
1. Typical value for tWHWH1 is 9µs.
2. For Toggle and Data Polling.
3. Guaranteed by design, but not tested.
AC CHARACTERISTICS – READ-ONLY OPERATIONS
(VCC = 3.3V, TA = -55°C to +125°C)
Parameter Symbol -100 -120 -150 Unit
Min Max Min Max Min Max
Read Cycle Time tAVAV tRC 100 120 150 ns
Address Access Time tAVQV tACC 100 120 150 ns
Chip Select Access Time tELQV tCE 100 120 150 ns
Output Enable to Output Valid tGLQV tOE 40 50 55 ns
Chip Select High to Output High Z (1) tEHQZ tDF 30 30 40 ns
Output Enable High to Output High Z (1) tGHQZ tDF 30 30 40 ns
Output Hold from Addresses, CS or OE Change, tAXQX tOH 000ns
whichever is First
1. Guaranteed by design, not tested.
6
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WEDPF2M64-XBX3
AC WAVEFORMS FOR READ OPERATIONS
Addresses
CS
OE
WE
Outputs High Z
Addresses Stable
t
OE
t
RC
Output Valid
t
CE
t
ACC
t
OH
High Z
t
DF
RESET
RY/BY OV
fig3/waveforms.eps
7White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WEDPF2M64-XBX3
AC CHARACTERISTICS – HARDWARE RESET (RESET#)
Parameter Symbol -100 -120 -150 Unit
Min Max Min Max Min Max
RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note) tready 20 20 20 µs
RESET# Pin Low (NOT During Embedded Algorithms)
to Read Mode (See Note) tready 500 500 500 ns
RESET # Pulse Width tRP 500 500 500 ns
RESET High Time Before Read (See Note) tRH 50 50 50 ns
RESET # Low to Standby Mode tRPD 20 20 20 µs
RY/BY# Recovery Time tRB 000ns
Note: Not 100% tested.
RY/BY#
CE#, OE#
RESET#
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tRP
tReady
tRH
tReady
tRB
tRP
RY/BY#
CE#, OE#
RESET#
8
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WEDPF2M64-XBX3
NOTES:
1. PA is the address of the memory location to be programmed.
2. PD is the data to be programmed at byte address.
3. D7 is the output of the complement of the data written to each chip.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
WRITE/ERASE/PROGRAM
OPERATION, WE CONTROLLED
Addresses
CS
OE
WE
Data
AAAH PA PA
t
WC
t
CS
PD
D
7
D
OUT
t
AH
t
WPH
t
DH
t
DS
Data Polling
t
AS
t
RC
t
WP
A0H
t
OE
t
DF
t
OH
t
GHWL
t
WHWH1
RY/BY
trb
tbusy
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WEDPF2M64-XBX3
AC WAVEFORMS CHIP/SECTOR
ERASE OPERATIONS
NOTE:
1. SA is the sector address for Sector Erase.
10
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WEDPF2M64-XBX3
AC WAVEFORMS FOR DATA POLLING
DURING EMBEDDED ALGORITHM OPERATIONS
CE
OE
WE
Fig. 21 Data Polling Timings (During Embedded Algorithms)
RY/BY
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WEDPF2M64-XBX3
NOTES:
1. PA represents the address of the memory location to be programmed.
2. PD represents the data to be programmed at byte address.
3. D7 is the output of the complement of the data written to each chip.
4. DOUT is the output of the data written to the device.
5. Figure indicates the last two bus cycles of a four bus cycle sequence.
ALTERNATE CS CONTROLLED
PROGRAMMING OPERATION TIMINGS
12
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WEDPF2M64-XBX3
PACKAGE 509: 68 LEAD, LOW PROFILE CERAMIC QUAD FLAT PACK, CQFP (G2T)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
13 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WEDPF2M64-XBX3
PACKAGE 401: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
14
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WEDPF2M64-XBX3
ORDERING INFORMATION
PROGRAMMING VOLTAGE
3 = 3.3V
DEVICE GRADE:
M= Military Screened -55 °C to +125°C
I = Industrial -40°C to +85°C
C = Commercial 0°C to +70°C
PACKAGE TYPE:
B = 119 Stacked TSOP BGA
ACCESS TIME (ns)
IMPROVEMENT MARK
B = Boot Block (Bottom Sector)
ORGANIZATION, 2M x 64
User configurable as 2M x 32, 8 x 16 or 16M x 8
Flash
Plastic
WHITE ELECTRONIC DESIGNS CORP.
WED P F 2M64 B - XXX X B 3
