CD40175BCMX - Fairchild Semiconductor

October 1987

Revised July 1999

CD40174BC • CD40175BC Hex D-Type Flip-Flop • Quad D-Type Flip-Flop

CD40174BC • CD40175BC

Hex D-Type Flip-Flop • Quad D-Type Flip-Flop

General Descript ion

The CD4 01 74B C con si sts o f six positi ve- ed ge trig ger ed D -

type flip-flops; the true outputs from each flip-flo p are exter -

nally available. The CD40175BC consists of four positive-

edge tri ggered D- type flip-flo ps; both th e true an d comple-

me nt outputs from each flip-flop are externally available.

All flip-flo ps are controll ed by a common clock and a com -

mon clear. Information at the D inputs meeting the set-up

time requirements is transferred to the Q outputs on the

positive-g oing ed ge of the cl ock puls e. T he clea ri ng op er a-

tion, en abled by a ne gative pulse at Clear input, clears all

Q outputs to logical “0” and Q s (CD4017 5BC only) to logi-

cal “1”.

All inputs are protected from static discharge by diode

clamps to VDD and VSS.

Features

■Wide supply voltage range: 3V to 15V

■High noise immunity: 0.45 VDD (typ.)

■Low power TTL compatibility:

fan out of 2 driving 74L or 1 driving 74 LS

■Equivalent to MC14174B, MC14175B

■Equivalent to MM74C174, MM74C175

Ordering Code:

Devices also available in Tape and Reel. Spe ci fy by append ing the suffix let t er “X” to the o rdering c ode.

Connection Diagrams Pin Assignments for DIP and SOIC

CD40174B

Top View

CD40175B

Top View

Order Number Package Number Package Description

CD40174BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body

CD40174BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

CD40175BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body

CD40175BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

www.fairchildsemi.com 2

CD40174BC • CD40175BC

Truth Table

H = HIGH Level

L = LOW Lev el

X = Irrele v ant

↑ = Transition from LO W-to-HIGH lev el

NC = No change

Note 1: Q for CD40175B o nly

Inputs Outputs

Clear Clock D Q Q

(Note 1)

LXXLH

H↑HHL

H↑LLH

HHXNCNC

HLXNCNC

3 www.fairchildsemi.com

CD40174BC • CD40175BC

Absolute Maximum Ratings(Note 2)

(Note 3) Recommended Operating

Conditions (Note 3)

Note 2: “Absolute Maximum Ratings” are those values beyond which the

safety of the device cannot be guaranteed. They are not meant to imply

that the de vices shou ld be ope rated at the se limits. The tables of “R ecom-

mende d Operati ng C onditions ” and “Electric al C haracteri s tics ” provide con-

ditions f or actual device o peration .

Note 3: VSS = 0V unless ot herwise specified .

DC Electrical Characteristics (N ote 3)

CD40174B C/C D40175BC

Note 4: IOH and IOL are tes t ed one ou tp ut at a ti m e.

DC Supply Voltage (VDD)−0.5V to +18V

Input Voltage (VIN)−0.5V to VDD +0.5VDC

Stora ge Tem per atu re R ang e (TS)−65°C to +150°C

Power Di ssipa tion (P D)

Dual-In-Line 700 mW

Small Outline 500 mW

Lead Temperature (TL)

(Soldering, 10 seconds) 260°C

DC Supply Voltage (VDD) 3V to 15 VDC

Input Voltage (VIN) 0V to VDD VDC

Operating Temperature Range (TA)−40°C to +85°C

Symbol Parameter Conditions −40°C+25°C+85°CUnits

Min Max Min Typ Max Min Max

IDD Quiescent Device VDD = 5V, VIN = VDD or VSS 4430µA

Current VDD = 10V, VIN = VDD or VSS 8860µA

VDD = 15V, VIN = VDD or VSS 16 16 120 µA

VOL LOW Level VDD = 5V 0.05 0.05 0.05 V

Output Voltage VDD = 10V 0.05 0.05 0.05 V

VDD = 15V 0.05 0.05 0.05 V

VOH HIGH Level VDD = 5V 4.95 4.95 5 4.95 V

Output Voltage VDD = 10V 9.95 9.95 10 9.95 V

VDD = 15V 14.95 14.95 15 14.95 V

VIL LOW Level VDD = 5V, VO = 0.5V or 4.5V 1.5 1.5 1.5 V

Input Voltage VDD = 10V, VO = 1V or 9V 3.0 3.0 3.0 V

VDD = 15V, VO = 1.5V or 13.5V 4.0 4.0 4.0 V

VIH HIGH Level VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 3.5 V

Input Voltage VDD = 10V, VO = 1V or 9V 7.0 7.0 7.0 V

VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 11.0 V

IOL LOW Level Output VDD = 5V, VO = 0.4V 0.52 0.44 0.88 0.36 mA

Current (Note 4) VDD = 10V, VO = 0.5V 1.3 1.1 2.25 0.9 mA

VDD = 15V, VO = 1.5V 3.6 3.0 8.8 2.4 mA

IOH HIGH Level Output VDD = 5V, VO = 4.6V −0.52 −0.44 −0.88 −0.36 mA

Current (Note 4) VDD = 10V, VO = 9.5V −1.3 −1.1 −2.25 −0.9 mA

VDD = 15V, VO = 13.5V −3.6 −3.0 −8.8 −2.4 mA

IIN Input Current VDD = 15V, VIN = 0V −0.30 −10−5−0.30 −1.0 µA

VDD = 15V, VIN = 15V 0.30 10−50.30 1.0 µA

www.fairchildsemi.com 4

CD40174BC • CD40175BC

AC Electrical Characteristics (Note 5)

TA = 25°C, CL = 50 pF, RL = 200k and tr = tf = 20 ns, unless otherwise specified

Note 5: AC Pa ram eters ar e guarant eed by DC c orrelat ed testing.

Note 6: CPD determine s the no load AC po wer consu mption of any CMOS device. Fo r comple te explanat ion, see 74 C Family Characte ristics application

note, AN-90.

Symbol Parameter Conditions Min Typ Max Units

tPHL, tPLH Propagation Delay Time to a VDD = 5V 190 300 ns

Logical “0” or Logical “1” from VDD = 10V 75 110 ns

Clock to Q or Q (CD40175 Only) VDD = 15V 60 90 ns

tPHL Propagation Delay Time to a VDD = 5V 180 300 ns

Logical “0” from Clear to Q VDD = 10V 70 110 ns

VDD = 15V 60 90 ns

tPLH Propagation Delay Time to a Logical VDD = 5V 230 4 00 ns

“1” from Clear to Q (CD40175 Only) VDD = 10V 90 150 ns

VDD = 15V 75 120 ns

tSU Time Prior to Clock Pulse that VDD = 5V 45 100 ns

Data must be Present VDD = 10V 15 40 ns

VDD = 15V 13 35 ns

tHTime after Clock Pulse that VDD = 5V −11 0 ns

Data Must be Held VDD = 10V −40 ns

VDD = 15V −30 ns

tTHL, tTLH Transition Time VDD = 5V 100 200 ns

VDD = 10V 50 100 ns

VDD = 15V 40 80 ns

tWH, tWL Minimum Clock Pulse Width VDD = 5V 130 250 ns

VDD = 10V 45 100 ns

VDD = 15V 40 80 ns

tWL Minimum Clear Pulse Width VDD = 5V 120 250 ns

VDD = 10V 45 100 ns

VDD = 15V 40 80 ns

tRCL Maximum Clock Rise Time VDD = 5V 15 µs

VDD = 10V 5.0 µs

VDD = 15V 5.0 µs

tfCL Maximum Clock Fall Time VDD = 5V 15 50 µs

VDD = 10V 5.0 50 µs

VDD = 15V 5.0 50 µs

fCL Maximum Clock Frequency VDD = 5V 2.0 3.5 MHz

VDD = 10V 5.0 10 MHz

VDD = 15V 6.0 12 MHz

CIN Input Capacitance Clear Input 10 15 pF

Other Input 5.0 7.5 pF

CPD Power Dissipation Per Package (Note 6) 130 pF

5 www.fairchildsemi.com

CD40174BC • CD40175BC

Switching Time Waveforms

tr = tf = 20 ns

www.fairchildsemi.com 6

CD40174BC • CD40175BC

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body

Package Number M16A

7 www.fairchildsemi.com

CD40174BC • CD40175BC Hex D-Type Flip-Flop • Quad D-Type Flip-Flop

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N16E

Fairchild does not assume any responsibility for use of any circu itry described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syst ems are devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use pr ovi de d in the labe l ing, can be re a-

sonably expected to result in a significant injury to the

user.

2. A criti cal com ponen t in any compo nent o f a l ife supp ort

device or system whose failure to perform can be rea-

sonabl y e xpec ted to c ause th e fa i lure of the li fe s upp or t

device or system, or to affect its safety or effectiveness.