74VHC123A Dual Retriggerable Monostable Multivibrator
©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC123A Rev. 1.2 5
Functional Description
1. Stand-by State
The external capacitor (C
x
) is fully charged to V
CC
in
the Stand-by State. That means, before triggering,
the Q
P
and Q
N
transistors which are connected to the
R
x
/C
x
node are in the off state. Two comparators that
relate to the timing of the output pulse, and two refer-
ence voltage supplies turn off. The total supply cur-
rent is only leakage current.
2. Trigger Operation
Trigger operation is effective in any of the following
three cases. First, the condition where the A input is
LOW, and B input has a rising signal; second, where
the B input is HIGH, and the A input has a falling sig-
nal; and third, where the A input is LOW and the B
input is HIGH, and the CLR input has a rising signal.
After a trigger becomes effective, comparators C
1
and C
2
start operating, and Q
N
is turned on. The
external capacitor discharges through Q
N
. The volt-
age level at the R
x
/C
x
node drops. If the R
x
/C
x
volt-
age level falls to the internal reference voltage V
ref
L,
the output of C
1
becomes LOW. The flip-flop is then
reset and Q
N
turns off. At that moment C
1
stops but
C
2
continues operating.
After Q
N
turns off, the voltage at the R
x
/C
x
node
starts rising at a rate determined by the time constant
of external capacitor C
x
and resistor R
x
.
Upon triggering, output Q becomes HIGH, following
some delay time of the internal F/F and gates. It stays
HIGH even if the voltage of R
x
/C
x
changes from fall-
ing to rising. When R
x
/C
x
reaches the internal refer-
ence voltage V
ref
H, the output of C
2
becomes LOW,
the output Q goes LOW and C
2
stops its operation.
That means, after triggering, when the voltage level
of the R
x
/C
x
node reaches V
ref
H, the IC returns to its
MONOSTABLE state.
With large values of C
x
and R
x
, and ignoring the dis-
charge time of the capacitor and internal delays of
the IC, the width of the output pulse, t
W
(OUT), is as
follows:
t
W
(OUT)
=
1.0 C
x
R
x
3. Retrigger operation (74VHC123A)
When a new trigger is applied to either input A or B
while in the MONOSTABLE state, it is effective only if
the IC is charging C
x
. The voltage level of the R
x
/C
x
node then falls to V
ref
L level again. Therefore the Q
output stays HIGH if the next trigger comes in before
the time period set by C
x
and R
x
.
If the new trigger is very close to a previous trigger,
such as an occurrence during the discharge cycle, it
will have no effect.
The minimum time for a trigger to be effective 2nd
trigger, t
RR
(Min), depends on V
CC
and C
x
.
4. Reset Operation
In normal operation, the CLR input is held HIGH. If
CLR is LOW, a trigger has no affect because the Q
output is held LOW and the trigger control F/F is
reset. Also, Q
p
turns on and C
x
is charged rapidly to
V
CC
.
This means if CLR is set LOW, the IC goes into a wait
state.