SEPTEMBER 2013
1
©2013 Integrated Device Technology, Inc. DSC-2946/13
Features
◆◆
◆◆
◆High-speed address/chip select time
– Military: 25/35/45/55/70/85/100ns (max.)
– Commercial/Industrial: 20/25/35ns (max.) low power only
◆◆
◆◆
◆Low-power operation
◆◆
◆◆
◆Battery Backup operation – 2V data retention
◆◆
◆◆
◆Produced with advanced high-performance CMOS
technology
◆◆
◆◆
◆Input and output directly TTL-compatible
◆◆
◆◆
◆Available in standard 28-pin (300 or 600 mil) ceramic DIP,
28-pin (300 mil) SOJ
◆◆
◆◆
◆Military product compliant to MIL-STD-883, Class B
Description
The IDT 71256 is a 262,144-bit high-speed static RAM organized as
32K x 8. It is fabricated using high-performance, high-reliability CMOS
technology.
Functional Block Diagram
Address access times as fast as 20ns are available with power
consumption of only 350mW (typ.). The circuit also offers a reduced power
standby mode. When CS goes HIGH, the circuit will automatically go to and
remain in, a low-power standby mode as long as CS remains HIGH. This
capability provides significant system level power and cooling savings.
The low-power (L) version also offers a battery backup data retention
capability where the circuit typically consumes only 5μW when operating
off a 2V battery.
The IDT71256 is packaged in a 28-pin (300 or 600 mil) ceramic DIP,
a 28-pin 300 mil SOJ providing high board level packing densities.
The IDT71256 military RAM is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally suited to military
temperature applications demanding the highest level of performance and
reliability.
CMOS Static RAM
256K (32K x 8-Bit) IDT71256S
IDT71256L
A
0
ADDRESS
DECODER
262,144 BIT
MEMORY ARRAY
I/O CONTROL
2946 drw 01
INPUT
DATA
CIRCUIT
WE
CS
V
CC
GND
A
14
I/O
0
I/O
7
CONTROL
CIRCUIT
OE
,
2
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
Absolute Maximum Ratings(1)
Pin Configurations
DIP/SOJ
Top View
Truth Table(1)
Pin Descriptions
Name Description
A
0
- A
14
Address Inputs
I/O
0
- I/O
7
Data Inp ut/ Outp ut
CS Chip Select
WE Write Enable
OE Outp ut Enab le
GND Ground
V
CC
Power
2946 tbl 01
Capacitance (TA = +25°C, f = 1.0MHz)
NOTE:
1. This parameter is determined by device characterization, but is not production
tested.
NOTE:
1 . H = VIH, L = VIL, X = Don't care.
WE CS OE I/O Function
XHXHigh-Z Standby (I
SB
)
XV
HC
X Hig h-Z Standb y (I
SB1
)
H L H High-Z Output Disabled
HLLD
OUT
Re ad Data
LLXD
IN
Write Data
2 946 t bl 02
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
Symbol Rating Com'l. Ind. Mil. Unit
V
TERM
Terminal Voltag e
with Re sp e ct
to GND
-0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 V
T
A
Operating
Temperature 0 to +70 -40 to + 85 -55 to + 125
o
C
T
BIAS
Temperature
Und e r Bi as -55 to +125 -55 to +125 -65 to +135
o
C
T
STG
Storage
Temperature -55 to +125 -55 to + 125 -65 to +150
o
C
P
T
Power
Dissipation 1.0 1.0 1.0 W
I
OUT
DC Output Curre nt 50 50 50 mA
2 946 t bl 03
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Inp ut Cap ac itanc e V
IN
= 0V 11 pF
C
I/O
I/O Cap ac itanc e V
OUT
= 0V 11 pF
2946 tbl 04
2946 drw 02
5
6
7
8
9
10
11
12
GND
1
2
3
4
24
23
22
21
20
19
18
17
D28-3
D28-1
SO28-5
13
14
28
27
26
25
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
V
CC
A
14
WE
A
13
A
8
A
10
A
11
OE
A
12
CS
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
A
9
16
15
6.42
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
3
Recommended Operating
Temperature and Supply Voltage Recommended DC Operating
Conditions
NOTE:
1. VIL (min.) = –3.0V for pulse width less than 20ns, once per cycle.
Grade Temperature GND Vcc
Military -55OC to + 125OC0V 5V ± 10%
Industrial -40OC to +85OC0V 5V ± 10%
Commercial 0OC to + 70OC0V 5V ± 10%
2 946 t bl 05
Symbol Parameter Min. Typ. Max. Unit
V
CC
Sup ply Vo ltag e 4.5 5.0 5.5 V
GND Ground 0 0 0 V
V
IH
Input High Voltage 2.2 ____ 6.0 V
V
IL
Inp ut Low Vo ltag e -0.5
(1)
____ 0.8 V
2 946 t b l 06
DC Electrical Characteristics(1,2) (VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V)
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NOTES:
1. All values are maximum guaranteed values.
2. fMAX = 1/tRC, all address inputs are cycling at fMAX; f = 0 means no address pins are cycling.
4
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
AC Test Conditions
*Includes scope and jig capacitances
Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
Figure 1. AC Test Load
Inp ut P uls e Le v e ls
Inp ut Ri se / Fall Ti me s
Inp ut Timi ng Re fe re nc e Le ve ls
Outp ut Re fe re nc e Le v e ls
AC Te s t Lo ad
GND to 3. 0V
5ns
1.5V
1.5V
S ee F igure s 1 and 2
2 946 t bl 09
2946 drw 04
480Ω
255Ω30pF*
DATA
OUT
5V
,
2946 drw 05
480Ω
255Ω5pF*
DATA
OUT
5V
,
DC Electrical Characteristics (VCC = 5.0V ± 10%)
Data Retention Characteristics Over All Temperature Ranges
(L Version Only) (VLC = 0.2V, VHC = VCC - 0.2V)
NOTES:
1. TA = +25°C.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by device characterization, but is not production tested.
Symbol Parameter Test Conditions
IDT71256S IDT71256L
UnitMin. Typ. Max. Min. Typ. Max.
|ILI|Inp ut Leak ag e Current VCC = Max.,
VIN = GND to VCC MIL.
COM"L & IND.
____
____
____
____
10
5
____
____
____
____
5
2µA
|ILO| Outp ut Le akag e Curre nt VCC = Max., CS = VIH,
VOUT = GND to V CC MIL.
COM"L & IND.
____
____
____
____
10
5
____
____
____
____
5
2µA
VOL Outp ut Low Vo ltag e IOL = 8mA, VCC = Min.
____ ____
0.4
____ ____
0.4 V
IOL = 10mA, VCC = Min.
____ ____
0.5
____ ____
0.5
VOH Outp ut Hig h Vo ltag e IOH = -4mA, VCC = Min. 2.4
____ ____
2.4
____ ____
V
2946 tbl 10
Typ.
(1)
V
CC
@ Max.
V
CC
@
Symbol Parameter Test Condition Min. 2.0V 3.0V 2.0V 3.0V Unit
V
DR
V
CC
fo r Data Re te ntio n
____
2.0
____ ____ ____ ____
V
I
CCDR
Data Re te ntion Current MIL.
COM 'L. & IND.
____
____
____
____
____
____
500
120 800
200 μA
t
CDR
Chip Deselect to Data
Re tentio n Time CS > V
HC
0
____ ____ ____ ____
ns
t
R
(3)
Op e rati on Re cov ery Time t
RC
(2)
____ ____ ____ ____
ns
29 46 tbl 11
6.42
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
5
AC Electrical Characteristics (VCC = 5.0V ± 10%, All Temperature Ranges)
Low VCC Data Retention Waveform
2946 drw 06
DATA
RETENTION
MODE
4.5V 4.5V
V
DR
≥2V
V
IH
V
IH
t
R
t
CDR
V
CC
CS
V
DR
NOTES:
1. 0° to +70°C or -40° to +85°C temperature range only.
2. This parameter is guaranteed by device characterization, but is not production tested.
3. –55°C to +125°C temperature range only.
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emiTelcyCetirW02
____
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54
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03
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04
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03
____
04
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21lbt6492
6
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
AC Electrical Characteristics (VCC = 5.0V ± 10%, Military Temperature Ranges)
NOTES:
1. -55° to +125°C temperature range only.
2. This parameter is guaranteed by device characterization, but is not production tested.
Symbol Parameter
71256S55
(1)
71256L55
(1)
71256S70
(1)
71256L70
(1)
71256S85
(1)
71256L85
(1)
71256S100
(1)
71256L100
(1)
Unit
Min. Max. Min. Max. Min. Max. Min. Max.
Read Cycle
t
RC
Re ad Cy c le Time 55
____
70
____
85
____
100
____
ns
t
AA
Address Access Time
____
55
____
70
____
85
____
100 ns
t
ACS
Chip Select Access Time
____
55
____
70
____
85
____
100 ns
t
CLZ
(2)
Chi p S e l ec t to Outp u t in Lo w-Z 5
____
5
____
5
____
5
____
ns
t
CHZ
(2)
Chip De sele ct to Output in High-Z
____
25
____
30
____
35
____
40 ns
t
OE
Outp ut Enab le to Outp ut Vali d
____
25
____
30
____
35
____
40 ns
t
OLZ
(2)
Outp ut E nabl e to Outp ut i n Low-Z 0
____
0
____
0
____
0
____
ns
t
OHZ
(2)
Output Disabl e to O utput i n High-Z 0 25 0 30
____
35
____
40 ns
t
OH
Output Hold from Address Change 5
____
5
____
5
____
5
____
ns
Wr ite C y cle
t
WC
Write Cyc le Time 55
____
70
____
85
____
100
____
ns
t
CW
Chip Se le ct to E nd-o f-Write 50
____
60
____
70
____
80
____
ns
t
AW
Address Valid to End-of-Write 50
____
60
____
70
____
80
____
ns
t
AS
Address Set-up Time 0
____
0
____
0
____
0
____
ns
t
WP
Write Pulse Wid th 40
____
45
____
50
____
55
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
0
____
ns
t
DW
Data to Write Time Ov e rlap 25
____
30
____
35
____
40
____
ns
t
WHZ
(2)
Write Enable to Output i n High-Z
____
25
____
30
____
35
____
40 ns
t
DH
Data H o ld fro m Write Time (WE)0
____
0
____
0
____
0
____
ns
t
OW
(2)
Outp u t A cti v e fro m E nd - o f-Write 5
____
5
____
5
____
5
____
ns
2 946 tbl 13
6.42
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
7
Timing Waveform of R ead Cyc le No. 2(1,2,4)
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. Address valid prior to or coincident with CS transition LOW.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
Timing Waveform of Read Cyc le No. 1(1)
ADDRESS
CS
OE
DATA
OUT
t
RC
t
AA
t
OH
t
OE
t
ACS
t
CLZ (5)
t
OLZ (5)
2946 drw 07
t
CHZ(5)
t
OHZ(5)
2946 drw 08
ADDRESS
DATA
OUT
t
RC
t
AA
t
OH
t
OH
,
Timing Waveform of R ead Cyc le No. 2(1,3,4)
CS
DATAOUT
tACS
tCLZ (5)
2946 drw 09
tCHZ(5)
8
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
Timing Wa vef orm of Write Cyc le No. 1 (WE Controlled Timing)(1,2,4,6)
NOTES:
1. A write occurs during the overlap of a LOW CS and a LOW WE.
2. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
3 . During this period, I/O pins are in the output state so that the input signals must not be applied.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
6. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ +t DW) to allow the I/O drivers to turn off and data to be placed
on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse width can be as short
as the specified tWP. For a CS controlled write cycle, OE may be LOW with no degradation to tCW.
Timing Wa veform of Write Cyc le No. 2 (CS Controlled Timing)(1,2,4)
CS
2946 drw 10
t
AW
t
WR
t
DW
DATA
IN
ADDRESS
t
WC
WE
t
WP
t
DH
DATA
OUT
t
WZ
t
t
AS
(5)
(3)
OE
(3)
(6)
OW
t
OHZ (5)
t
WR
CS
2946 drw 11
t
AW
t
DW
DATA
IN
ADDRESS
t
WC
WE
t
CW
t
DH2
AS
tt
(6)
6.42
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
9
Ordering Information — Commercial & Industrial
Ordering Information — Military
X
Power Speed
XXX
Package
X
Process/
Temperature
Range
BMilitary (–55°C to +125°C)
Compliant to MIL-STD-883, Class B
TD
D
300 mil CERDIP (D28-3)
600 mil CERDIP (D28-1)
25
35
45
55
70
85
100
S
L
Standard Power
Low Power
Device
Type
71256
Speed in nanoseconds
2946 drw 12
XXX
X
Power
XX
Speed
XXX
Package
X
Process/
Temperature
Range
Blank
ICommercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G
300 mil SOJ (SO28-5)
20
25
35
L Low Power Only
Device
Type
71256
Speed in nanoseconds
2946 drw 13
X
Y
Green
Blank
8
Tube or Tray
Tape and Reel
X
10
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
Datasheet Document History
11/4/99: Updated to new format
Pp. 1–5, 9 Added Industrial Temperature Range offerings
Pg. 1 Removed 30, 120, and 150ns military and 45ns commercial speed grade offerings.
Pg. 2 Removed P28-2 package from DIP/SOJ Top View
Pg. 3 Removed 30ns and 45ns (Commercial only) speed grade offerings from DC Electrical table
Revised notes and footnotes
Pg. 5 Removed 30ns speed grade offering from AC Electrical table
Revised notes and footnotes
Pg. 6 Expressed Military Temperature range on AC Electrical table
Revised notes and footnotes
Pg. 8 Removed Note 1 and renumbered notes and footnotes
Pg. 9 Revised Ordering Information and presented by temperature range offering
Pg. 10 Added Datasheet Document History
08/09/00: Not recommended for new designs
02/01/01: Remove "Not recommended for new designs"
11/15/06: Pg. 3 Changed power limits for commercial and industrial. Refer to PCN SR-0602-03. Added Restricted hazardous
substance devce to ordering information.
11/01/08: Pg. 2,9 Corrected typo on pin 21 in 32-Pin LCC diagram. Updated the ordering information by removing the
"IDT" notation.
04/28/11: Pg. 1, 2, 5, 9 Added 20ns to Industrial offering. Obsoleted 28-pin 600 mil, 32-pin LCC and Added Tape and Reel to
Ordering information and updated description of Restricted hazardous substance device to Green.
09/26/13: Pg. 1 In the Description: removed IDT’s reference to fabrication and removed the sentence "In the full standby
mode, the low-power device consumes less than 15µW, typically".
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
CORPORATE HEADQUARTERS for SALES:
6024 Silver Creek Valley Road 800-345-7015 or
San Jose, CA 95138 408-284-8200
fax: 408-284-2775
www.idt.com
for Tech Support:
sramhelp@idt.com
408-284-4532
