Low Cost, DC to 150 MHz
Variable Gain Amplifier
AD8330
Rev. E
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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FEATURES
Fully differential signal path, also used
with single-sided signals
Inputs from 0.3 mV to 1 V rms, rail-to-rail outputs
Differential RIN = 1 kΩ; ROUT (each output) 75 Ω
Automatic offset compensation (optional)
Linear-in-dB and linear-in-magnitude gain modes
0 dB to 50 dB, for 0 V < VDBS < 1.5 V (30 mV/dB)
Inverted gain mode: 50 dB to 0 dB at −30 mV/dB
×0.03 to ×10 nominal gain for 15 mV < VMAG < 5 V
Constant bandwidth: 150 MHz at all gains
Low noise: 5 nV/√Hz typical at maximum gain
Low distortion: ≤−62 dBc typical
Low power: 20 mA typical at VS of 2.7 V to 6 V
Available in a space-saving, 3 mm × 3 mm LFCSP package
APPLICATIONS
Pre-ADC signal conditioning
75 Ω cable driving adjust
AGC amplifiers
FUNCTIONAL BLOCK DIAGRAM
VDBS VMAGCOMM
15
CMGN
14 13
ENBL
VPSO
CNTRVPOSOFST
OPHI
VPSI
INHI
INLO
MODE CMOP
OPLO
BIAS AND VREF
VGA CORE
OUTPUT
CONTROL
GAIN INTERFACE
OUTPUT
STAGES
8765
4
10
11
12
16
3
2
1
9
CM AND
OFFSET
CONTROL
03217-001
Figure 1.
GENERAL DESCRIPTION
The AD8330 is a wideband variable gain amplifier for applications
requiring a fully differential signal path, low noise, well-defined
gain, and moderately low distortion, from dc to 150 MHz. The
input pins can also be driven from a single-ended source. The
peak differential input is ±2 V, allowing sine wave operation at
1 V rms with generous headroom. The output pins can drive
single-sided loads essentially rail-to-rail. The differential output
resistance is 150 Ω. The output swing is a linear function of the
voltage applied to the VMAG pin that internally defaults to 0.5 V,
providing a peak output of ±2 V. This can be raised to 10 V p-p,
limited by the supply voltage.
The basic gain function is linear-in-dB, controlled by the voltage
applied to Pin VDBS. The gain ranges from 0 dB to 50 dB for
control voltages between 0 V and 1.5 V—a slope of 30 mV/dB.
The gain linearity is typically within ±0.1 dB. By changing the
logic level on Pin MODE, the gain decreases over the same range,
with an opposite slope. A second gain control port is provided at
the VMAG pin and allows the user to vary the numeric gain from
a factor of 0.03 to 10. All the parameters of the AD8330 have low
sensitivities to temperature and supply voltages.
Using VMAG, the basic 0 dB to 50 dB range can be reposi-
tioned to any value from 20 dB higher (that is, 20 dB to 70 dB)
to at least 30 dB lower (that is, –30 dB to +20 dB) to suit the
application, thereby providing an unprecedented gain range of
over 100 dB. A unique aspect of the AD8330 is that its bandwidth
and pulse response are essentially constant for all gains, over both
the basic 50 dB linear-in-dB range, but also when using the
linear-in-magnitude function. The exceptional stability of the
HF response over the gain range is of particular value in those
VGA applications where it is essential to maintain accurate gain
law-conformance at high frequencies.
An external capacitor at Pin OFST sets the high-pass corner of
an offset reduction loop, whose frequency can be as low as 5 Hz.
When this pin is grounded, the signal path becomes dc-coupled.
When used to drive an ADC, an external common-mode control
voltage at Pin CNTR can be driven to within 0.5 V of either ground
or VS to accommodate a wide variety of requirements. By default,
the two outputs are positioned at the midpoint of the supply, VS/2.
Other features, such as two levels of power-down (fully off and a
hibernate mode), further extend the practical value of this excep-
tionally versatile VGA.
The AD8330 is available in 16-lead LFCSP and 16-lead QSOP
packages and is specified for operation from −40°C to +85°C.
AD8330
Rev. E | Page 2 of 32
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 14
Circuit Description..................................................................... 14
Using the AD8330 ...................................................................... 20
Applications Information .............................................................. 25
ADC Driving ............................................................................... 25
Simple AGC Amplifier .............................................................. 25
Wide Range True RMS Voltmeter ............................................ 26
Evaluation Board ............................................................................ 28
General Description ................................................................... 28
Basic Operation .......................................................................... 28
Options ........................................................................................ 29
Measurement Setup.................................................................... 29
AD8330-EVALZ Board Design ................................................ 29
Outline Dimensions ....................................................................... 31
Ordering Guide .......................................................................... 32
REVISION HISTORY
3/10—Rev. D to Rev. E
Changes to Figure 2 and Table 3 ..................................................... 6
Changes to Figure 69 ...................................................................... 28
Changes to Figure 71 ...................................................................... 29
Changes to Figure 72 ...................................................................... 30
Deleted Table 7 ................................................................................ 31
Changes to Ordering Guide .......................................................... 32
1/08—Rev. C to Rev. D
Changes to Figure 28 and Figure 29 ............................................. 12
Added Evaluation Board Section ................................................. 28
Changes to Ordering Guide .......................................................... 33
6/06—Rev. B to Rev. C
Updated Format .................................................................. Universal
Changes to Figure 1 .......................................................................... 1
Deleted Figure 2 ................................................................................ 1
Changes to Specifications Section .................................................. 3
Change to Absolute Maximum Ratings ......................................... 5
Changes to Typical Performance Characteristics
Summary Statement ......................................................................... 7
Changes to Figure 14 and Figure 15 ............................................... 8
Changes to Figure 31 and Figure 32 ............................................. 11
Updated Outline Dimensions ....................................................... 28
10/04—Rev. A to Rev. B
Changes to Absolute Maximum Ratings ........................................ 4
Changes to Ordering Guide ............................................................. 4
Change to TPC 14 ............................................................................. 8
Note added to CP-16 Package ....................................................... 26
4/03—Rev. 0 to Rev. A
Updated Outline Dimensions ....................................................... 26
AD8330
Rev. E | Page 3 of 32
SPECIFICATIONS
VS = 5 V, TA = 25°C, CL = 12 pF on OPHI and OPLO, RL = ∞, VDBS = 0.75 V, VMODE = high, VMAG = Pin VMAG open circuit (0.5 V),
VOFST = 0 V, differential operation, unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
INPUT INTERFACE Pin INHI, Pin INLO
Full-Scale Input VDBS = 0 V, differential drive ±1.4 ±2 V
V
DBS = 1.5 V ±4.5 ±6.3 mV
Input Resistance Pin-to-pin 800 1 k 1.2 k Ω
Input Capacitance Either pin to COMM 4 pF
Voltage Noise Spectral Density f = 1 MHz, VDBS = 1.5 V; inputs ac-shorted 5 nV/√Hz
Common-Mode Voltage Level 3.0 V
Input Offset Pin OFST connected to Pin COMM 1 mV rms
Drift 2 μV/°C
Permissible CM Range1 0 VS V
Common-Mode AC Rejection f = 1 MHz, 0.1 V rms −60 dB
f = 50 MHz −55 dB
OUTPUT INTERFACE Pin OPHI, Pin OPLO
Small Signal –3 dB Bandwidth 0 V < VDBS < 1.5 V 150 MHz
Peak Slew Rate VDBS = 0 V 1500 V/μs
Peak-to-Peak Output Swing ±1.8 ±2 ±2.2 V
V
MAG ≥ 2 V (peaks are supply limited) ±4 ±4.5 V
Common-Mode Voltage Pin CNTR O/C 2.4 2.5 2.6 V
Voltage Noise Spectral Density f = 1 MHz, VDBS = 0 V 62 nV/√Hz
Differential Output Impedance Pin-to-pin 120 150 180 Ω
HD22 VOUT = 1 V p-p, f = 10 MHz, RL = 1 kΩ −62 dBc
HD32 VOUT = 1 V p-p, f = 10 MHz, RL = 1 kΩ −53 dBc
OUTPUT OFFSET CONTROL Pin OFST
AC-Coupled Offset CHPF on Pin OFST (0 V < VDBS < 1.5 V) 10 mV rms
High-Pass Corner Frequency CHPF = 3.3 nF, from OFST to CNTR (scales as 1/CHPF) 100 kHz
COMMON-MODE CONTROL Pin CNTR
Usable Voltage Range 0.5 4.5 V
Input Resistance From Pin CNTR to VS/2 4 kΩ
DECIBEL GAIN CONTROL VDBS, CMGN, and MODE pins
Normal Voltage Range CMGN connected to COMM 0 to 1.5 V
Elevated Range CMGN O/C (VCMGN rises to 0.2 V) 0.2 to 1.7 V
Gain Scaling Mode high or low 27 30 33 mV/dB
Gain Linearity Error 0.3 V ≤ VDBS ≤ 1.2 V −0.35 ±0.1 +0.35 dB
Absolute Gain Error VDBS = 0 V −2 ±0.5 +2 dB
Bias Current Flows out of Pin VDBS 100 nA
Incremental Resistance 100 MΩ
Gain Settling Time to 0.5 dB Error VDBS stepped from 0.05 V to 1.45 V or 1.45 V to 0.05 V 250 ns
Mode Up/Down Pin MODE
Mode Up Logic Level Gain increases with VDBS, MODE = O/C 1.5 V
Mode Down Logic Level Gain decreases with VDBS 0.5 V
LINEAR GAIN INTERFACE Pin VMAG, Pin CMGN
Peak Output Scaling, Gain vs. VMAG See the Circuit Description section 3.8 4.0 4.2 V/V
Gain Multiplication Factor vs. VMAG Gain is nominal when VMAG = 0.5 V ×2
Usable Input Range 0 5 V
Default Voltage VMAG O/C 0.48 0.5 0.52 V
Incremental Resistance 4 kΩ
Bandwidth For VMAG ≥ 0.1 V 150 MHz
AD8330
Rev. E | Page 4 of 32
Parameter Conditions Min Typ Max Unit
CHIP ENABLE Pin ENBL
Logic Voltage for Full Shutdown 0.5 V
Logic Voltage for Hibernate Mode Output pins remain at CNTR 1.3 1.5 1.7 V
Logic Voltage for Full Operation 2.3 V
Current in Full Shutdown 20 100 μA
Current in Hibernate Mode 1.5 mA
Minimum Time Delay3 1.7 μs
POWER SUPPLY VPSI, VPOS, VPSO, COMM, and CMOP pins
Supply Voltage 2.7 6 V
Quiescent Current VDBS = 0.75 V 20 27 mA
1 The use of an input common-mode voltage significantly different from the internally set value is not recommended due to its effect on noise performance.
See Figure 56.
2 See the section for more detailed information on distortion in a variety of operating conditions. Typical Performance Characteristics
3 For minimum sized coupling capacitors.
AD8330
Rev. E | Page 5 of 32
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage 6 V
Power Dissipation
RQ-16 Package1 0.62 W
CP-16-3 Package 1.67 W
Input Voltage at Any Pin VS + 200 mV
Storage Temperature Range −65°C to +150°C
θJA
RQ-16 Package 105.4°C/W
CP-16-3 Package 60°C/W
θJC
RQ-16 Package 39°C/W
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering 60 sec) 300°C
1 Four-Layer JEDEC Board (252P).
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD8330
Rev. E | Page 6 of 32
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
NOTES
1. T HE EXPO SED PAD IS NOT CONNECT E D INTE RNALLY.
F OR INCREAS E D RE LIABIL ITY OF THE SO LDER JO INT S
AND MAXI M UM THERMAL CAPABIL ITY, IT IS RECOMME NDED
THAT THE PAD BE SOLDERED TO THE GROUND PLANE.
PIN 1
INDICATOR
1VPSI
2INHI 3INLO
4MODE
11 OPHI
12 VPSO
10 OPLO
9CMOP
5
VDBS
6
CMGN 7
COMM 8
VMAG
15 OFST
16 ENBL
14 VPOS
13 CNTR
TOP VIEW
(No t to Scale )
AD8330
03217-003
Figure 2. 16-Lead LFCSP Pin Configuration
1
SOPVTSFO
16
2
RTNCLBNE
15
3
OSPVISPV
14
4
IHPOIHNI
13
5
OLPOOLNI
12
6
POMCEDOM
11
7
GAMVSBDV
10
8
MMOCNGMC
9
AD8330
TOP VIEW
(No t to Scale)
03217-004
Figure 3. 16-Lead QSOP Pin Configuration
Table 3. 16-Lead LFCSP Pin Function Descriptions
Pin No. Mnemonic Description
1 VPSI Positive Supply for Input Stages.
2 INHI Differential Signal Input, Positive
Polarity.
3 INLO Differential Signal Input, Negative
Polarity.
4 MODE
Logic Input: Selects Gain Slope.
High = gain up vs. VDBS.
5 VDBS
Input for Linear-in-dB Gain Control
Voltage, VDBS.
6 CMGN
Common Baseline for Gain Control
Interfaces.
7 COMM
Ground for Input and Gain Control Bias
Circuitry.
8 VMAG Input for Gain/Amplitude Control, VMAG.
9 CMOP Ground for Output Stages.
10 OPLO Differential Signal Output, Negative
Polarity.
11 OPHI Differential Signal Output, Positive
Polarity.
12 VPSO Positive Supply for Output Stages.
13 CNTR Common-Mode Output Voltage Control.
14 VPOS Positive Supply for Inner Stages.
15 OFST Used in Offset Control Modes.
16 ENBL Power Enable, Active High.
EPAD
Exposed Pad. It is recommended that
the pad be soldered to the ground
plane.
Table 4. 16-Lead QSOP Pin Function Descriptions
Pin No. Mnemonic Description
1 OFST Used in Offset Control Modes.
2 ENBL Power Enable, Active High.
3 VPSI Positive Supply for Input Stages.
4 INHI Differential Signal Input, Positive
Polarity.
5 INLO Differential Signal Input, Negative
Polarity.
6 MODE
Logic Input: Selects Gain Slope.
High = gain up vs. VDBS.
7 VDBS
Input for linear-in-dB Gain Control
Voltage, VDBS.
8 CMGN
Common Baseline for Gain Control
Interfaces.
9 COMM
Ground for Input and Gain Control Bias
Circuitry.
10 VMAG Input for Gain/Amplitude Control, VMAG.
11 CMOP Ground for Output Stages.
12 OPLO Differential Signal Output, Negative
Polarity.
13 OPHI Differential Signal Output, Positive
Polarity.
14 VPSO Positive Supply for Output Stages.
15 CNTR Common-Mode Output Voltage Control.
16 VPOS Positive Supply for Inner Stages.
AD8330
Rev. E | Page 7 of 32
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, TA = 25°C, CL = 12 pF, VDBS = 0.75 V, VMODE = high (or O/C) VMAG = O/C (0.5 V), RL = ∞, VOFST = 0, differential operation, unless
otherwise noted.
V
DBS
(V)
50
0 0.25 0.50 1.00 1.25 1.50
GAIN (dB)
40
30
20
10
00.75
45
35
25
15
5
HI M ODELO MODE
03217-005
Figure 4. Gain vs. VDBS
V
MAG
(V)
10
54310
GAI N MULT I P LI CAT I O N F ACT OR
8
6
4
2
02
9
7
5
3
1
03217-006
Figure 5. Linear Gain Multiplication Factor vs. VMAG
V
DBS
(V)
1.0
06.14.10.12.0
GAI N ERRO R ( dB)
0.6
0.2
–0.2
–0.6
–1.0 0.6
0.8
0.4
0
–0.4
–0.8
0.8 1.20.4
T = +25°C
T = +85°C
T = –40°C
03217-007
Figure 6. Gain Linearity Error Normalized at 25°C vs. VDBS,
at Three Temperatures, f = 1 MHz
V
DBS
(V)
2.0
00.2 0.8 1.2 1.6
GAIN ERROR (d B)
1.0
0
–1.0
–2.0 0.4
1.5
0.5
–0.5
–1.5
0.6 1.0 1.4
1MHz
50MHz
NORM AL IZE D @V
DBS
= 0. 75V
10MHz
1MHz
100MHz
100MHz
10MHz, 50MHz
03217-008
Figure 7. Gain Error vs. VDBS at Various Frequencies
GAIN SCALING (mV/dB)
29.1 29.2 29.3 29.4 29.5 29.6 29.7 29.8 29.9 30.0 30.1 30.2 30.3 30.4 30.5 30.6
% OF UNIT S
10
0
15
5
20
–30.6–30.5–30.4–30.3–30.2–30.1–30.0–29.9–29.8–29.7–29.6–29.5–29.4–29.3–29.2–29.1–29.0
10
0
15
5
20 2340 UNITS
MODE = LO
MO DE = HI
03217-009
Figure 8. Gain Slope Histogram
FREQUE NCY (Hz)
60
100k
GAIN (dB)
–50
–40
–30
–20
–10
0
10
20
30
40
50 V
DBS
= 1. 5V
1.2V
0.9V
0.6V
0.3V
0V
1M 10M 100M 500M
03217-010
Figure 9. Frequency Response in 10 dB Steps for Various Values of VDBS
AD8330
Rev. E | Page 8 of 32
FREQUENCY ( Hz )
50
100k
GAIN (dB)
–40
–30
–20
–10
0
10
20
30
40
V
MAG
= 4. 8V
1M 10M 100M 500M
1.52V
0.48V
0.15V
0.048V
0.015V
03217-011
Figure 10. Frequency Response for Various Values of VMAG,
VDBS = 0.75 V
FREQUE NCY ( Hz )
10
100k
G
R
OUP DEL
A
Y (ns)
0
2
4
6
8
1M 10M 100M 300M
V
DBS
= 0.1V
03217-012
Figure 11. Group Delay vs. Frequency
V
DBS
(V)
0
0
OFFSETVOLT
A
GE (mV)
–7
–6
–5
–4
–2
–1
–3
T = +25° C
T = –40°C
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
T = +85° C
03217-013
Figure 12. Differential Output Offset vs. VDBS for Three Temperatures,
for a Representative Part
DIF FERENTI AL O F F S ET ( mV)
25
–0.9
% OF UNITS
0
5
15
20
10
1048 UNITS
ENABLE MODE
–0.8
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
03217-014
Figure 13. Differential Input Offset Histogram
FREQUENCY (Hz)
10
100k
OUT P UT BALANCE ERROR ( d B)
–90
–70
–50
–30
–10
1M 10M 100M
0
–80
–60
–40
–20
0
3217-015
Figure 14. Output Balance Error vs. Frequency for a Representative Part
FREQUE NCY (Hz)
200
100k
OUTPUT I M P E DANC E ( Ω)
100
120
140
160
180
M003M01M1
190
110
130
150
170
100M
03217-016
Figure 15. Output Impedance vs. Frequency
AD8330
Rev. E | Page 9 of 32
FREQUENCY (Hz)
90
50k
CMRR (dB)
–10
10
30
50
70
M001M1k001
80
0
20
40
60
10M
OFST: ENABLED
DISABLED
V
DBS
= 1.5V
V
DBS
= 0. 75V
V
DBS
= 0V
03217-017
Figure 16. CMRR vs. Frequency
VDBS (V)
1500
0
NOI SE (n V/
√
Hz)
0
300
600
900
1200
f = 1MHz
VMAG = 0.5V T = +85°C
T = +25° C
T = –40 °C
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
03217-018
Figure 17. Output Referred Noise vs. VDBS for Three Temperatures
V
MAG
(V)
700
0
NOISE (nV/√Hz)
0
100
200
300
500
5.20.15.01.5
f = 1MHz
600
400
2.0
03217-019
Figure 18. Output Referred Noise vs. VMAG,
VDBS = 0.75 V
V
MAG
(V)
6000
0
NOI S E ( nV/
√
Hz)
0
1000
2000
3000
5000
5.20.15.01.5
4000
2.0
V
DBS
= 1.5V
f = 1MHz
03217-020
Figure 19. Output Referred Noise vs. VMAG
V
DBS
(V)
80
0
NOISE (nV/√Hz)
0
10
20
30
60
1.6
40
V
MAG
= 0.5V
f = 1MHz
70
50
0.2 0.4 0.6 0.8 1.0 1.2 1.4
T = +85°C
T = –40°C
T = +25°C
03217-021
Figure 20. Input Referred Noise vs. VDBS for Three Temperatures
V
DBS
(V)
180
0
NOISE (nV/√Hz)
0
20
40
60
120
1.6
80
f = 1MHz
140
100
0.2 0.4 0.6 0.8 1.0 1.2 1.4
160
V
MAG
= 0.125V
V
MAG
= 0. 5V
V
MAG
= 2V
03217-022
Figure 21. Input Referred Noise vs. VDBS for Three Values of VMAG
AD8330
Rev. E | Page 10 of 32
FREQUENCY ( Hz )
7
100k
NOISE (nV/√Hz)
0
1
2
3
6
100M
4
5
1M 10M
V
DBS
= 1.5V
03217-023
Figure 22. Input Referred Noise vs. Frequency
FREQUE NCY (Hz )
0
100k
DISTORTION (dBc )
–80
–70
–60
–50
–20
100M
–40
–30
1M 10M
–10
HD3
HD2
V
DBS
= 0.75V
V
OUT
= 1V p-p
R
L
= 1kΩ
03217-024
Figure 23. Harmonic Distortion vs. Frequency
C
LOAD
(pF)
0
0
DISTO
R
TION (dBc)
–80
–70
–60
–50
–20
50
–40
–10
–30
10 20 30 40
V
DBS
= 0. 75V
V
OUT
= 1V p-p
R
L
= 1kΩ
HD2
HD3
03217-025
Figure 24. Harmonic Distortion vs. CLOAD
V
OUT
(V p-p)
0
0
DISTO
R
TION (dBc)
–80
–70
–60
–50
–20
1.5
–40
–10
–30
0.3 0.6 0.9 1.2
f = 10M Hz
HD3, R
L
= 1kΩ
HD2, R
L
= 1kΩ
03217-026
Figure 25. Harmonic Distortion vs. VOUT , VMAG = 0.5 V
V
OUT
(V p-p)
0
0
DIS TORTION (d Bc)
–80
–70
–60
–50
–20
5
–40
–10
–30
1234
f = 10M Hz
HD3, R
L
= 1kΩ
HD2, R
L
= 1kΩ
HD2 AND HD3, R
L
= 150 Ω
1
1
OU TPU T AMPLIT UD E HARD LIMITED
03217-027
Figure 26. Harmonic Distortion vs. VOUT , VMAG = 2.0 V
V
DBS
(V)
0
0
DISTO
R
TION (dBc)
–70
–60
–50
–20
1.6
–40
–10
–30
0.2 0.6 1.0 1.4
HD2
1.20.80.4
f = 10MHz
V
OUT
= 1V p-p
R
L
= 1kΩ
HD3
03217-028
Figure 27. Harmonic Distortion vs. VDBS
AD8330
Rev. E | Page 11 of 32
10
00.20.40.60.8
V
DBS
(V) 1.0 1.2 1.4 1.6
INPUT V1dB COMPRESSION (dBV rms)
–50
–40
–30
0
–20
–10
f = 10MHz
23
–37
–27
–17
13
–7
3
P1dB (REF 50Ω)
03217-029
Figure 28. Input V1dB Compression vs. VDBS
20
0
–40
–30
–20
10
654321
–10
0
V
MAG
(V)
f = 10MHz
33
–27
–17
–7
23
3
13
03217-030
INPUT V1dB COMPRESSION (dBV rms)
P1dB (REF 50Ω)
Figure 29. Output V1dB Compression vs. VMAG
FREQUE NCY ( Hz )
0
1M
IMD3 (dBc)
–90
–80
–70
–10
100M
–60
–20
10M
–50
–40
–30
V
DBS
= 0. 75 V
V
OUT
= 1V p-p
0
3217-031
Figure 30. IMD3 Distortion vs. Frequency
OIP3 (dBV rms)
15
20
0
10
0
30
5
25
0.2 V
DBS
(V)
0.6 0.8 1.00.4 1.41.2 1.6
OIP3 (dBm)
13
18
8
33
28
3
23
f = 50M Hz
03217-032
f = 10MHz
Figure 31. OIP3 vs. VDBS
OIP3 (dBV rms)
15
20
0
10
0
30
5
25
f = 10MHz
0.2 VMAG (V)
0.6 0.8 1.00.4 1.41.2 1.6
OIP3 (dBm)
13
18
8
33
28
3
23
f = 50M Hz
40
35
43
38
03217-033
Figure 32. OIP3 vs. VMAG
TIME (ns)
1.5
VOUT (V)
–1.5
–1.0
–0.5
0
1.0
0.5
–50–250 255075100
VDBS = 0V
0
3217-034
Figure 33. Full-Scale Transient Response, VDBS = 0 V
AD8330
Rev. E | Page 12 of 32
TIME (ns)
1.5
V
OUT
(V)
–1.5
–1.0
–0.5
0
1.0
0.5
–50–250 255075100
V
DBS
= 0. 75V
03217-035
Figure 34. Full-Scale Transient Response, VDBS = 0.75 V,
f = 1 MHz, VOUT = 2 V p-p
TIME (ns)
1.5
V
OUT
(V)
–1.5
–1.0
–0.5
0
1.0
0.5
–50–250 255075100
V
DBS
= 1.5V
03217-036
Figure 35. Full-Scale Transient Response, VDBS = 1.5 V,
f = 1 MHz, VOUT = 2 V p-p
12.5ns
500mV
C
L
= 24pF
C
L
= 54p F
C
L
= 12pF
03217-037
Figure 36. Transient Response vs. Various Load Capacitances, G = 25 dB
1V
1V
400ns
03217-038
Figure 37. VDBS Interface Response, Top: VDBS, Bottom: VOUT
1mV
2V
400ns
03217-039
Figure 38. VMAG Interface Response, Top: VMAG, Bottom: VOUT
12.5ns
1V
100mV
VMAG = 0.05V
VMAG = 0.5V
VMAG = 5V
03217-040
Figure 39. Transient Response vs. VMAG
AD8330
Rev. E | Page 13 of 32
25ns
4.00V
50mV
OUTPUT
INPUT
03217-041
Figure 40. Overdrive Response, VDBS = 1.5 V, VMAG = 0.5 V, 18.5 dB Overdrive
1V
2V
400ns
03217-042
Figure 41. ENBL Interface Response. Top: VENBL; Bottom: VOUT, f = 10 MHz
FREQUE NC Y (Hz )
–
10
1M
PSRR (dB)
–110
–100
–90
–30
200M
–70
–50
M001M01
–20
–40
–80
–60
V
DBS
= 0. 75V
V
POS
V
PSI
03217-043
V
PSO
Figure 42. PSRR vs. Frequency
V
DBS
(V)
26
0
SUPPLY CURRENT (mA)
14
16
18
1.6
22
20
24
0.20.40.60.81.01.21.4
–40°C
+25°C
+85°C
03217-044
Figure 43. Supply Current vs. VDBS at Three Temperatures
100ns
3.125V
3.125V
2.5V
1.875V
2.5V
1.875V
03217-045
Figure 44. CNTR Transient Response, Top: Input to CNTR,
Bottom: VOUT Single-Ended
AD8330
Rev. E | Page 14 of 32
THEORY OF OPERATION
CIRCUIT DESCRIPTION
Many monolithic variable gain amplifiers use techniques that
share common principles that are broadly classified as translinear.
This term refers to circuit cells whose functions depend directly
on the very predictable properties of bipolar junction transistors,
notably the linear dependence of their transconductance on collec-
tor current. Since the discovery of these cells in 1967, and their
commercial exploitation in products developed during the early
1970s, accurate wide bandwidth analog multipliers, dividers,
and variable gain amplifiers have invariably employed translinear
principles.
Although these techniques are well understood, the realization
of a high performance variable gain amplifier (VGA) requires
special technologies and attention to many subtle details in
its design. The AD8330 is fabricated on a proprietary silicon-
on-insulator, complementary bipolar IC process and draws
on decades of experience in developing many leading edge
products using translinear principles to provide an unprecedented
level of versatility.
Figure 45 shows a basic representative cell comprising just four
transistors. This, or a very closely related form, is at the heart
of most translinear multipliers, dividers, and VGAs. The key
concepts are as follows:
First, the ratio of the currents in the left-hand and right-hand
pairs of transistors is identical, represented by the modulation
factor, x, with values between −1 and +1. Second, the input
signal is arranged to modulate the fixed tail current, ID, to cause
the variable value of x, introduced in the left-hand pair, to be
replicated in the right-hand pair, and, thus, generate the output
by modulating its nominally fixed tail current, IN. Third, the
current gain of this cell is exactly G = IN/ID over many decades
of variable bias current.
In practice, the realization of the full potential of this circuit
involves many other factors, but these three elementary ideas
remain essential.
By varying IN, the overall function is that of a two-quadrant
analog multiplier, exhibiting a linear relationship to both the
signal modulation factor (x) and this numerator current. On
the other hand, by varying ID, a two-quadrant analog divider
is realized, having a hyperbolic gain function with respect to
the input factor, x, controlled by this denominator current. The
AD8330 exploits both modes of operation. However, because a
hyperbolic gain function is generally of less value than one in
which the decibel gain is a linear function of a control input, a
special interface is included to provide either increasing or
decreasing exponential control of ID.
INPUT IS xl
D
DENOMINATOR
BIAS CURRENT
I
D
Q1
Q2
Q4
Q3
(1–x) I
D
2
+–
LOOP
AMPLIFIER
(1–x) I
N
2
NUMERATOR
BIAS CURRENT I
N
OUTPUT IS xl
N
G = I
N
/
I
D
(1+x) I
N
2
(1–x) I
D
2
03217-046
Figure 45. Basic Core
COMM
OPHI
INLO OPLO
INHI
VPSI VPSO
CMOP
MODE
VDBS CMGN VMAG
OFST RTNCLBNEVPOS
BIAS AND
V
REF
GAIN INTERFACE
CM MO DE AND
OF FSET CONTROL
OUTPUT
STAGES
OUTPUT
CONTROL
VGA CO RE
AD8330
03217-047
Figure 46. Block Schematic
Overall Structure
Figure 46 shows a block schematic of the AD8330 locating the
key sections. More detailed descriptions of its structure and
features are provided throughout the Theory of Operation
section; however, Figure 46 provides a general overview of its
capabilities.
The VGA core contains a more elaborate version of the cell
shown in Figure 45. The current, ID, is controlled exponentially
(linear-in-decibels) through the decibel gain interface at
Pin VDBS and its local common, Pin CMGN. The gain span
(that is, the decibel difference between maximum and
minimum values) provided by this control function is slightly
more than 50 dB. The absolute gain from input to output is a
function of source and load impedance, and depends on the
voltage on a second gain control pin (VMAG), explained in the
Normal Operating Conditions section.
AD8330
Rev. E | Page 15 of 32
Normal Operating Conditions
To minimize confusion, normal operating conditions are
defined as follows:
The input pins are voltage driven (the source impedance is
assumed to be zero).
The output pins are open circuited (the load impedance is
assumed to be infinite).
Pin VMAG is unconnected setting up the output bias current
(IN in the four-transistor gain cell) to its nominal value.
Pin CMGN is grounded.
MODE is either tied to a logic high or left unconnected, to set
the up gain mode.
The effects of other operating conditions are considered
separately.
Throughout this data sheet, the end-to-end voltage gain for the
normal operating conditions is referred to as the basic gain.
Under these conditions, it runs from 0 dB when VDBS = 0 V
(where this voltage is more exactly measured with reference
to Pin CMGN, which is not necessarily tied to ground) up to
50 dB for VDBS = 1.5 V. The gain does not fold over when the
VDBS pin is driven below ground or above its nominal full-
scale value.
The input is accepted at the INHI/INLO differential port. These
pins are internally biased to roughly the midpoint of the supply,
VS (it is actually ~2.75 V for VS = 5 V, VDBS = 0 V, and 1.5 V for
VS = 3 V), but the AD8330 is able to accept a forced common-
mode value, from zero to VS, with certain limitations. This
interface provides good common-mode rejection up to high
frequencies (see Figure 16) and, thus, can be driven in either a
single-sided or differential manner. However, operation using a
differential drive is preferable, and this is assumed in the
specifications, unless otherwise stated.
The pin-to-pin input resistance is specified as 950 ± 20%. The
driving-point impedance of the signal source can range from
zero up to values considerably in excess of this resistance, with a
corresponding variation in noise figure (see Figure 53). In most
cases, the input is coupled via two capacitors, chosen to provide
adequate low frequency transmission. This results in the minimum
input noise that increases when some other common-mode volt-
age is forced onto these pins. The short-circuit, input-referred
noise at maximum gain is approximately 5 nV/√Hz.
Output Pin OPHI and Output Pin OPLO operate at a common-
mode voltage at the midpoint of the supply, VS/2, within a few
millivolts. This ensures that an analog-to-digital converter
(ADC) attached to these outputs operates within the often
narrow range permitted by their design. When a common-
mode voltage other than VS/2 is required at this interface, it can
easily be forced by applying an externally provided voltage to
the output centering pin, CNTR. This voltage can run from zero
to the full supply, though the use of such extreme values leaves
only a small range for the differential output signal swing.
The differential impedance measured between OPHI and
OPLO is 150 ± 20%. It follows that both the gain and the
full-scale voltage swing depend on the load impedance; both are
nominally halved when this is also 150 . A fixed impedance
output interface, rather than an op amp style voltage-mode
output, is preferable in high speed applications because the
effects of complex reactive loads on the gain and phase can be
better controlled. The top end of the AD8330 ac response is
optimally flat for a 12 pF load on each pin, but this is not
critical, and the system remains stable for any value of load
capacitance including zero.
Another useful feature of this VGA in connection with the
driving of an ADC is that the peak output magnitude can be
precisely controlled by the voltage on Pin VMAG. Usually, this
voltage is internally preset to 500 mV, and the peak differential
unloaded output swing is ±2 V ± 3%. However, any voltage
from zero to at least 5 V can be applied to this pin to alter the
peak output in an exactly proportional way. Because either
output pin can swing rail-to-rail, which in practice means down
to at least 0.35 V and to within the same voltage below the
supply, the peak-to-peak output between these pins can be as
high as 10 V using VS = 6 V.
INHI
INLO
VDBS
VPSI
COMM
TRANSIMPEDANCE
OUT P UT ST AGE
500Ω
500Ω
LINEAR-IN-dB
INTERFACE MAGNITUDE
INTERFACE
5kΩ
R
OUT =
150Ω
100µA
V
MAG
VPSO
OPHI
OPLO
ΔV = 0
12.65µA–4mA O R
4mA–12.65µACOMM
VMAG
MODE
CNTR
ΔV = 0
O/P CM-MODE
NORMALLY
AT V
P
/2
CM MO DE
FEEDBACK
V
DBS
03217-048
Figure 47. Schematic of Key Components
Linear-in-dB Gain Control (VDBS)
All Analog Devices, Inc., VGAs featuring a linear-in-dB gain
law, such as the X-AMP® family, provide exact, constant gain
scaling over the fully specified gain range, and the deviation
from the ideal response is within a small fraction of a dB. For
the AD8330, the scaling of both of its gain interfaces is
substantially independent of process, supply voltage, or
temperature. The basic gain, GB, is simply
()
mV30
DBS
B
V
dBG = (1)
where VDBS is in volts.
Alternatively, this can be expressed as a numerical gain
magnitude
AD8330
Rev. E | Page 16 of 32
V
V
BN
DBS
G6.0
10= (2)
The gain can be increased or decreased by changing the voltage,
VMAG, applied to the VMAG pin. The internally set default value
of 500 mV is derived from the same band gap reference that
determines the decibel scaling. The tolerance on this voltage,
and mismatches in certain on-chip resistors, cause small gain
errors (see the Specifications section). Though not all appli-
cations of VGAs demand accurate gain calibration, it is a
valuable asset in many situations, for example, in reducing
design tolerances.
Figure 47 shows the core circuit in more detail. The range and
scaling of VDBS is independent of the supply voltage, and the
gain control pin, VDBS, presents a high incremental input re-
sistance (~100 M) with a low bias current (~100 nA), making
the AD8330 easy to drive from a variety of gain control sources.
Inversion of the Gain Slope
The AD8330 supports many features that further extend the
versatility of this VGA in wide bandwidth gain control systems.
For example, the logic pin, MODE, allows the slope of the gain
function to be inverted, so that the basic gain starts at +50 dB
for a gain voltage, VDBS, of zero and runs down to 0 dB when
this voltage is at its maximum specified value of 1.5 V. The basic
forms of these two gain control modes are shown in Figure 48.
0.25
10
20
VDBS (V)
GAIN (dB)
0
30
40
50
0 0.50 0.75 1.0 1.25 1.50
MODE PIN
LOW, GAIN
DECREASES
WITH VDBS
MODE PIN
HIGH, GAIN
INCREASES
WITH VDBS
03217-049
Figure 48. Two Gain Directions of the AD8330
Gain Magnitude Control (VMAG)
In addition to the basic linear-in-dB control, two more gain
control features are provided. The voltage applied to Pin VMAG
provides accurate linear-in-magnitude gain control with a very
rapid response. The bandwidth of this interface is >100 MHz.
When this pin is unconnected, VMAG assumes its default value of
500 mV (see Figure 47) to set up the basic 0 dB to 50 dB range.
However, any voltage from ~15 mV to 5 V can be applied either
to lower the gain by up to 30 dB or to raise it by 20 dB. The
combined gain span is thus 100 dB, that is, the 50 dB basic gain
span provided by VDBS plus a 60 dB linear-in-magnitude span
provided by VMAG. The latter modifies the basic numerical gain
GBN to generate a total gain, expressed here in magnitude terms.
V5.0
MAG
BN
T
V
GG = (3)
Using this to calculate the output voltage,
VOUT = 2 × GIN × VIN × VMAG (4)
from which it is apparent that the AD8330 implements a linear,
two-quadrant multiplier with a bipolar VIN and a unipolar VMAG.
Because the AD8330 is a dc-coupled system, it can be used in
many applications where a wideband two-quadrant multiplier
function is required, from dc up to about 100 MHz from either
input (VIN or VMAG).
As VMAG is varied, so also is the peak output magnitude, up to a
point where this is limited by the absolute output limit imposed
by the supply voltage. In the absence of the latter effect, the
peak output into an open-circuited load is just
VOUT_PK = ±4 VMAG (5)
whereas for a load resistance of RL directly across OPHI and
OPLO, it is
()
150
2
_+
±
=
L
L
MAG
PKOUT R
RV
V (6)
These capabilities are illustrated in Figure 49, where VS = 6 V,
RL = O/C, VDBS = 0 V, VIN is swept from −2.5 V dc to +2.5 V dc, and
VMAG is set to 0.25 V, 0.5 V, 1 V, and 2 V. Except for the last value
of VMAG, the peak output follows Equation 5. This exceeds the
supply-limited value when VMAG = 2 V and the peak output is
±5.65 V, that is, ±6 V − 0.35 V. Figure 50 demonstrates the high
speed multiplication capability. The signal input is a 100 MHz,
0.1 V sine wave, VDBS is set to 0.6 V, and VMAG is a square wave at
5 MHz alternating from 0.25 V to 1 V. The output is ideally a
sine wave switching in amplitude between 0.5 V and 2 V.
V
IN
( V)
8
312–3–
V
OUT
(V)
4
0
–4
–8 –1
6
2
–2
–6
02
V
MAG
= 2V
1V
0.5V
0.25V
03217-050
Figure 49. Effect of VMAG on Gain and Peak Output
AD8330
Rev. E | Page 17 of 32
V
IN
V
MAG
TIME (ns)
0.10
–400 –300 –200 –100 0 100 200 300
0.05
0
–0.05
–0.10
1.2
1.0
0.8
0.6
0.4
0.2
0
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
V
OUT
03217-051
Figure 50. Using VMAG in Modulation Mode
Another gain related feature allows both gain control ranges
to be accurately raised by 200 mV. To enable this offset, open
circuit CMGN (Pin 6, LFCSP; Pin 8, LQFP) and add a 0.1 F
capacitor to ground. In use, the nominal range for VDBS extends
from 0.2 V to 1.7 V and VMAG from 0.2 V to 5.2 V. These
specifications apply for any supply voltage. This allows the use
of DACs whose output range does not include ground as sources
for the gain control function(s).
Note that the 200 mV that appears on this pin affects the
response to an externally applied VMAG, but when Pin VMAG is
unconnected, the internally set default value of 0.5 V still applies.
Furthermore, Pin CMGN can, if desired, be driven by a user-
supplied voltage to reposition the baseline for VDBS (or for an
externally applied VMAG) to any other voltage up to 500 mV. In
all cases, the gain scaling, its law conformance, and temperature
stability are unaffected.
Two Classes of Variable Gain Amplifiers
Note that there are two broad classes of VGAs. The first type is
designed to cope with a very wide range of input amplitudes
and, by virtue of its gain control function, compress this range
down to an essentially constant output. This is the function
needed in an AGC system. Such a VGA is called an IVGA,
referring to a structure optimized to address a wide range of
input amplitudes. By contrast, an OVGA is optimized to deliver
a wide range of output values while operating with an essentially
constant input amplitude. This function might be needed, for
example, in providing a variable drive to a power amplifier.
It is apparent from the foregoing sections that the AD8330 is
both an IVGA and an OVGA in one package. This is an unusual
and possibly confusing degree of versatility for a VGA; therefore,
these two distinct control functions are described at separate
points throughout this data sheet to explain the operation and
applications of this product. It is, nevertheless, useful to briefly
describe the capabilities of these features when used together.
Amplitude/Phase Response
The ac response of the AD8330 is remarkably consistent not
only over the full 50 dB of its basic gain range, but also with
changes of gain due to alteration of VMAG, as demonstrated in
Figure 51. This is an overlay of two sets of results: first, with a
very low VMAG of 16 mV that reduces the overall gain by 30 dB
[20 × log10(500 mV/16 mV)]; second, with VMAG = 5 V that
increases the gain by 20 dB = 20 × log10(5 V/0.5 V).
FRE QUE NCY ( Hz )
90
100k
10k
GAIN (dB)
30
–10
–350
50
10
–30
1M 10M 100M 300M
70
PHASE ( Degrees)
–50
–50
–100
–150
–200
–250
–300
0G = +70d B
G = –20dB
100k 1M 10M 100M 300M
03217-052
Figure 51. AC Performance over a 100 dB Gain Range Obtained by
Using Two Values of VMAG
This 50 dB step change in gain produces two sets of gain curves,
having a total gain span of 100 dB. It is apparent that the ampli-
tude and phase response are essentially independent of the gain
over this wide range, an aspect of the AD8330 performance
potential unprecedented in any prior VGA.
It is unusual for an application to require such a wide range of
gains; and, as a practical matter, the peak output voltage for
VMAG = 16 mV is reduced by the factor 16/500, compared to its
nominal value of ±2 V, to only ±64 mV. As previously noted,
most applications of VGAs require that they operate in a mode
that is predominantly of either an IVGA or OVGA style, rather
than mixed modes.
With this limitation in mind, and simply to illustrate the unusual
possibilities afforded by the AD8330, note that, with appropriate
drive to VDBS and VMAG in tandem, the gain span is a remarkable
120 dB, extending from −50 dB to +70 dB, as shown in Figure 52
for operation at 1 MHz and 100 MHz. In this case, VDBS and
VMAG are driven from a common control voltage, VGAIN, that
varies from 1.2 mV to 5 V, with 30% (1.5/5) of VGAIN applied
to VDBS, and 100% applied to VMAG.
The gain varies in a linear-in-dB manner with VDBS, although
the response from VMAG is linear-in-magnitude. Consequently, the
overall numerical gain as the product of these two functions is
V6.0
103.0V5.0/
GAIN
V
GAIN
VGAIN ××= (7)
In rare cases where such a wide gain range is of value, the
calibration is still accurate and the temperature is stable.
AD8330
Rev. E | Page 18 of 32
V
GAIN
(V)
80
0.001
1
NOISE (nV/√Hz) GAIN (dB)
–40
–60
–20
0
20
40
60
10
100
1k
10k
100k
0.01 0.1 1 10
03217-053
Figure 52. Gain Control Function and Input Referred Noise Spectral Density
over a 120 dB Range
Noise, Input Capacity, and Dynamic Range
The design of variable gain amplifiers invariably incurs some
compromises in noise performance. However, the structure of
the AD8330 is such that this penalty is minimal. Examination
of the simplified schematic (Figure 47) shows that the input
voltage is converted to current-mode form by the two 500 Ω
resistors at Pin INHI and Pin INLO, whose combined Johnson
noise contributes 4.08 nV/√Hz. The total input noise at full
gain, when driven from a low impedance source, is typically
5 nV/√Hz after accounting for the voltage and current noise
contributions of the loop amplifier. For a 200 kHz channel
bandwidth, this amounts to 2.24 V rms. The peak input at full
gain is ±6.4 mV, or +4.5 mV rms for a sine wave signal. The
signal-to-noise ratio at full input, that is, the dynamic range, for
these conditions is, thus, 20 log10(4.5 mV/2.24 V), or 66 dB.
The value of VMAG has essentially no effect on the input referred
noise, but it is assumed to be 0.5 V.
Below midgain (25 dB, VDBS = 0.75 V), noise in the output
section dominates, and the total input noise is 11 nV/√Hz, or
4.9 µV rms in a 200 kHz bandwidth, and the peak input is
78 mV rms. Thus, the dynamic range increases to 84 dB.
At minimum gain, the input noise is up to 120 nV/√Hz, or
53.7 mV rms in the assumed 200 kHz bandwidth, while the
input capacity is ±2 V, or +1.414 V rms (sine), a dynamic range
of 88.4 dB. In calculating the dynamic range for other channel
bandwidths, ∆f, subtract 10 log10(∆f/200 kHz) from these
illustrative values. A system operating with a 2 MHz bandwidth,
for example, exhibits dynamic range values that are uniformly
10 dB lower; used in an audio application with a 20 kHz band-
width, they are 10 dB higher.
Noise figure is a misleading metric for amplifiers that are not
impedance matched at their input, which is the special condi-
tion resulting only when both the voltage and current components
of a signal, that is, the signal power, are used at the input port.
When a source of impedance (RS) is terminated using a resistor
of RS (a condition that is not to be confused with matching),
only one of these components is used, either the current (as in
the AD8330) or the voltage. Then, even if the amplifier is
perfect, the noise figure cannot be better than 3 dB. The 1 kΩ
internal termination resistance would result in a minimum
noise figure of 3 dB for an RS of 1 kΩ if the amplifier were
noise-free. However, this is not the case, and the minimum
noise figure occurs at a slightly different value of RS (for an
example, see Figure 53 and the Using the AD8330 section).
RS (Ω)10k10010 1k
15
14
13
12
11
10
9
8
7
5
6
NOI S E FIGURE
03217-054
Figure 53. Noise Figure for Source Resistance of 50 Ω to 5 kΩ, at f = 10 MHz
(Lower) and 100 MHz (Simulation)
VDBS (V)
00.1
DYNAMI C RANGE ( dB/√Hz)
0.20.30.40.50.60.70.80.91.01.11.21.31.41.5
144
132
128
124
120
140
136
116
CO NST AN T 1V rm s
OUT P UT, BOTH CAS E S
X-AMP WITH 40dB
OF GAIN AND AN
INPUT NSD
OF nV/√Hz
03217-055
Figure 54. Dynamic Range in dB/√Hz vs. VDBS (VMAG = 0.5 V, 1 V rms Output)
Compared with a Representative X-AMP (Simulation)
Dynamic Range
The ratio of peak output swing, expressed in rms terms, to the
output-referred noise spectral density provides a measure of
dynamic range, in dB/√Hz. For a certain class of variable gain
amplifiers, exemplified by the Analog Devices X-AMP® family,
the dynamic range is essentially independent of the gain setting
because the peak output swing and noise are both constant. The
AD8330 provides a different dynamic range profile because
there is no longer a constant relationship between these two
parameters. Figure 54 compares the dynamic range of the
AD8330 to a representative X-AMP.
AD8330
Rev. E | Page 19 of 32
Input Common-Mode Range and Rejection Ratio
Input Pin INHI and Pin INLO should be ac-coupled in most
applications to achieve the stated noise performance. In general,
when direct coupling is used, care must be taken in setting the
dc voltage level at these inputs, and particularly when minimizing
noise is critical. This objective is complicated by the fact that
the common-mode level varies with the basic gain voltage, VDBS.
Figure 55 shows this relationship for a supply voltage of 5 V, for
temperatures of −40°C, +25°C, and +85°C. Figure 56 shows the
input noise spectral density (RS = 0) vs. the input common-
mode voltage, for VDBS = 0.5 V, 0.6 V, 0.75 V, and 1.5 V. It is
apparent that there is a broad range over which the noise is
unaffected by this dc level. The input CMRR is excellent (see
Figure 16).
V
DBS
(V)
0
DC VOLTAGE AT INHI, INLO (V)
2.6
3.2
3.1
3.0
2.9
2.8
2.7
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
T = +25°C
T = + 85°C
T = –40°C
03217-056
Figure 55. Common-Mode Voltage at Input Pins vs. VDBS, for VS = 5 V,
T = −40°C, + 25°C, and + 85°C
COMM ON-MO DE VOLTAGE AT INHI, INLO (V)
0
26
22
20
18
16
14
12
10
8
4
6
INPUT REFERRED NOI S E (nV /
√
Hz)
24
0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8
V
DBS
= 1.5V
V
DBS
= 0. 75V
V
DBS
= 0.6V
V
DBS
= 0.5V
SIMULATION
03217-057
Figure 56. Input Noise vs. Common-Mode Input Voltage for
VDBS = 0.5 V, 0.6 V, 0.75 V, and 1.5 V
Output Noise and Peak Swing
The output noise of the AD8330 is the input noise multiplied by
the overall gain, including any optional change to the voltage,
VMAG, applied to Pin VMAG. The peak output swing is also
proportional to this voltage, which, at low gains and high values
of VMAG, affects the output noise.
The scaling for VDBS = 0 V is as follows:
VOUT_PK = ±4 VMAG (8)
VNOISE_OUT = (85 + 70 VMAG) nV/√Hz (9)
For example, using a reduced value of VMAG = 0.25 V that lowers
all gain values by 6 dB, the peak output swing is ±1 V (differ-
entially) and the output noise spectral density evaluates to
102.5 nV/√Hz. The peak output swing is no different at full
gain, but the noise becomes
VNOISE_OUT = (0.1 + 0.32 VMAG) µV/√Hz (10)
for RS = 0 and VDBS = 1.5 V, assuming an input noise of 5 nV/√Hz.
The output noise for very small values of VMAG (at or below 15 mV)
is not precise, partly because the small input offset associated
with this interface has a large effect on the gain.
Offset Compensation
The AD8330 includes an offset compensation feature that is
operational in the default condition (no connection to Pin OFST).
This loop introduces a high-pass filter function into the signal
path, whose −3 dB corner frequency is at
()
HP
INT
HPF CR
fπ
=2
1 (11)
where:
CHP is the external capacitance added from OFST to CNTR.
RINT is an internal resistance of approximately 480 , having a
maximum uncertainty of about ±20%.
This evaluates to
HP
HPF C
f
μ
=330 (CHP in F) (12)
A small amount of peaking at this corner when using small
capacitor values can be avoided by adding a series resistor.
Useful combinations are CHP = 3 nF, RHP = 180 , f = 100 kHz;
CHP = 33 nF, RHP = 10 , f = 10 kHz; CHP = 0.33 F, RHP = 0 ,
f = 1 kHz; CHP = 3.3 F, RHP = 0 , f = 100 Hz.
The offset compensation feature can be disabled simply by
grounding the OFST pin. This provides a dc-coupled signal
path, with no other effects on the overall ac response. Input
offsets must be externally nulled in this mode of operation, as
shown in Figure 58.
Effects of Loading on Gain and AC Response
The differential output impedance (RO) is 150 , and the fre-
quency response of the output stage is optimized for operation
with a certain load capacitance on each output pin (OPHI and
OPLO) to ground, in combination with a load resistance (RL)
directly across these pins. In the absence of these capacitances,
there is a small amount of peaking at the top extremity of the
ac response. Suitable combinations are: RL = ∞, CL = 12 pF;
RL = 150 , CL = 25 pF; RL = 75 , CL = 40 pF; or RL = 50 ,
CL = 50 pF.
AD8330
Rev. E | Page 20 of 32
)
The gain calibration is specified for an open-circuited load,
such as the high input resistance of an ADC. When resistively
loaded, all gain values are nominally lowered as follows:
(
L
L
UNLOADED
LOADED R
RG
G+
=150 (13)
Thus, when RL = 150 , the gain is reduced by 6 dB; for
RL = 75 Ω, the reduction is 9.5 dB; and for RL = 50 , it is 12 dB.
Gain Errors Due to On-Chip Resistor Tolerances
In all cases where external resistors are used, keep in mind that
all on-chip resistances, including the RO and the input resistance
(RI), are subject to variances of up to ±20%.
These variances need to be accounted for when calculating the
gain with input and output loading. This sensitivity can be avoided
by adjusting the source and load resistances to bear an inverse
relationship as follows:
If RS = αRI, then make RL = RO/α; or,
if RL = αRO, then make RS = RI/α
The simplest case is when RS = 1 kΩ and RL = 150 , therefore,
the gain is 12 dB lower than the basic value. The reduction of
peak swing at the load can be corrected by using VMAG = 1 V,
thereby restoring 6 dB of gain; using VMAG = 2 V restores the full
basic gain and doubles the peak available output swing.
Output (Input) Common-Mode Control
The output voltages are nominally positioned at the midpoint of
the supply, VS/2, over the range 2.7 V < VS < 6 V, and this voltage
appears at Pin CNTR, which is not normally expected to be
loaded (the source resistance is ~4 k). However, some circum-
stances require a small change in this voltage, and a resistor
from CNTR to ground can lower this voltage, whereas a resistor
to the supply raises it. On the other hand, this pin can be driven
by an external voltage source to set the common-mode level to
satisfy, for example, the needs of a following ADC. Any value
from 0.5 V above ground to 0.5 V below the supply is permissible.
Of course, when using an extreme common-mode level, the
available output swing is limited, and it is recommended that
a value equal or close to the default of VCNTR = VS/2 be used.
There may be a few millivolts of offset between the applied
voltage and the actual common-mode level at the output pins.
The input common-mode voltage, VCMI, at Pin INHI and
Pin INLO is slaved to the output, but with a shifted value of
VCMI = 0.757 VCNTR + 1.12 V (14)
for VDBS = 0.75 and T = 25°C. Thus, the default value for VCMI
when VS = 5 V is 3.01 V (see Figure 55).
USING THE AD8330
This section describes a few general aspects of using the
AD8330. Applying the AD8330 to a wide variety of circum-
stances requires very few precautions.
As in all high frequency circuits, careful observation of the
ground nodes associated with each function is important. Three
positive supply pins are provided: VPSI supports the input cir-
cuitry that often operates at a relatively high sensitivity; VPOS
supports general bias sources and needs no decoupling; and
VPSO biases the output stage where decoupling can be useful in
maintaining a glitch-free output. Figure 57 shows the general
case, where VPSI and VPSO are each provided with their own
decoupling network, but this is not needed in all cases.
COMM
OPHI
INLO OPLO
INHI
VPSI VPSO
CMOP
MODE
VDBS CMGN VMAG
OFST RTNCLBNEVPOS
BIAS AND
V-REF
GAIN INTERFACE
CM MO DE AND
OFFSE T CONTROL
OUTPUT
STAGES
OUTPUT
CONTROL
VGA CORE OUTPUT,
±2V MAX
NC
BASIC G AIN BIAS
VDBS: 0V TO 1. 5V
CD2FPHC1DR
CD1 CD3
RD2
GROUND
VS 2.7V T O 6V
INPUT,
0V T O ±2V MAX
NC
03217-058
Figure 57. Power Supply Decoupling and Basic Connections
Because of the differential nature of the signal path, power
supply decoupling is, in general, much less critical than in a
single-sided amplifier; and where the minimization of board-
level components is especially crucial, it is possible that these
pins need no decoupling at all. On the other hand, when the
signal source is single-sided, giving extra attention to the
decoupling on Pin VPSI is sometimes required. Likewise,
care is required in decoupling the VPSO pin if the output is
loaded on only one of its two output pins. The general common
(COMM) and the output stage common (CMOP) are usually
grounded as shown in the Figure 57; however, the Applications
section shows how a negative supply can optionally be used.
The AD8330 is enabled by taking the ENBL pin to a logical high
(or, in all cases, the supply). The UP gain mode is enabled either
by leaving the MODE pin unconnected or taking it to a logical
high. When the opposite gain direction is needed, the MODE
pin should be grounded or driven to a logical low. The low-pass
corner of the offset loop is determined by Capacitor CHPF; this
is preferably tied to the CNTR pin that in turn, should be
decoupled to ground. The gain interface common pin (CMGN)
is grounded, and the output magnitude control pin (VMAG) is
left unconnected, or can optionally be connected to a 500 mV
source for basic gain calibration.
AD8330
Rev. E | Page 21 of 32
Connections to the input and output pins are not shown in
Figure 57 because of the many options that are available. When
the AD8330 is used to drive an ADC, connect the OPHI and
OPLO pins directly to the differential inputs of a suitable converter,
such as an AD9214. If an adjustment is needed to this common-
mode level, it can be introduced by applying that voltage to the
CNTR pin, or, more simply, by using a resistor from this pin to
either ground or the supply (see the Applications section). The
CNTR pin can also supply the common-mode voltage to an
ADC that supports such a feature.
When the loads to be driven introduce a dc resistive path to
ground, coupling capacitors must be used. These should be of
sufficient value to pass the lowest frequency components of the
signal without excessive attenuation. Keep in mind that the
voltage swing on such loads alternates both above and below
ground, requiring that the subsequent component must be able
to cope with negative signal excursions.
Gain and Swing Adjustments When Loaded
The output can also be coupled to a load via a transformer to
achieve a higher load power by impedance transformation. For
example, using a 2:1 turns ratio, a 50 final load presents a
200 load on the output. The gain loss (relative to the basic
value with no termination) is 20 log10{(200+150)/200} or
4.86 dB, which can be restored by raising the voltage on the
VMAG pin by a factor of 104.86/20 or × 1.75, from its basic value
of 0.5 V to 0.875 V. This also restores the peak swing at the 200
level to ±2 V, or ±1 V into the 50 final load.
Whenever a stable supply voltage is available, additional voltage
swing can be provided by adding a resistor from the VMAG pin
to the supply. The calculation is based on knowing that the in-
ternal bias is delivered via a 5 k source; because an additional
0.375 V is needed, the current in this external resistor must be
0.375 V/5 k = 75 A. Thus, using a 5 V supply, a resistor of
5 V − 0.875 V/75 A = 55 k is used. Based on this example,
the corrections for other load conditions are easy to calculate.
If the effects on gain and peak output swing due to supply
variations cannot be tolerated, VMAG must be driven by an
accurate voltage.
Input Coupling
The dc common-mode voltage at the input pins varies with
the supply, the basic gain bias, and temperature (see Figure 55);
for this reason, many applications need to use coupling capaci-
tors from the source that are large enough to support the lowest
frequencies to be transmitted. Using one capacitor at each input
pin, their minimum values can be readily found from the expression
HPF
IN_CPL f
CF320
= (15)
where fHPF is the –3dB frequency expressed in hertz. Thus, for
an fHPF of 10 kHz, 33 nF capacitors are used.
Occasionally, it is possible to avoid the use of coupling
capacitors when the dc level of the driving source is within a
certain range, as shown in Figure 56. This range extends from
3.5 V to 4.5 V when using a 5 V supply, and at high basic gains,
where the effect of an incorrect dc level degrades the noise level
due to internal aspects of the input stage. For example, suppose
the driver, IC, is an LNA having an output topology in which its
load resistors are taken to the supply, and the output is buffered
by emitter followers. This presents a source for the AD8330 that
can readily be directly coupled.
DC-Coupled Signal Path
In many cases, where the VGA is not required to provide its
lowest noise, the full common-mode input range of zero to VS
can be used without problems, avoiding the need for any ac
coupling means. However, such direct coupling at both the input
and output does not automatically result in a fully dc-coupled
signal path. The internal offset compensation loop must also be
disengaged by connecting the OFST pin to ground. Keep in
mind that at the maximum basic gain of 50 dB (×316), every
millivolt of offset at the input, arising from whatever source,
causes an output offset of 316 mV, which is an appreciable
fraction of the peak output swing.
Because the offset correction loop is placed after the front-end
variable gain sections of the AD8330, the most effective way
of dealing with such offsets is at the input pins, as shown in
Figure 58. For example, assume, for illustrative purposes, that
the resistances associated with each side of the source in a cer-
tain application are 50 . If this source has a very low (op amp)
output impedance, the extra resistors should be inserted, with a
negligible noise penalty and an attenuation of only 0.83 dB. The
resistor values shown provide a trim range of about ±2 mV.
COMM
OPHI
INLO OPLO
INHI
VPSI VPSO
CMOP
MODE
VDBS CMGN VMAG
OFST RTNCLBNEVPOS
BIAS AND
V-REF
GAIN INTERFACE
CM MODE AN D
OF F SE T CO NT ROL
OUTPUT
STAGES
OUTPUT
CONTROL
VG A C O RE OUTPUT,
±2V MAX
NC
BASI C GAIN BI A S
V
DBS:
0V TO 1. 5V
1DR
CD1 CD3
RD2
50kΩ
75kΩ
R
S
ASSU M E D
TO BE 50Ω
ON EACH
SIDE
GROUND
03217-059
CD2
V
S
2.7V T O 6V
Figure 58. Input Offset Nulling in a DC-Coupled System
AD8330
Rev. E | Page 22 of 32
FREQUE NCY ( Hz)
90
50k
CMRR (dB)
–10
10
30
50
70
M001M1k001
80
0
20
40
60
10M
OFST: ENABLED
DISABLED
V
DBS
= 1.5V
V
DBS
= 0. 75 V
V
DBS
= 0V
03217-060
Figure 59. Input CMRR vs. Frequency for Various Values of VDBS
Using Single-Sided Sources and Loads
Where the source provides a single-sided output, either INHI
or INLO can be used for the input, with a polarity change when
using INLO. The unused pin must be connected either through
a capacitor to ground, or through a dc bias point that corresponds
closely to the dc level on the active signal pin. The input CMRR
over the full frequency range is illustrated in Figure 59. In some
cases, an additional element such as a SAW filter (having a
single-sided balanced configuration) or a flux-coupled trans-
former can be interposed. Where this element must be terminated
in the correct impedance, other than 1 k, it is necessary to add
either shunt or series resistors at this interface.
FREQUE NCY (Hz)
30
1M
–600
PHASE (Degrees)
–20
–30
–10
0
10
20
–400
–300
–200
–100
0
LINE 1
LINE 3
LINE 4
LINE 2
LINE 4
LINE 1
LINE 3
LINE 2
10M 100M 500M
–500
03217-061
GAIN (dB)
Figure 60. AC Gain and Phase for Various Loading Conditions
When driving a single-sided load, either OPHI or OPLO can be
used. These outputs are very symmetric, so the only effect of
this choice is to select the desired polarity. However, when the
frequency range of interest extends to the upper limits of the
AD8330, a dummy resistor of the same value should be attached
to the unused output. Figure 60 illustrates the ac gain and phase
response for various loads and VDBS = 0.75 V. Line 1 shows the
unloaded (CL = 12 pF) case for reference; the gain is 6 dB lower
(20 dB) using only the single-sided output. Adding a 75 load
from OPHI to an ac ground results in Line 2. The gain becomes
a factor of ×1.5 V or 3.54 dB lower, but artifacts of the output
common-mode control loop appear in both the magnitude and
phase response.
Adding a dummy 75 to OPLO results in Line 3: the gain is a
further 2.5 dB lower, at about 14 dB. The CM artifacts are no
longer present but a small amount of peaking occurs. If objec-
tionable, this can be eliminated by raising both of the capacitors
on the output pins to 25 pF, as shown in Line 4 of Figure 60.
The gain reduction incurred both by using only one output and
by the additional effect of loading can be overcome by taking
advantage of the VMAG feature, provided primarily for just such
circumstances. Thus, to restore the basic gain in the first case
(Line 1), a 1 V source should be applied to this pin; to restore the
gain in the second case, this voltage should be raised by a factor
of ×1.5 to 1.5 V. In Case 3 and Case 4, a further factor of ×1.33
is needed to make up the 2.5 dB loss, that is, VMAG should be
raised to 2 V. With the restoration of gain, the peak output
swing at the load is, likewise restored to ±2 V.
Pulse Operation
When using the AD8330 in applications where its transient
response is of greater interest and the outputs are conveyed to
their loads via coaxial cables, the added capacitances can slightly
differ in value, and can be placed either at the sending or load
end of the cables, or divided between these nodes. Figure 61
shows an illustrative example where dual, 1 meter, 75 cables
are driven through dc-blocking capacitors and are independently
terminated at ground level.
Because of the considerable variation between applications,
only general recommendations can be made with regard to
minimizing pulse overshoot and droop. The former can be
optimized by adding small load capacitances, if necessary;
the latter requires the use of sufficiently large capacitors (C1).
COMM
OPHI
INLO OPLO
INHI
VPSI VPSO
CMOP
MODE
VDBS CMGN VMAG
OFST RTNCLBNEVPOS
BIAS AND
V-REF
GAI N INT ERFACE
CM MO DE AND
OF FSET CONTROL
OUTPUT
STAGES
OUTPUT
CONTROL
VGA CORE
NC
CD2
CD3
RD2 V
S
2.7V–6V
C1
C1
CL1
CL2
RL1
RL2
03217-062
Figure 61. Driving Dual Cables with Grounded Loads
AD8330
Rev. E | Page 23 of 32
1.2
0 5ns 10ns 15ns 25ns20ns
1.0
0.8
0.6
0.4
0.2
0
–
0.2
0.2
–
0.4
–
0.6
–
0.8
–
1.0
–
1.2
0
–
0.2
1.2
1.0
0.8
0.6
0.4
0.2
0
–
0.2
0.2
0
–
0.2
–
0.4
–
0.6
–
0.8
–
1.0
–
1.2
03217-063
Figure 62. Typical Pulse Response for Figure 61
Figure 62 shows typical results for VDBS = 0.24 V, a square wave
input amplitude of 450 mV (the actual combination is not
important), a rise time of 2 ns, and VMAG raised to 2.0 V. In the
upper waveforms, the load capacitors are both zero, and a small
amount of overshoot is visible; with 40 pF, the response is cleaner.
A shunt capacitance of 20 pF from OPHI to OPLO has a similar
effect. Coupling capacitors for this demonstration are suffi-
ciently large to prevent any visible droop over this time scale.
The outputs at the load side eventually assume a mean value of
zero, with negative and positive excursions depending on the
duty cycle.
The bandwidth from Pin VMAG to these outputs is somewhat
higher than from the normal input pins. Thus, when this pin is
used to rapidly modulate the primary signal, some further
experimentation with response optimization may be required.
In general, the AD8330 is very tolerant of a wide range of
loading conditions.
Preserving Absolute Gain
Although the AD8330 is not laser trimmed, its absolute gain
calibration, based mainly on ratios, is very good. Full details are
found in the Specifications section and in the typical performance
curves (see the Typical Performance Characteristics section).
Nevertheless, having finite input and output impedances, the
gain is necessarily dependent on the source and load conditions.
The loss that is incurred when either of these is finite causes an
error in the absolute gain. The absolute gain can also be
uncertain due to the approximately ±20% tolerance in the
absolute value of the input and output impedances.
Often, such losses and uncertainties can be tolerated and
accommodated by a correction to the gain control bias. On the
other hand, the error in the loss can be essentially nulled by
using appropriate modifications to either the source impedance
(RS) or the load impedance (RL), or both (in some cases by
padding them with series or shunt components).
The formulation for this correction technique was previously
described. However, to simplify its use, Table 5 shows spot
values for combinations of RS and RL resulting in an overall loss
that is not dependent on sample-to-sample variations in on chip
resistances. Furthermore, this fixed and predictable loss can be
corrected by an adjustment to VMAG , as indicated in Table 5.
Table 5. Preserving Absolute Gain
Uncorrected Loss
VMAG Required to
Correct Loss
RS (Ω) RL (Ω) Factor dB
10 15 k 0.980 0.17 0.510
15 10 k 0.971 0.26 0.515
20 7.5 k 0.961 0.34 0.520
30 5.0 k 0.943 0.51 0.530
50 3.0 k 0.907 0.85 0.551
75 2.0 k 0.865 1.26 0.578
100 1.5 k 0.826 1.66 0.605
150 1.0 k 0.756 2.43 0.661
200 750 0.694 3.17 0.720
300 500 0.592 4.56 0.845
500 300 0.444 7.04 1.125
750 200 0.327 9.72 1.531
1 k 150 0.250 12.0 2.000
1.5 k 100 0.160 15.9 3.125
2 k 75 0.111 19.1 4.500
Calculation of Noise Figure
The AD8330 noise is a consequence of its intrinsic voltage noise
spectral density (ENSD) and the current noise spectral density
(INSD). Their combined effect generates a net input noise,
VNOISE_IN, that is a function of the input resistance of the device
(RI), nominally 1 k, and the differential source resistance (RS)
as follows:
(
{
)
}
2
22
_++= S
I
NSDNSDINNOISE RRIEV (16)
Note that purely resistive source and input impedances as a conces-
sion to simplicity is assumed. A more thorough treatment of
noise mechanisms, for the case where the source is reactive, is
beyond the scope of these brief notes. Also note that VNOISE_IN is
the voltage noise spectral density appearing across INHI and
INLO, the differential input pins. In preparing for the calculation
of the noise figure, VSIG is defined as the open-circuit signal
voltage across the source, and VIN is defined as the differential
input to the AD8330. The relationship is simply
()
S
I
I
SIG
IN RR
RV
V+
= (17)
At maximum gain, ENSD is 4.1 nV/√Hz, and INSD is 3 pA/√Hz.
Thus, the short-circuit voltage noise is
(
)()
(
)
{
}
=+Ω+= 2
22
_0k1Hz/pA3Hz/Vn1.4
INNOISE
V
5.08 nV/√Hz (18)
Next, examine the net noise when RS = RI = 1 k, often incor-
rectly called the matching condition, rather than source impedance
termination, which is the actual situation in this case.
AD8330
Rev. E | Page 24 of 32
Repeating the procedure,
()()
()
2
22
_k1k1Hz/pA3Hz/nV1.4 ++=
INNOISE
V
= 7.3 nV/√Hz (19)
The noise figure is the decibel representation of the noise factor,
NFAC, commonly defined as follows:
outputatSNR
inputatSNR
NFAC = (20)
However, this is equivalent to
pinsinputtheatSNR
sourcetheatSNR
=NFAC (21)
Let VNSD be the voltage noise spectral density √kTRS due to the
source resistance. Using Equation 17 gives
(
)
{
}
()
{}
NSDS
INNOISE
I
S
I
SINNOISE
IN
NSDS
II
SIG
FAC
VR
VR
RRRVV
VRRRV
N
_
_//
//
=
+
+
=
(22)
Then, using the result from Equation 19 for a source resistance
of 1 k, having a noise-spectral density of 4.08 nV/√Hz
produces
()
(
)
()
()
79.1
HznV/08.4k1
Hz/nV3.7k1==
FAC
N (23)
Finally, converting this to decibels using
NFIG = 10 log10(NFAC) (24)
Thus, the resultant noise figure in this example is 5.06 dB,
which is somewhat lower than the value shown in Figure 53 for
this operating condition.
Noise as a Function of VDBS
The chief consequence of lowering the basic gain using VDBS is
that the current noise spectral density INSD increases with the
square root of the basic gain magnitude, GBN such that
INSD = (3 pA/√Hz)(√GBN) (25)
Therefore, at the minimum basic gain of ×0, INSD rises to
53.3 pA/√Hz. However, the noise figure rises to 17.2 db if it
is recalculated using the procedures in Equation 16 through
Equation 24.
Distortion Considerations
Continuously variable gain amplifiers invariably employ
nonlinear circuit elements; consequently, it is common for their
distortion to be higher than well-designed fixed gain amplifiers.
The translinear multiplier principles used in the AD8330, in
theory, yield extremely low distortion, a result of the funda-
mental linearization technique that is an inherent aspect of
these circuits.
In practice, however, the effect of device mismatches and junc-
tion resistances in the core cell, and other mechanisms in its
supporting circuitry inevitably cause distortion, further aggravated
by other effects in the later output stages. Some of these effects
are very consistent from one sample to the next, while those due
to mismatches (causing predominantly even-order distortion
components) are quite variable. Where the highest linearity
(and lowest noise) is demanded, consider using one of the X-
AMP products such as the AD603 (single-channel), AD604
(dual-channel), or AD8332 (wideband dual-channel with
ultralow noise LNAs).
P1dB and V1dB
In addition to the nonlinearities that arise within the core of the
AD8330, at moderate output levels, another metric that is more
commonly stated for RF components that deliver appreciable
power to a load is the 1 dB compression point. This is defined
in a very specific manner: it is that point at which, with increasing
output level, the power delivered to the load eventually falls to a
value that is 1 dB lower than it would be for a perfectly linear
system. (Although this metric is sometimes called the 1 dB gain
compression point, it is important to note that this is not the
output level at which the incremental gain has fallen by 1 dB).
As shown in Figure 49, the output of the AD8330 limits quite
abruptly, and the gain drops sharply above the clipping level.
The output power, on the other hand, using an external resistive
load, RL, continues to increase. In the most extreme case, the
waveform changes from the sinusoidal form of the test signal,
with an amplitude just below the clipping level, VCLIP, to a
square wave of precisely the same amplitude. The change in
power over this range is from (VCLIP/√2)2/RL to (VCLIP)2/RL, that
is, a factor of 2, or 3 dB in power terms. It can be shown that for
an ideal limiting amplifier, the 1 dB compression point occurs
for an overdrive factor of 2 dB.
For example, if the AD8330 is driving a 150 load and VMAG is
set to 2 V, the peak output is nominally ±4 V (as noted previously,
the actual value, when loaded. can differ because of a mismatch
between on-chip and external resistors), or 2.83 V rms for a sine
wave output that corresponds to a power of 53.3 mW, that is,
17.3 dBm in 150 . Thus, the P1dB level, at 2 dB above
clipping, is 19.3 dBm.
Though not involving power transfer, it is sometimes useful
to state the V1dB, which is the output voltage (unloaded or
loaded) that is 2 dB above clipping for a sine waveform. In the
above example, this voltage is still 2.83 V rms, which can be
expressed as 9.04 dBV (0 dBV corresponds to a 1 V sine wave).
Thus, the V1dB is at 11.04 dBV.
AD8330
Rev. E | Page 25 of 32
APPLICATIONS INFORMATION
The versatility of the AD8330, its very constant ac response over
a wide range of gains, the large signal dynamic range, output
swing, single supply operation, and low power consumption
commend this VGA to a diverse variety of applications. Only a
few can be described here, including the most basic uses and some
unusual ones.
from VMAG to ground. An overrange condition is signaled by a
high state on Pin OR of the AD9214. DFS/GAIN is unconnected
in this example producing an offset-binary output. To provide a
twos complement output, it should be connected to the REF pin.
For ADCs running at sampling rates substantially below the
bandwidth of the AD8330, an intervening noise filter is
recommended to limit the noise bandwidth. A one-pole filter
can easily be created with a single differential capacitor between
the OPHI and OPLO outputs. For a corner frequency of fC, the
capacitor should have a value of
ADC DRIVING
The AD8330 is well-suited to drive a high speed converter.
There are many high speed converters available, but to illustrate
the general features, the example in this data sheet uses one of
the least expensive, the AD9214. This is available in three
grades for operation at 65 MHz, 80 MHz, and 105 MHz; the
AD9214BRS-80 is a good complement to the general capabili-
ties of this VGA.
CFILT = 1/942 fC (26)
For example, a 10 MHz corner requires about 100 pF.
SIMPLE AGC AMPLIFIER
Figure 64 illustrates the use of the inverted gain mode and the
offset gain range (0.2 V < VDBS < 1.7 V) in supporting a low cost
AGC loop. Q1 is used as a detector. When OPHI is sufficiently
higher than CNTR, due to the signal swing, it conducts and
charges C1. This raises VDBS and rapidly lowers the gain. Note
that MODE is grounded (see Figure 48). The minimum voltage
needed across R1 to set up the full gain is 0.2 V because CMGN
is dc open-circuited (this does not alter VMAG) and the maxi-
mum voltage is 1.7 V.
Figure 63 shows the connections to drive an ADC. A 3.3 V
supply is used for both parts. The ADC requires that its input
pins be positioned at one third of the supply, or 1.1 V. Given
that the default output level of the VGA is one-half the supply
or 1.65 V, a small correction is introduced by the 8 k resistor
from CNTR to ground. The ADC specifications require that the
common-mode input be within ±0.2 V of the nominal 1.1 V;
variations of up to ±20% in the AD8330 on-chip resistors change
this voltage by only ±70 mV. With the connections shown in
Figure 63, the AD9214 is able to receive an input of 2 V p-p; the
peak output of the AD8330 can be reduced if desired by adding
a resistor
COMM
OPHI
INLO OPLO
INHI
VPSI VPSO
CMOP
MODE
VDBS CMGN
OFST CNTRENBL VPOS
BIAS AN D
V-REF CM MO DE AND
OFF SET CONT ROL
OUTPUT
STAGES
OUTPUT
CONTROL
VG A CORE
AD9214BRS-80
DATA OUTPUTS
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DGND
CLK
AGND
CLOCK
REF
0.1µF
REFSENSE
NC
ANALOG GROUND
A
IN
A
IN
DFS/GAIN
PWRDN
DIGITAL
GROUND
GA I N BIAS,
V
DBS
, 0V–1.5V
NC
INPUT,
±
2V MA X
0.1µF
10Ω
GAIN INTERFACE
CHPF
8kΩ
0.1µF 0.1µF
AV
DD
OR DrV
DD
3.3ΩOVER-
RANGE
3.3Ω
0.1µF
V
S
,3.3
V
03217-064
VMAG
Figure 63. Driving an Analog-to-Digital Converter (Preliminary)
AD8330
Rev. E | Page 26 of 32
COMM
OPHI
INLO OPLO
INHI
VPSI VPSO
CMOP
MODE
VDBS CMGN VMAG
OFST CNTRENBL VPOS
BIAS AND
V-REF CM MODE AND
OF FSET CONTROL
OUTPUT
STAGES
NC
INPUT,
5
mV TO 1V rms
0.1µF
10Ω
GAIN INTERFACE
33nF
R1
10kΩ0.1µF
0.1µF
4.7Ω
Q2 Q1
SEE
TEXT
C1
0.1µF
0.1µF
OUTPUT,
~1V rms
03217-065
V
S
,2.7V–6
V
OUTPUT
CONTROL
VGA CORE
Figure 64. Simple AGC Amplifier (Preliminary)
When the loop is settled, the average current in Q1 is VDBS/R1,
which varies from 2 A at maximum gain (VDBS = 0.2 V) to
17 A at minimum gain (VDBS = 1.7 V). This change in the Q1
current causes an increase of ~0.25 dB over the full gain range
in the differential output of nominally 0.75 dBV at midrange
(3.08 V p-p), corresponding to a 200:1 compression ratio. This
is plotted in Figure 65 for a representative 100 kHz input.
INPUT TO AD8330 ( d BV)
1.0
002–04–05–
LEVELED OUTPUT (dBV)
0.8
0.7
0.6
0.5 –30
0.9
–10
03217-066
Figure 65. AGC Output vs. Input Amplitude (Simulation)
The upper panel in Figure 66 shows the time-domain output for
fourteen 3 dB steps in input amplitude from 5.4 mV to 1.7 V.
The waveforms in Figure 65 show the AGC voltage (VDBS).
This simple detector exhibits a temperature variation in the
differential output amplitude of about 4 mV/°C. It provides a
fast attack time (an increase in the input is quickly leveled to the
nominal output, due to the high peak currents in Q1) and a
slow release time (a decrease in the input is not restored as
quickly). The voltage at the VDBS pin can be used as an RSSI
output, scaled 30 mV/dB. Note that the attack time can be
halved by adding a second transistor, labeled Q2 in Figure 64.
For operation at lower frequencies, the AGC hold capacitor
must be increased.
WIDE RANGE TRUE RMS VOLTMETER
The AD8362 is an rms responding detector providing a
dynamic range of 60 dB from low frequencies to 2.7 GHz.
This can increase to 110 dB using an AD8330 as a precondi-
tioner, provided the noise bandwidth is limited by an interstage
low-pass or band-pass filter.
The VGA also provides an input port that is easier to drive
than the 200 input of the AD8362. Figure 67 shows the
general scheme.
Both the AD8330 and AD8362 provide linear-in-decibel control
interfaces. Thus, when the output of the AD8362 is used to control
the gain of the AD8330, the functional form is unaffected. The
overall scaling is 33 mV/dB. Figure 68 shows the time domain
response using a loop filter capacitor of 10 nF, for inputs rang-
ing from 10 V to 1 V rms, that is, a 100 dB measurement range.
TIME (µs)
0
GAIN ER
R
OR (dB)
–1
1
–3
3
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
–2
0
–4
2
0.75
1.25
0.25
1.75
0.50
1.00
0
1.50 V
DBS
OUTPUT
03217-067
Figure 66. Time Domain Waveforms (Simulation)
AD8330
Rev. E | Page 27 of 32
OFSTENBL CNTRVPOS
OSPV1SPV
IHPOIHNI
OLPOOLNI
POMCEDOM
VMAGCOMMCMGNVDBS
AD8330
COMM
CHPF
DECL
INHI
INLO
DECL
PWDN
COMM
1
2
3
4
5
6
7
8
ACOM
VREF
VTGT
VPOS
VOUT
VSET
ACOM
CLPF
16
15
14
13
12
11
10
9
AD8362
10µF
VOUT
6.04kΩ
4.02kΩ
C
FLT
18nF 3.6V
3.6V 10µF
3.3Ω3.3Ω
5
V
3.3Ω
0.1µF 0.1µF 0.1µF 0.1µF
0.1µF
INPUT
0
3217-068
Figure 67. Wide Range True RMS Voltmeter (Preliminary)
TIME (ms)
4
08.44.0
OUTPUT (V)
0
3
2
1
0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4
03217-069
Figure 68. Time Domain Response of RMS Voltmeter (Simulation)
AD8330
Rev. E | Page 28 of 32
EVALUATION BOARD
GENERAL DESCRIPTION BASIC OPERATION
The AD8330-EVALZ is an easy-to-use accessory that enables a
hands-on evaluation of the AD8330 variable gain amplifier
(VGA). It includes test pins for connections to all of the functional
device inputs. Figure 69 is a full size photograph of the board.
The input SMA connector IN is terminated with a 49.9 Ω
resistor (see Figure 70). For convenience, the board includes an
AD8131 high speed differential amplifier to convert a single-
ended signal source to the differential input of the AD8330. If
desired, the AD8131 can be removed and the AD8330 can be
driven at one of its inputs from a single-ended source.
03217-070
The AD8330 output is observed at the SMA connectors OUT_HI
and OUT_LO or by using the 2-pin header OUT_HI/ OUT_LO
adjacent to the device.
The AD8330 requires only a +5 V power supply; however, because
of the AD8131 buffer bipolar power supply requirements, ±5 V
supplies are required to power the board. The current required
for the board is approximately 40 mA from the +5 V supply and
10 mA from the −5 V supply.
Figure 69. Photograph of the AD8330 Evaluation Board
0
3217-071
8
7
2
3
9
GAIN_SLOPE
C5
0.1µF
C3
0.1µF
INLO
MODE
VPSI
INHI
VPSO
CMOP
OPLO
CNTR
OFST
OPHI
8
ENBL
VPOS
+5V
1
6
5
4
15
16
14
13
COMM
VMAGVDBS
CMGN
12
11
10
C2
0.1µF
UP
C18
0.1µF
+5V
C6
0.1µF
IN
+5V
C7
0.1µF
CMGN
VDBS VMAG
C10
0.1µF
C19
0.1µF
C11
0.1µF C4
0.1µF
+5V
C14
10nF
C15
0.1µF
CNTR
ENBL
34
5
6
1
2
C16
10nF
C20
0.1µF
C17
10µF
10V
–5V
GND1 GND2 GND3 GND4
FLTR
C9
12pF
C8
12pF
C12
0.1µF
R4
0Ω
R2
49.9Ω
R1
24.9Ω
OUT_HI
OUT_ LO
R3
1kΩ
OUT_TEST
IN_TEST
C1
10µF
10V
+
OFST
C13
1nF
DOWN
+
A1
DUT1
AD8330
FILTER_OFFSET
AD8131
Figure 70. Schematic Diagram
AD8330
Rev. E | Page 29 of 32
OPTIONS
Table 6 lists the jumpers on the board and their functions.
Table 6. Functions of Jumpers
Name Function
FLTR Connects a high-pass filter to the offset control loop
pin. This jumper is normally not installed.
OFST Disables the offset correction loop. This jumper is
installed for dc or low frequency operation.
UP Mode up. Install for ascending gain with increasing
VDBS gain control voltage.
DOWN Mode down. Install for descending gain with
increasing VDBS gain control voltage.
MEASUREMENT SETUP
The basic board connections for a typical measurement are
shown in Figure 71. To minimize circuit-loading effects, a low
capacitance FET probe is recommended for observing input or
output waveforms. Two-pin headers, IN_TEST and OUT_TEST,
are provided for this purpose. The SMA connectors OUT_HI
and OUT_LO can also be used, but the user may need to
account for load capacitance effects.
AD8330-EVALZ BOARD DESIGN
The AD8330-EVALZ is a 4-layer design for maximum ground-
plane area. The evaluation board side silkscreen and wiring
patterns are shown in Figure 72 through Figure 77.
NETWOR
K
ANALYZER
DIFFERENTIAL
PROBE
+5V
PROBE
POW ER S UPPL Y
GND
03217-072
PRECI S ION V OLTAG E REFERE NCES
(FOR VDBS, VMAG)
POWER SUPPLY
SIGNAL
INPUT
Figure 71. Typical Connections
AD8330
Rev. E | Page 30 of 32
03217-073
Figure 72. Component-Side Silkscreen
03217-074
Figure 73. Component-Side Wiring
03217-075
Figure 74. Ground Plane
03217-076
Figure 75. Wiring-Side Silkscreen
03217-077
Figure 76. Wiring-Side Pattern
03217-078
Figure 77. Inner Layer 2
AD8330
Rev. E | Page 31 of 32
OUTLINE DIMENSIONS
*COMPLIANT
TO
JEDEC S T ANDARDS M O-220-VEE D- 2
EXCEPT F OR EXP OSED P AD DIMENS ION.
1
0.50
BSC
0.60 MA X
PIN 1
INDICATOR
1.50 RE F
0.50
0.40
0.30
0.25 M IN
0.45
2.75
BSC SQ
TOP
VIEW
12° M AX 0.80 M A X
0.65 TYP
SEATING
PLANE
PIN 1
INDICATOR
0.90
0.85
0.80
0.30
0.23
0.18
0.05 M A X
0.02 NOM
0.20 REF
3.00
BSC SQ
*1.65
1.50 SQ
1.35
16
5
13
8
9
12
4
EXPOSED
PAD
BOTTOM VIEW
071708-A
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE P IN CONFI GURATION AND
FUNCT ION DE S CRIPT IONS
SECT ION OF THIS DATA SHEE T.
Figure 78. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm × 3 mm Body, Very Thin Quad
(CP-16-3)
Dimensions shown in millimeters
COMPLIANT TO JEDEC STANDARDS MO-137-AB
16 9
8
1
PIN 1
SEATING
PLANE
0.010
0.004 0.012
0.008
0.025
BSC 0.010
0.006
0.050
0.016
8°
0°
COPLANARITY
0.004
0.065
0.049 0.069
0.053
0.197
0.193
0.189
0.158
0.154
0.150 0.244
0.236
0.228
Figure 79. 16-Lead Shrink Small Outline Package [QSOP]
(RQ-16)
Dimensions shown in inches
AD8330
Rev. E | Page 32 of 32
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Branding
AD8330ACPZ-R2 −40°C to +85°C 16-Lead LFCSP_VQ CP-16-3 JFZ
AD8330ACPZ-RL −40°C to +85°C 16-Lead LFCSP_VQ CP-16-3 JFZ
AD8330ACPZ-R7 −40°C to +85°C 16-Lead LFCSP_VQ CP-16-3 JFZ
AD8330ARQ −40°C to +85°C 16-Lead QSOP RQ-16
AD8330ARQ-REEL −40°C to +85°C 16-Lead QSOP RQ-16
AD8330ARQ-REEL7 −40°C to +85°C 16-Lead QSOP RQ-16
AD8330ARQZ −40°C to +85°C 16-Lead QSOP RQ-16
AD8330ARQZ-RL −40°C to +85°C 16-Lead QSOP RQ-16
AD8330ARQZ-R7 −40°C to +85°C 16-Lead QSOP RQ-16
AD8330-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
©2003–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03217-0-3/10(E)
