LP3875-ADJ
1.5A Fast Ultra Low Dropout Linear Regulators
General Description
The LP3875-ADJ fast ultra low-dropout linear regulators op-
erate from a +2.5V to +7.0V input supply. These ultra low
dropout linear regulators respond very quickly to step
changes in load, which makes them suitable for low voltage
microprocessor applications. The LP3875-ADJ is developed
on a CMOS process which allows low quiescent current
operation independent of output load current. This CMOS
process also allows the LP3875-ADJ to operate under ex-
tremely low dropout conditions.
Dropout Voltage: Ultra low dropout voltage; typically 38mV
at 150mA load current and 380mV at 1.5A load current.
Ground Pin Current: Typically 6mA at 1.5A load current.
Shutdown Mode: Typically 10nA quiescent current when
the shutdown pin is pulled low.
Adjustable Output Voltage: The output voltage may be
programmed via two external resistors.
Features
nUltra low dropout voltage
nLow ground pin current
nLoad regulation of 0.06%
n10nA quiescent current in shutdown mode
nGuaranteed output current of 1.5A DC
nAvailable in TO-263 and TO-220 packages
nMinimum output capacitor requirements
nOvertemperature/overcurrent protection
n−40˚C to +125˚C junction temperature range
Applications
nMicroprocessor power supplies
nGTL, GTL+, BTL, and SSTL bus terminators
nPower supplies for DSPs
nSCSI terminator
nPost regulators
nHigh efficiency linear regulators
nBattery chargers
nOther battery powered applications
Typical Application Circuit
20074645
*See Application Hints
September 2003
LP3875-ADJ 1.5A Fast Ultra Low Dropout Linear Regulators
© 2003 National Semiconductor Corporation DS200746 www.national.com
Connection Diagrams
20074605
Top View
TO220-5 Package
Bent, Staggered Leads
20074606
Top View
TO263-5 Package
Pin Description for TO220-5 and TO263-5 Packages
Pin # LP3875-ADJ
Name Function
1SD
Shutdown
2V
IN
Input Supply
3 GND Ground
4V
OUT
Output Voltage
5 ADJ Set Output Voltage
Ordering Information
20074631
Package Type Designator is "T" for TO220 package, and "S" for TO263 package.
TABLE 1. Package Marking and Ordering Information
Output
Voltage Order Number
Current
Description Package Type Package Marking Supplied As:
ADJ LP3875ES-ADJ 1.5A TO263-5 LP3875ES-ADJ Rail
ADJ LP3875ESX-ADJ 1.5A TO263-5 LP3875ES-ADJ Tape and Reel
ADJ LP3875ET-ADJ 1.5A TO220-5 LP3875ET-ADJ Rail
LP3875-ADJ
www.national.com 2
Block Diagram
LP3875-ADJ
20074629
LP3875-ADJ
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature Range −65˚C to +150˚C
Lead Temperature
(Soldering, 5 sec.) 260˚C
ESD Rating (Note 3) 2 kV
Power Dissipation (Note 2) Internally Limited
Input Supply Voltage (Survival) −0.3V to +7.5V
Shutdown Input Voltage
(Survival) −0.3V to +7.5V
Output Voltage (Survival), (Note
6), (Note 7) −0.3V to +6.0V
I
OUT
(Survival) Short Circuit Protected
Operating Ratings
Input Supply Voltage (Operating),
(Note 10) 2.5V to 7.0V
Shutdown Input Voltage
(Operating) −0.3V to 7.0V
Maximum Operating Current (DC) 1.5A
Operating Junction Temp. Range −40˚C to +125˚C
Electrical Characteristics
LP3875-ADJ
Limits in standard typeface are for T
J
= 25˚C, and limits in boldface type apply over the full operating temperature range.
Unless otherwise specified: V
IN
=V
O(NOM)
+ 1V, I
L
= 10 mA, C
OUT
= 10µF, V
SD
= 2V.
Symbol Parameter Conditions Typ
(Note 4)
LP3875-ADJ
(Note 5)
Units
Min Max
V
ADJ
Adjust Pin Voltage V
OUT
+1V ≤V
IN
≤7V
10 mA ≤I
L
≤1.5A 1.216 1.198
1.180
1.234
1.253 V
I
ADJ
Adjust Pin Input Current V
OUT
+1V ≤V
IN
≤7V
10 mA ≤I
L
≤1.5A 10 100 nA
∆V
OL
Output Voltage Line
Regulation (Note 8)
V
OUT
+1V ≤V
IN
≤7.0V 0.02
0.06
%
∆V
O
/∆I
OUT
Output Voltage Load
Regulation
(Note 8)
10 mA ≤I
L
≤1.5A 0.06
0.12
%
V
IN
-V
OUT
Dropout Voltage
(Note 9)
I
L
= 150 mA 38 50
60 mV
I
L
= 1.5A 380 450
550
I
GND
Ground Pin Current In
Normal Operation Mode
I
L
= 150 mA 5 9
10 mA
I
L
= 1.5A 6 14
15
I
GND
Ground Pin Current In
Shutdown Mode
V
SD
≤0.3V 0.01 10 µA
-40˚C ≤T
J
≤85˚C 50
I
O(PK)
Peak Output Current V
O
≥V
O(NOM)
- 4% 1.8 A
Short Circuit Protection
I
SC
Short Circuit Current 3.2 A
LP3875-ADJ
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Electrical Characteristics
LP3875-ADJ (Continued)
Limits in standard typeface are for T
J
= 25˚C, and limits in boldface type apply over the full operating temperature range.
Unless otherwise specified: V
IN
=V
O(NOM)
+ 1V, I
L
= 10 mA, C
OUT
= 10µF, V
SD
= 2V.
Symbol Parameter Conditions Typ
(Note 4)
LP3875-ADJ
(Note 5)
Units
Min Max
Shutdown Input
V
SDT
Shutdown Threshold Output = High V
IN
2V
Output = Low 0 0.3
T
dOFF
Turn-off delay I
L
= 1.5A 20 µs
T
dON
Turn-on delay I
L
= 1.5A 25 µs
I
SD
SD Input Current V
SD
=V
IN
1nA
AC Parameters
PSRR Ripple Rejection
V
IN
=V
OUT
+1V
C
OUT
= 10uF
V
OUT
= 3.3V, f = 120Hz
73
dB
V
IN
=V
OUT
+ 0.5V
C
OUT
= 10uF
V
OUT
= 3.3V, f = 120Hz
57
ρ
n(l/f)
Output Noise Density f = 120Hz 0.8 µV
e
n
Output Noise Voltage
BW = 10Hz – 100kHz
V
OUT
= 2.5V
150
µV (rms)
BW = 300Hz – 300kHz
V
OUT
= 2.5V
100
Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which the device is
intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and test conditions, see Electrical Characteristics. The
guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed
test conditions.
Note 2: At elevated temperatures, devices must be derated based on package thermal resistance. The devices in TO220 package must be derated at θjA = 50˚C/W
(with 0.5in2, 1oz. copper area), junction-to-ambient (with no heat sink). The devices in the TO263 surface-mount package must be derated at θjA = 60˚C/W (with
0.5in2, 1oz. copper area), junction-to-ambient. See Application Hints.
Note 3: The human body model is a 100pF capacitor discharged through a 1.5kΩresistor into each pin.
Note 4: Typical numbers are at 25˚C and represent the most likely parametric norm.
Note 5: Limits are guaranteed by testing, design, or statistical correlation.
Note 6: If used in a dual-supply system where the regulator load is returned to a negative supply, the output must be diode-clamped to ground.
Note 7: The output PMOS structure contains a diode between the VIN and VOUT terminals. This diode is normally reverse biased. This diode will get forward biased
if the voltage at the output terminal is forced to be higher than the voltage at the input terminal. This diode can typically withstand 200mA of DC current and 1Amp
of peak current.
Note 8: Output voltage line regulation is defined as the change in output voltage from the nominal value due to change in the input line voltage. Output voltage load
regulation is defined as the change in output voltage from the nominal value due to change in load current.
Note 9: Dropout voltage is defined as the minimum input to output differential voltage at which the output drops 2% below the nominal value. Dropout voltage
specification applies only to output voltages of 2.5V and above. For output voltages below 2.5V, the drop-out voltage is nothing but the input to output differential,
since the minimum input voltage is 2.5V.
Note 10: The minimum operating value for VIN is equal to either [VOUT(NOM) +V
DROPOUT] or 2.5V, whichever is greater.
LP3875-ADJ
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Typical Performance Characteristics Unless otherwise specified: T
J
= 25˚C, C
OUT
= 10µF,
C
IN
= 10µF, S/D pin is tied to V
IN
,V
OUT
= 2.5V, V
IN
=V
O(NOM)
+ 1V, I
L
= 10mA
Dropout Voltage vs Output Load Current
Ground Current vs Output Voltage
I
L
= 1.5A
20074660
20074654
Shutdown I
Q
vs Junction Temperature DC Load Reg. vs Junction Temperature
20074655
20074658
DC Line Regulation vs Temperature Noise vs Frequency
20074659 20074661
LP3875-ADJ
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Typical Performance Characteristics Unless otherwise specified: T
J
= 25˚C, C
OUT
= 10µF,
CIN = 10µF, S/D pin is tied to V
IN
,V
OUT
= 2.5V, V
IN
=V
O(NOM)
+ 1V, I
L
= 10mA (Continued)
Load Transient Response
C
IN
=C
OUT
= 10µF, OSCON
Load Transient Response
C
IN
=C
OUT
= 100µF, OSCON
20074676 20074677
Load Transient Response
C
IN
=C
OUT
= 100µF, POSCAP
Load Transient Response
C
IN
=C
OUT
= 10µF, TANTALUM
20074678 20074679
Load Transient Response
C
IN
=C
OUT
= 100µF, TANTALUM
20074680
LP3875-ADJ
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Application Hints
V
IN
RESTRICTIONS FOR PROPER START-UP
To prevent misoperation, ensure that V
IN
is below 50mV
before start-up is initiated. This scenario can occur in sys-
tems with a backup battery using reverse-biased "blocking"
diodes which may allow enough leakage current to flow into
the V
IN
node to raise it’s voltage slightly above ground when
the main power is removed. Using low leakage diodes or a
resistive pull down can prevent the voltage at V
IN
from rising
above 50mV. Large bulk capacitors connected to V
IN
may
also cause a start-up problem if they do not discharge fully
before re-start is initiated (but only if V
IN
is allowed to fall
below 1V). A resistor connected across the capacitor will
allow it to discharge more quickly. It should be noted that the
probability of a "false start" caused by incorrect logic states
is extremely low.
SETTING THE OUTPUT VOLTAGE
The output voltage is set using the resistors R1 and R2 (see
Typical Application Circuit). The output is also dependent on
the reference voltage (typically 1.216V) which is measured
at the ADJ pin. The output voltage is given by the equation:
V
OUT
=V
ADJ
x(1+R1/R2)
This equation does not include errors due to the bias current
flowing in the ADJ pin which is typically about 10 nA. This
error term is negligible for most applications. If R1 is >
100kΩ, a small error may be introduced by the ADJ bias
current.
The tolerance of the external resistors used contributes a
significant error to the output voltage accuracy, with 1%
resistors typically adding a total error of approximately 1.4%
to the output voltage (this error is in addition to the tolerance
of the reference voltage at V
ADJ
).
EXTERNAL CAPACITORS
Like any low-dropout regulator, external capacitors are re-
quired to assure stability. These capacitors must be correctly
selected for proper performance.
INPUT CAPACITOR: An input capacitor of at least 10µF is
required. Ceramic Ceramic, Tantalum, or Electrolytic capaci-
tors may be used, and capacitance may be increased with-
out limit
OUTPUT CAPACITOR: An output capacitor is required for
loop stability. It must be located less than 1 cm from the
device and connected directly to the output and ground pins
using traces which have no other currents flowing through
them (see PCB Layout section).
The minimum value of output capacitance that can be used
for stable full-load operation is 10µF, but it may be increased
without limit. The output capacitor must have an ESR value
as shown in the stable region of the curve below. Tantalum
capacitors are recommended for the output capacitor.
ESR Curve
20074670
C
FF
(Feed Forward Capacitor)
The capacitor C
FF
is required to add phase lead and help
improve loop compensation. The correct amount of capaci-
tance depends on the value selected for R1 (see Typical
Application Circuit). The capacitor should be selected such
that the zero frequency as given by the equation shown
below is approximately 45 kHz:
Fz = 45,000=1/(2xπxR1xC
FF
)
A good quality ceramic with X5R or X7R dielectric should be
used for this capacitor.
SELECTING A CAPACITOR
It is important to note that capacitance tolerance and varia-
tion with temperature must be taken into consideration when
selecting a capacitor so that the minimum required amount
of capacitance is provided over the full operating tempera-
ture range. In general, a good Tantalum capacitor will show
very little capacitance variation with temperature, but a ce-
ramic may not be as good (depending on dielectric type).
Aluminum electrolytics also typically have large temperature
variation of capacitance value.
Equally important to consider is a capacitor’s ESR change
with temperature: this is not an issue with ceramics, as their
ESR is extremely low. However, it is very important in Tan-
talum and aluminum electrolytic capacitors. Both show in-
creasing ESR at colder temperatures, but the increase in
aluminum electrolytic capacitors is so severe they may not
be feasible for some applications (see Capacitor Character-
istics Section).
CAPACITOR CHARACTERISTICS
CERAMIC: For values of capacitance in the 10 to 100 µF
range, ceramics are usually larger and more costly than
tantalums but give superior AC performance for bypassing
high frequency noise because of very low ESR (typically less
than 10 mΩ). However, some dielectric types do not have
good capacitance characteristics as a function of voltage
and temperature.
Z5U and Y5V dielectric ceramics have capacitance that
drops severely with applied voltage. A typical Z5U or Y5V
capacitor can lose 60% of its rated capacitance with half of
the rated voltage applied to it. The Z5U and Y5V also exhibit
LP3875-ADJ
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Application Hints (Continued)
a severe temperature effect, losing more than 50% of nomi-
nal capacitance at high and low limits of the temperature
range.
X7R and X5R dielectric ceramic capacitors are strongly rec-
ommended if ceramics are used, as they typically maintain a
capacitance range within ±20% of nominal over full operat-
ing ratings of temperature and voltage. Of course, they are
typically larger and more costly than Z5U/Y5U types for a
given voltage and capacitance.
TANTALUM: Solid Tantalum capacitors are recommended
for use on the output because their typical ESR is very close
to the ideal value required for loop compensation. They also
work well as input capacitors if selected to meet the ESR
requirements previously listed.
Tantalums also have good temperature stability: a good
quality Tantalum will typically show a capacitance value that
varies less than 10-15% across the full temperature range of
125˚C to −40˚C. ESR will vary only about 2X going from the
high to low temperature limits.
The increasing ESR at lower temperatures can cause oscil-
lations when marginal quality capacitors are used (if the ESR
of the capacitor is near the upper limit of the stability range at
room temperature).
ALUMINUM: This capacitor type offers the most capaci-
tance for the money. The disadvantages are that they are
larger in physical size, not widely available in surface mount,
and have poor AC performance (especially at higher fre-
quencies) due to higher ESR and ESL.
Compared by size, the ESR of an aluminum electrolytic is
higher than either Tantalum or ceramic, and it also varies
greatly with temperature. A typical aluminum electrolytic can
exhibit an ESR increase of as much as 50X when going from
25˚C down to −40˚C.
It should also be noted that many aluminum electrolytics only
specify impedance at a frequency of 120 Hz, which indicates
they have poor high frequency performance. Only aluminum
electrolytics that have an impedance specified at a higher
frequency (between 20 kHz and 100 kHz) should be used for
the LP387X. Derating must be applied to the manufacturer’s
ESR specification, since it is typically only valid at room
temperature.
Any applications using aluminum electrolytics should be
thoroughly tested at the lowest ambient operating tempera-
ture where ESR is maximum.
PCB LAYOUT
Good PC layout practices must be used or instability can be
induced because of ground loops and voltage drops. The
input and output capacitors must be directly connected to the
input, output, and ground pins of the LP387X using traces
which do not have other currents flowing in them (Kelvin
connect).
The best way to do this is to lay out C
IN
and C
OUT
near the
device with short traces to the V
IN
,V
OUT
, and ground pins.
The regulator ground pin should be connected to the exter-
nal circuit ground so that the regulator and its capacitors
have a "single point ground".
It should be noted that stability problems have been seen in
applications where "vias" to an internal ground plane were
used at the ground points of the IC and the input and output
capacitors. This was caused by varying ground potentials at
these nodes resulting from current flowing through the
ground plane. Using a single point ground technique for the
regulator and it’s capacitors fixed the problem.
Since high current flows through the traces going into V
IN
and coming from V
OUT
, Kelvin connect the capacitor leads to
these pins so there is no voltage drop in series with the input
and output capacitors.
RFI/EMI SUSCEPTIBILITY
RFI (radio frequency interference) and EMI (electromagnetic
interference) can degrade any integrated circuit’s perfor-
mance because of the small dimensions of the geometries
inside the device. In applications where circuit sources are
present which generate signals with significant high fre-
quency energy content (>1 MHz), care must be taken to
ensure that this does not affect the IC regulator.
If RFI/EMI noise is present on the input side of the regulator
(such as applications where the input source comes from the
output of a switching regulator), good ceramic bypass ca-
pacitors must be used at the input pin of the IC.
If a load is connected to the IC output which switches at high
speed (such as a clock), the high-frequency current pulses
required by the load must be supplied by the capacitors on
the IC output. Since the bandwidth of the regulator loop is
less than 100 kHz, the control circuitry cannot respond to
load changes above that frequency. The means the effective
output impedance of the IC at frequencies above 100 kHz is
determined only by the output capacitor(s).
In applications where the load is switching at high speed, the
output of the IC may need RF isolation from the load. It is
recommended that some inductance be placed between the
output capacitor and the load, and good RF bypass capaci-
tors be placed directly across the load.
PCB layout is also critical in high noise environments, since
RFI/EMI is easily radiated directly into PC traces. Noisy
circuitry should be isolated from "clean" circuits where pos-
sible, and grounded through a separate path. At MHz fre-
quencies, ground planes begin to look inductive and RFI/
EMI can cause ground bounce across the ground plane.
In multi-layer PCB applications, care should be taken in
layout so that noisy power and ground planes do not radiate
directly into adjacent layers which carry analog power and
ground.
OUTPUT NOISE
Noise is specified in two ways-
Spot Noise or Output noise density is the RMS sum of all
noise sources, measured at the regulator output, at a spe-
cific frequency (measured with a 1Hz bandwidth). This type
of noise is usually plotted on a curve as a function of fre-
quency.
Total output Noise or Broad-band noise is the RMS sum
of spot noise over a specified bandwidth, usually several
decades of frequencies.
Attention should be paid to the units of measurement. Spot
noise is measured in units µV/√Hz or nV/√Hz and total output
noise is measured in µV(rms).
The primary source of noise in low-dropout regulators is the
internal reference. In CMOS regulators, noise has a low
frequency component and a high frequency component,
which depend strongly on the silicon area and quiescent
current. Noise can be reduced in two ways: by increasing the
transistor area or by increasing the current drawn by the
internal reference. Increasing the area will decrease the
chance of fitting the die into a smaller package. Increasing
LP3875-ADJ
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Application Hints (Continued)
the current drawn by the internal reference increases the
total supply current (ground pin current). Using an optimized
trade-off of ground pin current and die size, LP3875-ADJ
achieves low noise performance and low quiescent current
operation.
The total output noise specification for LP3875-ADJ is pre-
sented in the Electrical Characteristics table. The Output
noise density at different frequencies is represented by a
curve under typical performance characteristics.
SHORT-CIRCUIT PROTECTION
The LP3875-ADJ is short circuit protected and in the event of
a peak over-current condition, the short-circuit control loop
will rapidly drive the output PMOS pass element off. Once
the power pass element shuts down, the control loop will
rapidly cycle the output on and off until the average power
dissipation causes the thermal shutdown circuit to respond
to servo the on/off cycling to a lower frequency. Please refer
to the section on thermal information for power dissipation
calculations.
SHUTDOWN OPERATION
A CMOS Logic level signal at the shutdown ( SD) pin will
turn-off the regulator. Pin SD must be actively terminated
through a 10kΩpull-up resistor for a proper operation. If this
pin is driven from a source that actively pulls high and low
(such as a CMOS rail to rail comparator), the pull-up resistor
is not required. This pin must be tied to Vin if not used.
DROPOUT VOLTAGE
The dropout voltage of a regulator is defined as the minimum
input-to-output differential required to stay within 2% of the
nominal output voltage. For CMOS LDOs, the dropout volt-
age is the product of the load current and the Rds(on) of the
internal MOSFET.
REVERSE CURRENT PATH
The internal MOSFET in the LP3875-ADJ has an inherent
parasitic diode. During normal operation, the input voltage is
higher than the output voltage and the parasitic diode is
reverse biased. However, if the output is pulled above the
input in an application, then current flows from the output to
the input as the parasitic diode gets forward biased. The
output can be pulled above the input as long as the current
in the parasitic diode is limited to 200mA continuous and 1A
peak.
POWER DISSIPATION/HEATSINKING
The LP3875-ADJ can deliver a continuous current of 1.5A
over the full operating temperature range. A heatsink may be
required depending on the maximum power dissipation and
maximum ambient temperature of the application. Under all
possible conditions, the junction temperature must be within
the range specified under operating conditions. The total
power dissipation of the device is given by:
P
D
=(V
IN
−V
OUT
)I
OUT
+(V
IN
)I
GND
where I
GND
is the operating ground current of the device
(specified under Electrical Characteristics).
The maximum allowable temperature rise (T
Rmax
) depends
on the maximum ambient temperature (T
Amax
) of the appli-
cation, and the maximum allowable junction temperature
(T
Jmax
):
T
Rmax
=T
Jmax
−T
Amax
The maximum allowable value for junction to ambient Ther-
mal Resistance, θ
JA
, can be calculated using the formula:
θ
JA
=T
Rmax
/P
D
The LP3875-ADJ is available in TO-220 and TO-263 pack-
ages. The thermal resistance depends on amount of copper
area or heat sink, and on air flow. If the maximum allowable
value of θ
JA
calculated above is ≥60 ˚C/W for TO-220
package and ≥60 ˚C/W for TO-263 package no heatsink is
needed since the package can dissipate enough heat to
satisfy these requirements. If the value for allowable θ
JA
falls
below these limits, a heat sink is required.
HEATSINKING TO-220 PACKAGE
The thermal resistance of a TO220 package can be reduced
by attaching it to a heat sink or a copper plane on a PC
board. If a copper plane is to be used, the values of θ
JA
will
be same as shown in next section for TO263 package.
The heatsink to be used in the application should have a
heatsink to ambient thermal resistance,
θ
HA
≤θ
JA
−θ
CH
−θ
JC
.
In this equation, θ
CH
is the thermal resistance from the case
to the surface of the heat sink and θ
JC
is the thermal resis-
tance from the junction to the surface of the case. θ
JC
is
about 3˚C/W for a TO220 package. The value for θ
CH
de-
pends on method of attachment, insulator, etc. θ
CH
varies
between 1.5˚C/W to 2.5˚C/W. If the exact value is unknown,
2˚C/W can be assumed.
HEATSINKING TO-263 PACKAGE
The TO-263 package uses the copper plane on the PCB as
a heatsink. The tab of these packages are soldered to the
copper plane for heat sinking. Figure 1 shows a curve for the
θ
JA
of TO-263 package for different copper area sizes, using
a typical PCB with 1 ounce copper and no solder mask over
the copper area for heat sinking.
As shown in the figure, increasing the copper area beyond 1
square inch produces very little improvement. The minimum
value for θ
JA
for the TO-263 package mounted to a PCB is
32˚C/W.
Figure 2 shows the maximum allowable power dissipation
for TO-263 packages for different ambient temperatures,
assuming θ
JA
is 35˚C/W and the maximum junction tempera-
ture is 125˚C.
20074632
FIGURE 1. θ
JA
vs Copper (1 Ounce) Area for TO-263
package
LP3875-ADJ
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Application Hints (Continued)
20074633
FIGURE 2. Maximum power dissipation vs ambient
temperature for TO-263 package
LP3875-ADJ
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Physical Dimensions inches (millimeters) unless otherwise noted
TO220 5-lead, Molded, Stagger Bend Package (TO220-5)
NS Package Number T05D
For Order Numbers, refer to the “Ordering Information” section of this document.
LP3875-ADJ
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
TO263 5-Lead, Molded, Surface Mount Package (TO263-5)
NS Package Number TS5B
For Order Numbers, refer to the “Ordering Information” section of this document.
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LP3875-ADJ 1.5A Fast Ultra Low Dropout Linear Regulators
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
