POWER MANAGEMENT
1www.semtech.com
SC1109
Synchronous PWM Controller with Dual
Low Dropout Regulator Controllers
Features
Applications
Revision: May 13, 2004
Description
Dual linear controllers
LDOs track input voltage within 200mV (function of
the MOSFETs used) until regulation
Integrated drivers
Power good signal (SC1109A, SC1109B)
Soft start
Lossless current sense
Programmable over current limit (SC1109C)
200kHz (SC1109A, SC1109C), and 500kHz (SC1109B)
fixed frequency.
Pentium® III Motherboards
Triple power supplies
The SC1109 was designed for the latest high speed
motherboards. It combines a synchronous voltage mode
controller (switching section) with two low-dropout linear
regulator controllers. The voltage mode controller pro-
vides the power supply for the system AGTL bus. The Dual
linear controllers power the chip set and clock circuitry.
The SC1109A switching section features lossless current
sensing, while SC1109C provides programmable over cur-
rent limit. SC1109 also utilizes latched driver outputs for
enhanced noise immunity. SC1109A and SC1109C oper-
ate at a fixed frequency of 200kHz, and the SC1109B is
available at a fixed frequency of 500kHz. The VTT output
voltage is internally fixed at 1.2V
The SC1109 linear sections are low dropout regulators
designed to track the 3.3V power supply when it turns on
or off. The voltage for the linear controllers LDO1, and LDO2
are 1.8V/1.5V.
Typical Application Circuit
R2 2.2
+
C7
3x1500uF
C5
0.1uF
Q4
MOSFET N
C6
0.1uF
LDO1 = 1.8V
LDO2 = 1.5V
+
C12
330uF
Q3
MOSFET N
R1 2.2
C9
0.1uF
C3
0.1uF
Q1
MOSFET N
5V STBY
Q2
MOSFET N
VTT
+
C2
2x1500uF
+
C11
330uF
5V IN
+
C10
330uF
U1
SC1109CCSTR
12
5
3
7
6
9
10
13
14
4
11
8
15 2
116
OCSET
BCAP-
STBY
PHASE
GND
DH
BST
VOSENSE
SS/EN
BCAP+
VCC
DL
GATE2 GATE1
LDOS1LDOS2
C8
0.1uF
C1
0.1uF
R3
TBD
L1 4uH
12V IN
3.3V IN
C4
0.1uF
C13
1nF
1.2V 6A
OCSET
C6
0.1uF
Q2
MOSFET N
+
C7
3x1500uF
Q3
MOSFET N
Q1
MOSFET N
C5
0.1uF
+
C11
330uF
U1
SC1109ACSTR or SC1109BCSTR
12
5
3
7
6
9
10
13
14
4
11
8
15 2
116
PWRGD
BCAP-
STBY
PHASE
GND
DH
BST
VOSENSE
SS/EN
BCAP+
VCC
DL
GATE2 GATE1
LDOS1LDOS2
L1 4uH
C1
0.1uF
+
C10
330uF
LDO2 = 1.5V
5V STBY
POWER GOOD
12V IN
C8
0.1uF
+
C12
330uF
+
C2
2x1500uF
C9
0.1uF
LDO1 = 1.8V
3.3V IN
C3
0.1uF
VTT
R2 2.2
1.2V 6A
5V IN
R1 2.2
Q4
MOSFET N
C4
0.1uF
22004 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1109
Electrical Characteristics
Absolute Maximum Ratings
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Unless specified: VOSENSE = VO; Vcc=4.75V to 5.25V; STBY=4.75V to 5.25V; BST = 11.4V to 12.6V; TA = 0 to 70°C
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Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified
in the Electrical Characteristics section is not implied.
3
2004 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1109
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Electrical Characteristics (Cont.)
Notes:
(1) All electrical characteristics are for the application circuit on page 16.
(2) Soft start function is performed after Vcc is above the UVLO and SS/EN is above 600mV. The Soft start
capacitor is then charged at a 10uA constant current until SS/EN is charged to above 1V.
(3) Guaranteed by design
(4) Tracking Difference is defined as the delta between 3.3V Vin and the LDO1, LDO2 output voltages during
the linear ramp up until regulation is achieved. The tracking voltage difference might vary depending on
MOSFETs RdSON, and load conditions.
(5) This device is ESD sensitive. Use of standard ESD handling precautions is required.
Unless specified: VOSENSE = VO; Vcc=4.75V to 5.25V; STBY=4.75V to 5.25V; BST = 11.4V to 12.6V; TA = 0 to 70°C
42004 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1109
Pin Configuration
Ordering Information
Pin Descriptions
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Note:
(1) Only available in tape and reel
packaging. A reel contains 2500 devices.
Top View
(SC1109A/B)
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GATE1
LDOS1
STBY
BCAP+
BCAP-
GND
PHASE
DH
LDOS2
GATE2
SS/EN
PWRGD
VOSENSE
VCC
BST
DL
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Top View
(SC1109C)
GATE1
LDOS1
STBY
BCAP+
BCAP-
GND
PHASE
DH
LDOS2
GATE2
SS/EN
OCSET
VOSENSE
VCC
BST
DL
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
5
2004 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1109
Block Diagram
R
S
Q
STBY
VOSENSE
GND
+
-
OSCILLATOR
5VSTBY
+
-
PHASE
BCAP+
BST
SET DOMINATES
PWM
0.8V
VCC
+
-
+10%
+
-
BCAP-
+
-
0.6V
VBG
LOW
SIDE
DRIVE
200mV
+
-
SHOOT
THRU
CONTROL
LDOS1
FAULT LOW SIDE OFF
+
-
PWRGD
2uA
-10%
DL
10uA
5VSTBY
VBG
CHARGE
PUMP
5VSTBY
+
-
GATE2
VBG
+
-
DH
VBG
R
S
Q
LDOS2
1.2V
VCC
OVER
CURRENT
Bandgap
VCC
+
-
GATE1
OSCILLATOR
5VSTBY
HIGH
SIDE
DRIVE
ERROR AMP
HICCUP LATCH
SS/EN
UVLO
SS/EN
Marking Information
yyww = Datecode (Example: 9912)
xxxxx = Semtech Lot # (Example: 90101)
SC1109ACS
yyww
xxxxx
SC1109A SC1109BS
yyww
xxxxx
SC1109B SC1109CS
yyww
xxxxx
SC1109C
R
S
Q
STBY
VOSENSE
GND
OSCILLATOR
5VSTBY
+
-
PHASE
BCAP+
BST
SET DOMINATES
PWM
0.8V
VCC
+
-
BCAP-
+
-
0.6V
VBG
LOW
SIDE
DRIVE
160uA
+
-
SHOOT
THRU
CONTROL
LDOS1
FAULT LOW SIDE OFF
+
-
2uA
DL
10uA
5VSTBY
VBG
CHARGE
PUMP
5VSTBY
+
-
GATE2
VBG
+
-
DH
VBG
R
S
Q
LDOS2
1.2V
VCC
OVER
CURRENT
Bandgap
VCC
+
-
GATE1
OSCILLATOR
5VSTBY
HIGH
SIDE
DRIVE
ERROR AMP
HICCUP LATCH
SS/EN
UVLO
SS/EN
OCSET
SC1109A/B
SC1109C
62004 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1109
THEORY OF OPERATION
The SC1109 has integrated a synchronous buck control-
ler and two Low drop out regulator controllers into a 16
Pin SOIC package. The switching regulator provides a 1.2V
(VTT) bus termination voltage for use in AGTL (Assisted
Gunning Transceiver Logic), while the dual LDO regulators
provide 1.5V, and 1.8V to power up the Chip set and the
Clock circuitry used in Pentium® III Motherboards.
SUPPLIES
Two supplies, VSTBY, and VCC are used to power the
SC1109 . VSTBY supply provides the bias for the Internal
Reference, Oscillator, and the LDO FET controllers. This
supply should always be brought up first and turned off
last in accordance with PC power configuration require-
ments. The VCC supply provides the bias for the Power
Good circuitry, and the high side FET Rdson sensing/
over current circuitry, VCC also is used to drive the low
side MOSFET gate. An external 12V supply or a classical
boot strapping technique can provide the gate drive for
the upper Mosfet.
PWM CONTROLLER
SC1109 is a voltage mode buck controller that utilizes an
internally compensated high bandwidth error amplifier to
sense the VTT output voltage. External compensation com-
ponents are not needed and a stable closed loop re-
sponse is insured due to the internal compensation.
START UP SEQUENCE
Initially during the power up, the SC1109 is in under volt-
age lockout condition. The latch (SET dominant) in the
hiccup section is set , and the SS/EN pin is pulled low by
the 2µA soft start current source.
Mean while, the high side and low side gate drivers DH,
and DL are kept low. Once the VCC exceeds the UVLO
threshold of 4.2V, the latch is reset and the external soft
start capacitor starts to be charged by a 10µA current
source.
The gate drives are still kept off until the soft start ca-
pacitors voltage rises above 600mV, when the low side
gate is turned on, and the high side gate is kept off.
The gate drive status stays the same until the capacitors
voltage reaches 1V, when the error amplifier output starts
to cross the oscillator triangular ramp of 1V to 2V.
As the SS/EN pin continues to rise, the error amplifier
output also rises at the same rate and the duty cycle
increases.
Once the VTT output has reached regulation and is within
1.2V ± 12% , an open collector power good flag is acti-
vated, and the error amplifier output will no longer be
clamped to the SS/EN voltage and will stay between 1V
to 2V and maintain regulation of ± 1%. The SS/EN volt-
age continues to rise up to 2.5V and will stay at that
voltage level during normal operation.
Vcc
PowerGood
Soft start
PhaseNode
If an over current condition occurs, the SS/EN pin will
discharge by a 2µA current source, from 2.5V to 800mV.
During this time both DH, and DL will be turned off. Once
the SS/EN reaches 800mV, the low side gate will be
turned on, and the SS/EN pin will again start to be charged
by the 10µA current source, and the same soft start se-
quence mentioned above will be repeated.
OVER CURRENT
SC1109A/B monitor the Upper MOSFETs Rdson voltage
drop due to an over current condition. This method of cur-
rent sensing minimizes any unnecessary losses due to ex-
ternal sense resistance.
Application Information
7
2004 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1109
An internal comparator with a 200mV reference moni-
tors the Drop across the upper FET, Once the Vdson of
the MOSFET exceeds the 200mV limit, the low side gate
is turned on and the upper FET is turned off. Also an
internal latch is set and the soft start capacitor is dis-
charged. Once the lower threshold of the soft start cir-
cuit is crossed, the same softstart sequence mentioned
previously is repeated. This sequence is repeated until
the over condition is removed.
Upper Gate
Low er Gat e
Pha s e No de
Vtt Sho rted
Upper Gate
Lower Gate
The SC1109C utilizes an internal current source and an
external resistor connected from the OCSET pin to the
Mosfet’s supply to program a current limit level. This limit
is programmable by choosing the resistor according to
the level required. To reduce any noise pick up a 1nF
capacitor should be placed across the programing resis-
tor. The device operation is similar to the SC1109A/B
during the over current condition as mentioned above.
GATE DRIVERS
The Low side gate driver is supplied from VCC and provide
a peak source/sink current of and 500mA.
The high side gate drive is also capable of sourcing and
sinking peak currents of 500mA. The high side MOSFET
gate drive can be provided by an external 12V supply that
is connected from BST to GND. The actual gate to source
voltage of the upper MOSFET will approximately equal
7V (12V-VCC). If the external 12V supply is not available,
a classical boot strap technique can be implemented
from the VCC supply. A boot strap capacitor is connected
from BST to Phase while VCC is connected through a
diode (Schottky or other fast low VF diode) to the BST.
This will provide a gate to source voltage approximately
to VCC-Vdiode drop.
Low er Gat e
Pha s eNode
Low er Gat e
Shoot through control circuitry provides a 100ns dead time
to ensure both upper and lower MOSFET will not turn on
simultaneously and cause a shoot through condition.
DUAL LDO CONTROLLERS
SC1109 also provides two low drop out linear regulator
controllers that can be used to generate a 1.8V and a
1.5V output. The LDO output voltage is achieved by con-
trolling the voltage drop across an external MOSFET from
a 3.3V supply voltage.
The output voltage is sensed at the LDOS pin of the SC1109
and compared to an internal reference. The gate drive to
the external MOSFET is then adjusted until regulation is
achieved. In order to have sufficient voltage to the gate
drives of the external MOSFET, an internal charge pump is
utilized to boost the gate drive voltage to about two times
the VSTBY.
Application Information (Cont.)
82004 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1109
The internal charge pump charges an external Bucket
capacitor to VSTBY and then connects it in series with
VSTBY to the LDOs supply at a frequency of about
200kHz. This ensures sufficient gate drive voltage for
the LDOs independent of the VCC or the 12V external
supply being available due to start up timing sequence
from the silver box.
The LDO1, and LDO2 output voltages are forced to track
the 3.3V input supply. This feature ensures that during
the start up application of the 3.3V, the LDO1, and LDO2
outputs track the 3.3V within 200mV typical until regula-
tion is achieved. However, the VSTBY should be established
at least 500us, to allow the charge pump to reach its
maximum voltage, before the linear section will track within
200mV. This tracking will sequence the correct start up
timing for the external Chipset and Clock circuitry.
LAYOUT GUIDELINES
Careful attention to layout requirements are necessary
for successful implementation of the SC1109 PWM con-
troller. High currents switching are present in the appli-
cation and their effect on ground plane voltage differen-
tials must be understood and minimized.
1). The high power parts of the circuit should be laid out
first. A ground plane should be used, the number and
position of ground plane interruptions should be such as
to not unnecessarily compromise ground plane integrity.
Isolated or semi-isolated areas of the ground plane may
be deliberately introduced to constrain ground currents
to particular areas, for example the input capacitor and
bottom FET ground.
2). The loop formed by the Input Capacitor(s) (Cin), the
Top FET (Q1) and the Bottom FET (Q2) must be kept as
small as possible. This loop contains all the high current,
fast transition switching. Connections should be as wide
and as short as possible to minimize loop inductance.
Minimizing this loop area will a) reduce EMI, b) lower
ground injection currents, resulting in electrically “cleaner”
grounds for the rest of the system and c) minimize source
ringing, resulting in more reliable gate switching signals.
3). The connection between the junction of Q1, Q2 and
the output inductor should be a wide trace or copper
region. It should be as short as practical. Since this con-
nection has fast voltage transitions, keeping this con-
nection short will minimize EMI. Also keep the Phase con-
nection to the IC short, top FET gate charge currents
flow in this trace.
+
1.5V
+
1.8V
3.3V IN
+
C10
330uF
VTT
5V IN
U4 SC1109A
PWRGD
BCAP-
STBY
PHASE
GND
DH
BST
VOSENSE
SS/EN
BCAP+
VCC
DL
GATE2 GATE1
LDOS1LDOS2
+
5V STBY
+
12V IN
high current paths.
Heavy Lines indicate
Application Information (Cont.)
3.3V Vin
1.8V Vout
1.5V Vout
9
2004 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1109
4) The Output Capacitor(s) (Cout) should be located as
close to the load as possible, fast transient load cur-
rents sre supplied by Cout only, and connections between
Cout and the load must be short, wide copper areas to
minimize inductance and resistance.
5) The SC1109 is best placed over a quiet ground plane
area, avoid pulse currents in the Cin, Q1, Q2 loop flowing
in this area. GND should be returned to the ground plane
close to the package and close to the ground side of
(one of) the output capacitor(s). If this is not possible,
the GND pin may be connected to the ground path be-
tween the Output Capacitor(s) and the Cin, Q1, Q2 loop.
Under no circumstances should GND be returned to a
ground inside the Cin, Q1, Q2 loop.
Vout
5V
+
+
Application Information (Cont.)
6) BST for the SC1109 should be supplied from the 12V
supply, the BST pin should be decoupled directly to GND
by a 0.1mF ceramic capacitor, trace lengths should be as
short as possible. If a 12V supply is not available, a classi-
cal boot strap method could be implemented to achieve
the upper MOSFETs gate drive.
7) The Phase connection should be short .
8) Ideally, the grounds for the two LDO sections should
be returned to the ground side of (one of) the output
capacitor(s).
102004 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1109
COMPONENT SELECTION
SWITCHING SECTION
OUTPUT CAPACITORS - Selection begins with the most
critical component. Because of fast transient load cur-
rent requirements in modern microprocessor core sup-
plies, the output capacitors must supply all transient load
current requirements until the current in the output in-
ductor ramps up to the new level. Output capacitor ESR
is therefore one of the most important criteria. The maxi-
mum ESR can be simply calculated from:
step current Transient
excursion voltage transient Maximum
Where
==
≤
t
t
t
t
ESR
I
V
I
V
R
For example, to meet a 100mV transient limit with a 10A
load step, the output capacitor ESR must be less than
10mΩ. To meet this kind of ESR level, there are three
available capacitor technologies.
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hcaE
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latoT
C
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RSE
m( Ω)
C
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RSE
m( Ω)
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NOC-SO033523 0993.8
munimulARSEwoL0051445 00578.8
The choice of which to use is simply a cost/performance
issue, with Low ESR Aluminum being the cheapest, but
taking up the most space.
INDUCTOR - Having decided on a suitable type and value
of output capacitor, the maximum allowable value of in-
ductor can be calculated. Too large an inductor will pro-
duce a slow current ramp rate and will cause the output
capacitor to supply more of the transient load current
for longer - leading to an output voltage sag below the
ESR excursion calculated above.
The maximum inductor value may be calculated from:
()
OIN
t
ESR VV
I
CR
L−≤
The calculated maximum inductor value assumes 100%
duty cycle, so some allowance must be made. Choosing
an inductor value of 50 to 75% of the calculated maxi-
mum will guarantee that the inductor current will ramp
fast enough to reduce the voltage dropped across the
ESR at a faster rate than the capacitor sags, hence en-
suring a good recovery from transient with no additional
excursions. We must also be concerned with ripple cur-
rent in the output inductor and a general rule of thumb
has been to allow 10% of maximum output current as
ripple current. Note that most of the output voltage ripple
is produced by the inductor ripple current flowing in the
output capacitor ESR. Ripple current can be calculated
from:
OSC
IN
LfL4
V
IRIPPLE ⋅⋅
=
Ripple current allowance will define the minimum permit-
ted inductor value.
POWER FETS - The FETs are chosen based on several
criteria with probably the most important being power
dissipation and power handling capability.
TOP FET - The power dissipation in the top FET is a com-
bination of conduction losses, switching losses and bot-
tom FET body diode recovery losses.
a) Conduction losses are simply calculated as:
IN
O
)on(DS
2
OCOND
V
V
RIP
≈
⋅⋅=
cycle duty =
where
δ
δ
b) Switching losses can be estimated by assuming a
switching time, if we assume 100ns then:
3
INOSW 10VIP −
⋅⋅=
Application Information (Cont.)
11
2004 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1109
or more generally,
4
f)tt(VI
POSCfrINO
SW ⋅+⋅⋅
=
c) Body diode recovery losses are more difficult to esti-
mate, but to a first approximation, it is reasonable to
assume that the stored charge on the bottom FET body
diode will be moved through the top FET as it starts to
turn on. The resulting power dissipation in the top FET
will be:
OSCINRRRR fVQP ⋅⋅=
To a first order approximation, it is convenient to only
consider conduction losses to determine FET suitability.
For a 5V in; 2.8V out at 14.2A requirement, typical FET
losses would be:
Using 1.5X Room temp RDS(ON) to allow for temperature
rise.
epyTTEFR
)no(SD
m( Ω))W(DPegakcaP
S2043LRI5196.1D
2
KAP
3022LRI5.0191.1D
2
KAP
0144iS0262.28-OS
BOTTOM FET - Bottom FET losses are almost entirely
due to conduction. The body diode is forced into conduc-
tion at the beginning and end of the bottom switch con-
duction period, so when the FET turns on and off, there
is very little voltage across it, resulting in low switching
losses. Conduction losses for the FET can be determined
by:
)1(RIP )on(DS
2
OCOND δ−⋅⋅=
For the example above:
epyTTEFR
)no(SD
m( Ω)P
D
)W(egakcaP
S2043LRI5133.1D
2
KAP
3022LRI5.0139.0D
2
KAP
0144iS0277.18-OS
Each of the package types has a characteristic thermal
impedance, for the TO-220 package, thermal impedance
is mostly determined by the heatsink used. For the sur-
face mount packages on double sided FR4, 2 oz printed
circuit board material, thermal impedances of 40oC/W
for the D2PAK and 80oC/W for the SO-8 are readily achiev-
able. The corresponding temperature rise is detailed be-
low:
(esirerutarepmeT
0
)C
epyTTEFTEFpoTTEFmottoB
S2043LRI6.762.35
3022LRI6.742.73
0144iS8.0816.141
It is apparent that single SO-8 Si4410 are not adequate
for this application, but by using parallel pairs in each
position, power dissipation will be approximately halved
and temperature rise reduced by a factor of 4.
INPUT CAPACITORS - since the RMS ripple current in the
input capacitors may be as high as 50% of the output
current, suitable capacitors must be chosen accordingly.
Also, during fast load transients, there may be restric-
tions on input di/dt. These restrictions require useable
energy storage within the converter circuitry, either as
extra output capacitance or, more usually, additional in-
put capacitors. Choosing low ESR input capacitors will
help maximize ripple rating for a given size.
Application Information (Cont.)
122004 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1109
SC1109 Gain & Phase Margin
Typical VTT Gain/Phase plot at Vin = 5V, Iout = 3A
SC1109A Gain & Phase Margin
-20
-10
0
10
20
30
40
50
10 100 1,000 10,000 100,000
frequency(Hz)
20
40
60
80
100
120
140
160
180
200
Gain
Phase Margin
Gain (dB)
Phase Margin (Deg.)
13
2004 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1109
Typical Characteristics
Typical Icc (Switching section)
Typical Soft start source Current Vss = 0V
Typical Soft start sink Current Vss = 0V Typical Soft start sink Current Vss = 1.5V
Typical Soft start source Current Vss = 1.5V
Typical ISTBYQ (Linear section)
SC1109 Quiescent Current vs Ta
7.40
7.45
7.50
7.55
7.60
7.65
7.70
7.75
7.80
7.85
7.90
0 10203040506070
Ta (°C.)
Icc (mA)
Vcc = 5.25
Vcc = 4.75
SC1109 Soft start Source Current vs Ta
9.14
9.16
9.18
9.20
9.22
9.24
9.26
9.28
9.30
9.32
0 10203040506070
Ta (°C.)
Iss (uA)
Vcc = 5.25V , Vss = 0V
Vcc = 4.75V , Vss = 0V
SC1109 Soft start Sink Current vs Ta
9.08
9.10
9.12
9.14
9.16
9.18
9.20
9.22
9.24
9.26
9.28
9.30
0 10203040506070
Ta (°C.)
Iss (uA)
Vcc = 5.25V , Vss = 0V
Vcc = 4.75V , Vss = 0V
SC1109 Quiescent Current (Linear) vs Ta
3.95
4.00
4.05
4.10
4.15
4.20
4.25
4.30
4.35
4.40
4.45
0 10203040506070
Ta (°C.)
ISTBYQ (mA)
Vcc = 5.25
Vcc = 4.75
SC1109 Soft start Source Current vs Ta
7.94
7.96
7.98
8.00
8.02
8.04
8.06
8.08
8.10
0 10203040506070
Ta (°C)
Iss (uA)
Vcc = 4.75V , Vss = 1.5V
Vcc = 5.25V , Vss = 1.5V
SC1109 Soft start Sink Current vs Ta
1.77
1.77
1.78
1.78
1.79
1.79
1.80
0 10203040506070
Ta (°C.)
Iss (uA)
Vcc = 4.75V , Vss = 1.5V
Vcc = 5.25V , Vss = 1.5V
142004 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1109
Typical Characteristics
Typical Tracking difference (BetweenVin3.3 & LDO)
SC1109 Tracking Difference (Io LDO1,2 = 2A) vs Ta
160.0
180.0
200.0
220.0
240.0
260.0
280.0
0 10203040506070
Ta (°C.)
Delta (mV)
LDO2 Vcc = 4.75
LDO2 Vcc = 5.25
LDO1 Vcc = 4.75
LDO1 Vcc = 5.25
15
2004 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1109
Typical VTT Load Regulation at Vin=5V Typical VTT Line Regulation at Iout = 3 Amps
Typical Characteristics
Typical VTT Efficiency at Vin=5V Typical VTT Line Regulation at Iout = 6 Amps
SC1109 (VTT) Eff. vs Iout (Vin = 5.0V)
0.0%
10.0%
20.0%
30.0%
40.0%
50.0%
60.0%
70.0%
80.0%
90.0%
0.00 2.00 4.00 6.00 8.00
Iout_Vtt (Amps)
Efficiency(%)
IRL3103R(V1.8,V2.5 No load)
SC1109 (VTT) Load Reg. vs Iout (Vin = 5.0V)
-0.600%
-0.500%
-0.400%
-0.300%
-0.200%
-0.100%
0.000%
0.00 2.00 4.00 6.00 8.00
Iout_Vtt (Amps)
Load Reg.(%)
IRL3103R(V1.8,V2.5 No load)
SC1109 (VTT) Line Reg. vs Vin (Iout = 3.0A)
0.000%
0.020%
0.040%
0.060%
0.080%
0.100%
0.120%
4.700 4.800 4.900 5.000 5.100 5.200 5.300
Vin (V)
Line Reg.(%)
IRL3103R(V1.8,V2.5 No load)
SC1109 (VTT) Line Reg. vs Vin (Iout = 6.0A)
0.000%
0.050%
0.100%
0.150%
0.200%
0.250%
0.300%
0.350%
4.000 4.500 5.000 5.500 6.000 6.500 7.000
Vin (V)
Line Reg.(%)
IRL3103R(V1.8,V2.5 No load)
162004 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1109
D1
D1N4148
Q3
IRLR3103
1.2V 6A
GND J8
VTT
J7
R3 0
+
C8
1500uF
GND J4
5V IN J6
J15
C6
0.1uF
U1 SC1109A/B
12
5
3
7
6
9
10
13
14
4
11
8
15 2
116
PWRGD
BCAP-
STBY
PHASE
GND
DH
BST
VOSENSE
SS/EN
BCAP+
VCC
DL
GATE2 GATE1
LDOS1LDOS2
+
C14
330uF
1.8V
J16
R5
0
GND J2
+
C10
1500uF
12V IN J1
+
C5
1500uF
C3
0.1uF
VTT
J9
+
C13
330uF
GND
J13
+
C9
1500uF
C7
0.1uF
Q4
IRLR3103
GND
J17
L1 4uH
C16
0.1uF
R1
10k
C4
0.1uF
POWER GOOD J11
R2 0
C1
0.1uF
R4 2.2
+
C2
1500uF
GND
J18
GND
J19
Q1
IRLR3103
GND J10
GND
J12
5V IN J5
3.3V IN
J14
C12
0.1uF
C11
0.1uF
5V STBY J3
Q2
IRLR3103
+
C15
330uF
1.5V
Evaluation Board Schematic
D1
D1N4148
Q3
IRLR3103
1.2V 6A
GND J8
VTT
J7
R3 0
+
C8
1500uF
GND J4
5V IN J6
J15
C6
0.1uF
U1 SC1109C
12
5
3
7
6
9
10
13
14
4
11
8
15 2
116
OCSET
BCAP-
STBY
PHASE
GND
DH
BST
VOSENSE
SS/EN
BCAP+
VCC
DL
GATE2 GATE1
LDOS1LDOS2
+
C14
330uF
1.8V
J16
R5
0
GND J2
+
C10
1500uF
12V IN J1
+
C5
1500uF
C3
0.1uF
VTT
J9
+
C13
330uF
GND
J13
+
C9
1500uF
C7
0.1uF
Q4
IRLR3103
GND
J17
L1 4uH
R1
TBD
C4
0.1uF
OCSET J11
R2 0
C1
0.1uF
R4 2.2
+
C2
1500uF
GND
J18
GND
J19
Q1
IRLR3103
GND J10
GND
J12
5V IN J5
3.3V IN
J14
C12
0.1uF
C11
0.1uF
5V STBY J3
Q2
IRLR3103
+
C15
330uF
1.5V
C16
1nF
17
2004 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1109
Evaluation Board Bill of Materials
metI.ytQecnerefeR traP
18 31C,21C,11C,7C,6C,4C,3C,1CFµ1.0
25 01C,9C,8C,5C,2CFµ0051
33 51C,41C,31CFµ033
41 61C )C9011CS(Fn1,)B/A9011CS(Fu1.0
511D8414N1D
611JNIV21
79 91J,81J,71J,31J,21J,01J,8J,4J,2JDNG
813JYBTSV5
92 6J,5JNIV5
012 9J,7JTTV
11111J TESCO/DOOGREWOP
21141JNIV3.3
31151JV5.2
41161JV8.1
5111LHµ4
614 4Q,3Q,2Q,1Q3013RLRI
7111R )C9011CS(DBT,)B/A9011CS(k01
813 5R,3R,2R0
9114R2.2
0211UC/B/A9011CS
182004 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1109
Evaluation Board Gerber Plots
Board Layout Assembly Top Board Layout Bottom
Board Layout Top
19
2004 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1109
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
Outline Drawing - SO-16
Contact Information
Land Pattern - SO-16