17.5 GHz to 24 GHz, GaAs, MMIC, I/Q Downconverter ADMV1012 Data Sheet FUNCTIONAL BLOCK DIAGRAM RF input frequency range: 17.5 GHz to 24 GHz IF output frequency range: 2.5 GHz to 3.5 GHz LO input frequency range: 7 GHz to 13.5 GHz Conversion gain (with hybrid): 15 dB typical SSB noise figure: 2.5 dB typical Input IP3: 3 dBm typical Input P1dB: -5 dBm typical 25 dB of image rejection Single-ended, 50 RF and LO input ports Exposed pad, 4.9 mm x 4.9 mm, 32-terminal LCC VDRF VGRF 27 31 ADMV1012 RFIN 3 LOIN 10 20 IF2 x2 VDLO 15 22 IF1 2 GND 4 GND 11 GND 16349-001 FEATURES Figure 1. APPLICATIONS Point to point microwave radios Radars and electronic warfare systems Instrumentation, automatic test equipment (ATE) Satellite communications GENERAL DESCRIPTION The ADMV1012 is a compact, gallium arsenide (GaAs) design, monolithic microwave integrated circuit (MMIC), in phase/quadrature (I/Q) downconverter in a RoHS compliant package optimized for point to point microwave radio designs that operate in the 17.5 GHz to 24 GHz input frequency range. The I/Q mixer topology reduces the need for filtering of unwanted sideband. The ADMV1012 is a much smaller alternative to hybrid style, double sideband (DSB) downconverter assemblies and eliminates the need for wire bonding by allowing the use of surface-mount manufacturing assemblies. The ADMV1012 provides 15 dB of conversion gain with 25 dB of image rejection, and 2.5 dB noise figure. The ADMV1012 uses a radio frequency (RF) low noise amplifier (LNA) followed by an I/Q, double balanced mixer, where a driver amplifier drives the local oscillator (LO) with a x2 multiplier. IF1 and IF2 mixer quadrature outputs are provided, and an external 90 hybrid is required to select the required sideband. The ADMV1012 downconverter comes in a compact, thermally enhanced, 4.9 mm x 4.9 mm, 32-terminal LCC. The ADMV1012 operates over the -40C to +85C temperature range. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. 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Technical Support www.analog.com ADMV1012 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Return Loss Performance .......................................................... 12 Applications ....................................................................................... 1 Spurious Performance ............................................................... 13 Functional Block Diagram .............................................................. 1 M x N Spurious Performance for LO = 0 dBm ...................... 13 General Description ......................................................................... 1 Theory of Operation ...................................................................... 14 Revision History ............................................................................... 2 LO Driver Amplifier .................................................................. 14 Specifications..................................................................................... 3 Mixer ............................................................................................ 14 Absolute Maximum Ratings............................................................ 4 LNA .............................................................................................. 14 Thermal Resistance ...................................................................... 4 Applications Information .............................................................. 15 ESD Caution .................................................................................. 4 Typical Application Circuit ....................................................... 15 Pin Configuration and Function Descriptions ............................. 5 Evaluation Board Information ................................................. 16 Typical Performance Characteristics ............................................. 6 Bill of Materials ........................................................................... 18 Upper Sideband (Low-Side LO) ................................................. 6 Outline Dimensions ....................................................................... 19 Lower Sideband (High-Side LO) ................................................ 8 Ordering Guide .......................................................................... 19 IF Bandwidth .............................................................................. 10 Leakage Performance ................................................................. 11 REVISION HISTORY 2/2018--Rev. 0 to Rev. A Changes to Features Section, General Description Section, and Figure 1 .............................................................................................. 1 Changes to Table 1 ............................................................................ 3 Changes to Table 2 ............................................................................ 4 Added Thermal Resistance Section and Table 3; Renumbered Sequentially ....................................................................................... 4 Changes to Figure 2 and Table 4 ..................................................... 5 Changes to Figure 3 and Figure 6 ................................................... 6 Changes to Figure 12 ........................................................................ 7 Changes to Figure 24, Figure 25, and Figure 26 ......................... 10 Changes to Figure 27 through Figure 30 ..................................... 11 Changed M x N Spurious Performance for LO = 4 dBm Section to M x N Spurious Performance for LO = 0 dBm Section ....... 13 Changes to M x N Spurious Performance for LO = 0 dBm Section.............................................................................................. 13 Changes to LO Driver Amplifier Section .................................... 14 Changes to Applications Information Section and Figure 34........ 15 Changes to Power-On Sequence Section .................................... 16 Changes to Figure 37...................................................................... 17 Changes to Table 6.......................................................................... 18 Changes to Ordering Guide .......................................................... 19 10/2017--Revision 0: Initial Version Rev. A | Page 2 of 19 Data Sheet ADMV1012 SPECIFICATIONS Data taken at VDRF = 3 V, VDLO = 3 V, LO = -4 dBm LO +4 dBm, -40C TA +85C, with a Mini-Circuits(R) QCN-45+ power splitter for both upper sideband (low-side LO) and lower sideband (high-side LO), unless otherwise noted. Table 1. Parameter INPUT FREQUENCY RANGE Radio Frequency Local Oscillator LO AMPLITUDE OUTPUT FREQUENCY RANGE Intermediate Frequency RF PERFORMANCE Conversion Gain Single Sideband (SSB) Noise Figure Lower Sideband (High-Side LO) Upper Sideband (Low-Side LO) Input Third-Order Intercept Input 1 dB Compression Point Image Rejection Leakage LO to RF LO to IF 2x LO to IF IM3 at Input -20 dBm Input Power -25 dBm Input Power -30 dBm Input Power Return Loss RF Input IF Output LO Input POWER INTERFACE RF LNA Bias Voltage LO Amplifier Bias Voltage RF LNA Gate Voltage RF Amplifier Bias Current LO Amplifier Bias Current RF Amplifier Gate Current Total Power Symbol Test Conditions/Comments RF LO Min 17.5 7 -4 IF Typ Max Unit 0 24 13.5 +4 GHz GHz dBm 3.5 GHz 2.5 With hybrid 10.5 15 20 dB 3.5 4 0 -9 20 2.1 2.5 3 -5 25 dB dB dBm dBm dB -37 -40 -40 -25 -25 -25 dBm dBm dBm SSB NF IP3 P1dB At -20 dBm/tone -23 dBm per tone -28 dBm per tone -33 dBm per tone VDRF VDLO VGRF IDRF IDLO IGRF 46 52 56 52 60 70 -11 -23 -11 -10 -10 -10 dB dB dB 3 3 3.5 3.5 -0.4 V V -1.8 Adjust VGRF between -1.8 V to -0.4 V to get IDRF Rev. A | Page 3 of 19 dBc dBc dBc 68 170 <1 0.7 0.8 mA mA mA W ADMV1012 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter Supply Voltage VDLO VGRF VDRF - VGRF1 Input Power RF LO Maximum Junction Temperature Maximum Power Dissipation Lifetime at Maximum Junction Temperature (TJ) Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering 60 sec) Moisture Sensitivity Level (MSL) Rating Electrostatic Discharge (ESD) Sensitivity Human Body Model (HBM) Field Induced Charged Device Model (FICDM) 1 Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Rating 4V 0V 6V JA is thermal resistance, junction to ambient (C/W), and JC is thermal resistance, junction to case (C/W). 15 dBm 15 dBm 175C 2W >1 million hours -40C to +85C -65C to +150C 260C MSL3 Table 3. Thermal Resistance Package Type E-32-1 1 JA1 33.4 JC 34 Unit C/W See JEDEC standard JESD51-2 for additional information on optimizing the thermal impedance (PCB with 3 x 3 vias). ESD CAUTION 750 V 500 V The maximum VDRF voltage and the minimum VGRF voltage is determined by this difference. If a maximum VDRF voltage of +4 V is required, then the minimum VGRF voltage is -2 V. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. A | Page 4 of 19 Data Sheet ADMV1012 32 31 30 29 28 27 26 25 NIC VGRF NIC NIC NIC VDRF NIC NIC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 ADMV1012 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 NIC NIC IF1 NIC IF2 NIC NIC NIC NOTES 1. NIC = NOT INTERNALLY CONNECTED. IT IS RECOMMENDED TO GROUND THESE PINS ON THE PCB. 2. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO GND. GOOD RF AND THERMAL GROUNDING IS RECOMMENDED. 16349-002 NIC LOIN GND NIC NIC NIC VDLO NIC 9 10 11 12 13 14 15 16 NIC GND RFIN GND NIC NIC NIC NIC Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1, 5 to 9, 12 to 14, 16 to 19, 21, 23 to 26, 28 to 30, 32 2, 4, 11 3 10 15 Mnemonic NIC Description Not Internally Connected. It is recommended to ground these pins on the PCB. GND RFIN LOIN VDLO 20, 22 27 IF2, IF1 VDRF 31 VGRF Ground. RF Input. This pin is ac-coupled internally and matched to 50 single ended. LO Input. This pin is ac-coupled internally and matched to 50 single ended. Power Supply Voltage for the LO Amplifier. Refer to the Applications Information section for the required external components and biasing. Quadrature IF Outputs. Matched to 50 and ac coupled. No external dc block is required. Power Supply Voltage for the RF Amplifier. Refer to the Applications Information section for the required external components and biasing. Power Supply Gate Voltage for the RF Amplifier. Refer to the Applications Information section for the required external components and biasing. Exposed Pad. The exposed pad must be connected to GND. Good RF and thermal grounding is recommended. EPAD Rev. A | Page 5 of 19 ADMV1012 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS UPPER SIDEBAND (LOW-SIDE LO) Data taken at VDRF = 3 V, VDLO = 3 V, IDRF = 68 mA, LO = -4 dBm LO +4 dBm, -40C TA +85C, with Mini-Circuits QCN-45+, power splitter as upper sideband (low-side LO), unless otherwise noted. 20 18 16 16 10 +85C, 3.5GHz IF +25C, 3.5GHz IF -40C, 3.5GHz IF +85C, 3.0GHz IF +25C, 3.0GHz IF -40C, 3.0GHz IF +85C, 2.5GHz IF +25C, 2.5GHz IF -40C , 2.5GHz IF 8 6 4 2 0 20.0 20.5 21.0 21.5 22.0 22.5 23.0 10 6 23.5 24.0 0 20.0 50 IMAGE REJECTION (dBc) 50 40 30 -40C, 2.5GHz IF +25C, 2.5GHz IF +85C, 2.5GHz IF -40C, 3.0GHz IF +25C, 3.0GHz IF +85C, 3.0GHz IF -40C, 3.5GHz IF +25C, 3.5GHz IF +85C, 3.5GHz IF 20.5 21.0 21.5 22.0 22.5 23.0 23.5 24.0 RF FREQUENCY (GHz) 8 INPUT IP3 (dBm) 8 6 21.5 22.0 +85C, 2.5GHz IF +25C, 2.5GHz IF -40C, 2.5GHz IF -4dB, 2.5GHz IF 0dB, 2.5GHz IF +4dB, 2.5GHz IF -4dB, 3.0GHz IF 0dB, 3.0GHz IF +4dB, 3.0GHz IF -4dB, 3.5GHz IF 0dB, 3.5GHz IF +4dB, 3.5GHz IF 20.5 21.0 22.5 RF FREQUENCY (GHz) 23.0 23.5 24.0 21.5 22.0 22.5 23.0 23.5 24.0 6 4 +4dB, 3.5GHz IF 0dB, 3.5GHz IF -4dB, 3.5GHz IF +4dB, 3.0GHz IF 0dB, 3.0GHz IF -4dB, 3.0GHz IF 2 0 20.0 16349-005 21.0 24.0 Figure 7. Image Rejection vs. RF Frequency at Various LO Powers and Various IF Frequencies 10 20.5 23.5 RF FREQUENCY (GHz) 10 0 20.0 23.0 20 12 2 22.5 30 12 +85C, 3.5GHz IF +25C, 3.5GHz IF -40C, 3.5GHz IF +85C, 3.0GHz IF +25C, 3.0GHz IF -40C, 3.0GHz IF 22.0 40 0 20.0 Figure 4. Image Rejection vs. RF Frequency at Various Temperatures and Various IF Frequencies 4 21.5 10 16349-004 0 20.0 21.0 Figure 6. Conversion Gain vs. RF Frequency at Various LO Powers and Various IF Frequencies 60 10 20.5 RF FREQUENCY (GHz) 60 20 +4C, 3.5GHz IF 0C, 3.5GHz IF -4C, 3.5GHz IF +4C, 3.0GHz IF 0C, 3.0GHz IF -4C, 3.0GHz IF +4C, 2.5GHz IF 0C, 2.5GHz IF -4C, 2.5GHz IF 8 2 Figure 3. Conversion Gain vs. RF Frequency at Various Temperatures and Various IF Frequencies IMAGE REJECTION (dBc) 12 4 RF FREQUENCY (GHz) INPUT IP3 (dBm) 14 20.5 21.0 21.5 22.0 +4dB, 2.5GHz IF 0dB, 2.5GHz IF -4dB, 2.5GHz IF 22.5 RF FREQUENCY (GHz) Figure 5. Input IP3 vs. RF Frequency at Various Temperatures and Various IF Frequencies 16349-007 12 23.0 23.5 24.0 16349-008 14 16349-006 CONVERSION GAIN (dB) 18 16349-003 CONVERSION GAIN (dB) 20 Figure 8. Input IP3 vs. RF Frequency at Various LO Powers and Various IF Frequencies Rev. A | Page 6 of 19 Data Sheet ADMV1012 0 0 +85C, 3.5GHz IF +25C, 3.5GHz IF -40C, 3.5GHz IF +85C, 3.0GHz IF +25C, 3.0GHz IF -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -2.0 -2.5 -3.0 21.5 22.0 22.5 23.0 23.5 24.0 RF FREQUENCY (GHz) Figure 9. Input P1dB vs. RF Frequency at Various Temperatures and Various IF Frequencies 4.0 4.0 3.5 3.5 NOISE FIGURE (dB) 4.5 3.0 2.5 2.0 1.5 0.5 0 20.0 20.5 21.0 21.5 22.5 RF FREQUENCY (GHz) 23.0 22.5 23.0 23.5 24.0 2.0 1.5 0.5 24.0 22.0 2.5 1.0 23.5 21.5 3.0 -40C, 3.0GHz IF +85C, 2.5GHz IF +25C, 2.5GHz IF -40C, 2.5GHz IF 22.0 21.0 Figure 11. Input P1dB vs. RF Frequency at Various LO Powers and Various IF Frequencies 4.5 +85C, 3.5GHz IF +25C, 3.5GHz IF -40C, 3.5GHz IF +85C, 3.0GHz IF +25C, 3.0GHz IF 20.5 RF FREQUENCY (GHz) 0 20.0 16349-010 NOISE FIGURE (dB) -4.0 20.0 Figure 10. Noise Figure vs. RF Frequency at Various Temperatures and Various IF Frequencies +4C, 3.5GHz IF 0C, 3.5GHz IF -4C, 3.5GHz IF +4C, 3.0GHz IF 0C, 3.0GHz IF 20.5 21.0 21.5 -4C, 3.0GHz IF +4C, 2.5GHz IF 0C, 2.5GHz IF -4C, 2.5GHz IF 22.0 22.5 23.0 23.5 24.0 RF FREQUENCY (GHz) Figure 12. Noise Figure vs. RF Frequency at Various LO Powers and Various IF Frequencies Rev. A | Page 7 of 19 16349-012 21.0 16349-009 20.5 16349-011 -3.5 -4.0 1.0 -4dB, 3.0GHz IF +4dB, 2.5GHz IF 0dB, 2.5GHz IF -4dB, 2.5GHz IF -1.5 -3.5 -4.5 20.0 +4dB, 3.5GHz IF 0dB, 3.5GHz IF -4dB, 3.5GHz IF +4dB, 3.0GHz IF 0dB, 3.0GHz IF -0.5 INPUT P1dB (dBm) INPUT P1dB (dBm) -1.0 -40C, 3.0GHz IF +85C, 2.5GHz IF +25C, 2.5GHz IF -40C, 2.5GHz IF ADMV1012 Data Sheet LOWER SIDEBAND (HIGH-SIDE LO) 20 20 18 18 16 16 14 12 +85C, 3.5GHz IF +25C, 3.5GHz IF -40C, 3.5GHz IF +85C, 3.0GHz IF +25C, 3.0GHz IF -40C, 3.0GHz IF +85C, 2.5GHz IF +25C, 2.5GHz IF -40C, 2.5GHz IF 6 4 2 17.5 18.0 18.5 19.0 19.5 20.0 0 17.0 28.0 IMAGE REJECTION (dBc) 28.5 28.0 27.5 -40C, 2.5GHz IF +25C, 2.5GHz IF +85C, 2.5GHz IF -40C, 3.0GHz IF 26.0 25.5 25.0 +25C, 3.0GHz IF +85C, 3.0GHz IF -40C, 3.5GHz IF +25C, 3.5GHz IF +85C, 3.5GHz IF 24.0 23.5 17.0 17.5 18.0 18.5 27.0 19.5 20.0 RF FREQUENCY (GHz) 26.0 19.5 20.0 25.5 25.0 23.5 17.0 -4dB, 3.5GHz IF 0dB, 3.5GHz IF +4dB, 3.5GHz IF 17.5 18.0 18.5 19.0 19.5 20.0 RF FREQUENCY (GHz) Figure 14. Image Rejection vs. RF Frequency at Various Temperatures and Various IF Frequencies Figure 17. Image Rejection vs. RF Frequency at Various LO Powers and Various IF Frequencies 7 7 +85C, 3.5GHz IF +25C, 3.5GHz IF -40C, 3.5GHz IF +85C, 3.0GHz IF +25C, 3.0GHz IF -40C, 3.0GHz IF 5 +85C, 2.5GHz IF +25C, 2.5GHz IF -40C, 2.5GHz IF 5 4 3 3 2 1 1 18.5 19.0 19.5 20.0 RF FREQUENCY (GHz) Figure 15. Input IP3 vs. RF Frequency at Various Temperatures and Various IF Frequencies 0 17.0 16349-015 18.0 +4dB, 2.5GHz IF 0dB, 2.5GHz IF -4dB, 2.5GHz IF 4 2 17.5 +4dB, 3.5GHz IF 0dB, 3.5GHz IF -4dB, 3.5GHz IF +4dB, 3.0GHz IF 0dB, 3.0GHz IF -4dB, 3.0GHz IF 6 INPUT IP3 (dBm) 6 0 17.0 19.0 -4dB, 2.5GHz IF 0dB, 2.5GHz IF +4dB, 2.5GHz IF -4dB, 3.0GHz IF 0dB, 3.0GHz IF +4dB, 3.0GHz IF 26.5 24.0 19.0 18.5 27.5 24.5 16349-014 IMAGE REJECTION (dBc) 29.0 28.5 24.5 18.0 Figure 16. Conversion Gain vs. RF Frequency at Various LO Powers and Various IF Frequencies 29.0 26.5 17.5 RF FREQUENCY (GHz) Figure 13. Conversion Gain vs. RF Frequency at Various Temperatures and Various IF Frequencies INPUT IP3 (dBm) 6 2 RF FREQUENCY (GHz) 27.0 +4dB, 3.5GHz IF 0dB, 3.5GHz IF -4dB, 3.5GHz IF +4dB, 3.0GHz IF 0dB, 3.0GHz IF -4dB, 3.0GHz IF +4dB, 2.5GHz IF 0dB, 2.5GHz IF -4dB, 2.5GHz IF 8 17.5 18.0 18.5 19.0 RF FREQUENCY (GHz) 19.5 20.0 16349-018 0 17.0 10 4 16349-013 8 12 16349-017 10 14 16349-016 CONVERSION GAIN (dB) CONVERSION GAIN (dB) Data taken at VDRF = 3 V, VDLO = 3 V, IDRF = 68 mA, LO = -4 dBm LO +4 dBm, -40C TA +85C, with Mini-Circuits QCN-45+, power splitter as lower sideband (high-side LO), unless otherwise noted. Figure 18. Input IP3 vs. RF Frequency at Various LO Powers and Various IF Frequencies Rev. A | Page 8 of 19 Data Sheet ADMV1012 0 -40C, 3.0GHz IF +85C, 2.5GHz IF +25C, 2.5GHz IF -40C, 2.5GHz IF -1 INPUT P1dB (dBm) -2 -3 -4 -4dB, 3.0GHz IF +4dB, 2.5GHz IF 0dB, 2.5GHz IF -4dB, 2.5GHz IF -2 -3 -4 -5 -5 17.5 18.0 18.5 19.0 19.5 20.0 RF FREQUENCY (GHz) -6 17.0 16349-019 -6 17.0 +4dB, 3.5GHz IF 0dB, 3.5GHz IF -4dB, 3.5GHz IF +4dB, 3.0GHz IF 0dB, 3.0GHz IF Figure 19. Input P1dB vs. RF Frequency at Various Temperatures and Various IF Frequencies 17.5 18.0 18.5 19.0 19.5 20.0 RF FREQUENCY (GHz) 16349-021 INPUT P1dB (dBm) -1 0 +85C, 3.5GHz IF +25C, 3.5GHz IF -40C, 3.5GHz IF +85C, 3.0GHz IF +25C, 3.0GHz IF Figure 21. Input P1dB vs. RF Frequency at Various LO Powers and Various IF Frequencies 4.0 3.0 3.5 2.5 NOISE FIGURE (dB) 2.0 1.5 1.0 0.5 0 17.0 +85C, 3.5GHz IF +25C, 3.5GHz IF -40C, 3.5GHz IF +85C, 3.0GHz IF +25C, 3.0GHz IF 17.5 18.0 2.0 1.5 1.0 -40C, 3.0GHz IF +85C, 2.5GHz IF +25C, 2.5GHz IF -40C, 2.5GHz IF 18.5 19.0 RF FREQUENCY (GHz) 0.5 19.5 20.0 0 17.0 Figure 20. Noise Figure vs. RF Frequency at Various Temperatures and Various IF Frequencies +4dB, 3.5GHz IF 0dB, 3.5GHz IF -4dB, 3.5GHz IF +4dB, 3.0GHz IF 0dB, 3.0GHz IF 17.5 18.0 -4dB, 3.0GHz IF +4dB, 2.5GHz IF 0dB, 2.5GHz IF -4dB, 2.5GHz IF 18.5 19.0 19.5 20.0 RF FREQUENCY (GHz) Figure 22. Noise Figure vs. RF Frequency at Various LO Powers and Various IF Frequencies Rev. A | Page 9 of 19 16349-022 2.5 16349-020 NOISE FIGURE (dB) 3.0 ADMV1012 Data Sheet IF BANDWIDTH 25 20 20 15 10 +85C, UPPER +25C, UPPER -40C, UPPER +85C, LOWER +25C, LOWER -40C, LOWER 5 2.2 2.4 2.6 2.8 3.0 3.4 3.2 3.6 3.8 4.0 IF FREQUENCY (GHz) 0 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 IF FREQUENCY (GHz) Figure 25. Conversion Gain vs. IF Frequency at Various LO Powers and Sidebands 10 10 9 8 8 7 7 INPUT IP3 (dBm) 9 6 5 4 6 5 4 3 3 +85C, UPPER +25C, UPPER -40C, UPPER +85C, LOWER +25C, LOWER -40C, LOWER 1 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 IF FREQUENCY (GHz) Figure 24. Input IP3 vs. IF Frequency at Various Temperatures and Sidebands +4dBm, UPPER 0dBm, UPPER -4dBm, UPPER +4dBm, LOWER 0dBm, LOWER -4dBm, LOWER 2 1 0 2.0 16349-025 2 0 2.0 +4dBm, UPPER 0dBm, UPPER -4dBm, UPPER +4dBm, LOWER 0dBm, LOWER -4dBm, LOWER 5 Figure 23. Conversion Gain vs. IF Frequency at Various Temperatures and Sidebands INPUT IP3 (dBm) 10 2.2 2.4 2.6 2.8 3.0 3.2 IF FREQUENCY (GHz) 3.4 3.6 3.8 4.0 16349-028 0 2.0 15 16349-026 CONVERSION GAIN (dB) 25 16349-023 CONVERSION GAIN (dB) Data taken at VDRF = 3 V, VDLO = 3 V, IDRF = 68 mA, LO = -4 dBm LO +4 dBm at 10 GHz, -40C TA +85C, with Mini-Circuits QCN-45+, power splitter, unless otherwise noted. Figure 26. Input IP3 vs. IF Frequency at Various LO Powers and Sidebands Rev. A | Page 10 of 19 Data Sheet ADMV1012 LEAKAGE PERFORMANCE Data taken at VDRF = 3 V, VDLO = 3 V, LO = -4 dBm LO +4 dBm, -40C TA +85C, with Mini-Circuits QCN-45+, power splitter, unless otherwise noted. 0 0 LO LEAKAGE (dBm) -20 -30 -40 -50 -30 -40 -50 -60 -60 -70 -70 -80 6 7 8 9 10 11 12 13 14 LO FREQUENCY (GHz) -80 16349-034 6 8 9 10 11 12 13 14 LO FREQUENCY (GHz) Figure 27. LO Leakage at IF Output vs. LO Frequency at Various Temperatures and Sidebands Figure 29. LO Leakage at IF Output vs. LO Frequency at Various LO Powers and Sidebands -30 -30 +4dBm 0dBm -4dBm +85C +25C -40C -35 LO LEAKAGE (dBm) -35 LO LEAKAGE (dBm) 7 -40 -45 -50 -40 -45 -50 6 7 8 9 10 11 LO FREQUENCY (GHz) 12 13 14 -55 16349-033 -55 6 7 8 9 10 11 LO FREQUENCY (GHz) Figure 28. LO Leakage at RFIN vs. LO Frequency at Various Temperatures 12 13 14 16349-036 LO LEAKAGE (dBm) -20 +4dBm, UPPER 0dBm, UPPER -4dBm, UPPER +4dBm, LOWER 0dBm, LOWER -4dBm, LOWER -10 16349-037 +85C, UPPER +25C, UPPER -40C, UPPER +85C, LOWER +25C, LOWER -40C, LOWER -10 Figure 30. LO Leakage at RFIN vs. LO Frequency at Various LO Powers Rev. A | Page 11 of 19 ADMV1012 Data Sheet RETURN LOSS PERFORMANCE Data taken at VDRF = 3 V, VDLO = 3 V, IDRF = 68 mA, LO = -4 dBm LO +4 dBm, -40C TA +85C, with Mini-Circuits QCN-45+, power splitter, unless otherwise noted. Measurement reference plane at connector. 0 0 IF OUTPUT RETURN LOSS (dB) -15 +85C +25C -40C -20 -10 -15 -20 -25 -30 18.5 19.5 20.5 21.5 22.5 23.5 RF FREQUENCY (GHz) -35 2.5 16349-043 -30 17.5 -5 -10 -15 +85C +25C -40C 8 9 10 11 LO FREQUENCY (GHz) 12 13 16349-044 -25 7 3.1 3.3 3.5 Figure 33. IF Output Return Loss vs. IF Frequency at Various Temperatures and Sidebands 0 -30 2.9 IF FREQUENCY (GHz) Figure 31. RF Input Return Loss vs. RF Frequency at Various Temperatures -20 2.7 16349-045 RF INPUT RETURN LOSS (dB) -10 -25 LO INPUT RETURN LOSS (dB) +85C, UPPER +85C, LOWER +25C, UPPER +25C, LOWER -40C, UPPER -40C, LOWER -5 -5 Figure 32. LO Input Return Loss vs. LO Frequency at Various Temperatures Rev. A | Page 12 of 19 Data Sheet ADMV1012 SPURIOUS PERFORMANCE Data taken at VDRF = 3 V, VDLO = 3 V, IDRF = 68 mA, LO = 0 dBm, and -40C TA +85C with a Mini-Circuits QCN-45+, power splitter, unless otherwise noted. Table 5. LO Harmonic Leakage at IF Output LO Frequency (MHz) 7000 8500 9000 10,000 11,000 12,000 13,000 13,500 1.0 -48 -47 -50 -49 -49 -58 -54 -55 Frequency 2.0 3.0 -65 -42 -64 -57 -51 -51 -40 -52 -47 -61 -46 -56 -42 -59 -40 N/A 4.0 -57 -64 -61 -61 N/A N/A N/A N/A M x N SPURIOUS PERFORMANCE FOR LO = 0 dBm Mixer spurious products are measured in dBc from the IF output power level. Spurious values are measured using the following equation: (M x RF)+ (N x LO). N/A means not applicable. The frequencies are referred from the frequencies applied to the pin of the ADMV1012. IF = 3.5 GHz RF = 18000 MHz at RF power of -20 dBm, and LO = 10750 MHz at LO power of 4 dBm. All values in dBc below IF power level. N/A means not applicable. M x RF -2 -1 0 1 2 M x RF 0 N/A N/A N/A -49.1 -66.5 N x LO 1 2 N/A N/A N/A 0 -42 -38.4 -70.2 -65.7 -74.4 N/A 3 N/A -68.5 -52.2 -67.9 N/A 4 -58.6 -71.1 -53.2 N/A N/A M x RF -2 -1 0 1 2 0 N/A N/A N/A -48.8 -71.7 1 N/A N/A -42.3 -68.3 -65.8 3 N/A -72.5 -54.1 -63.4 N/A 4 -56 -83.9 -56.9 N/A N/A 4 -57.5 -74.2 -46.2 N/A N/A -2 -1 0 1 2 0 N/A N/A N/A -53.2 -60.9 1 N/A N/A -39.9 -77.8 N/A N x LO 2 N/A 0 -40.2 -64.9 N/A 3 N/A -62.6 -46.9 N/A N/A 4 -56.4 -72.3 -47 N/A N/A IF = 3.3 GHz RF = 23000 MHz at RF power of -20 dBm, and LO = 9850 MHz at LO power of 4 dBm. All values in dBc below IF power level. N/A means not applicable. M x RF N x LO 2 N/A 0 -44.7 -69.5 N/A 3 N/A -76.6 -47.2 N/A N/A RF = 23000 MHz at RF power of -20 dBm, and LO = 10100 MHz at LO power of 4 dBm. All values in dBc below IF power level. N/A means not applicable. IF = 3.3 GHz RF = 18000 MHz at RF power of -20 dBm, and LO = 10650 MHz at LO power of 4 dBm. All values in dBc below IF power level. N/A means not applicable. N x LO 2 N/A 0 -33.4 -83.8 N/A IF = 2.8 GHz IF = 2.8 GHz RF = 18000 MHz at -20 dBm and LO = 10400 MHz at 4 dBm. All values in dBc below IF power level. N/A means not applicable. 1 N/A N/A -42.7 -74.5 -59.9 Upper Sideband M xRF Lower Sideband -2 -1 0 1 2 0 N/A N/A N/A -48.2 -77.2 -2 -1 0 1 2 0 N/A N/A N/A -52.9 -74.9 1 N/A N/A -40.6 -99.8 N/A N x LO 2 N/A 0 -42 -65.3 N/A 3 N/A -53.8 -44.2 N/A N/A 4 -61.5 -69 -56.5 N/A N/A IF = 3.5 GHz RF = 23000 MHz at RF power of -20 dBm, and LO = 9750 MHz at LO power of 4 dBm. All values in dBc below IF power level. N/A means not applicable. M x RF Rev. A | Page 13 of 19 -2 -1 0 1 2 0 N/A N/A N/A -53.6 -70.7 1 N/A N/A -41.5 -68.7 N/A N x LO 2 N/A 0 -40.8 -72.2 N/A 3 N/A -50.1 -47.4 N/A N/A 4 -67.6 -63.9 -64.8 N/A N/A ADMV1012 Data Sheet THEORY OF OPERATION The ADMV1012 is a compact GaAs, MMIC, double sideband (DSB) downconverter in a RoHS compliant package optimized for both upper sideband and lower sideband point to point microwave radio applications operating in the 17.5 GHz to 24 GHz input frequency range. The ADMV1012 supports LO input frequencies of 7 GHz to 13.5 GHz and IF output frequencies of 2.5 GHz to 3.5 GHz. The ADMV1012 uses a RF LNA followed by an I/Q double balanced mixer, where a driver amplifier drives the LO (see Figure 1). This combination of design, process, and packaging technology allows the functions of these subsystems to be integrated into a single die, using mature packaging and interconnection technologies to provide a high performance, low cost design with excellent electrical, mechanical, and thermal properties. In addition, the need for external components is minimized, optimizing cost and size. LO DRIVER AMPLIFIER The LO driver amplifier takes a single LO input and doubles the frequency and amplifies it to the desired LO signal level for the mixer to operate optimally. The LO driver amplifier is self biased, and it requires only a single dc bias voltage (VDLO), which draws approximately 170 mA at 3 V under the LO drive. The LO amplitude range of -4 dBm to +4 dBm makes it compatible with the Analog Devices, Inc., wideband synthesizer portfolio without the need for an external LO driver amplifier. MIXER The mixer is an I/Q double balanced mixer, and this mixer topology reduces the need for filtering unwanted sideband. An external 90 hybrid is required to select the upper sideband of operation. The ADMV1012 has been optimized to work with the Mini-Circuits QCN-45+ RF 90 hybrid. LNA The LNA requires a single dc bias voltage (VDRF) and a single dc gate bias (VGRF) to operate. Starting at -1.8 V at the gate supply (VGRF), the LNA is biased at +3 V (VDRF). Then, the gate bias (VGRF) is varied until the desired LNA bias current (IDRF) is achieved. The desired LNA bias current is 68 mA at 3 V under small signal conditions. The typical application circuit (see Figure 34) shows the necessary external components on the bias lines to eliminate any undesired stability problems for the RF amplifier and the LO amplifier. The ADMV1012 is a much smaller alternative to hybrid style image reject converter assemblies, and it eliminates the need for wire bonding by allowing the use of surface-mount manufacturing assemblies. The ADMV1012 downconverter comes in a compact, thermally enhanced, 4.9 mm x 4.9 mm, 32-terminal ceramic leadless chip carrier (LCC) package. The ADMV1012 operates over the -40C to +85C temperature range. Rev. A | Page 14 of 19 Data Sheet ADMV1012 APPLICATIONS INFORMATION TYPICAL APPLICATION CIRCUIT The evaluation board and typical application circuit are optimized for low-side LO (upper sideband) performance with the Mini-Circuit QCN-45+ RF 90 hybrid. Because the I/Q mixers are double balanced, the ADMV1012 can support IF frequencies from 3.5 GHz to low frequency. VGRF VDRF 5019 1 The typical applications circuit is shown in Figure 34. The application circuit shown has been replicated for the evaluation board circuit. 5019 1 C13 C9 1F 1F C11 C8 0.01F 0.01F C12 C7 IF_OUTPUT_USB 1 R1 0 100pF 100pF AGND PAD 32 31 30 29 28 27 26 25 RF_INPUT 4 3 2 25-146-1000-92 PAD NIC VGRF NIC NIC NIC VDRF NIC NIC NIC GND RFIN GND NIC NIC NIC NIC ADMV1012AEZ NIC NIC IF1 NIC IF2 NIC NIC NIC 24 23 22 21 20 19 18 17 X1 1 4 SUM_PORT AGND GND GND 2 5 QCN-45+ 6 3 R4 IF_OUTPUT_LSB 1 0 4 3 2 25-146-1000-92 AGND AGND AGND AGND LO_INPUT 4 3 2 25-146-1000-92 C5 AGND 100pF C10 0.01F C3 1F 1 VDLO AGND 16349-049 LO_INPUT 1 PORT_2 50 _TERM PORT_1 9 10 11 12 13 14 15 16 AGND 1 2 3 4 5 6 7 8 25-146-1000-92 DUT NIC LOIN GND NIC NIC NIC VDLO NIC RF_INPUT 1 4 3 2 AGND AGND 5019 VDLO Figure 34. Typical Application Circuit Rev. A | Page 15 of 19 ADMV1012 Data Sheet EVALUATION BOARD INFORMATION Power-On Sequence The circuit board used in the application must use RF circuit design techniques. Signal lines must have 50 impedance, and the package ground leads and exposed pad must be connected directly to the ground plane similarly to that shown in Figure 35 and Figure 36. Use a sufficient number of via holes to connect the top and bottom ground planes. The evaluation circuit board shown in Figure 34 is available from Analog Devices upon request. To set up the ADMV1012-EVALZ, take the following steps: Layout Solder the exposed pad on the underside of the ADMV1012 to a low thermal and electrical impedance ground plane. This pad is typically soldered to an exposed opening in the solder mask on the evaluation board. Connect these ground vias to all other ground layers on the evaluation board to maximize heat dissipation from the device package. Figure 35 shows the PCB land pattern footprint for the ADMV1012-EVALZ, and Figure 36 shows the solder paste stencil for the ADMV1012-EVALZ evaluation board. 1. 2. 3. 4. 5. 6. 7. Power up the VGRF with a -1.8 V supply. Power up the VDRF with a 3 V supply. Power up the VDLO with a 3 V supply. Adjust the VGRF supply between -1.8 V to -0.4 V until IDRF = 68 mA. Connect LOIN to the LO signal generator with an LO power of between -4 dBm to +4 dBm. For the upper sideband, add a 50 termination to the IF_OUTPUT_LSB connector. For the lower sideband, add a 50 termination to the IF_OUTPUT_USB connector. Apply a RF signal to the RF_INPUT and LO_INPUT ports. Power-Off Sequence To turn off the ADMV1012-EVALZ, take the following steps: 1. 2. 3. 4. 5. Turn off the LO and RF signals. Set VGRF to -1.8 V. Set the VDRF supply to 0 V and then turn off the VDRF supply. Set the VDLO supply to 0 V and then turn off the VDLO supply. Turn off the VGRF supply. 0.217" SQUARE SOLDER MASK 0.004" MASK/METAL OVERLAP 0.010" MINIMUM MASK WIDTH GROUND PAD PAD SIZE 0.026" x 0.010" PIN 1 0.197" [0.50] 0.156" MASK OPENING o.034" TYPICAL VIA SPACING o.010" TYPICAL VIA 0.138" SQUARE MASK OPENING 0.02 x 45 CHAMFER FOR PIN 1 0.146" SQUARE GROUND PAD Figure 35. PCB Land Pattern Footprint of the ADMV1012-EVALZ Rev. A | Page 16 of 19 16349-050 0.010" REF 0.030" MASK OPENING Data Sheet ADMV1012 0.017 0.0197 TYP 0.219 SQUARE 0.132 SQUARE 0.017 R0.0040 TYP 132 PLCS 0.010 TYP 16349-051 0.027 TYP NOTES 1. NOT ALL COMPONENTS OR BIAS LINES ARE USED ON THE EVALUATION BOARD. Figure 37. ADMV1012-EVALZ Evaluation Board Top Layer Rev. A | Page 17 of 19 16349-052 Figure 36. Solder Paste Stencil of the ADMV1012-EVALZ ADMV1012 Data Sheet BILL OF MATERIALS Table 6. Qty. 1 4 Component Evaluation board C5, C7, C12 4 4 7 C8, C10, C11 C3, C9, C13 GND, VDLO, VDRF, VGRF 4 2 1 LO_INPUT, RF_INPUT, IF_OUTPUT_LSB, IF_OUTPUT_USB R1, R4 X1 1 Device under test (DUT) 1 Heatsink Description PCB 100 pF, high temperature, multilayer ceramic capacitors, NP0, 0402 0.01 F ceramic capacitors, X7R, 0402 1 F ceramic capacitors, X5R, 0603 CONN-PCB test points, compact mini, CNKEY5019 CONN-PCB, SMA K_SRI-NS, CNSMAL460W295H156 0 resistor chips, SMD, JMPR, 0402 XFMR, power splitter/combiner, 2500 MHz to 4500 MHz, TSML126W63H42 17.5 GHz to 24 GHz, GaAs, MMIC, I/Q downconverter Heatsink Rev. A | Page 18 of 19 Manufacturer/Part No. Analog Devices, Supplied/042365 TDK/C1005NP01H101J050BA Murata Manufacturing/GRM155R71E103KA01D Murata Manufacturing/GRM188R61E105KA12D Keystone Electronics Corporation/5019.00 SRI CONNECTOR GAGE/25-146-1000-92 Panasonic/ERJ-2GE0R00X Mini-Circuits/QCN-45+ Analog Devices Supplied/ADMV1012AEZ Analog Devices Supplied/104365 Data Sheet ADMV1012 OUTLINE DIMENSIONS 5.05 4.90 SQ 4.75 PIN 1 INDICATOR 0.36 0.30 0.24 0.08 REF 1 0.50 BSC 3.60 3.50 SQ 3.40 EXPOSED PAD 17 0.38 0.32 0.26 TOP VIEW 1.10 1.00 0.90 PIN 1 32 25 24 8 16 9 BOTTOM VIEW 0.20 MIN 3.50 REF 4.10 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. PKG-004843 SEATING PLANE 04-24-2017-D SIDE VIEW Figure 38. 32-Terminal Ceramic Leadless Chip Carrier [LCC] (E-32-1) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADMV1012AEZ ADMV1012AEZ-R7 ADMV1012-EVALZ 1 Package Body Material Alumina Ceramic Alumina Ceramic Lead Finish Gold Over Nickel Gold Over Nickel Temperature Range -40C to +85C -40C to +85C Z = RoHS Compliant Part. (c)2017-2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D16349-0-2/18(A) Rev. A | Page 19 of 19 Package Description 32-Terminal LCC 32-Terminal LCC Evaluation Board Package Option E-32-1 E-32-1