Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
1
SR020-1P
07/17/2002
FEATURES
• High-speed access time: 10, 12, 15, 20 ns
• Low active power: 400 mW (typical)
• Low standby power
— 250 µW (typical) CMOS standby
— 55 mW (typical) TTL standby
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 5V power supply
DESCRIPTION
The
ISSI
IS61C256AH is a very high-speed, low power,
32,768 word by 8-bit static RAMs. They are fabricated using
ISSI
's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design
techniques, yields access times as fast as 10 ns maximum.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 250 µW (typical) with CMOS input levels.
Easy memory expansion is provided by using an active
LOW Chip Enable (CE) input and an active LOW Output
Enable (OE) input. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
The IS61C256AH is pin compatible with other 32K x 8
SRAMs and are available in 28-pin SOJ and TSOP (Type I)
packages.
IS61C256AH
32K x 8 HIGH-SPEED CMOS STATIC RAM JULY 2002
FUNCTIONAL BLOCK DIAGRAM
A0-A14
CE
OE
WE
32K X 8
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VCC
I/O
DATA
CIRCUIT
I/O0-I/O7
ISSI
®
ISSI reserves the right to make changes this specification herein and it products at any time without notice. ISSI assumes no responsibility or liability arising out of the application or use of any information,
product or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
© Copyright 2001, Integrated Silicon Solution, Inc.
2
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
SR020-1P
07/17/02
IS61C256AH ISSI
®
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
PIN CONFIGURATION
28-Pin SOJ PIN CONFIGURATION
28-Pin TSOP
PIN DESCRIPTIONS
A0-A14 Address Inputs
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7 Bidirectional Ports
Vcc Power
GND Ground
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND –0.5 to +7.0 V
TBIAS Temperature Under Bias –55 to +125 °C
TSTG Storage Temperature –65 to +150 ° C
PTPower Dissipation 1.5 W
IOUT DC Output Current (LOW) 20 mA
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
TRUTH TABLE
Mode WEWE
WEWE
WE CECE
CECE
CE OEOE
OEOE
OE I/O Operation Vcc Current
Not Selected X H X High-Z ISB1, ISB2
(Power-down)
Output Disabled H L H High-Z ICC
Read H L L DOUT ICC
Write L L X DIN ICC
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
3
SR020-1P
07/17/02
IS61C256AH ISSI
®
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-10 -12 -15 -20
Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit
ICC Vcc Dynamic Operating VCC = Max., CE = VIL Com. — 165 — 155 — 145 — 135 mA
Supply Current IOUT = 0 mA, f = fMAX Ind. — — — 165 — 155 — 145
ISB1TTL Standby Current VCC = Max., C o m. — 2 5 — 2 5 — 2 5 — 25 mA
(TTL Inputs) VIN = VIH or VIL Ind. — — — 30 — 30 — 30
CE • VIH, f = 0
ISB2CMOS Standby VCC = Max., C om . — 2 — 2 — 2 — 2 mA
Current (CMOS Inputs) CE • VCC – 0.2V, Ind. — — — 1 0 — 10 — 10
VIN • VCC – 0.2V, or
VIN - 0.2V, f = 0
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
OPERATING RANGE
Range Ambient Temperature Speed VCC
Commercial 0°C to +70°C -10, -12 5V ± 5%
-15, -20 5V ± 10%
Industrial –40°C to +85°C -12 5V ± 5%
-15, -20 5V ± 10%
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 — V
VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA — 0.4 V
VIH Input HIGH Voltage 2.2 VCC + 0.5 V
VIL Input LOW Voltage(1) –0.5 0.8 V
ILI Input Leakage GND - VIN - VCC Com. –5 5 µA
Ind. –10 10
ILO Output Leakage GND - VOUT - VCC, Com. –5 5 µA
Outputs Disabled Ind. –10 10
Note:
1. VIL = –3.0V for pulse width less than 10 ns.
4
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
SR020-1P
07/17/02
IS61C256AH ISSI
®
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-10 ns -12 ns -15 ns -20 ns
Symbol Parameter Min. Max Min. Max. Min. Max. Min. Max. Unit
tRC Read Cycle Time 10 — 12 — 15 — 20 — ns
tAA Address Access Time — 10 — 12 — 1 5 — 2 0 ns
tOHA Output Hold Time 2 — 2 — 2 — 2 — ns
tACE CE Access Time — 1 0 — 1 2 — 1 5 — 2 0 ns
tDOE OE Access Time — 5 — 5 — 7 — 8 ns
tLZOE
(2)
OE to Low-Z Output 0 — 0 — 0 — 0 — ns
tHZOE
(2)
OE to High-Z Output — 5 — 6 — 7 — 9 ns
tLZCE
(2)
CE to Low-Z Output 2 — 3 — 3 — 3 — ns
tHZCE
(2)
CE to High-Z Output — 5 — 7 — 8 — 9 ns
tPU
(3)
CE to Power-Up 0 — 0 — 0 — 0 — ns
tPD
(3)
CE to Power-Down — 10 — 12 — 15 — 18 ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 3 ns
Input and Output Timing 1.5V
and Reference Levels
Output Load See Figures 1 and 2
CAPACITANCE(1,2)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 8 pF
COUT Output Capacitance VOUT = 0V 10 p F
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
5
SR020-1P
07/17/02
IS61C256AH ISSI
®
DATA VALID
READ1.eps
PREVIOUS DATA VALID
t AA
t OHA t OHA
t RC
D
OUT
ADDRESS
t RC
t OHA
t AA
t DOE
t LZOE
t ACE
t LZCE
t HZOE
HIGH-Z DATA VALID
CE_RD2.eps
ADDRESS
OE
CE
D
OUT
t HZCE
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
READ CYCLE NO. 2(1,3)
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
AC TEST LOADS
Figure 2
480 Ω
5 pF
Including
jig and
scope
255 Ω
OUTPUT
5V
480 Ω
30 pF
Including
jig and
scope
255 Ω
OUTPUT
5V
Figure 1
6
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
SR020-1P
07/17/02
IS61C256AH ISSI
®
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-10 ns -12 ns -15 ns -20 ns
Symbol Parameter Min. Max Min. Max. Min. Max. Min. Max. Unit
tWC Write Cycle Time 10 — 12 — 15 — 20 — ns
tSCE CE to Write End 9 — 1 0 — 1 0 — 1 3 — ns
tAW Address Setup Time 9 — 10 — 12 — 15 — ns
to Write End
tHA Address Hold 0 — 0 — 0 — 0 — ns
from Write End
tSA Address Setup Time 0 — 0 — 0 — 0 — ns
tPWE1WE Pulse Width (OE LOW) 8 — 8 — 1 0 — 1 3 — ns
tPWE2WE Pulse Width (OE HIGH) 6.5 — 7 — 8 — 1 0 — ns
tSD Data Setup to Write End 7 — 7 — 9 — 1 0 — ns
tHD Data Hold from Write End 0 — 0 — 0 — 0 — ns
tHZWE
(2)
WE LOW to High-Z Output — 6 — 6 — 7 — 8 ns
tLZWE
(2)
WE HIGH to Low-Z Output 0 — 0 — 0 — 0 — ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
AC WAVEFORMS
WRITE CYCLE NO. 1 (WEWE
WEWE
WE Controlled)(1,2)
DATA UNDEFINED
t WC
VALID ADDRESS
t SCE
t PWE1
t PWE2
t AW
t HA
HIGH-Z
t HD
t SA
t HZWE
ADDRESS
CE
WE
DOUT
DIN DATAIN VALID
t LZWE
t SD
CE_WR1.eps
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
7
SR020-1P
07/17/02
IS61C256AH ISSI
®
WRITE CYCLE NO. 2
(OE is HIGH During Write Cycle)
(1,2)
WRITE CYCLE NO. 3
(OE is LOW During Write Cycle)
(1)
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE • VIH.
DATA UNDEFINED
LOW
t WC
VALID ADDRESS
t PWE1
t AW
t HA
HIGH-Z
t HD
t SA t HZWE
ADDRESS
CE
WE
DOUT
DIN
OE
DATAIN VALID
t LZWE
t SD
CE_WR2.eps
DATA UNDEFINED
t
WC
VALID ADDRESS
LOW
LOW
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
DOUT
DIN
OE
DATA
IN
VALID
t
LZWE
t
SD
CE_WR3.e
p
s
8
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
SR020-1P
07/17/02
IS61C256AH ISSI
®
ORDERING INFORMATION: IS61C256AH
Commercial Range: 0°C to +70°C
Speed (ns) Order Part Number Package
10 IS61C256AH-10J 300-mil Plastic SOJ
IS61C256AH-10T TSOP (Type 1)
12 IS61C256AH-12J 300-mil Plastic SOJ
IS61C256AH-12T TSOP (Type 1)
15 IS61C256AH-15J 300-mil Plastic SOJ
IS61C256AH-15T TSOP (Type 1)
20 IS61C256AH-20J 300-mil Plastic SOJ
IS61C256AH-20T TSOP (Type 1)
ORDERING INFORMATION: IS61C256AH
Industrial Range: –40°C to +85°C
Speed (ns) Order Part Number Package
12 IS61C256AH-12JI 300-mil Plastic SOJ
IS61C256AH-12TI TSOP (Type 1)
15 IS61C256AH-15JI 300-mil Plastic SOJ
IS61C256AH-15TI TSOP (Type 1)
20 IS61C256AH-20JI 300-mil Plastic SOJ
IS61C256AH-20TI TSOP (Type 1)
