UJA1079ATW/3V3,118 - NXP Semiconductors

1. General description

The UJA1079A core System Basis Chip (SBC) replaces the basic discrete components

commonly found in Electronic Control Units (ECU) with a Local Interconnect Network

(LIN) interface.

The UJA1079A supports the networking applications used to control power and sensor

peripherals by using the LIN interface as a local sub-bus.

The core SBC contains the following integr ated devices:

•LIN transceiver compliant with LIN 2.1, LIN 2.0 and SAE J2602, and compatible with

LIN 1.3

•Advanced independent watchdog (UJA1079A/xx/WD versions)

•250 mA volt age regulator for supplying a microcontroller; extendable with external

PNP transistor for increased current capability and dissipation distribution

•Serial Peripheral Interface (SPI) (full duplex)

•2 local wake-up input ports

•Limp home output port

In addition to the advantages gained from integrating these common ECU functions in a

single package, the core SBC offers an intelligent combination of system-specific

functions such as:

•Advanced low-power concep t

•Safe and controlled system start-up behavior

•Detailed status reporting on system and sub-system levels

The UJA1079A is designed to be used in combination with a microcontroller. The SBC

ensures that the microcontroller always starts up in a controlle d manner.

UJA1079A

LIN core system basis chip

Rev. 2 — 31 January 2011 Product data sheet

Product data sheet Rev. 2 — 31 January 20 11 2 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

2. Features and benefits

2.1 General

Contains LIN ECU functions:

LIN transceiver

Scalable 3.3 V or 5 V voltage regulator delivering up to 250 mA for a

microcontroller and peripheral circuitry; an external PNP transistor can be

connected for better heat distribution over the PCB

Watchdog with Window and Timeout modes and on-chip oscillator

Serial Peripheral Interface (SPI) for communicating with the microcontroller

ECU power management system

Designed for auto mo tiv e ap plic at ion s:

Enhanced ElectroMagnetic Compatibility (EMC) performance

±8 kV ElectroStatic Discharge (ESD) protection Human Body Model (HBM) on the

LIN bus pin and the wake-up pins

±6 kV ElectroS t atic Discharge protection IEC 61000-4-2 on the LIN bus pin and the

wake-up pins

±58 V short-circuit proof LIN bus pin

Battery and LIN bus pins are protected against transients in accordance with

ISO 7637-3

Small 6.1 mm × 11 mm HTSSOP32 package with low thermal resistance

Pb-free; Restriction of Hazardous Substances Directive (RoHS) and dark green

compliant

2.2 LIN transceiver

LIN 2.1 compliant LIN transceiver

Compliant with SAE J2602

Downward compatible with LIN 2.0 and LIN 1.3

Low slope mode for optimized EMC performance

Integrated LIN termination diode at pin DLIN

2.3 Power management

Wake-up via LIN or local wak e- up pins with wake-up source detection

2 wake-up pins:

WAKE1 and WAKE2 inputs can be switched off to reduce current flow

Output signal (WBIAS) to bias the wake-up pins, se lectable sampling time of 16 ms

or 64 ms

Standby mode with very low standby current and full wake-up capability; V1 active to

maintain supply to the microcontroller

Sleep mode with very low sleep current and full wake-up capability

2.4 Control and diagnostic features

Safe and predictable behavior under all conditions

Programmable watchdog with independent clock source

Product data sheet Rev. 2 — 31 January 20 11 3 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

Window, Timeout (with optional cyclic wake-up) and Off modes supported (with

automatic re-enable in the event of an interrupt)

16-bit Serial Peripher al Interface (SPI) for configuration, control and diagnosis

Global enable output for controlling safety-critical hardware

Limp home output (LIMP) for activating application-specific ‘limp home’ hardware in

the event of a serious system malfunction

Overtemperature shutdown

Interrupt output pin; interrupt s can be individually configured to signal V1 under voltage,

LIN/local wake-up and cyclic and power-on interrupt events

Bidirectional reset pin with variable power-on reset length to support a variety of

microcontrollers

Software-initiated system reset

2.5 Voltage regulator V1

Scalable voltage regulator for the microcontroller, its periph erals and additional

external tran sce ive rs

±2 % ac curacy

3.3 V and 5 V versions available

Delivers up to 250 mA and ca n be combi ned with a n external PNP tra nsistor for better

heat distribution over the PCB

Selectable current threshold at which the external PNP transistor starts to deliver

current

Undervoltage warning at 90 % of nominal output voltage and undervoltage reset at

90 % or 70 % of nominal output voltage

Can operate at V BAT voltages down to 4.5 V (e .g. during cran king), in accordan ce with

ISO 7637 pulse 4/4b and ISO16750-2

Stable output under all conditions

3. Ordering information

[1] UJA1079ATW/5V0xx versions contain a 5 V regulator (V1); UJA1079ATW/3V3xx versions contain a 3.3 V regulator (V1); WD versions

contain a watchdog.

Table 1. Ordering information

Type number[1] Package

Name Description Version

UJA1079ATW/5V0/WD HTSSOP32 plastic thermal enhanced thin shrink small outline package;

32 leads; body width 6.1 mm; lead pitch 0.65 mm; exposed die

pad

SOT549-1

UJA1079ATW/3V3/WD

UJA1079ATW/5V0

UJA1079ATW/3V3

Product data sheet Rev. 2 — 31 January 20 11 4 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

4. Block diagram

Fig 1. Block diagram

SYSTEM

CONTROLLER

LIN

BAT

UJA1079A

SDI

SCK

SCSN

SDO

WAKE2

WAKE1

WDOFF

LIN

RXDL

TXDL

DLIN BAT

BAT

LIMP

OSC

TEMP

INTN

RSTN

EXT. PNP

CTRL VEXCC

VEXCTRL

V1 V1

GND

WAKE

WBIAS

015aaa194

Product data sheet Rev. 2 — 31 January 20 11 5 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

5. Pinning information

5.1 Pinning

5.2 Pin description

Fig 2. Pin configuration

UJA1079A

i.c. BAT

i.c. VEXCTRL

TXDL TEST2

V1 VEXCC

RXDL WBIAS

RSTN i.c.

INTN DLIN

EN LIN

SDI i.c.

SDO GND

SCK i.c.

SCSN i.c.

i.c. i.c.

i.c. WAKE2

TEST1 WAKE1

WDOFF LIMP

015aaa195

Table 2. Pin description

Symbol Pin Description

i.c. 1 internally connected; should be left floating

i.c. 2 internally connected; should be left floating

TXDL 3 LIN transmit data input

V1 4 voltage regulator output for the microcontroller (5 V or 3.3 V depending on

SBC version)

RXDL 5 LIN receive data output

RSTN 6 reset input/output to and from the microcontroller

INTN 7 i nterrupt output to the microcontroller

EN 8 enable output

SDI 9 SPI data input

SDO 10 SPI data output

SCK 11 SPI clock input

SCSN 12 SPI chip select input

i.c. 13 internally connected; should be left floating

i.c. 14 internally connected; should be left floating

TEST1 15 test pin; pin should be connected to ground

WDOFF 16 WDOFF pin for deactivating the watchdog

LIMP 17 l imp home output

Product data sheet Rev. 2 — 31 January 20 11 6 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

The exposed die pad at the bottom of the package allows for better heat dissipation from

the SBC via the printed- circuit b oar d. The expose d d ie pad is not conn ected to any active

part of the IC and can be left floating, or can be connected to GND.

6. Functional description

The UJA1079A combines the functionality of a LIN transceiver, a voltage regulator and a

watchdog (UJA1079A/xx/WD versions) in a single, dedicated chip. It handles the

power-up and power-down functionality of the ECU and ensures advanced system

reliability. The SBC offers wake-up by bus activity, by cyclic wake-up and by the activation

of external switches. Additionally, it provides a periodic control signal for pulsed testing of

wake-up switches, allowing low-current operation even when the wake-up switches are

closed in Standby mode.

The LIN transceiver is optimized to be highly flexible with regard to bus topologies.

V1, the voltage regulator, is designed to power the ECU's microcontroller, its peripherals

and additional e xte rn al tra nsceive rs. An e xterna l PNP tr ansisto r can be ad ded to impr ove

heat distribution. The watchdog is clocked directly by the on-chip oscillator and can be

operated in Window, Timeout an d Off modes.

6.1 System Controller

6.1.1 Introduction

The system controller manages register configuration and controls the internal functions

of the SBC. Detailed device status information is collected and presented to the

microcontroller. The system controller also provides the reset and interrupt signals.

WAKE1 18 local wake-up input 1

WAKE2 19 local wake-up input 2

i.c. 20 internally connected; should be left floating

i.c. 21 internally connected; should be left floating

i.c. 22 internally connected; should be left floating

GND 23 ground

i.c. 24 internally connected; should be left floating

LIN 25 LIN bus line

DLIN 26 LIN termination resistor connection

i.c. 27 internally connected; should be left floating

WBIAS 28 control pin for external wake biasin g transistor

VEXCC 29 current measurement for external PNP transistor; this pin is connected to

the collector of the external PNP transistor

TEST2 30 test pin; pin should be connected to ground

VEXCTRL 31 control pin of the external PNP transistor; this pin is connected to the base

of the external PNP transistor

BAT 32 battery supply for the SBC

Table 2. Pin description …continued

Symbol Pin Description

Product data sheet Rev. 2 — 31 January 20 11 7 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

The system controller is a state machine. The SBC ope ratin g modes, and how transitions

between modes are triggered, are illustrated in Figure 3. These modes are discussed in

more detail in the following sections.

Product data sheet Rev. 2 — 31 January 20 11 8 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

Fig 3. UJA1079A system controller

V1: ON

LIN: Lowpower/Off

watchdog: Timeout/Off

MC = 00

Standby

watchdog

trigger

V1: ON

LIN: Active/Lowpower

watchdog: Window/

Timeout/Off

MC = 1x

Normal

V1: OFF

LIN: Lowpower/Off

watchdog: OFF

RSTN: LOW

MC = 01

Sleep

successful

watchdog

trigger

watchdog overflow or

V1 undervoltage

V1: OFF

LIN: Off and

high resistance

watchdog: OFF

INTN: HIGH

Off

VBAT below

power-on threshold Vth(det)pon

VBAT below

power-off threshold Vth(det)poff

(from all modes)

V1: OFF

limp home = LOW (active)

LIN: Off and

high resistance

watchdog: OFF

Overtemp

from Standby or Normal

chip temperature above

OTP activation threshold Tth(act)otp

chip temperature below

OTP release threshold Tth(rel)otp

VBAT above

power-on threshold Vth(det)pon

MC = 01 and

INTN = HIGH and

one wake-up enabled and

no wake-up pending

wake-up event if enabled

MC = 01 and

INTN = HIGH and

one wake-up enabled and

no wake-up pending

reset event or

MC = 00 MC = 10 or MC = 11

015aaa12

Product data sheet Rev. 2 — 31 January 20 11 9 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

6.1.2 Off mode

The SBC switches to Off mode from all other mod es if the battery supply drops below the

power-off detection threshold (Vth(det)poff). In Off mode, the voltage regulator is disabled

and the bus system is in a high-resistive state.

As soon as the battery supply rises above the power-on detection threshold (Vth(det)pon),

the SBC goes to Standby mode, and a syste m re se t is exec ut ed (re se t puls e width of

tw(rst), long or short; see Section 6.5.1 and Table 11).

6.1.3 Standby mode

The SBC will enter Standby mode:

•From Off mode if VBAT rises above the power-on detection thresho ld (Vth(det)pon)

•From Sleep mode on the occurrence of a LIN or local wake-up event

•From Overtemp mode if the chip temperature drops below the overtemperature

protection release threshold, Tth(rel)otp

•From Normal mode if bit MC is set to 00 or a system reset is performed (see

Section 6.5)

In Standby mode, V1 is switched on. The LIN transceiver will either be in a low-power

state (Lowpower mode; STBCL = 1; see Table 6) with bus wake-up detection enabled or

completely switched of f (Of f mode; STBCL = 0) - see Section 6.7.1. The watchdog can be

running in Timeout mode or Off mode, depending on the state of the WDOFF pin and the

setting of the watchdog mode control bit (WMC) in the WD_and_Status register (Table 4).

The SBC will exit Standby mode if:

•Normal mode is selected by setting bits MC to 10 or 11

•Sleep mode is selected by setting bits MC to 01

•The chip temperature rises above the OverTemperature Prote ctio n (OT P) activation

threshold, Tth(act)otp, causing the SBC to enter Overtemp mode

6.1.4 Normal mode

Normal mode is selected from Standby mode by setting bits MC in the Mode_Control

In Normal mode, the LIN physical layer (LIN) will be enabled (Active mode; STBCL = 0;

see Table 6) or in a low-power state (Lowpower mode; STBCL = 1) with bus wake-up

detection active.

The SBC will exit Normal mode if:

•Standby mode is selected by setting bits MC to 00

•Sleep mode is selected by setting bits MC to 01

•A system reset is generated (see Section 6.1.3; the SBC will enter Standby mode)

•The chip temperature rises above the OTP activation threshold, Tth(act)otp, causing the

SBC to switch to Overtemp mode

Product data sheet Rev. 2 — 31 January 2011 10 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

6.1.5 Sleep mode

Sleep mode is selected from Standby mode or Normal mode by setting bits MC in the

Mode_Control register (Table 5) to 01. The SBC will enter Sleep mode providing there are

no pending interrupts (pin INTN = HIGH) or wake-up events and at least one wake-up

source is enabled (LIN or WAKE). Any attempt to enter Sleep mode while one of these

conditions has not been satisfied will result in a short reset (3.6 ms minimum pulse width;

see Section 6.5.1 and Table 11).

In Sleep mode, V1 is off and the LIN transceiver will be switched off (Off mode;

STBCL = 0; see Table 6) or in a low-power state (Lowpower mode; STBCL = 1) with bus

wake-up detection active - see Section 6.7.1). The watchdog is off and the reset pin is

LOW.

A LIN or local wake-up event will cause the SBC to switch from Sleep mode to S tandby

mode, generating a (short or lon g; see Section 6.5.1) system reset. The value of the mode

control bits (MC) will be changed to 00 and V1 will be enabled.

6.1.6 Overtemp mode

The SBC will enter Overtemp mode from Normal mode or S tandby mode when the chip

temperature exceeds the overtemperature protection activation threshold, Tth(act)otp.

In Overtemp mode, the voltage regulator is switched off and the bus system is in a

high-resistive state. When the SBC enters Overtemp mode, the RSTN pin is driven LOW

and the limp home control bit, LHC, is set so that the LIMP pin is driven LOW.

The chip temperature must drop a hysteresis level below the overtemperature shutdown

threshold before the SBC can exit Overtemp mode. After leaving Overtemp mode the

SBC enters Standby mode and a system r eset is generated (reset pulse width of tw(rst),

long or short; see Section 6.5.1 and Table 11).

6.2 SPI

6.2.1 Introduction

The Serial Peripheral Interface (SPI) provides the communication link wi th the

microcontroller, supporting multi-slave operations. The SPI is configured for full duplex

data transfer, so status information is returned when new control data is shifted in. The

interface also offers a read-only access option, allowing registers to be read back by the

application without changing the register content.

The SPI uses four interface signals for synchronization and data transfer:

•SCSN: SPI chip select; active LOW

•SCK: SPI clock; default level is LOW due to low-power concept

•SDI: SPI data input

•SDO: SPI data output; floating when pin SCSN is HIGH

Bit sampling is performed on the falling clock edge and data is shifted on the rising clock

edge (see Figure 4).

Product data sheet Rev. 2 — 31 January 20 11 11 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

6.2.2 Register map

The first three bits (A2, A1 and A0) of th e me ss ag e he a de r defin e th e re gis ter ad dr es s.

The fourth bit (RO) defines the selected register as read/write or read only.

Fig 4. SPI timing protocol

SCSN

SCK 01

sampled

floating floating

015aaa20

MSB 14 13 12 01 LSB

SDI

SDO

02 03 04 15 16

Table 3. Register map

Address bits 15, 14 and 13 Write access bit 12 = 0 Read/Write access bits 11... 0

000 0 = read/write, 1 = read only WD_and_Status register

001 0 = read/write, 1 = read only Mode_Control register

010 0 = read/write, 1 = read only Int_Control register

011 0 = read/write, 1 = read only Int_Status register

Product data sheet Rev. 2 — 31 January 2011 12 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

6.2.3 WD_and_Status register

[1] Bit NWP is set to its default value (100) after a reset.

Table 4. WD_and_Status register

Bit Symbol Access Power-on

default Description

15:13 A2, A1, A0 R 000 register addre ss

12 RO R/W 0 access status

0: register set to read/write

1: register set to read only

11 WMC R/W 0 watchdog mode control

0: Normal mode: watchdog in Window mode; Standby mode: watchdog in

Timeout mode

1: Normal mode: watchdog in Timeout mode; Standby mode: watchdog in

Off mode

10:8 NWP[1] R/W 100 nominal watchdog period

000: 8 ms

001: 16 ms

010: 32 ms

011: 64 ms

100: 128 ms

101: 256 ms

110: 1024 ms

111: 4096 ms

7 WOS/SWR R/W - watchdog off status/software reset

0: WDOFF pin LOW; watchdog mode determined by bit WMC

1: watchdog disabled due to HIGH level on pin WDOFF; results in software

reset

6 V1S R - V1 status

0: V1 output voltage above 90 % und ervoltage recovery threshold

(Vuvr;seeTable 10)

1: V1 output voltage below 90 % un dervoltage detection threshold

(Vuvd;seeTable 10)

5 reserved R 1

4 WLS1 R - wake-up 1 status

0: WAKE1 input voltage below switching threshold (Vth(sw))

1: WAKE1 input voltage above switching threshold (Vth(sw))

3 WLS2 R - wake-up 2 status

0: WAKE2 input voltage below switching threshold (Vth(sw))

1: WAKE2 input voltage above switching threshold (Vth(sw))

2:0 reserved R 000

Product data sheet Rev. 2 — 31 January 2011 13 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

6.2.4 Mode_Control register

[1] Bit LHWC is set to 1 after a reset.

[2] Bit LHC is set to 1 after a reset, if LHWC was set to 1 prior to the reset.

Table 5. Mode_Control register

Bit Symbol Access Power-on

default Description

15:13 A2, A1, A0 R 001 register address

12 RO R/W 0 access status

0: register set to read/write

1: register set to read only

11:10 MC R/W 00 mode control

00: Standby mode

01: Sleep mode

10: Normal mode

11: Normal mode

9LHWC

[1] R/W 1 limp home warning control

0: no limp home warning

1: limp home warning is set; next reset will activate LIMP output

8LHC

[2] R/W 0 limp home control

0: LIMP pin set floatin g

1: LIMP pin driven LOW

7 ENC R/W 0 enable control

0: EN pin driven LOW

1: EN pin driven HIGH in Normal mode

6 LSC R/W 0 LIN slope control

0: normal slope, 20 kbit/s

1: low slope, 10 .4 kbit/s

5 WBC R/W 0 wa ke bias control

0: pin WBIAS floating if WSEn = 0; 16 ms sampling if WSEn = 1

1: pin WBIAS LOW if WSEn = 0; 64 ms sampling if WSEn = 1

4 PDC R/W 0 power distribution control

0: V1 threshold current for activating the external PNP transistor; load current

rising; Ith(act)PNP = 85 mA; V1 threshold current for deactivating the external

PNP transistor; load current falling; Ith(deact)PNP =50mA; see Figure 7

1: V1 threshold current for activating the external PNP transistor; load current

rising; Ith(act)PNP = 50 mA; V1 threshold current for deactivating the external

PNP transistor; load current falling; Ith(deact)PNP =15mA; see Figure 7

3:0 reserved R 0000

Product data sheet Rev. 2 — 31 January 2011 14 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

6.2.5 Int_Control register

Table 6. Int_Control register

Bit Symbol Access Power-on

default Description

15:13 A2, A1, A0 R 010 register address

12 RO R/W 0 access status

0: register set to read/write

1: register set to read only

11 V1UIE R/W 0 V1 un dervoltage interrupt enable

0: V1 undervoltage warning interrupts cannot be requested

1: V1 undervoltage warning interrupts can be requested

10 reserved R 0

9 STBCL R/W 0 LIN standby control

0: When the SBC is in Normal mode (MC = 1x):

LIN is in Active mode. The wake-up flag (visible on RXDL) is cleared

regardless of the value of VBAT.

When the SBC is in Standby/Sleep mode (MC = 0x):

LIN is in Off mode. Bus wake-up detection is disabled. LIN wake-up

interrupts cannot be requested.

1: LIN is in Lowpower mode with bus wake-up detection enabled, regardless

of the SBC mode (MC = xx). LIN wake-up interrupts can be requested.

8 reserved R 0

7:6 WIC1 R/W 00 wake-up interrupt 1 control

00: wake-up interrupt 1 disabled

01: wake-up interrupt 1 on rising edge

10: wake-up interrupt 1 on fall ing edge

11: wake-up interrupt 1 on both edges

5:4 WIC2 R/W 00 wake-up interrupt 2 control

00: wake-up interrupt 2 disabled

01: wake-up interrupt 2 on rising edge

10: wake-up interrupt 2 on fall ing edge

11: wake-up interrupt 2 on both edges

3 reserved R 0

2 RTHC R/W 0 reset threshold control

0: The reset threshold is set to the 90 % V1 undervoltage dete ction voltage

(Vuvd; see Table 10)

1: The reset threshold is set to the 70 % V1 undervoltage dete ction voltage

(Vuvd; see Table 10)

1 WSE1 R/W 0 WAKE1 sample enable

0: sampling continuously

1: sampling of WAKE1 is synchronized with WBIAS (sample rate controlled

by WBC)

Product data sheet Rev. 2 — 31 January 2011 15 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

6.2.6 Int_Status register

[1] An interrupt can be cleared by writing 1 to the relevant bit in the Int_Status register.

0 WSE2 R/W 0 WAKE2 sample enable

0: sampling continuously

1: sampling of WAKE1 is synchronized with WBIAS (sample rate controlled

by WBC)

Table 6. Int_Control register …continued

Bit Symbol Access Power-on

default Description

Table 7. Int_Status register[1]

Bit Symbol Access Power-on

default Description

15:13 A2, A1, A0 R 011 register ad d re ss

12 RO R/W 0 access status

0: register set to read/write

1: register set to read only

11 V1UI R/W 0 V1 undervoltage interrupts

0: no V1 undervoltage warning interrupt pending

1: V1 undervoltage warning interrupt pending

10 reserved R 0

9 LWI R/W 0 L IN wake-up interrupt

0: no LIN wake-up interrupt pending

1: LIN wake-up interrupt pending

8 reserved R 0

7 CI R/W 0 cyclic interrupt

0: no cyclic interrupt pending

1: cyclic interrupt pending

6 WI1 R/W 0 wa ke-up interrupt 1

0: no wake-up interrupt 1 pending

1: wake-up interrupt 1 pending

5 POSI R/W 1 power-on status interrupt

0: no power-on interrupt pending

1: power-on interrupt pending

4 WI2 R/W 0 wa ke-up interrupt 2

0: no wake-up interrupt 2 pending

1: wake-up interrupt 2 pending

3:0 reserved R 0000

Product data sheet Rev. 2 — 31 January 2011 16 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

6.3 On-chip oscillator

The on-chip oscillator provides the timing reference for the on-chip watchdog and the

internal timers. The on-chip oscillator is supplied b y an internal supply th at is connected to

VBAT and is independent of V1.

6.4 Watchdog (UJA1079A/xx/WD versions)

Three watchdog modes ar e supported: Window, Ti meout and Of f. The watchdog p eriod is

programmed via the NWP control bits in the WD_and_Status register (see Table 4). The

default watchdog period is 128 ms.

A watchdog trigger event is any write access to the WD_and_Status register. When the

watchdog is triggered, the watchdog timer is reset.

In watchdog Window mode, a watchdog trigger event within a closed watchdog window

(i.e. the fir st half of the window befor e ttrig(wd)1) will generate an SBC reset. If the watchdog

is triggered before the watchdog timer overflows in Timeout or Window mode, or within

the open watchdog window (after ttrig(wd)1 but before ttrig(wd)2), the timer restarts

immediately.

The following watchdog events result in an immediate system r eset:

•the watchdog overflows in Window mode

•the watchdog is triggered in the first half of the watchdog period in Window mode

•the watchdog overflows in Timeout mode while a cyclic interrupt (CI) is pending

•the state of the WDOFF pin changes in Normal mode or Standby mode

•the watchdog mode control bit (WMC) changes state in Normal mode

After a watchdog reset (short reset; see Section 6.5.1 and Table 11), the default watchdog

period is selected (NWP = 100). The watchdog can be switched off completely by forcing

pin WDOFF HIGH. The watchdog can also be switched off by setting bit WMC to 1 in

Standby mode. If the watchdog was turned off by setting WMC, any pending interrupt will

re-enable it.

Note that the state of bit WMC cannot be changed in Standby mode if an interrupt is

pending. Any attempt to change WMC when an interrupt is pending will be ignored.

6.4.1 Watchdog Window behavior

The watchdog runs continuously in Window mode.

If the watchdog overflows, or is trigger ed in the first half of th e watchdog period (less than

ttrig(wd)1 after the start of the watchdog period), a system reset will be performed.

Watchdog overflow occurs if the watchdog is not triggered within ttrig(wd)2 after the start of

the watchdog period.

If the watchdog is triggered in the second half of the watchdog period (at least t trig(wd)1, but

not more than ttrig(wd)2, after the start of the watchdog period), the watchdog will be reset.

The watchdog is in Window mode when pin WDOFF is LOW, the SBC is in Normal mode

and the watchdog mode control bit (WMC) is set to 0.

Product data sheet Rev. 2 — 31 January 2011 17 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

6.4.2 Watchdog Timeout behavior

The watchdog runs continuously in Timeout mode. It can be reset at any time by a

watchdog trigger. If the watchdog overflows, the CI bit is set. If a CI is already pending, a

system reset is performed.

The watchdog is in Timeout mode when pin WDOFF is LOW and:

•the SBC is in Standby mode and bit WMC = 0 or

• the SBC is in Normal mode and bit WMC = 1

6.4.3 Watchdog Off behavior

The watchdog is disabled in this state.

The watchdog is in Off mode when:

•the SBC is in Off, Overtemp or Sleep modes

•the SBC is in Standby mode and bit WMC = 1

•the SBC is in any mode and the WDOFF pin is HIGH

6.5 System reset

The following events will cause the SBC to perform a system reset:

•V1 undervolt age (reset pulse length selected via external pull-up resistor on RSTN

pin)

•An external reset (pin RSTN forced LOW)

•Watchdog overflow (Window mode)

•Watchdog overflow in Timeout mode with CI pending

•Watchdog triggered too early in Window mode

•WMC value changed in Normal mode

•WDOFF pin state changed

•SBC goes to Sleep mode (MC set to 01; see Table 5) while pin INTN is driven LOW

•SBC goes to Sleep mode (MC set to 01; see Table 5) while

STBCL = WIC1 = WIC2 = 0

•SBC goes to Sleep mode (MC set to 01; see Table 5) while wake-up pending

•Software reset (SWR = 1)

•SBC leaves Overtemp mode (reset pulse length selected via external pull-up resistor

on RSTN pin)

A watchdog overflow in Timeout mode requests a CI, if a CI is not already pending.

The UJA1079A provides three signals for dealing with reset events:

•RSTN pin input/output for performing a global ECU system reset or forcing an

external rese t

•EN pin, a fail-safe global enable output

•LIMP pin, a fail-safe limp home output

Product data sheet Rev. 2 — 31 January 2011 18 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

6.5.1 RSTN pin

A system reset is triggered if the bidirectional RSTN pin is forced LOW for at least tfltr by

the microcontroller (external reset). A reset pulse is output on pin RSTN by the SBC when

a system reset is triggered internally.

The reset pulse width (tw(rst)) is selectable (short or long) if the system reset was

generated by a V1 undervolt age event (see Section 6.6.2) or by the SBC leaving Off

(VBAT > Vth(det)pon) or Overtemp (temperature < Tth(rel)otp) modes. A short reset pulse is

selected by connecting a 9 00 Ω ±10 % resistor between pins RSTN and V1. If a resistor is

not connected, the reset pulse will be long (see Table 11).

In all other cases (e.g. watchdog-related reset events) the reset pulse length will be short.

6.5.2 EN output

The EN pin can be used to control external hardware, such as power comp onents, or as a

general-purpose output when the system is running properly.

In Normal and Standby modes, the microcontroller can set the EN control bit (bit ENC in

the Mode_Control register; see Table 5) via the SPI interface. Pin EN will be HIGH when

ENC = 1 and MC = 10 or 11. A reset event will cause pin EN to go LOW. EN pin behavior

is illustrated in Figure 5.

6.5.3 LIMP output

The LIMP pin can be used to enable the so called ‘limp home’ hardware in the event of an

ECU failure. Detectable failure conditions include SBC overtempe rature events, loss of

watchdog service, pins RSTN or V1 clamped LOW and user-initiated or external reset

events.

The LIMP pin is a battery-related, active-LOW, open-drain output.

A system reset will cause the limp home warning control bit (bit LHWC in the

Mode_Control register; see Table 5) to be set. If LHWC is already set when the system

reset is generated, bit LHC will be set which will force the LIMP pin LOW. The application

should clear LHWC after each reset event to ensure the LIMP output is not activated

during normal operation.

In Overtemp mode, bit LHC is always set and, consequently, the LIMP output is always

active. If the application manages to recover from the event that activated the LIMP

output, LHC can be cleared to deactivate the LIMP output.

Fig 5. Behavior of EN pin

RSTN

ENC

mode STANDBY NORMAL STANDBY

015aaa07

Product data sheet Rev. 2 — 31 January 2011 19 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

6.6 Power supplies

6.6.1 Battery pin (BAT)

The SBC contains a single supply pin, BAT. An external diode is needed in series to

protect the device against negative voltages. The operating range is from 4.5 V to 28 V.

The SBC can handle maximum voltages up to 40 V.

If the volt age on pin BAT falls below the power-of f dete ction threshold, Vth(det)poff, the SBC

immediately enters Off mode, which means that the voltage regulator and the intern al

logic are shut down. The SBC leaves Off mode for Standby mode as soon as the voltage

rises above the power-on detection threshold, Vth(det)pon. The POSI bit in the Int_Status

6.6.2 Volt age reg ulator V1

Voltage regulator V1 is inte nde d to sup ply the microcontr oller, its periphery and ad dition al

transceivers. V1 is supplied by pin BAT and delivers up to 250 mA at 3.3 V or 5 V

(depending on the UJA1079A version).

To prevent the device overheating at h igh ambient temperatu res or high average cur rents,

an external PNP transistor can be connected as illustrated in Figure 6. In this

configuration, the power dissipation is distributed between the SBC and the PNP

transistor. Bit PDC in the Mode_Control register (Table 5) is used to regulate how the

power dissipation is distributed. If PDC = 0, the PNP transistor will be activated when the

load current re aches 85 mA (50 mA if PDC = 1) at Tvj =150°C. V1 will continue to deliver

85 mA while the transistor delivers th e additional load current (see Figure 7 and Figure 8).

Fig 6. External PNP transistor control circuit

UJA1079A

VEXCTRL

VEXCC

015aaa196

BAT

battery

Product data sheet Rev. 2 — 31 January 2011 20 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

Figure 7 illustrates how V1 and the PNP transistor combine to supply a slow ramping load

current of 250 mA with PDC = 0. Any additional load current requirement will be supplied

by the PNP transistor, up to its current limit. If the load current continues to rise, IV1 will

increase above the selected PDC threshold (to a maximum of 250 mA).

For a fast ramping load current, V1 will deliver the required load current (to a maximum of

250 mA) until the PNP tr ansistor has switche d on. Once the transistor has been activa ted,

V1 will deliver 85 mA (PDC = 0) with the transistor contributing the balance of the load

current (see Figure 8).

Fig 7. V1 and PNP currents at a slow ramping load current of 250 mA (PDC = 0)

Fig 8. V1 and PNP currents at a fast ramping load current of 250 mA (PDC = 0)

015aaa11

250 mA

85 mA 50 mA

load

current

215 mA

165 mA

PNP

current

IV1

th(act)PNP

= 85 mA

(PDC = 0) Ith(deact)PNP = 50 mA

(PDC = 0)

load

current

250 mA

−165 mA

0 mA

IV1

165 mA

250 mA

PNP

current 015aaa075

Ith(act)PNP = 85 mA

(PDC = 0)

Product data sheet Rev. 2 — 31 January 2011 21 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

For short-circuit protection, a resistor needs to be connected between pins V1 and

VEXCC to allow the current to be monitored. This resistor limits the current delivered by

the external tra n sisto r. If the voltage difference between pins VEXCC an d V1 re ac hes

Vth(act)Ilim, the PNP current limiting activation threshold voltage, the transistor current will

not increase further.

The thermal performance of the transistor needs to be considered when calculating the

value of this resistor . A 3 .3 Ω resistor was used with the BCP52-16 (NXP Semiconductors)

employed during testing. Note th at the selectio n of the transistor is not critical. In general,

any PNP transistor with a current amplification factor (β) of between 60 an d 50 0 ca n be

used.

If an external PNP transistor is not used, pin VEXCC must be connected to V1 while pin

VEXCTRL can be left open.

One advantage of this scalable voltage regulator concept is that there are no PCB layout

restrictions when usin g the external PNP. The distance between the UJA1079A and the

external PNP doesn’t affect the stability of the regulator loop because the loop is realized

within the UJA1079A. Therefore, it is recommended that the distance between the

UJA1079A and PNP transistor be maximized for optimal thermal distribution.

The output voltage on V1 is monitored continuously and a system reset signal is

generated if an undervoltage event occurs. A system reset is generated if the volta ge on

V1 falls below the undervoltage detection voltage (Vuvd; see Table 10). The reset

threshold (90 % or 70 % of the nominal value) is set via the Reset Threshold Control bit

(RTHC) in the Int_Control register (Table 6). In addition, an undervolt age war ning (a V1UI

interrupt) will be generated at 90 % of the nominal output voltage. The st atus of V1 can be

read via bit V1S in the WD_and_Status register (Table 4).

6.7 LIN transceiver

The analog sections of the UJA1079A LIN transceiver are derived from those integrated

into the TJA1021. Unlike the TJA1021 however, the UJA1079A does not include an

internal slave termination resistor . Therefore, external termination resistors need to be

connected in both master and slave applications (see Figure 9 and Figure 10).

The transceiv er is the in te r fac e be twe e n th e LIN master/slav e pr ot oco l con tr olle r an d the

physical bus in a LIN. It is primarily intended for in-vehicle sub-networks using baud rates

from 1 kBd up to 20 kBd and is LIN 2.0/LIN 2.1/SAE J2602 compliant.

Product data sheet Rev. 2 — 31 January 2011 22 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

6.7.1 LIN operating modes

6.7.1.1 Active mode

The LIN transceiver will be in Active mode when:

•the SBC is in Normal mode (MC = 10 or 11) and

•the transceiver is enabled (STBCL = 0; see Table 6) and

•the battery voltage (VBAT) is above the LIN undervoltage recovery threshold, Vuvr(LIN).

In LIN Active mode, the transceiver can transmit and receive data via the LIN bus pin.

The receiver detects data streams on the LIN bus pin (LIN) and transfers them to the

microcontroller via pin RXDL (see Figure 1) - LIN recessive is represented by a HIGH

level on pin RXDL, LIN dominant by a LOW level.

The transmit data streams of the protocol controller at the TXDL input are converted by

the transmitte r int o bu s sign a ls with op tim ize d sle w rate an d wa ve shap in g to m inim ize

Electromagnetic Emissions (EME).

6.7.1.2 Lowpowe r /O ff mo de s

The LIN transceiver will be in Lowpower mode with bus wake-up detection enabled if bit

STBCL = 1 (see Table 6). The LIN transceiver can be woken up remotely via pin LIN in

Lowpower mode.

When the SBC is in Standby mode or Sleep mode (MC = 00 or 01), the LIN transceiver

will be in Off mode if bit STBCL = 0. The LIN transceiver is powered down completely in

Off mode to minimize quiescent current consumption.

Filters at the receiver input s prevent unwanted wake-up events due to automotive

transients or Electromagnetic Interferance (EMI).

The wake-up event must remain valid for at least the minimum dominant bus time for

wake-up of the LIN transceiver, twake(busdom)min (see Table 11).

Fig 9. Typical master application Fig 10. Typical slave application

UJA1079A

GND

015aaa23

LIN LIN wire

DLIN

BAT to supply

Rmaster

1 kΩ

Cmaster

UJA1079A

GND

015aaa23

LIN LIN wire

DLIN

BAT to supply

Rslave

30 kΩ

Cslave

Product data sheet Rev. 2 — 31 January 2011 23 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

6.7.2 Fail-safe features

6.7.2.1 General fail- sa fe fea t ure s

The following fail-safe features have been implemented:

•Pin TXDL has an internal pull-up towards VV1 to guarantee safe, defined states if

these pins are left floating

•The current of th e transmi tter outpu t st age is limited in orde r to prote ct the tran smitter

against short circuits to pin BAT

•A loss of power (pins BAT and GND) has no impact on the bus lines or on the

microcontroller. There will be no reverse currents from the bus.

6.7.2.2 TXDL dominant time-out function

A TXDL dominant time-out timer circ uit prevents the bus lines being driven to a pe rmanent

dominant state (blocking all network communications) if pin TXDL is forced permanently

LOW by a hardware and/or software application failure. The timer is triggered by a

negative edge on the TXDL pin. If the pin remains LOW for longer than the TXDL

dominant time-out time (tto(dom)TXDL), the transmitter is disabled, driving the bus lines to a

recessive state. The timer is reset by a positive edge on the TXDL pin.

6.8 Local wake-up input

The SBC provides 2 local wake-up pins (WAKE1 and WAKE2). The edge sensitivity

(falling, rising or both) of the wake-up pins can be configured independently via the WIC1

and WIC2 bits in the Int_Control register Table 6). These bits can also be used to disable

wake-up via the wake-up pins. When wake -up is enabled, a valid wa ke-up event on eith er

of these pins will cause a wake-up interrupt to be generated in Standby mode or Normal

mode. If the SBC is in Sleep mode when the wake-up event occurs, it will wake up and

enter Standby mode. The status of the wake-up pins can be read via the wake-up level

status bits (WLS1 and WLS2) in the WD_and_Status register (Table 4).

Note that bits WLS1 and WLS2 are only active when at least one of the wake up interru pts

is enabled (WIC1 ≠00 or WIC2 ≠00).

Fig 11. Wake-up pin sam pl ing sy nchro nize d with WBIAS signal

Wake-up int

WAKEx pin

WBIAS pin

WBIASI

(internal)

enable bias disable bias

disable bias

wake level latched 015aaa07

Product data sheet Rev. 2 — 31 January 2011 24 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

The sampling of the wake-up pins can be synchronized with the WBIAS signal by setting

bits WSE1 and WSE2 in the Int_Control register to 1 (if WSEx = 0, wake-up pins are

sampled continuously). The sampling will be performed on the rising edge of WBIAS (see

Figure 11). The sampling time, 16 ms or 64 ms, is selected via the Wake Bias Control bit

(WBC) in the Mode_Control register.

Figure 12 shows a typical circuit for imp lem e nt ing cyclic sa mp lin g of th e wa ke- u p inputs.

6.9 Interrupt output

Pin INTN is an active-LOW, open-drain interrupt output. It is driven LOW when at least

one interrupt is pending. An interrupt can be cleared by writing 1 to the corresponding bit

in the Int_Status register (Table 7). Clearing bit LWI in Standby mode only clears the

interrupt status bit and not the pending wake-up. The pending wake-up is cleared on

entering Normal mode and when the corresponding standby control bit (STBCL) is 0.

On devices that contain a watchdog, the CI is enabled when the watchdog switches to

Timeout mode while the SBC is in Standby mode or Normal mode (provided pin

WDOFF = LOW). A CI is generated if the watchdog overflows in Timeout mode.

The CI is provided to alert the microcontroller when the watchdo g overflows in Timeout

mode. The CI will wake up the microcontroller from a μC standby mode. After polling the

Int_Status register, the microcontroller will be aware that the application is in cyclic wake

up mode. It can then perform some checks on LIN before returning to the μC standby

mode.

6.10 Temperature protection

The temperature of the SBC chip is monitored in Normal and Standby modes. If the

temperature is too high, the SBC will go to Overtemp mode, where the RSTN pin is driven

LOW and limp home is activated. In addition, the volt age r egulator and th e LIN transmitte r

Fig 12. Typical application for cyclic sampling of wa ke-up signals

UJA1079A

WAKE1

WAKE2

BAT

WBIAS

015aaa19

47 kΩ

47 kΩPDTA144E

sample of

WAKEx

sample of

WAKEx

sample of

WAKEx

GND

biasing of

switches

Product data sheet Rev. 2 — 31 January 2011 25 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

are switched of f (s ee also Section 6.1.6 “Overtemp mode”). When the temperature falls

below the temperature shutdown threshold, the SBC will go into the Standby mode. The

temperature shutdown threshold is between 165 °C and 200 °C.

Product data sheet Rev. 2 — 31 January 2011 26 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

7. Limiting values

Table 8. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

Vxvoltage on pin x DC value

pins V1 and INTN −0.3 7 V

pins EN, SDI, SDO, SCK, SCSN, TXDL, RXDL,

RSTN and WDOFF −0.3 VV1 + 0.3 V

pin VEXCC VV1 −0.3 VV1 + 0.35 V

pins WAKE1, WAKE2, WBIAS and LIN;

with respect to any other pin −58 +58 V

pin LIMP and BAT −0.3 +40 V

pin VEXCTRL −0.3 VBAT + 0.3 V

pin DLIN; with respect to any other pin VBAT − 0.3 +58 V

IR(V1-BAT) reverse current from

pin V1 to pin BAT VV1 ≤5V [1] - 250 mA

IDLIN current on pin DLIN −65 0 mA

Vtrt transient voltage on pins

BAT: via reverse polarity diode/capacitor

LIN: coupling via 1 nF capacitor

DLIN, W AKE1, WAKE2: via 1 kΩ series resistor

[2] −150 +100 V

VESD electrostatic

discharge voltage IEC 61000-4-2 [3]

pins BAT with capacitor and LIN; via a series

resistor on pins DLIN, WAKE1, WAKE2, LIMP and

WBIAS; via transistor on pin VEXCTRL

[4] −6+6kV

HBM [5]

pins LIN, DLIN, WAKE1 and WAKE2 [6] −8+8kV

pin BAT; referenced to ground −4+4kV

pin TEST2; referenced to pin BAT −1.25 +2 kV

pin TEST2; referenced to other reference pins −2+2kV

any other pin −2+2kV

MM [7]

any pin −300 +300 V

CDM [8]

corner pins −750 +750 V

any other pin −500 +500 V

Tvj virtual junction

temperature [9] −40 +150 °C

Tstg storage temperature −55 +150 °C

Product data sheet Rev. 2 — 31 January 2011 27 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

[1] A reverse diode connected between V1 (anode) and BAT (cathode) limits the voltage drop voltage from V1(+) to BAT (−).

[2] Verified by an external test house to ensure pins can withstand ISO 7637 part 2 automotive transient test pulses 1, 2a, 3a and 3b.

[3] IEC 61000-4-2 (150 pF, 330 Ω).

[4] ESD performance according to IEC 61000-4-2 (150 pF, 330 Ω) has been verified by an external test house for pins BAT, LIN, WAKE1

and WAKE2. The result is equal to or better than ±6 kV.

[5] Human Body Model (HBM): according to AEC-Q100-002 ( 100 pF, 1.5 kΩ).

[6] V1 and BAT connected to GND, emulating application circuit.

[7] Machine Model (MM): according to AEC-Q100-003 (200 pF, 0.75 μH, 10 Ω).

[8] Charged Device Model (CDM): according to AEC-Q100-011 (field Induced charge; 4 pF).

[9] In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: Tvj =T

amb +P×Rth(vj-a), where Rth(vj-a) is a

fixed value to be used for the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient

temperature (Tamb).

Tamb ambient

temperature −40 +125 °C

Table 8. Limiting values …continued

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

Product data sheet Rev. 2 — 31 January 2011 28 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

8. Thermal characteristics

Layout conditions for Rth(j-a) measurements: board finish thickness 1.6 mm ±10 %, board double

layer, board dimensions 129 mm × 60 mm, board material FR4, Cu thickness 0.070 mm, thermal

via separation 1.2 mm, thermal via diameter 0.3 mm ±0.08 mm, Cu thickness on vias 0.025 mm.

Optional heat sink top layer of 3.5 mm × 25 mm will reduce thermal resistance (see Figure 14).

Fig 13. HTSSOP PCB

PCB copper area:

(bottom layer)

2 cm2

PCB copper area:

(bottom layer)

8 cm2

015aaa137

optional heatsink top layer

Product data sheet Rev. 2 — 31 January 2011 29 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

[1] According to JEDEC JESD51-2 and JESD51-3 at natura l convection on 1s board.

[2] According to JEDEC JESD51-2, JESD51-5 and JESD51-7 at natural convection on 2s2p board. Board with

two inner copper layers (thickness: 35 μm) and thermal via array under the exposed pad connected to the

first inner copper layer.

Fig 14. HTSSOP32 thermal resistance junction to ambient as a function of PCB copper

area

Table 9. Thermal characteristics

Symbol Parameter Conditions Typ Unit

Rth(j-a) thermal resistance from junction to

ambient single-layer board [1] 78 K/W

four-layer board [2] 36 K/W

PCB Cu heatsink area (cm2)

0 108462

015aaa138

Rth(j-a)

(K/W)

without heatsink top layer

with heatsink top layer

Product data sheet Rev. 2 — 31 January 2011 30 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

9. Static characteristics

Table 10. Static characteristics

Tvj =

−

C to +150

C; VBAT = 4.5 V to 28 V; VBAT > VV1; RLIN =500

; all voltages are defined with respect to ground;

positive currents flow in the IC; typical values are given at VBAT = 14 V; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Supply; pin BAT

VBAT battery supply voltage 4.5 - 28 V

IBAT batter y supply current MC = 00 (Standby; V1 on)

STBCL = 1 (LIN wake-up ena bled)

WIC1 = WIC2 = 11 (WAKE interrupts

enabled); 7.5 V < VBAT <28V

IV1 =0mA; V

RSTN = VSCSN = VV1

VTXDL = VV1; VSDI =V

SCK =0V

Tvj =−40 °C-7589μA

Tvj =25°C-6880μA

Tvj =150°C-6273μA

MC = 01 (Sleep; V1 off)

STBCL = 1 (LIN wake-up ena bled)

WIC1 = WIC2 = 11 (WAKE interrupts

enabled); 7.5 V < VBAT <28V

VV1 =0V

Tvj =−40 °C-5362μA

Tvj =25°C-4957μA

Tvj =150°C-4551μA

contributed by LIN wake-up receiver

STBCL = 1

VLIN =V

BAT; 5.5 V < VBAT <28V

-1.12 μA

contributed by WAKEx pin edge

detectors; WIC1 = WIC2 = 11

VWAKE1 =V

WAKE2 =V

BAT

0510μA

IBAT(add) additional battery supply

current 5.1 V < VBAT <7.5V - - 50 μA

4.5 V < VBAT <5.1V

V1 on (5 V version) --3 mA

LIN Active mode (recessive)

STBCL = 0; MC = 1x

VTXDL= VV1; IDLIN =I

LIN = 0 mA

5.5 V < VBAT <28V

- - 1300 μA

LIN Active mode (dominant)

STBCL = 0; MC = 1x

VTXDL = 0 V; IDLIN =I

LIN = 0 mA

VBAT =14V

--5 mA

LIN Active mode (dominant)

STBCL = 0; MC = 1x

VTXDL= 0 V; IDLIN =I

LIN = 0 mA

VBAT =28V

--10mA

Vth(det)pon power-on dete cti on threshold

voltage 4.5 - 5.5 V

Vth(det)poff power-off detection threshold

voltage 4.25 - 4.5 V

Product data sheet Rev. 2 — 31 January 2011 31 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

Vhys(det)pon power-on detection hysteresis

voltage 200 - - mV

Vuvd(LIN) LIN undervoltage detection

voltage 5- 5.3V

Vuvr(LIN) LIN undervoltage recovery

voltage 5- 5.5V

Vhys(uvd)LIN LIN undervoltage detection

hysteresis voltage 25 - 300 mV

Vuvd(ctrl)Iext external current control

undervoltage detection

voltage

5.9 - 7.5 V

Voltage source; pin V1

VOoutput voltage VO(V1)nom = 5 V; VBAT = 5.5 V to 28 V

IV1 =−200 mA to −5 mA 4.9 5 5.1 V

VO(V1)nom = 5 V; VBAT = 5.5 V to 28 V

IV1 = −250 mA to −200 mA 4.75 5 5.1 V

VO(V1)nom = 5 V; VBAT = 5.5 V to 5.75 V

IV1 = −250 mA to −5 mA

150 °C< T

vj <200°C

4.5 5 5.1 V

VO(V1)nom = 5 V; VBAT = 5.75 V to 28 V

IV1 = −250 mA to −5 mA

150 °C< T

vj <200°C

4.85 5 5.1 V

VO(V1)nom = 3.3 V; VBAT = 4.5 V to 28 V

IV1 = −250 mA to −5 mA 3.234 3.3 3.366 V

VO(V1)nom = 3.3 V; VBAT = 4.5 V to 28 V

IV1 = −250 mA to −5 mA

150 °C< T

vj <200°C

2.97 3.3 3.366 V

R(BAT-V1) resistance between pin BAT

and pin V1 VO(V1)nom = 5 V; VBAT = 4.5 V to 5.5 V

IV1 = −250 mA to −5 mA

regulator in saturation

--3 Ω

Vuvd undervoltage detection

voltage 90 %; VO(V1)nom = 5 V; RTHC = 0 4.5 - 4.75 V

90 %; VO(V1)nom = 3.3 V; RTHC = 0 2.97 - 3.135 V

70 %; VO(V1)nom = 5 V; RTHC = 1 3.5 - 3.75 V

Vuvr undervoltage recovery

voltage 90 %; VO(V1)nom = 5 V 4.56 - 4.9 V

90 %; VO(V1)nom = 3.3 V 3.025 - 3.234 V

IO(sc) short-circuit ou tput current IVEXCC = 0 mA −600 - −250 mA

Load regulation

ΔVV1 voltage variation on pin V1 as a function of load current variation

VBAT = 5.75 V to 28 V

IV1 = −250 mA to −5 mA

--25mV

Line regula ti on

ΔVV1 voltage variation on pin V1 as a function of supply voltage variation

VBAT = 5.5 V to 28 V; IV1 = −30 mA --25mV

Table 10. Static characteristics …continued

Tvj =

−

C to +150

C; VBAT = 4.5 V to 28 V; VBAT > VV1; RLIN =500

; all voltages are defined with respect to ground;

positive currents flow in the IC; typical values are given at VBAT = 14 V; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 2 — 31 January 2011 32 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

PNP base; pin VEXCTRL

IO(sc) short-circuit ou tput current VVEXCTRL ≥ 4.5 V; VBAT = 6 V to 28 V 3.5 5.8 8 mA

Ith(act)PNP PNP activation threshold

current load current increasing; external PNP

transistor connected - see Section 6.6.2

PDC 0 74 130 191 mA

PDC 0; Tvj =150°C748599mA

PDC 1 44 76 114 mA

PDC 1; Tvj =150°C445059mA

Ith(deact)PNP PNP deactivation threshold

current load current falling; external PNP

transistor connected - see Section 6.6.2

PDC 0 40 76 120 mA

PDC 0; Tvj =150°C445059mA

PDC 1 11 22 36 mA

PDC 1; Tvj =150°C121518mA

PNP collector; pin VEXCC

Vth(act)Ilim current limiting activation

threshold vo ltage measured across resistor connected

between pins VEXCC and V1 (see

Section 6.6.2)

2.97 V ≤ VV1 ≤ 5.5V; 6V < V

BAT < 28 V

240 - 330 mV

Serial peripheral interface inputs; pins SDI. SCK and SCSN

Vth(sw) switching threshold voltage VV1 = 2.97 V to 5.5 V 0.3VV1 -0.7V

V1 V

Vhys(i) input hysteresis voltage VV1 = 2.97 V to 5.5 V 100 - 900 mV

Rpd(SCK) pull-down resistance on pin

SCK 50 130 400 kΩ

Rpu(SCSN) pull-up resistance on pin

SCSN 50 130 400 kΩ

ILI(SDI) input leakage current on pin

SDI −5- +5 μA

Serial peripheral interface data output; pin SDO

IOH HIGH-level output current VSCSN = 0 V; VO = VV1 − 0.4 V

VV1 = 2.97 V to 5.5 V −30 - −1.6 mA

IOL LOW-level output current VSCSN = 0 V; VO = 0.4 V

VV1 = 2.97 V to 5.5 V 1.6 - 30 mA

ILO output leakage current VSCSN = VV1; VO = 0 V to VV1

VV1 = 2.97 V to 5.5 V −5- 5 μA

Reset output with clamping detection; pin RSTN

IOH HIGH-level output current VRSTN = 0.8VV1

VV1 = 2.97 V to 5.5 V −1500 - −100 μA

IOL LOW-level output current strong; VRSTN = 0.2VV1

VV1 = 2.97 V to 5.5 V

−40 °C< T

vj < 200 °C

4.9 - 40 mA

weak; VRSTN =0.8V

VV1 = 2.97 V to 5.5 V

−40 °C< T

vj < 200 °C

200 - 540 μA

Table 10. Static characteristics …continued

Tvj =

−

C to +150

C; VBAT = 4.5 V to 28 V; VBAT > VV1; RLIN =500

; all voltages are defined with respect to ground;

positive currents flow in the IC; typical values are given at VBAT = 14 V; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 2 — 31 January 2011 33 of 46

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VOL LOW-level output voltage VV1 = 1V to 5.5V

pull-up resistor to VV1 ≥ 900 Ω

−40 °C< T

vj < 200 °C; VBAT < 28 V

0 - 0.2VV1 V

VV1 = 2.975 V to 5.5 V

pull-up resistor to V1 ≥ 900 Ω

−40 °C< T

vj < 200 °C

0- 0.5V

VOH HIGH-level output voltage -40 °C< T

vj < 200 °C0.8V

V1 -V

V1 +

0.3 V

Vth(sw) switching threshold voltage VV1 = 2.97 V to 5.5 V 0.3VV1 -0.7V

V1 V

Vhys(i) input hysteresis voltage VV1 = 2.97 V to 5.5 V 100 - 900 mV

Interrupt output; pin INTN

IOL LOW-level output current VOL = 0.4 V 1.6 - 15 mA

Enable output; pin EN

IOH HIGH-level output current VOH = VV1 − 0. 4 V

VV1 = 2.97 V to 5.5 V −20 - −1.6 mA

IOL LOW-level output current VOL = 0.4 V; VV1 = 2.97 V to 5.5 V 1.6 - 20 mA

VOL LOW-level output voltage IOL = 20 μA; VV1 = 1.5 V - - 0.4 V

Watchdog off input; pin WDOFF

Vth(sw) switching threshold voltage VV1 = 2.97 V to 5.5 V 0.3VV1 -0.7V

V1 V

Vhys(i) input hysteresis voltage VV1 = 2.97 V to 5.5 V 100 - 900 mV

Rpupd pull-up/pull-down resistance VV1 = 2.97 V to 5.5 V 5 10 20 kΩ

Wake input; pin WAKE1, WAKE2

Vth(sw) switching threshold voltage 2 - 3.75 V

Vhys(i) input hysteresis voltage 100 - 1000 mV

Ipu pull-up current VWAKE = 0 V for t < twake −2- 0 μA

Ipd pull-down current VWAKE = VBAT for t < twake 0- 2 μA

Limp home output; pin LIMP

IOoutput current VLIMP = 0.4 V; LHC = 1

Tvj = −40 °C to 200 °C0.8 - 8 mA

Wake bias output; pin WBIAS

IOoutput current VWBIAS = 1.4 V 1 - 7 mA

LIN transmit data input; pin TXDL

Vth(sw) switching threshold voltage VV1 = 2.97 V to 5.5 V 0.3VV1 -0.7V

V1 V

Vhys(i) input hysteresis voltage VV1 = 2.97 V to 5.5 V 100 - 900 mV

Rpu pull-up resistance 4 12 25 kΩ

LIN receive data output; pin RXDL

IOH HIGH-level output current LIN Active mode; VRXDL = VV1 − 0.4 V −20 - −1.5 mA

IOL LOW-level output current VRXDL= 0.4 V 1.6 - 20 mA

Rpu pull-up resistance MC = 00; S tandby mode 4 12 25 kΩ

Table 10. Static characteristics …continued

Tvj =

−

C to +150

C; VBAT = 4.5 V to 28 V; VBAT > VV1; RLIN =500

; all voltages are defined with respect to ground;

positive currents flow in the IC; typical values are given at VBAT = 14 V; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 2 — 31 January 2011 34 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

LIN bus line; pin LIN

IBUS_LIM current limitation for driver

dominant state LIN Active mode; VBAT = VLIN = 18 V

VTXDL = 0 V 40 - 100 mA

IBUS_PAS_rec receiver recessive input

leakage current VLIN = 28 V; VBAT = 5.5 V; VTXDL = VV1 --2 μA

IBUS_PAS_dom receiver dominant input

leakage current including

pull-up resistor

VTXDL = VV1; VLIN = 0 V; VBAT = 14 V −10 - +10 μA

IL(log) loss of ground leakage

current VBAT = VGND =28V; V

LIN = 0 V −100 - 10 μA

IL(lob) loss of battery leakage

current VBAT = 0 V; VLIN = 28 V - - 2 μA

Vrec(RX) receiver recessive voltage VBAT = 5.5 V to 18 V 0.6 ×

VBAT

-- V

Vdom(RX) receiver dominant voltage VBAT = 5.5 V to 18 V - - 0.4VBAT V

Vth(cntr)RX receiver center threshold

voltage Vth(cntr)RX =(V

th(rec)RX + Vth(dom)RX)/2

VBAT = 5.5 V to 18 V ; LIN Active mode 0.475

× VBAT

0.5 ×

VBAT

0.525 ×

VBAT

Vth(hys)RX receiver hysteresis threshold

voltage Vth(hys)RX =V

th(rec)RX − Vth(dom)RX

VBAT = 5.5 V to 18 V; LIN Active mode 0.05 ×

VBAT

0.15 ×

VBAT

0.175 ×

VBAT

CLIN capacitance on pin LIN with respect to GND - - 30 pF

VO(dom) domin ant output volt ag e LIN Active mo de ; VTXDL = 0 V

VBAT = 7 V --1.4V

LIN Active mode; VTXDL = 0 V

VBAT = 18 V --2.0V

LIN bus termination; pin DLIN

ΔV(DLIN-BAT) voltage difference between

pin DLIN and pin BAT 5mA < I

DLIN < 20 mA 0.4 0.65 1 V

Temperature protection

Tth(act)otp overte mperature protection

activation threshold

temperature

165 180 200 °C

Tth(rel)otp overte mperature protection

release threshold

temperature

126 138 150 °C

Table 10. Static characteristics …continued

Tvj =

−

C to +150

C; VBAT = 4.5 V to 28 V; VBAT > VV1; RLIN =500

; all voltages are defined with respect to ground;

positive currents flow in the IC; typical values are given at VBAT = 14 V; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 2 — 31 January 2011 35 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

10. Dynamic characteristics

Table 11. Dynamic character istics

Tvj =

−

C to +150

C; VBAT = 4.5 V to 28 V; VBAT > VV1; RLIN =500

; all voltages are defined with respect to ground;

positive currents flow in the IC; typical values are given at VBAT = 14 V; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Voltage source; pin V1

td(uvd) undervoltage detection delay

time VV1 falling; dVV1/dt = 0.1 V/μs7-23μs

tdet(CL)L LOW-level clamping detection

time VV1 <0.9V

O(V1)nom; V1 active

VWDOFF = 0 V (WD versions only) 95 - 140 ms

Serial peripheral interface timin g; pin s SCSN, SCK, SDI and SDO

tcy(clk) clock cycle time VV1 = 2.97 V to 5.5 V 320 - - ns

tSPILEAD SPI enable lead time VV1 = 2.97 V to 5.5 V; clock is LOW

when SPI select falls 110 - - ns

tSPILAG SPI enable lag time VV1 = 2.97 V to 5.5 V; clock is LOW

when SPI select rises 140 - - ns

tclk(H) clock HIGH time VV1 = 2.97 V to 5.5 V 160 - - ns

tclk(L) clock LOW time VV1 = 2.97 V to 5.5 V 160 - - ns

tsu(D) data input set-up time VV1 = 2.97 V to 5.5 V 0 - - ns

th(D) data input hold time VV1 = 2.97 V to 5.5 V 80 - - ns

tv(Q) data output valid time pin SDO; VV1 = 2.97 V to 5.5 V

CL = 100 pF --110ns

tWH(S) chip select pulse width HIGH VV1 = 2.97 V to 5.5 V 20 - - ns

Reset output; pin RSTN

tw(rst) reset pulse width long; Rpu(RSTN) > 25 kΩ20 - 25 ms

short; Rpu(RSTN) = 900 Ω to 1100 Ω3.6 - 5 ms

tdet(CL)L LOW-level clamping detection

time RSTN driven HIGH internally but pin

RSTN remains LOW; VWDOFF =0 V

(WD versions only)

95 - 140 ms

tfltr filter time 7 - 18 μs

Watchdog off input; pin WDOFF

tfltr filter time 0.9 - 2.3 ms

Wake input; pin WAKE1, WAKE2

twake wake-up time 10 - 40 μs

td(po) power-on delay time 113 - 278 μs

LIN transceiver; pins LIN, TXDL, RXDL

δ1 duty cycle 1 Vth(rec)RX(max) = 0.744 VBAT

Vth(dom)RX(max) = 0.581VBAT; tbit = 50 μs

VBAT = 7 V to 18 V; LSC = 0

[1]

[2] 0.396 - -

Vth(rec)RX(max) = 0.76VBAT

Vth(dom)RX(max) = 0.593VBAT; tbit = 50 μs

VBAT = 5.5 V to 7 V; LSC = 0

[1]

[2] 0.396 - -

Product data sheet Rev. 2 — 31 January 2011 36 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

[1] .

[2] Bus load conditions are: CL= 1 nF and RL=1kΩ; CL= 6.8 nF and RL= 660 Ω; CL= 10 nF and RL= 500 Ω.

δ2 duty cycle 2 Vth(rec)RX(min) = 0.422VBAT

Vth(dom)RX(min) = 0.284VBAT; tbit = 50 μs

VBAT = 7.6 V to 18 V; LSC = 0

[2]

[3] - - 0.581

Vth(rec)RX(min) = 0.41VBAT

Vth(dom)RX(min) = 0.275VBAT; tbit = 50 μs

VBAT = 6.1 V to 7.6 V; LSC = 0

[2]

[3] - - 0.581

δ3 duty cycle 3 Vth(rec)RX(max) = 0.778 VBAT

Vth(dom)RX(max) = 0.616VBAT

tbit = 96 μs; VBAT = 7 V to 18 V

LSC = 1

[1]

[2] 0.417 - -

Vth(rec)RX(max) = 0.797 VBAT

Vth(dom)RX(max) = 0.630VBAT

tbit = 96 μs; VBAT = 5.5 V to 7 V

LSC = 1

[1]

[2] 0.417 - -

δ4 duty cycle 4 Vth(rec)RX(min) = 0.389VBAT

Vth(dom)RX(min) = 0.251VBAT; tbit = 96 μs

VBAT = 7.6 V to 18 V; LSC = 1

[2]

[3] - - 0.590

Vth(rec)RX(min) = 0.378VBAT

Vth(dom)RX(min) = 0.242VBAT; tbit = 96 μs

VBAT = 6.1 V to 7.6 V; LSC = 1

[2]

[3] - - 0.590

tPD(RX)r rising receiver propagation

delay VBAT = 5.5 V to 18 V; RRXDL = 2.4 kΩ

CRXDL = 20 pF --6 μs

tPD(RX)f falling receiver propagation

delay VBAT = 5.5 V to 18 V; RRXDL = 2.4 kΩ

CRXDL = 20 pF --6 μs

tPD(RX)sym receiver propagation delay

symmetry VBAT = 5.5 V to 18 V; RRXDL = 2.4 kΩ

CRXDL = 20 pF [4] −2-+2 μs

twake(busdom)min minimum bus dominant

wake-up time 28 - 104 μs

tto(dom)TXDL TXDL dominant time-out time LIN online mode; VTXDL = 0 V 20 - 80 ms

Wake bias output; pin WBIAS

tWBIASL WBIAS LOW time 227 - 278 μs

tcy cycle time WBC = 1 58.1 - 71.2 ms

WBC = 0 14.5 - 17.8 ms

Watchdog

ttrig(wd)1 watchdog trigger time 1 Normal mode

watchdog Window mode only [5] 0.45 ×

NWP[6] - 0.555 ×

NWP[6] ms

ttrig(wd)2 watchdog trigger time 2 Normal, Standby and Sleep modes

watchdog Window mode only [7] 0.9 ×

NWP[6] -1.11 ×

NWP[6] ms

Oscillator

fosc oscillator frequency 460.8 512 563.2 kHz

Table 11. Dynamic character istics …continued

Tvj =

−

C to +150

C; VBAT = 4.5 V to 28 V; VBAT > VV1; RLIN =500

; all voltages are defined with respect to ground;

positive currents flow in the IC; typical values are given at VBAT = 14 V; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

δ1δ3,tbus rec()min()

bit

-------------------------------

Product data sheet Rev. 2 — 31 January 2011 37 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

[3] .

[4] tPD(RX)sym =t

PD(RX)r − tPD(RX)f.

[5] A system reset will be performed if the watchdog is in Window mode and is triggered less than ttrig(wd)1 after the start of the watchdog

period (or in the first half of the watchdog period).

[6] The nominal watchdog period is programmed via the NWP control bits in the WD_and_Status register (see Table 4); valid in watchdog

Window mode only.

[7] The watchdog will be reset if it is in window mode and is triggered at least ttrig(wd)1, but not more than ttrig(wd)2, after the start of the

watchdog period (or in the second half of the watchdog period). A system reset will be performed if the watchdog is triggered more than

ttrig(wd)2 after the start of the watchdog period (watchdog overflows).

δ2δ4,tbus rec()max()

bit

--------------------------------

Fig 15. Timing test circuit for LIN transceiver

SBC

BAT

DLIN

TXDL

RLIN

CLIN

RXDL

CRXDL

LIN

GND

015aaa20

Fig 16. LIN transceiver timing diagram

015aaa133

VTXDL

LIN bus signal

VBAT

tbit

tbus(rec)(min)

Vth(rec)RX(max) thresholds of

receiving node A

Vth(dom)RX(max)

Vth(rec)RX(min)

Vth(dom)RX(min)

tPD(RX)r

tPD(RX)f

tPD(RX)r tPD(RX)f

tbus(rec)(max)

tbit tbit

thresholds of

receiving node B

output of receiving

node A VRXDL

output of receiving

node B VRXDL

tbus(dom)(max)

tbus(dom)(min)

Product data sheet Rev. 2 — 31 January 2011 38 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

11. Test information

11.1 Quality information

This product has been qualified in accordance with the Automotive Electronics Council

(AEC) standard Q100 - Failure mechanism based stress test qualification for integrated

circuits, and is suitable for use in automotive applications.

Fig 17. SPI timing diagram

015aaa04

SCSN

SCK

SDI

SDO X

X X

MSB LSB

tv(Q)

floating floating

th(D)

tsu(D)

tclk(L)

tclk(H)

tSPILEAD Tcy(clk) tSPILAG tWH(S)

Product data sheet Rev. 2 — 31 January 2011 39 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

12. Package outline

Fig 18. Package outline SOT549-1 (HTSSOP32)

UNIT A1A2A3bpcD

(1) E(2) eH

ELL

pZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05

0.1

DIMENSIONS (mm are the original dimensions).

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

SOT549-1 03-04-07

05-11-02

detail X

exposed die pad side

(A3)

0.25

116

32 17

0.95

0.85

0.30

0.19

5.1

4.9

3.6

3.4

0.20

0.09

11.1

10.9

6.2

6.0

8.3

7.9

0.65 1 0.2 0.78

0.48

0.1

0.75

0.50

vMA

HTSSOP32: plastic thermal enhanced thin shrink small outline package; 32 leads;

body width 6.1 mm; lead pitch 0.65 mm; exposed die pad SOT549-

max.

1.1

2.5

5 mm

scale

pin 1 index

MO-153

Product data sheet Rev. 2 — 31 January 2011 40 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

13. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

13.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on on e printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

13.2 Wave and reflow soldering

W ave soldering is a joining te chnology in which the joints are m ade by solder coming from

a standing wave of liquid solder. The wave soldering process is suit able for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solde r lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads ha ving a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

•Board specifications, including the board finish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering ve rsus SnPb soldering

13.3 Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath specifications, including temperature and impurities

Product data sheet Rev. 2 — 31 January 2011 41 of 46

NXP Semiconductors UJA1079A

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13.4 Reflow soldering

Key characteristics in reflow soldering are :

•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to

higher minimum peak temperatures (see Figure 19) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) an d cooling down. It is imperative that the peak

temperature is high enoug h for the solder to make reliable solder joint s (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on p ackage thickness and volume and is classified in accordance with

Table 12 and 13

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 19.

Table 12. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm3)

< 350 ≥ 350

< 2.5 235 220

≥ 2.5 220 220

Table 13. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 2 — 31 January 2011 42 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

For further informa tion on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

MSL: Moisture Sensitivity Level

Fig 19. Temperature profiles for large and small components

001aac84

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Product data sheet Rev. 2 — 31 January 2011 43 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

14. Revision history

Table 14. Revision history

Document ID Release date Data sheet status Change notice Supersedes

UJA1079A v.2 20110131 P roduct data sheet - UJA1079A v.1

Modifications: •Section 6.7: text amended

•Figure 9, Figure 10: added

•Table 8: parameter values/conditions revised - Vtrt

•Table 9: parameter values/conditions revised - Rth(j-a)

•Table 10: parameter values/conditions revised - Cext changed to CLIN

•Table 11: parameter values/conditions revised - tdet(CL)L for pins V1 a nd RSTN, δ1, δ2, δ3, δ4

UJA1079A v. 1 20100709 Product data sheet - -

Product data sheet Rev. 2 — 31 January 2011 44 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

15. Legal information

15.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

15.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not b e relied u pon to cont ain det ailed and

full information. For detailed and full information se e the relevant full data

sheet, which is available on request via the local NXP Semicond uctors sales

office. In case of any inconsistency or conflict with the shor t data sheet, the

full data sheet shall pre va il.

Product specificat ion — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

15.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warrant ies, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequ ential damages (including - wit hout limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggreg ate and cumulative liabil ity towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use in automotive applications — This NXP

Semiconductors product has been qualified for use in automotive

applications. The product is not designed, authorized or warranted to be

suitable for use in medica l, military, aircraft, space or life support equipment,

nor in applications where failure or malf unction of an NXP Semiconductors

product can reasonably be expected to result in personal injury, death or

severe property or environmental damage. NXP Semiconductors accepts no

liability for inclusion and/or use of NXP Semiconductors products in such

equipment or applications and therefore such inclusion and/or use is at the

customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Custo mers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liability rela ted to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party custo m er(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings onl y and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter m s and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, patents or

other industrial or inte llectual property rights.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contain s data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document cont ains data from the preliminar y specification.

Product [short] data sheet Production This document contains the product specification.

Product data sheet Rev. 2 — 31 January 2011 45 of 46

NXP Semiconductors UJA1079A

LIN core system basis ch ip

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

15.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respective ow ners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors UJA1079A

LIN core system basis ch ip

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 31 January 2011

Document identifier: UJA1079A

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

17. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2

2.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.2 LIN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.3 Power management . . . . . . . . . . . . . . . . . . . . . 2

2.4 Control and diagnostic features . . . . . . . . . . . . 2

2.5 Voltage regulator V1. . . . . . . . . . . . . . . . . . . . . 3

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 3

4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

6 Functional description . . . . . . . . . . . . . . . . . . . 6

6.1 System Controller. . . . . . . . . . . . . . . . . . . . . . . 6

6.1.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

6.1.2 Off mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

6.1.3 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 9

6.1.4 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 9

6.1.5 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 10

6.1.6 Overtemp mode . . . . . . . . . . . . . . . . . . . . . . . 10

6.2 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

6.2.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . 10

6.2.2 Register map . . . . . . . . . . . . . . . . . . . . . . . . . 11

6.2.3 WD_and_Status register . . . . . . . . . . . . . . . . . 12

6.2.4 Mode_Control register . . . . . . . . . . . . . . . . . . 13

6.2.5 Int_Control register. . . . . . . . . . . . . . . . . . . . . 14

6.2.6 Int_Status register. . . . . . . . . . . . . . . . . . . . . . 15

6.3 On-chip oscillator . . . . . . . . . . . . . . . . . . . . . . 16

6.4 Watchdog (UJA1079A/xx/WD versions). . . . . 16

6.4.1 Watchdog Window behavior. . . . . . . . . . . . . . 16

6.4.2 Watchdog Timeout behavior. . . . . . . . . . . . . . 17

6.4.3 Watchdog Off behavior. . . . . . . . . . . . . . . . . . 17

6.5 System reset. . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.5.1 RSTN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.5.2 EN output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.5.3 LIMP output . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.6 Power supplies. . . . . . . . . . . . . . . . . . . . . . . . 19

6.6.1 Battery pin (BAT) . . . . . . . . . . . . . . . . . . . . . . 19

6.6.2 Voltage regulator V1. . . . . . . . . . . . . . . . . . . . 19

6.7 LIN transceiver . . . . . . . . . . . . . . . . . . . . . . . . 21

6.7.1 LIN operating modes . . . . . . . . . . . . . . . . . . . 22

6.7.1.1 Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.7.1.2 Lowpower/Off modes . . . . . . . . . . . . . . . . . . . 22

6.7.2 Fail-safe features . . . . . . . . . . . . . . . . . . . . . . 23

6.7.2.1 General fail-safe features. . . . . . . . . . . . . . . . 23

6.7.2.2 TXDL dominant time-out function. . . . . . . . . . 23

6.8 Local wake-up input . . . . . . . . . . . . . . . . . . . . 23

6.9 Interrupt output. . . . . . . . . . . . . . . . . . . . . . . . 24

6.10 Temperature protection . . . . . . . . . . . . . . . . . 24

7 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 26

8 Thermal characteristics . . . . . . . . . . . . . . . . . 28

9 Static characteristics . . . . . . . . . . . . . . . . . . . 30

10 Dynamic characteristics. . . . . . . . . . . . . . . . . 35

11 Test information . . . . . . . . . . . . . . . . . . . . . . . 38

11.1 Quality information. . . . . . . . . . . . . . . . . . . . . 38

12 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 39

13 Soldering of SMD packages. . . . . . . . . . . . . . 40

13.1 Introduction to soldering. . . . . . . . . . . . . . . . . 40

13.2 Wave and reflow soldering. . . . . . . . . . . . . . . 40

13.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 40

13.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 41

14 Revision history . . . . . . . . . . . . . . . . . . . . . . . 43

15 Legal information . . . . . . . . . . . . . . . . . . . . . . 44

15.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 44

15.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 44

15.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 45

16 Contact information . . . . . . . . . . . . . . . . . . . . 45

17 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46