UPD70F3033BGF3BAA - RENESAS TECHNOLOGY

To our customers,

Old Company Name in Catalogs and Other Documents

On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology

Corporation, and Renesas Electronics Corporation took over all the business of both

companies. Therefore, although the old company name remains in this document, it is a valid

Renesas Electronics document. We appreciate your understanding.

Renesas Electronics website: http://www.renesas.com

April 1st, 2010

Renesas Electronics Corporation

Issued by: Renesas Electronics Corporation (http://www.renesas.com)

Send any inquiries to http://www.renesas.com/inquiry.

Notice

1. All information included in this document is current as of the date this document is issued. Such information, however, is

subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please

confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to

additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.

2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights

of third parties by or arising from the use of Renesas Electronics products or technical information described in this document.

No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights

of Renesas Electronics or others.

3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.

4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of

semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,

and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by

you or third parties arising from the use of these circuits, software, or information.

5. When exporting the products or technology described in this document, you should comply with the applicable export control

laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas

Electronics products or the technology described in this document for any purpose relating to military applications or use by

the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and

technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited

under any applicable domestic or foreign laws or regulations.

6. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics

does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages

incurred by you resulting from errors in or omissions from the information included herein.

7. Renesas Electronics products are classified according to the following three quality grades: “Standard”, “High Quality”, and

“Specific”. The recommended applications for each Renesas Electronics product depends on the product’s quality grade, as

indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular

application. You may not use any Renesas Electronics product for any application categorized as “Specific” without the prior

written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for

which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way

liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an

application categorized as “Specific” or for which the product is not intended where you have failed to obtain the prior written

consent of Renesas Electronics. The quality grade of each Renesas Electronics product is “Standard” unless otherwise

expressly specified in a Renesas Electronics data sheets or data books, etc.

“Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual

equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots.

“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-

crime systems; safety equipment; and medical equipment not specifically designed for life support.

“Specific”: Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or

systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare

intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.

8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,

especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation

characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or

damages arising out of the use of Renesas Electronics products beyond such specified ranges.

9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have

specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further,

Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to

guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a

Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire

control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because

the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system

manufactured by you.

10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental

compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable

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applicable laws and regulations.

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12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this

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(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majority-

owned subsidiaries.

(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.

User’s Manual

V850/SB1TM, V850/SB2TM

32-Bit Single-Chip Microcontroller

Hardware

µµ

PD703031A

µµ

PD703030B

µµ

PD703034A

µµ

PD703034B

µµ

PD703031AY

µµ

PD703030BY

µµ

PD703034AY

µµ

PD703034BY

µµ

PD703032A

µµ

PD703031B

µµ

PD703035A

µµ

PD703035B

µµ

PD703032AY

µµ

PD703031BY

µµ

PD703035AY

µµ

PD703035BY

µµ

PD703033A

µµ

PD703032B

µµ

PD703037A

µµ

PD703036H

µµ

PD703033AY

µµ

PD703032BY

µµ

PD703037AY

µµ

PD703036HY

µµ

PD70F3032A

µµ

PD703033B

µµ

PD70F3035A

µµ

PD703037H

µµ

PD70F3032AY

µµ

PD703033BY

µµ

PD70F3035AY

µµ

PD703037HY

µµ

PD70F3033A

µµ

PD70F3030B

µµ

PD70F3037A

µµ

PD70F3035B

µµ

PD70F3033AY

µµ

PD70F3030BY

µµ

PD70F3037AY

µµ

PD70F3035BY

µµ

PD70F3032B

µµ

PD70F3036H

µµ

PD70F3032BY

µµ

PD70F3036HY

µµ

PD70F3033B

µµ

PD70F3037H

µµ

PD70F3033BY

µµ

PD70F3037HY

Printed in Japan

Document No. U13850EJ6V0UD00 (6th edition)

Date Published February 2003 N CP(K)

1999, 2000, 2003

User’s Manual U13850EJ6V0UD

[MEMO]

User’s Manual U13850EJ6V0UD 3

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V

or GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these

components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined

by Philips.

V850 Series, V850/SA1, V850/SB1, V850/SB2, IEBus, and Inter Equipment Bus are trademarks of NEC

Electronics Corporation.

Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or

other countries.

4User’s Manual U13850EJ6V0UD

These commodities, technology or software, must be exported in accordance

with the export administration regulations of the exporting country.

Diversion contrary to the law of that country is prohibited.

The information in this document is current as of December, 2002. The information is subject to

change without notice. For actual design-in, refer to the latest publications of NEC Electronics data

sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not

all products and/or types are available in every country. Please check with an NEC Electronics sales

representative for availability and additional information.

No part of this document may be copied or reproduced in any form or by any means without the prior

written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may

appear in this document.

NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual

property rights of third parties by or arising from the use of NEC Electronics products listed in this document

or any other liability arising from the use of such products. No license, express, implied or otherwise, is

granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.

Descriptions of circuits, software and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these

circuits, software and information in the design of a customer's equipment shall be done under the full

responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by

customers or third parties arising from the use of these circuits, software and information.

While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,

customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To

minimize risks of damage to property or injury (including death) to persons arising from defects in NEC

Electronics products, customers must incorporate sufficient safety measures in their design, such as

redundancy, fire-containment and anti-failure features.

NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and

"Specific".

The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-

designated "quality assurance program" for a specific application. The recommended applications of an NEC

Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of

each NEC Electronics product before using it in a particular application.

"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment

and industrial robots.

"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support).

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC

Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications

not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to

determine NEC Electronics' willingness to support a given application.

(Note)

(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its

majority-owned subsidiaries.

(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics

(as defined above).

•

M8E 02. 11-1

User’s Manual U13850EJ6V0UD 5

Regional Information

• Device availability

• Ordering information

• Product release schedule

• Availability of related technical literature

• Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

• Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary

from country to country.

NEC Electronics America, Inc. (U.S.)

Santa Clara, California

Tel: 408-588-6000

800-366-9782

Fax: 408-588-6130

800-729-9288

NEC Electronics Hong Kong Ltd.

Hong Kong

Tel: 2886-9318

Fax: 2886-9022/9044

NEC Electronics Hong Kong Ltd.

Seoul Branch

Seoul, Korea

Tel: 02-528-0303

Fax: 02-528-4411

NEC Electronics Shanghai, Ltd.

Shanghai, P.R. China

Tel: 021-6841-1138

Fax: 021-6841-1137

NEC Electronics Taiwan Ltd.

Taipei, Taiwan

Tel: 02-2719-2377

Fax: 02-2719-5951

NEC Electronics Singapore Pte. Ltd.

Novena Square, Singapore

Tel: 6253-8311

Fax: 6250-3583

J02.11

NEC Electronics (Europe) GmbH

Duesseldorf, Germany

Tel: 0211-65 03 01

Fax: 0211-65 03 327

• Sucursal en España

Madrid, Spain

Tel: 091-504 27 87

Fax: 091-504 28 60

Vélizy-Villacoublay, France

Tel: 01-30-67 58 00

Fax: 01-30-67 58 99

• Succursale Française

• Filiale Italiana

Milano, Italy

Tel: 02-66 75 41

Fax: 02-66 75 42 99

• Branch The Netherlands

Eindhoven, The Netherlands

Tel: 040-244 58 45

Fax: 040-244 45 80

• Tyskland Filial

Taeby, Sweden

Tel: 08-63 80 820

Fax: 08-63 80 388

• United Kingdom Branch

Milton Keynes, UK

Tel: 01908-691-133

Fax: 01908-670-290

Some information contained in this document may vary from country to country. Before using any NEC

Electronics product in your application, pIease contact the NEC Electronics office in your country to

obtain a list of authorized representatives and distributors. They will verify:

6User’s Manual U13850EJ6V0UD

Major Revisions in This Edition (1/3)

Page Description

Throughout •Addition of the following products.

PD703030B, 703030BY, 703031B, 703031BY, 703032B, 703032BY, 703033B, 703033BY, 703034B,

703034BY, 703035B, 703035BY, 703036H, 703036HY, 703037H, 703037HY, 70F3030B, 70F3030BY,

70F3032B, 70F3032BY, 70F3033B, 70F3033BY, 70F3035B, 70F3035BY, 70F3036H, 70F3036HY,

70F3037H, 70F3037HY

•Deletion of the following products.

PD703030A, 703030AY, 703036A, 703036AY

p. 63 Addition of description on minimum instruction execution time in 1.5.1

p. 63 Addition of description on instruction set in 1.5.1

p. 73 Addition of description in Table 2-1 Pin I/O Buffer Power Supplies

p. 80 Modification of description and addition of Notes in Table 2-3 Operating States of Pins in Each

Operating Mode

p. 87 Addition of description in 2.3 (9) (b) (i) LBEN

p. 92 Modification of P23 I/O circuit type and description on P33 in 2.4 Pin I/O Circuit Types, I/O Buffer Power

Supplies and Connection of Unused Pins

p. 96 Addition of description on minimum instruction execution time in 3.1

p. 100 Modification of description and addition of Note in 3.2.2 (2) Program status word (PSW)

p. 110 Addition of 3.4.5 (2) (a) V850/SB1 (

µµ

PD703031B, 703031BY), V850/SB2 (

µµ

PD703034B, 703034BY)

pp. 119, 124, 125 Modification of Note and addition of registers in 3.4.8 Peripheral I/O registers

p. 126 Addition of description in 3.4.9 Specific registers

p. 126 Modification of [Description example] in 3.4.9 Specific registers

p. 126 Modification of Caution 2 in 3.4.9 Specific registers

p. 127 Addition of Remarks in 3.4.9 (2) (b) Reset conditions (PRERR = 1)

p. 129 Addition of Note and Caution in 4.2.2 (1) System control register (SYC)

p. 158 Addition of Remark in 5.3.3 Priorities of maskable interrupts

p. 162 Addition of Caution 2 in 5.3.4 Interrupt control register (xxICn)

p. 165 Addition of Caution in 5.3.5 In-service priority register (ISPR)

p. 165 Addition of Remark in 5.3.6 ID flag

p. 176 Addition of Remark in 5.6.2 (2) To generate exception in service program

p. 178 Addition of 5.8.1 Interrupt request valid timing after EI instruction

p. 179 Addition of 5.9 Interrupt Control Register Bit Manipulation Instructions During DMA Transfer

p. 184 Addition of description in Cautions in 6.3.1 (1) Processor clock control register (PCC)

p. 185 Modification of description in 6.3.1 (1) (b) Example of subclock operation → main clock operation

setup

p. 186 Modification of description in 6.3.1 (2) Power save control register (PSC)

pp. 190, 191 Addition and deletion of description in Table 6-1 Operating Statuses in HALT Mode

p. 192 Modification of description in Table 6-2 Operating Statuses in IDLE Mode

p. 194 Addition of description in 6.4.4 (1) Settings and operating states

p. 194 Modification of description in Table 6-3 Operating Statuses in Software STOP Mode

User’s Manual U13850EJ6V0UD 7

Major Revisions in This Edition (2/3)

Pages Description

p. 197 Addition of 6.6 (1) While an instruction is being executed on internal ROM

p. 198 Addition of 6.6 (2) While an instruction is being executed on external ROM

p. 206 Addition of description in Caution in 7.1.4 (1) 16-bit timer mode control registers 0, 1 (TMC0, TMC1)

p. 207 Addition of description in Caution in 7.1.4 (2) Capture/compare control registers 0, 1 (CRC0, CRC1)

p. 213 Modification of description in Figure 7-5 (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1)

p. 214 Addition of Figure 7-6 Configuration of PPG Output

p. 214 Addition of Figure 7-7 PPG Output Operation Timing

p. 215 Modification of description in Figure 7-8 (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1)

p. 217 Modification of description in Figure 7-11 (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1)

p. 219 Modification of description in Figure 7-14 (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1)

p. 221 Modification of description in Figure 7-17 Timing of Pulse Width Measurement by Restarting (with

Rising Edge Specified)

p. 222 Modification of description in Figure 7-18 (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1)

p. 227 Modification of description in Caution in 7.2.6 (2) One-shot pulse output with external trigger

p. 231 Modification of description in 7.2.7 (6) (a) One-shot pulse output by software

p. 231 Modification of description in 7.2.7 (6) (b) One-shot pulse output with external trigger

p. 234 Addition of 7.3.1 Outline

p. 242 Change of Figure 7-32 Timing of Interval Timer Operation (3/3)

p. 246 Addition of description to Remarks in Figure 7-34 Square Wave Output Operation Timing

p. 248 Addition of description to Remarks in Figure 7-35 Timing of PWM Output

p. 253 Addition of registers and Caution in Figure 8-1 Block Diagram of Watch Timer

p. 254 Addition of registers and Note in Table 8-2 Configuration of Watch Timer

p. 255 Addition of description and Caution in 8.3 Watch Timer Control Register

p. 256 Addition of 8.3 (2) Watch timer high-speed clock selection register (WTNHC)

p. 257 Addition of description in 8.3 (3) Watch timer clock selection register (WTNCS)

p. 263 Addition of Caution in 9.3 (2) Watchdog timer clock selection register (WDCS)

p. 268 Addition of description in 10.2 (2) 3-wire serial I/O mode (fixed to MSB first)

p. 280 Modification of Caution in 10.3.2 (1) IIC control registers 0, 1 (IICC0, IICC1)

p. 288 Addition of Caution in 10.3.2 (3) IIC clock selection registers 0, 1 (IICCL0, IICCL1)

p. 334 Addition of 10.4 I2C Bus (B and H Versions)

p. 402 Addition of description to Cautions in 10.5.2 (1) Asynchronous serial interface mode registers 0, 1

(ASIM0, ASIM1)

p. 405 Addition of description to Cautions in 10.5.2 (4) Baud rate generator mode control registers n0, n1

(BRGMCn0, BRGMCn1)

p. 406 Addition of description to Cautions in Figure 10-45 ASIMn Setting (Operation Stop Mode)

p. 407 Addition of description to Cautions in Figure 10-46 ASIMn Setting (Asynchronous Serial Interface

Mode)

p. 410 Addition of description to Cautions in Figure 10-49 BRGMCn0 and BRGMCn1 Settings (Asynchronous

Serial Interface Mode)

8User’s Manual U13850EJ6V0UD

Major Revisions in This Edition (3/3)

Pages Description

p. 437 Addition of Caution in 11.3 (2) Analog input channel specification register (ADS)

p. 447 Addition of 11.7 How to Read A/D Converter Characteristics Table

p. 452 Addition of 12.3 Configuration

p. 455 Addition of 12.4 (2) (a) V850/SB1 (

µµ

PD703031B, 703031BY), V850/SB2 (

µµ

PD703034B, 703034BY)

p. 460 Addition of Caution in 12.4 (5) DMA channel control registers 0 to 5 (DCHC0 to DCHC5)

p. 462 Addition of 12.5 Operation

p. 463 Addition of 12.6 Cautions

p. 466 Addition of 13.2 Features

p. 468 Addition of 13.3 (2) Output latch

p. 471 Addition of description in 13.5 Usage

p. 473 Addition of 13.7 (3)

p. 474 Addition of description in Table 14-1 Pin I/O Buffer Power Supplies

p. 501 Addition of Caution in 14.2.8 (1) Function of P9 pins

p. 504 Addition of Caution in 14.2.9 (1) Function of P10 pins

p. 511, 512 Addition of description in Table 14-12 Setting When Port Pin is Used as Alternate Function

p. 515 Addition of 14.4 Port Function Operation

p. 517 Addition of description in 16.1 Outline

p. 517 Addition of description in Figure 16-1 Regulator

p. 524 Addition of 18.1.1 (2) V850/SB1 (

µµ

PD70F3030B, 70F3030BY), V850/SB2 (

µµ

PD70F3036H, 70F3036HY)

p. 526 Addition of Figure 18-1 Wiring Example of V850/SB1 and V850/SB2 Flash Writing Adapter (FA-

100GC-8EU)

p. 527 Addition of Table 18-1 Table for Wiring of V850/SB1 and V850/SB2 Flash Writing Adapter (FA-100GC-

8EU)

p. 528 Addition of Figure 18-2 Wiring Example of V850/SB1 and V850/SB2 Flash Writing Adapter (FA-100GF-

3BA)

p. 529 Addition of Table 18-2 Table for Wiring of V850/SB1 and V850/SB2 Flash Writing Adapter (FA-100GF-

3BA)

p. 549 Modification of description in Table 19-5 Acknowledge Signal Output Condition of Control Field

p. 560 Addition of register to Table 19-7 Internal Registers of IEBus Controller

p. 582 Addition of Remark in 19.3.2 (13) IEBus clock selection register (IECLK)

p. 583 Addition of 19.3.2 (14) IEBus high-speed clock selection register (IEHCLK)

p. 600 Addition of CHAPTER 20 ELECTRICAL SPECIFICATIONS

p. 635 Addition of CHAPTER 21 PACKAGE DRAWINGS

p. 637 Addition of CHAPTER 22 RECOMMENDED SOLDERING CONDITIONS

p. 642 Addition of APPENDIX A NOTES ON TARGET SYSTEM DESIGN

p. 658 Modification of APPENDIX D INDEX

p. 664 Addition of APPENDIX E REVISION HISTORY

The mark shows major revised points.

User’s Manual U13850EJ6V0UD 9

INTRODUCTION

Readers This manual is intended for users who wish to understand the functions of the V850/SB1 and

V850/SB2 and design application systems using the V850/SB1 or V850/SB2.

Purpose This manual is intended to give users to an understanding of the hardware functions described in the

Organization below.

Organization The V850/SB1, V850/SB2 User’s Manual is divided into two parts: hardware (this manual) and

architecture (V850 SeriesTM Architecture User’s Manual).

Hardware Architecture

•Pin function

•CPU function

•On-chip peripheral function

•Flash memory programming

•IEBus controller (V850/SB2 only)

•Electrical specifications

•Data type

•Register set

•Instruction format and instruction set

•Interrupt and exception

•Pipeline operation

How to Read This Manual It is assumed that the reader of this manual has general knowledge in the fields of

electrical engineering, logic circuits, and microcontrollers.

To find out the details of a register whose name is known:

→ Refer to APPENDIX B REGISTER INDEX.

To find out the details of a function, etc., whose name is known:

→ Refer to APPENDIX D INDEX.

To understand the details of a instruction function:

→ Refer to V850 Series Architecture User’s Manual available separately.

To know the electrical specifications of the V850/SB1 and V850/SB2:

→ Refer to CHAPTER 20 ELECTRICAL SPECIFICATIONS.

How to read register formats:

→ Names of bits whose numbers are enclosed in a square are defined in the device file under

reserved words.

To understand the overall functions of the V850/SB1 and V850/SB2:

→ Read this manual in accordance with the CONTENTS.

10 User’s Manual U13850EJ6V0UD

Conventions Data significance: Higher digits on the left and lower digits on the right

Active low: xxx (overscore over pin or signal name)

Memory map address: Higher addresses at the top and lower addresses at the bottom

Note: Footnote for items marked with Note in the text

Caution: Information requiring particular attention

Remark: Supplementary information

Number representation: Binary … xxxx or xxxxB

Decimal … xxxx

Hexadecimal … xxxxH

Prefixes indicating power of 2 (address space, memory capacity):

K (kilo): 210 … 1024

M (mega): 220 … 10242

G (giga): 230 … 10243

User’s Manual U13850EJ6V0UD 11

Related Documents The related documents indicated in this publication may include preliminary versions.

However, preliminary versions are not marked as such.

Related documents for V850/SB1 and V850/SB2

Document Name Document No.

V850 Series Architecture User’s Manual U10243E

V850/SB1, V850/SB2 Hardware User’s Manual This manual

Related documents for development tool (user’s manual)

Document Name Document No.

Operation U15024E

C Language U15025E

Project Manager U15026E

CA850 Ver. 2.40 or Later C Compiler Package

Assembly Language U15027E

ID850 Ver. 2.40 Integrated Debugger Operation (Windows™ Based) U15181E

SM850 Ver. 2.40 System Simulator Operation (Windows Based) U15182E

SM850 Ver. 2.00 or Later System Simulator External Part User Open Interface Specifications U14873E

Basic U13430E

Installation U13410E

RX850 Ver. 3.13 or Later Real-time OS

Technical U13431E

Basic U13773E

Installation U13774E

RX850 Pro Ver. 3.13 Real-time OS

Technical U13772E

RD850 Ver. 3.01 Task Debugger U13737E

RD850 Pro Ver. 3.01 Task Debugger U13916E

AZ850 Ver. 3.0 System Performance Analyzer U14410E

PG-FP3 Flash Memory Programmer U13502E

PG-FP4 Flash Memory Programmer U15260E

User’s Manual U13850EJ6V0UD

CONTENTS

CHAPTER 1 INTRODUCTION.................................................................................................................29

1.1 General.......................................................................................................................................29

1.2 V850/SB1 (A Versions) .............................................................................................................33

1.2.1 Features (V850/SB1 (A versions)) ..............................................................................................33

1.2.2 Application fields (V850/SB1 (A versions)) .................................................................................34

1.2.3 Ordering information (V850/SB1 (A versions))............................................................................35

1.2.4 Pin configuration (top view) (V850/SB1 (A versions)) .................................................................36

1.2.5 Function blocks (V850/SB1 (A versions)) ...................................................................................39

1.3 V850/SB1 (B Versions) .............................................................................................................43

1.3.1 Features (V850/SB1 (B versions)) ..............................................................................................43

1.3.2 Application fields (V850/SB1 (B versions)) .................................................................................44

1.3.3 Ordering information (V850/SB1 (B versions))............................................................................45

1.3.4 Pin configuration (top view) (V850/SB1 (B versions)) .................................................................46

1.3.5 Function blocks (V850/SB1 (B versions)) ...................................................................................49

1.4 V850/SB2 (A Versions) .............................................................................................................53

1.4.1 Features (V850/SB2 (A versions)) ..............................................................................................53

1.4.2 Application fields (V850/SB2 (A versions)) .................................................................................54

1.4.3 Ordering information (V850/SB2 (A versions))............................................................................55

1.4.4 Pin configuration (top view) (V850/SB2 (A versions)) .................................................................56

1.4.5 Function blocks (V850/SB2 (A versions)) ...................................................................................59

1.5 V850/SB2 (B and H Versions) ..................................................................................................63

1.5.1 Features (V850/SB2 (B and H versions))....................................................................................63

1.5.2 Application fields (V850/SB2 (B and H versions)).......................................................................64

1.5.3 Ordering information (V850/SB2 (B and H versions)) .................................................................65

1.5.4 Pin configuration (top view) (V850/SB2 (B and H versions)).......................................................66

1.5.5 Function blocks (V850/SB2 (B and H versions)).........................................................................69

CHAPTER 2 PIN FUNCTIONS ...............................................................................................................73

2.1 List of Pin Functions ................................................................................................................73

2.2 Pin States...................................................................................................................................80

2.3 Description of Pin Functions...................................................................................................81

2.4 Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins...........92

2.5 Pin I/O Circuits ..........................................................................................................................94

CHAPTER 3 CPU FUNCTIONS..............................................................................................................96

3.1 Features .....................................................................................................................................96

3.2 CPU Register Set ......................................................................................................................97

3.2.1 Program register set....................................................................................................................98

3.2.2 System register set .....................................................................................................................99

3.3 Operation Modes ....................................................................................................................102

3.4 Address Space ........................................................................................................................103

3.4.1 CPU address space ..................................................................................................................103

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3.4.2 Image ........................................................................................................................................ 104

3.4.3 Wrap-around of CPU address space ........................................................................................ 105

3.4.4 Memory map ............................................................................................................................. 106

3.4.5 Area .......................................................................................................................................... 107

3.4.6 External expansion mode ......................................................................................................... 114

3.4.7 Recommended use of address space ...................................................................................... 117

3.4.8 Peripheral I/O registers ............................................................................................................. 119

3.4.9 Specific registers....................................................................................................................... 126

CHAPTER 4 BUS CONTROL FUNCTION ..........................................................................................128

4.1 Features...................................................................................................................................128

4.2 Bus Control Pins and Control Register................................................................................128

4.2.1 Bus control pins ........................................................................................................................ 128

4.2.2 Control register ......................................................................................................................... 129

4.3 Bus Access ............................................................................................................................. 129

4.3.1 Number of access clocks.......................................................................................................... 129

4.3.2 Bus width .................................................................................................................................. 130

4.4 Memory Block Function.........................................................................................................131

4.5 Wait Function..........................................................................................................................132

4.5.1 Programmable wait function...................................................................................................... 132

4.5.2 External wait function................................................................................................................ 133

4.5.3 Relationship between programmable wait and external wait.................................................... 133

4.6 Idle State Insertion Function .................................................................................................134

4.7 Bus Hold Function..................................................................................................................135

4.7.1 Outline of function ..................................................................................................................... 135

4.7.2 Bus hold procedure................................................................................................................... 136

4.7.3 Operation in power save mode ................................................................................................. 136

4.8 Bus Timing ..............................................................................................................................137

4.9 Bus Priority .............................................................................................................................144

4.10 Memory Boundary Operation Conditions ............................................................................145

4.10.1 Program space.......................................................................................................................... 145

4.10.2 Data space................................................................................................................................ 145

CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION .................................................146

5.1 Outline .....................................................................................................................................146

5.1.1 Features.................................................................................................................................... 146

5.2 Non-Maskable Interrupt .........................................................................................................149

5.2.1 Operation .................................................................................................................................. 150

5.2.2 Restore ..................................................................................................................................... 152

5.2.3 NP flag ...................................................................................................................................... 153

5.2.4 Noise eliminator of NMI pin....................................................................................................... 153

5.2.5 Edge detection function of NMI pin ........................................................................................... 154

5.3 Maskable Interrupts................................................................................................................155

5.3.1 Operation .................................................................................................................................. 155

5.3.2 Restore ..................................................................................................................................... 157

5.3.3 Priorities of maskable interrupts................................................................................................ 158

User’s Manual U13850EJ6V0UD

5.3.4 Interrupt control register (xxICn) ...............................................................................................162

5.3.5 In-service priority register (ISPR) ..............................................................................................165

5.3.6 ID flag........................................................................................................................................165

5.3.7 Watchdog timer mode register (WDTM)....................................................................................166

5.3.8 Noise elimination.......................................................................................................................166

5.3.9 Edge detection function.............................................................................................................168

5.4 Software Exceptions ..............................................................................................................169

5.4.1 Operation ..................................................................................................................................169

5.4.2 Restore......................................................................................................................................170

5.4.3 EP flag.......................................................................................................................................171

5.5 Exception Trap........................................................................................................................171

5.5.1 Illegal opcode definition.............................................................................................................171

5.5.2 Operation ..................................................................................................................................171

5.5.3 Restore......................................................................................................................................173

5.6 Priority Control........................................................................................................................174

5.6.1 Priorities of interrupts and exceptions .......................................................................................174

5.6.2 Multiple interrupt servicing ........................................................................................................174

5.7 Interrupt Latency Time ...........................................................................................................177

5.8 Periods in Which Interrupt Is Not Acknowledged ...............................................................177

5.8.1 Interrupt request valid timing after EI instruction.......................................................................178

5.9 Interrupt Control Register Bit Manipulation Instructions During DMA Transfer..............179

5.10 Key Interrupt Function ...........................................................................................................180

CHAPTER 6 CLOCK GENERATION FUNCTION...............................................................................182

6.1 Outline......................................................................................................................................182

6.2 Configuration ..........................................................................................................................183

6.3 Clock Output Function ...........................................................................................................183

6.3.1 Control registers........................................................................................................................184

6.4 Power Save Functions ...........................................................................................................188

6.4.1 Outline.......................................................................................................................................188

6.4.2 HALT mode ...............................................................................................................................189

6.4.3 IDLE mode ................................................................................................................................192

6.4.4 Software STOP mode ...............................................................................................................194

6.5 Oscillation Stabilization Time................................................................................................196

6.6 Notes on Power Save Function .............................................................................................197

CHAPTER 7 TIMER/COUNTER FUNCTION........................................................................................200

7.1 16-Bit Timer (TM0, TM1) .........................................................................................................200

7.1.1 Outline.......................................................................................................................................200

7.1.2 Function ....................................................................................................................................200

7.1.3 Configuration.............................................................................................................................202

7.1.4 Timer 0, 1 control registers .......................................................................................................205

7.2 16-Bit Timer Operation ...........................................................................................................211

7.2.1 Operation as interval timer (16 bits) ..........................................................................................211

7.2.2 PPG output operation................................................................................................................213

7.2.3 Pulse width measurement.........................................................................................................215

User’s Manual U13850EJ6V0UD 15

7.2.4 Operation as external event counter......................................................................................... 222

7.2.5 Operation to output square wave.............................................................................................. 223

7.2.6 Operation to output one-shot pulse........................................................................................... 225

7.2.7 Cautions.................................................................................................................................... 230

7.3 8-Bit Timer (TM2 to TM7)........................................................................................................234

7.3.1 Outline....................................................................................................................................... 234

7.3.2 Functions .................................................................................................................................. 234

7.3.3 Configuration............................................................................................................................. 235

7.3.4 Timer n control register ............................................................................................................. 236

7.4 8-Bit Timer Operation.............................................................................................................242

7.4.1 Operation as interval timer (8-bit operation) ............................................................................. 242

7.4.2 Operation as external event counter......................................................................................... 245

7.4.3 Operation as square wave output (8-bit resolution) .................................................................. 246

7.4.4 Operation as 8-bit PWM output................................................................................................. 247

7.4.5 Operation as interval timer (16 bits).......................................................................................... 250

7.4.6 Cautions.................................................................................................................................... 252

CHAPTER 8 WATCH TIMER................................................................................................................253

8.1 Function ..................................................................................................................................253

8.2 Configuration ..........................................................................................................................254

8.3 Watch Timer Control Registers.............................................................................................255

8.4 Operation.................................................................................................................................258

8.4.1 Operation as watch timer .......................................................................................................... 258

8.4.2 Operation as interval timer........................................................................................................ 258

8.4.3 Cautions.................................................................................................................................... 259

CHAPTER 9 WATCHDOG TIMER .......................................................................................................260

9.1 Functions ................................................................................................................................260

9.2 Configuration ..........................................................................................................................262

9.3 Watchdog Timer Control Register ........................................................................................262

9.4 Operation.................................................................................................................................265

9.4.1 Operation as watchdog timer .................................................................................................... 265

9.4.2 Operation as interval timer........................................................................................................ 266

9.5 Standby Function Control Register......................................................................................267

CHAPTER 10 SERIAL INTERFACE FUNCTION................................................................................268

10.1 Overview..................................................................................................................................268

10.2 3-Wire Serial I/O (CSI0 to CSI3) .............................................................................................268

10.2.1 Configuration............................................................................................................................. 269

10.2.2 CSIn control registers ............................................................................................................... 270

10.2.3 Operations ................................................................................................................................ 272

10.3 I2C Bus (A Versions) ...............................................................................................................275

10.3.1 Configuration............................................................................................................................. 278

10.3.2 I2C control registers................................................................................................................... 280

10.3.3 I2C bus mode functions ............................................................................................................. 291

User’s Manual U13850EJ6V0UD

10.3.4 I2C bus definitions and control methods ....................................................................................292

10.3.5 I2C interrupt requests (INTIICn).................................................................................................299

10.3.6 Interrupt request (INTIICn) generation timing and wait control .................................................317

10.3.7 Address match detection method..............................................................................................318

10.3.8 Error detection...........................................................................................................................318

10.3.9 Extension code..........................................................................................................................318

10.3.10 Arbitration..................................................................................................................................319

10.3.11 Wakeup function .......................................................................................................................320

10.3.12 Communication reservation.......................................................................................................321

10.3.13 Cautions ....................................................................................................................................324

10.3.14 Communication operations........................................................................................................325

10.3.15 Timing of data communication ..................................................................................................327

10.4 I2C Bus (B and H Versions) ....................................................................................................334

10.4.1 Configuration.............................................................................................................................337

10.4.2 I2C control register.....................................................................................................................339

10.4.3 I2C bus mode functions .............................................................................................................352

10.4.4 I2C bus definitions and control methods ....................................................................................353

10.4.5 I2C interrupt requests (INTIICn).................................................................................................360

10.4.6 Interrupt request (INTIICn) generation timing and wait control .................................................378

10.4.7 Address match detection method..............................................................................................379

10.4.8 Error detection...........................................................................................................................379

10.4.9 Extension code..........................................................................................................................379

10.4.10 Arbitration..................................................................................................................................380

10.4.11 Wakeup function .......................................................................................................................382

10.4.12 Communication reservation.......................................................................................................383

10.4.13 Cautions ....................................................................................................................................388

10.4.14 Communication operations........................................................................................................389

10.4.15 Timing of data communication ..................................................................................................392

10.5 Asynchronous Serial Interface (UART0, UART1) ................................................................399

10.5.1 Configuration.............................................................................................................................399

10.5.2 UARTn control registers............................................................................................................401

10.5.3 Operations.................................................................................................................................406

10.5.4 Standby function .......................................................................................................................418

10.6 3-Wire Variable-Length Serial I/O (CSI4)...............................................................................419

10.6.1 Configuration.............................................................................................................................419

10.6.2 CSI4 control registers................................................................................................................422

10.6.3 Operations.................................................................................................................................426

CHAPTER 11 A/D CONVERTER..........................................................................................................431

11.1 Function...................................................................................................................................431

11.2 Configuration ..........................................................................................................................433

11.3 Control Registers....................................................................................................................435

11.4 Operation .................................................................................................................................438

11.4.1 Basic operation .........................................................................................................................438

11.4.2 Input voltage and conversion result ..........................................................................................440

11.4.3 A/D converter operation mode ..................................................................................................441

11.5 Low Power Consumption Mode ............................................................................................443

User’s Manual U13850EJ6V0UD 17

11.6 Cautions ..................................................................................................................................443

11.7 How to Read A/D Converter Characteristics Table .............................................................447

CHAPTER 12 DMA FUNCTIONS .........................................................................................................451

12.1 Functions ................................................................................................................................451

12.2 Transfer Completion Interrupt Request ...............................................................................451

12.3 Configuration ..........................................................................................................................452

12.4 Control Registers ...................................................................................................................453

12.5 Operation.................................................................................................................................462

12.6 Cautions ..................................................................................................................................463

CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) ...................................................................466

13.1 Function ..................................................................................................................................466

13.2 Features...................................................................................................................................466

13.3 Configuration ..........................................................................................................................467

13.4 RTO Control Registers...........................................................................................................469

13.5 Usage.......................................................................................................................................471

13.6 Operation.................................................................................................................................472

13.7 Cautions ..................................................................................................................................473

CHAPTER 14 PORT FUNCTION..........................................................................................................474

14.1 Port Configuration..................................................................................................................474

14.2 Port Pin Function....................................................................................................................474

14.2.1 Port 0 ........................................................................................................................................ 474

14.2.2 Port 1 ........................................................................................................................................ 479

14.2.3 Port 2 ........................................................................................................................................ 483

14.2.4 Port 3 ........................................................................................................................................ 488

14.2.5 Ports 4 and 5............................................................................................................................. 492

14.2.6 Port 6 ........................................................................................................................................ 495

14.2.7 Ports 7 and 8............................................................................................................................. 498

14.2.8 Port 9 ........................................................................................................................................ 500

14.2.9 Port 10 ...................................................................................................................................... 503

14.2.10 Port 11 ..................................................................................................................................... 507

14.3 Setting When Port Pin Is Used as Alternate Function ........................................................511

14.4 Port Function Operation ........................................................................................................515

14.4.1 Write operation to I/O port......................................................................................................... 515

14.4.2 Read operation from I/O port .................................................................................................... 515

CHAPTER 15 RESET FUNCTION........................................................................................................516

15.1 General ....................................................................................................................................516

15.2 Pin Operations ........................................................................................................................516

CHAPTER 16 REGULATOR .................................................................................................................517

16.1 Outline .....................................................................................................................................517

User’s Manual U13850EJ6V0UD

16.2 Operation .................................................................................................................................517

CHAPTER 17 ROM CORRECTION FUNCTION .................................................................................518

17.1 General.....................................................................................................................................518

17.2 ROM Correction Peripheral I/O Registers ............................................................................519

CHAPTER 18 FLASH MEMORY ..........................................................................................................523

18.1 Features ...................................................................................................................................523

18.1.1 Erase unit ..................................................................................................................................524

18.1.2 Write/read time..........................................................................................................................524

18.2 Writing with Flash Programmer ............................................................................................525

18.3 Programming Environment ...................................................................................................530

18.4 Communication Mode ............................................................................................................530

18.5 Pin Connection .......................................................................................................................533

18.5.1 VPP pin.......................................................................................................................................533

18.5.2 Serial interface pin ....................................................................................................................533

18.5.3 RESET pin.................................................................................................................................536

18.5.4 Port pins (including NMI)...........................................................................................................536

18.5.5 Other signal pins .......................................................................................................................536

18.5.6 Power supply.............................................................................................................................536

18.6 Programming Method.............................................................................................................537

18.6.1 Flash memory control................................................................................................................537

18.6.2 Flash memory programming mode ...........................................................................................538

18.6.3 Selection of communication mode ............................................................................................539

18.6.4 Communication command.........................................................................................................539

18.6.5 Resources used ........................................................................................................................540

CHAPTER 19 IEBus CONTROLLER (V850/SB2) ..............................................................................541

19.1 IEBus Controller Function .....................................................................................................541

19.1.1 Communication protocol of IEBus.............................................................................................541

19.1.2 Determination of bus mastership (arbitration) ...........................................................................542

19.1.3 Communication mode ...............................................................................................................542

19.1.4 Communication address............................................................................................................543

19.1.5 Broadcasting communication ....................................................................................................543

19.1.6 Transfer format of IEBus ...........................................................................................................544

19.1.7 Transfer data.............................................................................................................................554

19.1.8 Bit format...................................................................................................................................557

19.2 IEBus Controller Configuration.............................................................................................558

19.3 Internal Registers of IEBus Controller..................................................................................560

19.3.1 Internal register list....................................................................................................................560

19.3.2 Internal registers .......................................................................................................................561

19.4 Interrupt Operations of IEBus Controller .............................................................................584

19.4.1 Interrupt control block................................................................................................................584

19.4.2 Interrupt source list....................................................................................................................585

19.4.3 Communication error source processing list .............................................................................586

User’s Manual U13850EJ6V0UD 19

19.5 Interrupt Generation Timing and Main CPU Processing ....................................................588

19.5.1 Master transmission.................................................................................................................. 588

19.5.2 Master reception ....................................................................................................................... 590

19.5.3 Slave transmission.................................................................................................................... 592

19.5.4 Slave reception ......................................................................................................................... 594

19.5.5 Interval of occurrence of interrupt for IEBus control.................................................................. 596

CHAPTER 20 ELECTRICAL SPECIFICATIONS .................................................................................600

CHAPTER 21 PACKAGE DRAWINGS ................................................................................................635

CHAPTER 22 RECOMMENDED SOLDERING CONDITIONS ...........................................................637

APPENDIX A NOTES ON TARGET SYSTEM DESIGN ...................................................................642

APPENDIX B REGISTER INDEX .........................................................................................................644

APPENDIX C INSTRUCTION SET LIST .............................................................................................651

APPENDIX D INDEX.............................................................................................................................. 658

APPENDIX E REVISION HISTORY......................................................................................................664

User’s Manual U13850EJ6V0UD

LIST OF FIGURES (1/6)

Figure No. Title Page

3-1 CPU Register Set ...........................................................................................................................................97

3-2 CPU Address Space.....................................................................................................................................103

3-3 Image on Address Space .............................................................................................................................104

3-4 Program Space.............................................................................................................................................105

3-5 Data Space...................................................................................................................................................105

3-6 Memory Map.................................................................................................................................................106

3-7 Internal ROM Area (128 KB).........................................................................................................................107

3-8 Internal ROM/Flash Memory Area (256 KB) .................................................................................................107

3-9 Internal ROM/Flash Memory Area (384 KB) .................................................................................................108

3-10 Internal ROM/Flash Memory Area (512 KB).................................................................................................108

3-11 Internal RAM Area (8 KB) .............................................................................................................................110

3-12 Internal RAM Area (12 KB) ...........................................................................................................................110

3-13 Internal RAM Area (16 KB) ...........................................................................................................................111

3-14 Internal RAM Area (24 KB) ...........................................................................................................................111

3-15 On-Chip Peripheral I/O Area.........................................................................................................................112

3-16 External Memory Area (When Expanded to 64 K, 256 K, or 1 MB)..............................................................113

3-17 External Memory Area (When Expanded to 4 MB).......................................................................................114

3-18 Application of Wrap-Around..........................................................................................................................117

3-19 Recommended Memory Map (Flash Memory Version) ................................................................................118

4-1 Byte Access (8 Bits)......................................................................................................................................130

4-2 Halfword Access (16 Bits).............................................................................................................................130

4-3 Word Access (32 Bits) ..................................................................................................................................130

4-4 Memory Block...............................................................................................................................................131

4-5 Wait Control..................................................................................................................................................133

4-6 Example of Inserting Wait States..................................................................................................................133

4-7 Bus Hold Procedure......................................................................................................................................136

4-8 Memory Read ...............................................................................................................................................137

4-9 Memory Write ...............................................................................................................................................141

4-10 Bus Hold Timing ...........................................................................................................................................143

5-1 Non-Maskable Interrupt Servicing ................................................................................................................150

5-2 Acknowledging Non-Maskable Interrupt Request.........................................................................................151

5-3 RETI Instruction Processing .........................................................................................................................152

5-4 Maskable Interrupt Servicing ........................................................................................................................156

5-5 RETI Instruction Processing .........................................................................................................................157

5-6 Example of Multiple Interrupt Servicing ........................................................................................................159

5-7 Example of Servicing Interrupt Requests Generated Simultaneously ..........................................................161

5-8 Software Exception Processing....................................................................................................................169

5-9 RETI Instruction Processing .........................................................................................................................170

5-10 Illegal Opcode...............................................................................................................................................171

5-11 Exception Trap Processing...........................................................................................................................172

5-12 RETI Instruction Processing .........................................................................................................................173

User’s Manual U13850EJ6V0UD 21

LIST OF FIGURES (2/6)

Figure No. Title Page

5-13 Pipeline Operation at Interrupt Request Acknowledgment...........................................................................177

5-14 Pipeline Flow and Interrupt Request Signal Generation Timing...................................................................179

5-15 Key Return Block Diagram ........................................................................................................................... 181

6-1 Clock Generator ........................................................................................................................................... 183

6-2 Oscillation Stabilization Time .......................................................................................................................196

7-1 Block Diagram of TM0 and TM1................................................................................................................... 201

7-2 Control Register Settings When TMn Operates as Interval Timer ...............................................................211

7-3 Configuration of Interval Timer .....................................................................................................................212

7-4 Timing of Interval Timer Operation...............................................................................................................212

7-5 Control Register Settings in PPG Output Operation..................................................................................... 213

7-6 Configuration of PPG Output........................................................................................................................214

7-7 PPG Output Operation Timing...................................................................................................................... 214

7-8 Control Register Settings for Pulse Width Measurement with Free-Running Counter

and One Capture Register............................................................................................................................215

7-9 Configuration for Pulse Width Measurement with Free-Running Counter.................................................... 216

7-10 Timing of Pulse Width Measurement with Free-Running Counter and One Capture Register

(with Both Edges Specified) ......................................................................................................................... 216

7-11 Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter....................217

7-12 CRn1 Capture Operation with Rising Edge Specified .................................................................................. 218

7-13 Timing of Pulse Width Measurement with Free-Running Counter (with Both Edges Specified) ..................218

7-14 Control Register Settings for Pulse Width Measurement with Free-Running Counter

and Two Capture Registers..........................................................................................................................219

7-15 Timing of Pulse Width Measurement with Free-Running Counter and Two Capture Registers

(with Rising Edge Specified).........................................................................................................................220

7-16 Control Register Settings for Pulse Width Measurement by Restarting ....................................................... 221

7-17 Timing of Pulse Width Measurement by Restarting (with Rising Edge Specified) .......................................221

7-18 Control Register Settings in External Event Counter Mode.......................................................................... 222

7-19 Configuration of External Event Counter...................................................................................................... 223

7-20 Timing of External Event Counter Operation (with Rising Edge Specified)..................................................223

7-21 Control Register Settings in Square Wave Output Mode .............................................................................224

7-22 Timing of Square Wave Output Operation ................................................................................................... 225

7-23 Control Register Settings for One-Shot Pulse Output with Software Trigger ...............................................226

7-24 Timing of One-Shot Pulse Output Operation with Software Trigger............................................................. 227

7-25 Control Register Settings for One-Shot Pulse Output with External Trigger ................................................ 228

7-26 Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified)................229

7-27 Start Timing of 16-Bit Timer Register n ........................................................................................................ 230

7-28 Timing After Changing Compare Register During Timer Count Operation................................................... 230

7-29 Data Hold Timing of Capture Register.......................................................................................................... 231

7-30 Operation Timing of OVFn Bit ...................................................................................................................... 232

7-31 Block Diagram of TM2 to TM7......................................................................................................................235

7-32 Timing of Interval Timer Operation...............................................................................................................242

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LIST OF FIGURES (3/6)

Figure No. Title Page

7-33 Timing of External Event Counter Operation (with Rising Edge Specified) ..................................................245

7-34 Square Wave Output Operation Timing........................................................................................................246

7-35 Timing of PWM Output .................................................................................................................................248

7-36 Timing of Operation Based on CRn0 Transitions .........................................................................................249

7-37 Cascade Connection Mode with 16-Bit Resolution.......................................................................................251

7-38 Start Timing of Timer n .................................................................................................................................252

7-39 Timing After Compare Register Changes During Timer Count Operation....................................................252

8-1 Block Diagram of Watch Timer .....................................................................................................................253

8-2 Operation Timing of Watch Timer/Interval Timer..........................................................................................259

8-3 Watch Timer Interrupt Request (INTWTN) Generation (Interrupt Period = 0.5 s).........................................259

9-1 Block Diagram of Watchdog Timer ...............................................................................................................260

10-1 Block Diagram of 3-Wire Serial I/O...............................................................................................................269

10-2 CSIMn Setting (Operation Stop Mode) .........................................................................................................272

10-3 CSIMn Setting (3-Wire Serial I/O Mode).......................................................................................................273

10-4 Timing of 3-Wire Serial I/O Mode .................................................................................................................274

10-5 Block Diagram of I2C.....................................................................................................................................276

10-6 Serial Bus Configuration Example Using I2C Bus .........................................................................................277

10-7 Pin Configuration Diagram............................................................................................................................292

10-8 I2C Bus’s Serial Data Transfer Timing ..........................................................................................................292

10-9 Start Condition..............................................................................................................................................293

10-10 Address.........................................................................................................................................................293

10-11 Transfer Direction Specification....................................................................................................................294

10-12 ACK Signal ...................................................................................................................................................295

10-13 Stop Condition ..............................................................................................................................................296

10-14 Wait Signal....................................................................................................................................................297

10-15 Arbitration Timing Example...........................................................................................................................319

10-16 Communication Reservation Timing.............................................................................................................322

10-17 Timing for Acknowledging Communication Reservations.............................................................................322

10-18 Communication Reservation Flowchart ........................................................................................................323

10-19 Master Operation Flowchart .........................................................................................................................325

10-20 Slave Operation Flowchart ...........................................................................................................................326

10-21 Example of Master to Slave Communication

(When 9-Clock Wait Is Selected for Both Master and Slave) .......................................................................328

10-22 Example of Slave to Master Communication

(When 9-Clock Wait Is Selected for Both Master and Slave) .......................................................................331

10-23 Block Diagram of I2C.....................................................................................................................................335

10-24 Serial Bus Configuration Example Using I2C Bus .........................................................................................336

10-25 Pin Configuration Diagram............................................................................................................................353

10-26 I2C Bus’s Serial Data Transfer Timing ..........................................................................................................353

10-27 Start Conditions ............................................................................................................................................354

User’s Manual U13850EJ6V0UD 23

LIST OF FIGURES (4/6)

Figure No. Title Page

10-28 Address ........................................................................................................................................................ 354

10-29 Transfer Direction Specification ................................................................................................................... 355

10-30 ACK Signal ................................................................................................................................................... 356

10-31 Stop Condition ..............................................................................................................................................357

10-32 Wait Signal ................................................................................................................................................... 358

10-33 Arbitration Timing Example ..........................................................................................................................381

10-34 Communication Reservation Timing............................................................................................................. 384

10-35 Timing for Accepting Communication Reservations.....................................................................................384

10-36 Communication Reservation Flowchart........................................................................................................385

10-37 Timing at Which STTn = 1 Cannot Be Set.................................................................................................... 386

10-38 Master Communication Start or Stop Flowchart........................................................................................... 387

10-39 Master Operation Flowchart (1)....................................................................................................................389

10-40 Master Operation Flowchart (2)....................................................................................................................390

10-41 Slave Operation Flowchart ...........................................................................................................................391

10-42 Example of Master to Slave Communication

(When 9-Clock Wait Is Selected for Both Master and Slave).......................................................................393

10-43 Example of Slave to Master Communication

(When 9-Clock Wait Is Selected for Both Master and Slave).......................................................................396

10-44 Block Diagram of UARTn .............................................................................................................................400

10-45 ASIMn Setting (Operation Stop Mode) .........................................................................................................406

10-46 ASIMn Setting (Asynchronous Serial Interface Mode) ................................................................................. 407

10-47 ASISn Setting (Asynchronous Serial Interface Mode)..................................................................................408

10-48 BRGCn Setting (Asynchronous Serial Interface Mode)................................................................................ 409

10-49 BRGMCn0 and BRGMCn1 Settings (Asynchronous Serial Interface Mode)................................................ 410

10-50 Error Tolerance (When k = 16), Including Sampling Errors..........................................................................412

10-51 Format of Transmit/Receive Data in Asynchronous Serial Interface............................................................ 413

10-52 Timing of Asynchronous Serial Interface Transmit Completion Interrupt ..................................................... 415

10-53 Timing of Asynchronous Serial Interface Receive Completion Interrupt ......................................................416

10-54 Receive Error Timing....................................................................................................................................417

10-55 Block Diagram of CSI4 ................................................................................................................................. 420

10-56 When Transfer Bit Length Other Than 16 Bits Is Set ................................................................................... 421

10-57 CSIM4 Setting (Operation Stop Mode)......................................................................................................... 426

10-58 CSIM4 Setting (3-Wire Variable-Length Serial I/O Mode) ............................................................................427

10-59 CSIB4 Setting (3-Wire Variable-Length Serial I/O Mode).............................................................................428

10-60 Timing of 3-Wire Variable-Length Serial I/O Mode....................................................................................... 429

10-61 Timing of 3-Wire Variable-Length Serial I/O Mode (When CSIB4 = 08H) ....................................................430

11-1 Block Diagram of A/D Converter ..................................................................................................................432

11-2 Basic Operation of A/D Converter ................................................................................................................439

11-3 Relationship Between Analog Input Voltage and A/D Conversion Result .................................................... 440

11-4 A/D Conversion by Hardware Start (with Falling Edge Specified)................................................................441

11-5 A/D Conversion by Software Start................................................................................................................ 442

11-6 Handling of Analog Input Pin........................................................................................................................ 444

User’s Manual U13850EJ6V0UD

LIST OF FIGURES (5/6)

Figure No. Title Page

11-7 A/D Conversion End Interrupt Generation Timing ........................................................................................445

11-8 Handling of AVDD Pin ....................................................................................................................................446

11-9 Overall Error .................................................................................................................................................447

11-10 Quantization Error.........................................................................................................................................448

11-11 Zero-Scale Error ...........................................................................................................................................448

11-12 Full-Scale Error.............................................................................................................................................449

11-13 Differential Linearity Error .............................................................................................................................449

11-14 Integral Linearity Error ..................................................................................................................................450

11-15 Sampling Time..............................................................................................................................................450

12-1 Block Diagram of DMA .................................................................................................................................452

12-2 Correspondence Between DRAn Setting Value and Internal RAM (8 KB) ...................................................455

12-3 Correspondence Between DRAn Setting Value and Internal RAM (12 KB) .................................................456

12-4 Correspondence Between DRAn Setting Value and Internal RAM (16 KB) .................................................457

12-5 Correspondence Between DRAn Setting Value and Internal RAM (24 KB) .................................................458

12-6 DMA Transfer Operation Timing...................................................................................................................462

12-7 Processing When Transfer Requests DMA0 to DMA5 Are Generated Simultaneously ...............................463

12-8 When Interrupt Servicing Occurs Twice During DMA Operation ..................................................................464

13-1 Block Diagram of RTO..................................................................................................................................467

13-2 Configuration of Real-Time Output Buffer Registers ....................................................................................468

13-3 Example of Operation Timing of RTO (When EXTR = 0, BYTE = 0)............................................................472

14-1 Block Diagram of P00 to P07........................................................................................................................478

14-2 Block Diagram of P10 to P12, P14, and P15................................................................................................481

14-3 Block Diagram of P13 ...................................................................................................................................482

14-4 Block Diagram of P20 to P22, P24, and P25................................................................................................486

14-5 Block Diagram of P23, P26, and P27 ...........................................................................................................487

14-6 Block Diagram of P30 to P32 and P35 to P37..............................................................................................490

14-7 Block Diagram of P33 and P34.....................................................................................................................491

14-8 Block Diagram of P40 to P47 and P50 to P57..............................................................................................494

14-9 Block Diagram P60 to P65............................................................................................................................497

14-10 Block Diagram of P70 to P77 and P80 to P83..............................................................................................499

14-11 Block Diagram of P90 to P96........................................................................................................................502

14-12 Block Diagram of P100 to P107....................................................................................................................506

14-13 Block Diagram of P110 to P113....................................................................................................................510

15-1 System Reset Timing....................................................................................................................................516

16-1 Regulator ......................................................................................................................................................517

17-1 Block Diagram of ROM Correction................................................................................................................518

17-2 ROM Correction Operation and Program Flow.............................................................................................522

User’s Manual U13850EJ6V0UD 25

LIST OF FIGURES (6/6)

Figure No. Title Page

18-1 Wiring Example of V850/SB1 and V850/SB2 Flash Writing Adapter (FA-100GC-8EU)...............................526

18-2 Wiring Example of V850/SB1 and V850/SB2 Flash Writing Adapter (FA-100GF-3BA) ............................... 528

18-3 Environment Required for Writing Programs to Flash Memory .................................................................... 530

18-4 Communication with Dedicated Flash Programmer (UART0) ...................................................................... 530

18-5 Communication with Dedicated Flash Programmer (CSI0) ..........................................................................531

18-6 Communication with Dedicated Flash Programmer (CSI0 + HS) ................................................................. 531

18-7 VPP Pin Connection Example........................................................................................................................ 533

18-8 Conflict of Signals (Serial Interface Input Pin).............................................................................................. 534

18-9 Malfunction of Other Device .........................................................................................................................535

18-10 Conflict of Signals (RESET Pin) ................................................................................................................... 536

18-11 Procedure for Manipulating Flash Memory...................................................................................................537

18-12 Flash Memory Programming Mode .............................................................................................................. 538

18-13 Communication Command ........................................................................................................................... 539

19-1 IEBus Transfer Signal Format ...................................................................................................................... 544

19-2 Master Address Field....................................................................................................................................545

19-3 Slave Address Field ..................................................................................................................................... 546

19-4 Control Field .................................................................................................................................................548

19-5 Telegraph Length Field ................................................................................................................................550

19-6 Data Field ..................................................................................................................................................... 551

19-7 Bit Configuration of Slave Status..................................................................................................................555

19-8 Configuration of Lock Address .....................................................................................................................556

19-9 Bit Format of IEBus ......................................................................................................................................557

19-10 IEBus Controller Block Diagram ................................................................................................................... 558

19-11 Interrupt Generation Timing (for (1), (3), and (4))......................................................................................... 567

19-12 Interrupt Generation Timing (for (2) and (5)) ................................................................................................ 568

19-13 Timing of INTIE2 Interrupt Generation in Locked State (for (4) and (5)) ......................................................568

19-14 Timing of INTIE2 Interrupt Generation in Locked State (for (3))................................................................... 569

19-15 Example of Broadcasting Communication Flag Operation...........................................................................573

19-16 Configuration of Interrupt Control Block .......................................................................................................584

19-17 Master Transmission .................................................................................................................................... 588

19-18 Master Reception .........................................................................................................................................590

19-19 Slave Transmission ...................................................................................................................................... 592

19-20 Slave Reception ........................................................................................................................................... 594

19-21 Master Transmission (Interval of Interrupt Occurrence) ...............................................................................596

19-22 Master Reception (Interval of Interrupt Occurrence) .................................................................................... 597

19-23 Slave Transmission (Interval of Interrupt Occurrence) .................................................................................598

19-24 Slave Reception (Interval of Interrupt Occurrence) ......................................................................................599

A-1 100-Pin Plastic LQFP (Fine Pitch) (14 × 14) ................................................................................................ 642

A-2 100-Pin Plastic QFP (14 × 20)......................................................................................................................643

User’s Manual U13850EJ6V0UD

LIST OF TABLES (1/3)

Table No. Title Page

1-1 Product Lineup of V850/SB1 ..........................................................................................................................30

1-2 Product Lineup of V850/SB2 ..........................................................................................................................31

2-1 Pin I/O Buffer Power Supplies ........................................................................................................................73

2-2 Differences in Pins Between V850/SB1 and V850/SB2 .................................................................................73

2-3 Operating States of Pins in Each Operating Mode .........................................................................................80

3-1 Program Registers..........................................................................................................................................98

3-2 System Register Numbers..............................................................................................................................99

3-3 Interrupt/Exception Table..............................................................................................................................109

4-1 Bus Control Pins...........................................................................................................................................128

4-2 Number of Access Clocks.............................................................................................................................129

4-3 Bus Priority ...................................................................................................................................................144

5-1 Interrupt Source List .....................................................................................................................................147

5-2 Interrupt Control Register (xxICn).................................................................................................................164

5-3 Priorities of Interrupts and Exceptions..........................................................................................................174

5-4 Description of Key Return Detection Pin ......................................................................................................180

6-1 Operating Statuses in HALT Mode ...............................................................................................................190

6-2 Operating Statuses in IDLE Mode ................................................................................................................192

6-3 Operating Statuses in Software STOP Mode ...............................................................................................194

7-1 Configuration of Timers 0 and 1 ...................................................................................................................202

7-2 Valid Edge of TIn0 Pin and Capture Trigger of CRn0...................................................................................203

7-3 Valid Edge of TIn1 Pin and Capture Trigger of CRn0...................................................................................203

7-4 TIn0 Pin Valid Edge and CRn1 Capture Trigger...........................................................................................204

7-5 Configuration of Timers 2 to 7 ......................................................................................................................235

8-1 Interval Time of Interval Timer......................................................................................................................254

8-2 Configuration of Watch Timer.......................................................................................................................254

8-3 Interval Time of Interval Timer......................................................................................................................258

9-1 Inadvertent Program Loop Detection Time of Watchdog Timer....................................................................261

9-2 Interval Time of Interval Timer......................................................................................................................261

9-3 Configuration of Watchdog Timer.................................................................................................................262

9-4 Inadvertent Program Loop Detection Time of Watchdog Timer....................................................................265

9-5 Interval Time of Interval Timer......................................................................................................................266

10-1 Configuration of CSIn ...................................................................................................................................269

10-2 Configuration of I2Cn.....................................................................................................................................278

10-3 Selection Clock Setting.................................................................................................................................290

User’s Manual U13850EJ6V0UD 27

LIST OF TABLES (2/3)

Table No. Title Page

10-4 INTIICn Generation Timing and Wait Control...............................................................................................317

10-5 Extension Code Bit Definitions ..................................................................................................................... 319

10-6 Status During Arbitration and Interrupt Request Generation Timing ............................................................320

10-7 Wait Periods ................................................................................................................................................. 321

10-8 Configuration of I2Cn.....................................................................................................................................337

10-9 Selection Clock Setting ................................................................................................................................ 351

10-10 INTIICn Generation Timing and Wait Control............................................................................................... 378

10-11 Extension Code Bit Definitions .....................................................................................................................380

10-12 Status During Arbitration and Interrupt Request Generation Timing ............................................................ 381

10-13 Wait Periods .................................................................................................................................................383

10-14 Wait Time ..................................................................................................................................................... 386

10-15 Configuration of UARTn ...............................................................................................................................399

10-16 Relationship Between Main Clock and Baud Rate ....................................................................................... 411

10-17 Receive Error Causes ..................................................................................................................................417

10-18 Configuration of CSI4 ................................................................................................................................... 419

11-1 Configuration of A/D Converter .................................................................................................................... 433

12-1 Internal RAM Area Usable in DMA ............................................................................................................... 454

13-1 Configuration of RTO....................................................................................................................................467

13-2 Operation When Real-Time Output Buffer Registers Are Manipulated ........................................................ 468

13-3 Operation Mode and Output Trigger of Real-Time Output Port....................................................................470

14-1 Pin I/O Buffer Power Supplies ...................................................................................................................... 474

14-2 Port 0 Alternate Function Pins......................................................................................................................475

14-3 Port 1 Alternate Function Pins......................................................................................................................479

14-4 Port 2 Alternate Function Pins......................................................................................................................483

14-5 Port 3 Alternate Function Pins......................................................................................................................488

14-6 Alternate Function Pins of Ports 4 and 5......................................................................................................492

14-7 Port 6 Alternate Function Pins......................................................................................................................495

14-8 Alternate Function Pins of Ports 7 and 8......................................................................................................498

14-9 Port 9 Alternate Function Pins......................................................................................................................500

14-10 Port 10 Alternate Function Pins....................................................................................................................503

14-11 Port 11 Alternate Function Pins....................................................................................................................507

14-12 Setting When Port Pin Is Used as Alternate Function .................................................................................. 511

18-1 Table for Wiring of V850/SB1 and V850/SB2 Flash Writing Adapter (FA-100GC-8EU)............................... 527

18-2 Table for Wiring of V850/SB1 and V850/SB2 Flash Writing Adapter (FA-100GF-3BA) ............................... 529

18-3 Signal Generation of Dedicated Flash Programmer (PG-FP3)..................................................................... 532

18-4 Pins Used in Serial Interfaces ......................................................................................................................533

18-5 List of Communication Modes ...................................................................................................................... 539

18-6 Flash Memory Control Command.................................................................................................................540

User’s Manual U13850EJ6V0UD

LIST OF TABLES (3/3)

Table No. Title Page

18-7 Response Command ....................................................................................................................................540

19-1 Transfer Rate and Maximum Number of Transfer Bytes in Communication Mode 1....................................542

19-2 Contents of Control Bits................................................................................................................................547

19-3 Control Field for Locked Slave Unit ..............................................................................................................548

19-4 Control Field for Unlocked Slave Unit...........................................................................................................548

19-5 Acknowledge Signal Output Condition of Control Field ................................................................................549

19-6 Contents of Telegraph Length Bit.................................................................................................................550

19-7 Internal Registers of IEBus Controller ..........................................................................................................560

19-8 Reset Conditions of Flags in ISR Register ...................................................................................................575

19-9 Interrupt Source List .....................................................................................................................................585

19-10 Communication Error Source Processing List ..............................................................................................586

22-1 Surface Mounting Type Soldering Conditions ..............................................................................................637

C-1 Symbols in Operand Description ..................................................................................................................651

C-2 Symbols Used for Opcode............................................................................................................................652

C-3 Symbols Used for Operation Description......................................................................................................652

C-4 Symbols Used for Flag Operation.................................................................................................................653

C-5 Condition Codes ...........................................................................................................................................653

User’s Manual U13850EJ6V0UD 29

CHAPTER 1 INTRODUCTION

The V850/SB1 and V850/SB2 are products in the NEC Electronics V850 Series of single-chip microcontrollers

designed for low power operation.

1.1 General

The V850/SB1 and V850/SB2 are 32-bit single-chip microcontrollers that include the V850 Series CPU core, and

peripheral functions such as ROM/RAM, a timer/counter, a serial interface, an A/D converter, a timer, and DMA

controller.

Based on the V850/SA1™, the V850/SB1 and V850/SB2 feature various additions, including 3 to 5 V I/O interface

support, and ROM correction. For V850/SB2, based on the V850/SB1™, the peripheral functions of automobile LAN

(IEBus™ (Inter Equipment Bus™)) are added. In addition to high real-time response characteristics and 1-clock-pitch

basic instructions, the V850/SB1 and V850/SB2 have multiply, saturation operation, and bit manipulation instructions

realized with a hardware multiplier for digital servo control. Moreover, as a real-time control system, the V850/SB1

and V850/SB2 enable the realization of extremely high cost-performance for applications that require low power

consumption, such as audio equipment, car audio systems, and VCRs.

Table 1-1 shows the outlines of the V850/SB1 and V850/SB2 product lineup.

CHAPTER 1 INTRODUCTION

User’s Manual U13850EJ6V0UD

Table 1-1. Product Lineup of V850/SB1

Product Name ROM

Commercial Name Part Number

On-Chip

I2CType Size

RAM Size Package On-Chip

IEBus

PD703031A No

PD703031AY Yes

Mask ROM 128 KB 12 KB 100-pin QFP (14 × 20)/

100-pin LQFP (14 × 14)

PD703033A Mask ROM

PD70F3033A

Flash memory

PD703033AY Mask ROM

PD70F3033AY

Yes

Flash memory

256 KB 16 KB 100-pin QFP (14 × 20)/

100-pin LQFP (14 × 14)

PD703032A Mask ROM

PD70F3032A

Flash memory

PD703032AY Mask ROM

PD70F3032AY

Yes

Flash memory

512 KB 24 KB 100-pin QFP (14 × 20)

PD703031B No

PD703031BY Yes

Mask ROM 128 KB 8 KB 100-pin QFP (14 × 20)/

100-pin LQFP (14 × 14)

PD703033B Mask ROM

PD70F3033B

Flash memory

PD703033BY Mask ROM

PD70F3033BY

Yes

Flash memory

256 KB 16 KB 100-pin QFP (14 × 20)/

100-pin LQFP (14 × 14)

PD703030B Mask ROM

PD70F3030B

Flash memory

PD703030BY Mask ROM

PD70F3030BY

Yes

Flash memory

384 KB 24 KB 100-pin QFP (14 × 20)/

100-pin LQFP (14 × 14)

PD703032B Mask ROM

PD70F3032B

Flash memory

PD703032BY Mask ROM

V850/SB1

PD70F3032BY

Yes

Flash memory

512 KB 24 KB 100-pin QFP (14 × 20)

CHAPTER 1 INTRODUCTION

User’s Manual U13850EJ6V0UD 31

Table 1-2. Product Lineup of V850/SB2

Product Name ROM

Commercial Name Part Number

On-Chip

I2CType Size

RAM Size Package On-Chip

IEBus

PD703034A No

PD703034AY Yes

Mask ROM 128 KB 12 KB 100-pin QFP (14 × 20)/

100-pin LQFP (14 × 14)

PD703035A Mask ROM

PD70F3035A

Flash memory

PD703035AY Mask ROM

PD70F3035AY

Yes

Flash memory

256 KB 16 KB 100-pin QFP (14 × 20)/

100-pin LQFP (14 × 14)

PD703037A Mask ROM

PD70F3037A

Flash memory

PD703037AY Mask ROM

PD70F3037AY

Yes

Flash memory

512 KB 24 KB 100-pin QFP (14 × 20)

PD703034B No

PD703034BY Yes

Mask ROM 128 KB 8 KB 100-pin QFP (14 × 20)/

100-pin LQFP (14 × 14)

PD703035B Mask ROM

PD70F3035B

Flash memory

PD703035BY Mask ROM

PD70F3035BY

Yes

Flash memory

256 KB 16 KB 100-pin QFP (14 × 20)/

100-pin LQFP (14 × 14)

PD703036H Mask ROM

PD70F3036H

Flash memory

PD703036HY Mask ROM

PD70F3036HY

Yes

Flash memory

384 KB 24 KB 100-pin QFP (14 × 20)/

100-pin LQFP (14 × 14)

PD703037H Mask ROM

PD70F3037H

Flash memory

PD703037HY Mask ROM

V850/SB2

PD70F3037HY

Yes

Flash memory

512 KB 24 KB 100-pin QFP (14 × 20)

Yes

The part numbers of the V850/SB1 and V850/SB2 are described as follows in this manual.

•A versions

A versions of the V850/SB1:

PD703031A, 703031AY, 703032A, 703032AY, 703033A, 703033AY,

70F3032A, 70F3032AY, 70F3033A, 70F3033AY

A versions of the V850/SB2:

PD703034A, 703034AY, 703035A, 703035AY, 703037A, 703037AY,

70F3035A, 70F3035AY, 70F3037A, 70F3037AY

•B versions, H versions

B versions of the V850/SB1:

PD703030B, 703030BY, 703031B, 703031BY, 703032B, 703032BY,

703033B, 703033BY, 70F3030B, 70F3030BY, 70F3032B, 70F3032BY,

70F3033B, 70F3033BY

B and H versions of the V850/SB2:

PD703034B, 703034BY, 703035B, 703035BY, 703036H, 703036HY,

703037H, 703037HY, 70F3035B, 70F3035BY, 70F3036H, 70F3036HY,

70F3037H, 70F3037HY

CHAPTER 1 INTRODUCTION

User’s Manual U13850EJ6V0UD

•Flash memory versions

Flash memory versions of the V850/SB1:

PD70F3030B, 70F3030BY, 70F3032A, 70F3032AY, 70F3032B,

70F3032BY, 70F3033A, 70F3033AY, 70F3033B, 70F3033BY

Flash memory versions of the V850/SB2:

PD70F3035A, 70F3035AY, 70F3035B, 70F3035BY, 70F3036H,

70F3036HY, 70F3037A, 70F3037AY, 70F3037H, 70F3037HY

•Mask ROM versions

Mask ROM versions of the V850/SB1:

PD703030B, 703030BY, 703031A, 703031AY, 703031B, 703031BY,

703032A, 703032AY, 703032B, 703032BY, 703033A, 703033AY,

703033B, 703033BY

Mask ROM versions of the V850/SB2:

PD703034A, 703034AY, 703034B, 703034BY, 703035A, 703035AY,

703035B, 703035BY, 703036H, 703036HY, 703037A, 703037AY,

703037H, 703037HY

•Y versions (with on-chip I2C)

Y versions of the V850/SB1 (with on-chip I2C):

PD703030BY, 703031AY, 703031BY, 703032AY, 703032BY,

703033AY, 703033BY, 70F3030BY, 70F3032AY, 70F3032BY,

70F3033AY, 70F3033BY

Y versions of the V850/SB2 (with on-chip I2C):

PD703034AY, 703034BY, 703035AY, 703035BY, 703036HY,

703037AY, 703037HY, 70F3035AY, 70F3035BY, 70F3036HY,

70F3037AY, 70F3037BY

CHAPTER 1 INTRODUCTION

User’s Manual U13850EJ6V0UD 33

1.2 V850/SB1 (A Versions)

1.2.1 Features (V850/SB1 (A versions))

{Number of instructions: 74

{Minimum instruction execution time

50 ns (operating at 20 MHz, external power supply 5 V, regulator output 3.3 V)

{General-purpose registers 32 bits × 32 registers

{Instruction set Signed multiplication (16 × 16 → 32): 100 ns (operating at 20 MHz)

(able to execute instructions in parallel continuously without creating any register

hazards).

Saturation operations (overflow and underflow detection functions are included)

32-bit shift instruction: 1 clock

Bit manipulation instructions

Load/store instructions with long/short format

{Memory space 16 MB of linear address space (for programs and data)

External expandability: expandable to 4 MB

Memory block allocation function: 2 MB per block

Programmable wait function

Idle state insertion function

{External bus interface 16-bit data bus (address/data multiplex)

Address bus: separate output enabled

3 V to 5 V interface enabled

Bus hold function

External wait function

{Internal memory

PD703031A, 703031AY (mask ROM: 128 KB/RAM: 12 KB)

PD703033A, 703033AY (mask ROM: 256 KB/RAM: 16 KB)

PD703032A, 703032AY (mask ROM: 512 KB/RAM: 24 KB)

PD70F3033A, 70F3033AY (flash memory: 256 KB/RAM: 16 KB)

PD70F3032A, 70F3032AY (flash memory: 512 KB/RAM: 24 KB)

{Interrupts and exceptions Non-maskable interrupts: 2 sources

Maskable interrupts: 37 sources (

PD703031A, 703032A, 703033A, 70F3032A,

70F3033A)

38 sources (

PD703031AY, 703032AY, 703033AY,

70F3032AY, 70F3033AY)

Software exceptions: 32 sources

Exception trap: 1 source

{I/O lines Total: 83 (12 input ports and 71 I/O ports)

3 V to 5 V interface enabled

{Timer/counter 16-bit timer: 2 channels (PWM output)

8-bit timer: 6 channels (4 PWM outputs, cascade connection enabled)

{Watch timer When operating under subclock or main clock: 1 channel

Operation using the subclock or main clock is also possible in the IDLE mode.

{Watchdog timer 1 channel

CHAPTER 1 INTRODUCTION

User’s Manual U13850EJ6V0UD

{Serial interface (SIO) Asynchronous serial interface (UART)

Clocked serial interface (CSI)

I2C bus interface (I2C) (only for

PD703031AY, 703032AY, 703033AY, 70F3032AY,

and 70F3033AY)

8-/16-bit variable-length serial interface

CSI/UART: 2 channels

CSI/I2C: 2 channels

CSI (8-/16-bit valuable): 1 channel

Dedicated baud rate generator: 3 channels

{A/D converter 10-bit resolution: 12 channels

{DMA controller Internal RAM ←→ on-chip peripheral I/O: 6 channels

{Real-time output port (RTP) 8 bits × 1 channel or 4 bits × 2 channels

{ROM correction Modifiable 4 points

{Regulator 4.0 V to 5.5 V input → internal 3.3 V

{Key return function 4 to 8 selecting enabled, falling edge fixed

{Clock generator During main clock or subclock operation

5-level CPU clock (including sub operations)

{Power-saving functions HALT/IDLE/STOP modes

{Package 100-pin plastic LQFP (fine pitch, 14 × 14)

100-pin plastic QFP (14 × 20)

{CMOS structure All static circuits

1.2.2 Application fields (V850/SB1 (A versions))

AV equipment

Example: Audio, car audio equipment, VCR, and TV.

CHAPTER 1 INTRODUCTION

User’s Manual U13850EJ6V0UD 35

1.2.3 Ordering information (V850/SB1 (A versions))

Part Number Package Internal ROM

PD703031AGC-xxx-8EU

PD703031AGF-xxx-3BA

PD703031AYGC-xxx-8EU

PD703031AYGF-xxx-3BA

PD703033AGC-xxx-8EU

PD703033AGF-xxx-3BA

PD703033AYGC-xxx-8EU

PD703033AYGF-xxx-3BA

PD703032AGF-xxx-3BA

PD703032AYGF-xxx-3BA

PD70F3033AGC-8EU

PD70F3033AGF-3BA

PD70F3033AYGC-8EU

PD70F3033AYGF-3BA

PD70F3032AGF-3BA

PD70F3032AYGF-3BA

100-pin plastic LQFP (fine pitch) (14 × 14)

100-pin plastic QFP (14 × 20)

100-pin plastic LQFP (fine pitch) (14 × 14)

100-pin plastic QFP (14 × 20)

100-pin plastic LQFP (fine pitch) (14 × 14)

100-pin plastic QFP (14 × 20)

100-pin plastic LQFP (fine pitch) (14 × 14)

100-pin plastic QFP (14 × 20)

100-pin plastic LQFP (fine pitch) (14 × 14)

100-pin plastic QFP (14 × 20)

100-pin plastic LQFP (fine pitch) (14 × 14)

100-pin plastic QFP (14 × 20)

Mask ROM (128 KB)

Mask ROM (256 KB)

Mask ROM (512 KB)

Flash memory (256 KB)

Flash memory (512 KB)

Remarks 1. ××× indicates ROM code suffix.

2. ROMless devices are not provided.

CHAPTER 1 INTRODUCTION

User’s Manual U13850EJ6V0UD

1.2.4 Pin configuration (top view) (V850/SB1 (A versions))

100-pin plastic LQFP (fine pitch) (14 × 14)

•

PD703031AGC-xxx-8EU •

PD70F3033AGC-8EU

•

PD703031AYGC-xxx-8EU •

PD70F3033AYGC-8EU

•

PD703033AGC-xxx-8EU

•

PD703033AYGC-xxx-8EU

P20/SI2/SDA1

P14/SO1/TXD0

P13/SI1/RXD0

P11/SO0

P10/SI0/SDA0

P07/INTP6

P05/INTP4/ADTRG

P04/INTP3

P03/INTP2

P02/INTP1

P01/INTP0

P00/NMI

P83/ANI11

P82/ANI10

P81/ANI9

P80/ANI8

P77/ANI7

P76/ANI6

P75/ANI5

P74/ANI4

P73/ANI3

P72/ANI2

P107/RTP7/KR7/A12

P110/WAIT/A1

P111/A2

P112/A3

P113/A4

XT1

XT2

REGC

VSS

VDD

P94/ASTB

P40/AD0

P41/AD1

P42/AD2

P43/AD3

100

P21/SO2

P23/RXD1/SI3

P24/TXD1/SO3

EVDD

EVSS

P26/TI2/TO2

P27/TI3/TO3

P30/TI00

P31/TI01

P33/TI11/SO4

P34/TO0/A13/SCK4

P35/TO1/A14

P36/TI4/TO4/A15

P37/TI5/TO5

IC/VPPNote 1

P100/RTP0/KR0/A5

P101/RTP1/KR1/A6

P102/RTP2/KR2/A7

P103/RTP3/KR3/A8

P104/RTP4/KR4/A9

P105/RTP5/KR5/A10

P106/RTP6/KR6/A11

P71/ANI1

P70/ANI0

VSS

VREF

VDD

P65/A21

P64/A20

P63/A19

P62/A18

P61/A17

P60/A16

P57/AD15

P56/AD14

P55/AD13

P54/AD12

P53/AD11

P52/AD10

P51/AD9

P50/AD8

BVSS

BVDD

P47/AD7

P46/AD6

P45/AD5

P44/AD4

P22/SCK2/SCL1Note 2

RESET

CLKOUT

P90/LBEN/WRL

P91/UBEN

P92/R/W/WRH

P93/DSTB/RD

P95/HLDAK

P96/HLDRQ

P15/SCK1/ASCK0

P12/SCK0/SCL0

P25/ASCK1/SCK3

P32/TI10/SI4

P06/INTP5/RTPTRG

Notes 1. IC (

PD703031A, 703031AY, 703033A, 703033AY): Connect directly to VSS.

VPP (

PD70F3033A, 70F3033AY): Connect to VSS in normal operation mode.

2. SCL0, SCL1, SDA0, and SDA1 are available only in the

PD703031AY, 703033AY, and 70F3033AY.

CHAPTER 1 INTRODUCTION

User’s Manual U13850EJ6V0UD 37

100-pin plastic QFP (14 × 20)

•

PD703031AGF-xxx-3BA •

PD703033AGF-xxx-3BA •

PD70F3033AGF-3BA

•

PD703031AYGF-xxx-3BA •

PD703033AYGF-xxx-3BA •

PD70F3033AYGF-3BA

•

PD703032AGF-xxx-3BA •

PD70F3032AGF-3BA

•

PD703032AYGF-xxx-3BA •

PD70F3032AYGF-3BA

P13/SI1/RXD0

P11/SO0

P10/SI0/SDA0Note 2

P07/INTP6

P06/INTP5/RTPTRG

P05/INTP4/ADTRG

P04/INTP3

P03/INTP2

P02/INTP1

P01/INTP0

P00/NMI

P83/ANI11

P82/ANI10

P81/ANI9

P80/ANI8

P77/ANI7

P76/ANI6

P75/ANI5

P74/ANI4

P111/A2

P112/A3

P113/A4

XT1

XT2

REGC

VSS

VDD

P94/ASTB

P40/AD0

10031

P21/SO2

P23/RXD1/SI3

P24/TXD1/SO3

EVDD

EVSS

P26/TI2/TO2

P27/TI3/TO3

P30/TI00

P31/TI01

P33/TI11/SO4

P34/TO0/A13/SCK4

P35/TO1/A14

P36/TI4/TO4/A15

P37/TI5/TO5

IC/VPPNote 1

P100/RTP0/KR0/A5

P101/RTP1/KR1/A6

P102/RTP2/KR2/A7

P103/RTP3/KR3/A8

P104/RTP4/KR4/A9

P105/RTP5/KR5/A10

P106/RTP6/KR6/A11

P71/ANI1

P70/ANI0

AVSS

AVREF

AVDD

P65/A21

P64/A20

P63/A19

P62/A18

P61/A17

P60/A16

P57/AD15

P56/AD14

P55/AD13

P54/AD12

P53/AD11

P52/AD10

P51/AD9

P50/AD8

BVSS

BVDD

P47/AD7

P46/AD6

P45/AD5

P44/AD4

P22/SCK2/SCL1Note 2

RESET

CLKOUT

P90/LBEN/WR

P91/UBEN

P92/R/W/WRH

P93/DSTB/RD

P95/HLDAK

P96/HLDRQ

P12/SCK0/SCL0Note 2

P25/ASCK1/SCK3

P32/TI10/SI4

P14/SO1/TXD0

P20/SI2/SDA1Note 2

P107/RTP7/KR7/A12

P110/WAIT/A1

P43/AD3

P42/AD2

P41/AD1

P73/ANI3

P72/ANI2P15/SCK1/ASCK0

Notes 1. IC (

PD703031A, 703031AY, 703032A, 703032AY, 703033A, 703033AY):

Connect directly to VSS.

VPP (

PD70F3032A, 70F3032AY, 70F3033A, 70F3033AY):

Connect to VSS in normal operation mode.

2. SCL0, SCL1, SDA0, and SDA1 are available only in the

PD703031AY, 703032AY, 703033AY,

70F3032AY, and 70F3033AY.

CHAPTER 1 INTRODUCTION

User’s Manual U13850EJ6V0UD

Pin names (V850/SB1 (A versions))

A1 to A21: Address bus P70 to P77: Port 7

AD0 to AD15: Address/data bus P80 to P83: Port 8

ADTRG: A/D trigger input P90 to P96: Port 9

ANI0 to ANI11: Analog input P100 to P107: Port 10

ASCK0, ASCK1: Asynchronous serial clock P110 to P113: Port 11

ASTB: Address strobe RD: Read

AVDD: Analog VDD REGC: Regulator control

AVREF: Analog reference voltage RESET: Reset

AVSS: Analog VSS RTP0 to RTP7: Real-time output port

BVDD: Power supply for bus interface RTPTRG: RTP trigger

BVSS: Ground for bus interface R/W: Read/write status

CLKOUT: Clock output RXD0, RXD1: Receive data

DSTB: Data strobe SCK0 to SCK4: Serial clock

EVDD: Power supply for port SCL0, SCL1: Serial clock

EVSS: Ground for port SDA0, SDA1: Serial data

HLDAK: Hold acknowledge SI0 to SI4: Serial input

HLDRQ: Hold request SO0 to SO4: Serial output

IC: Internally connected TI00, TI01, TI10,

INTP0 to INTP6: Interrupt request from peripherals TI11, TI2 to TI5: Timer input

KR0 to KR7:Key return TO0 to TO5: Timer output

LBEN: Lower byte enable TXD0,TXD1: Transmit data

NMI: Non-maskable interrupt request UBEN: Upper byte enable

P00 to P07: Port 0 VDD: Power supply

P10 to P15: Port 1 VPP: Programming power supply

P20 to P27: Port 2 VSS: Ground

P30 to P37: Port 3 WAIT: Wait

P40 to P47: Port 4 WRH: Write strobe high level data

P50 to P57: Port 5 WRL: Write strobe low level data

P60 to P65: Port 6 X1, X2: Crystal for main clock

XT1, XT2: Crystal for subclock

CHAPTER 1 INTRODUCTION

User’s Manual U13850EJ6V0UD 39

1.2.5 Function blocks (V850/SB1 (A versions))

(1) Internal block diagram

INTP0 to INTP6

NMI

INTC

TI2/TO2

TI3/TO3

TI4/TO4

TI5/TO5

SIO

SO0

SI0/SDA0

ote

Timer/counter

TI00,TI01,

TI10,TI11

SO1/TXD0

SI1/RXD0

SO4

SI4

CSI0/I

Note 4

CSI1/UART0

Variable

length CSI4

Watchdog

timer

Note

ROM CPU

Note

Multiplier

16 ×16→32

RAM

32-bit barrel

shifter

System

General-purpose

registers

32 bits × 32

Instruction

queue

BCU

STB

(

P94

)

A16 to A21 (P60 to P65)

AD0 to AD15

(P40 to P47, P50 to P57)

A/D

converter

RTP

Ports

CLKOUT

XT1

VDD

VSS

BVDD

BVSS

EVDD

ANI0 to ANI11

AVREF

AVSS

AVDD

ADTRG

RTP0 to RTP7

P110 to P113

P100 to P107

P70 to P77

P60 to P65

P50 to P57

P40 to P47

P30 to P37

P20 to P27

P10 to P15

P00 to P07

SCK0/SCL0

SCK1/ASCK0

SCK4 RESET

XT2

HLDAK

(

P95

)

HLDRQ

(

P96

)

WAIT

(

P110

)

UBEN

(

P91

)

ALU

16-bit timer:

TM0, TM1

8-bit timer:

TM2 to TM7

TO0,TO1

DMAC: 6 ch

Watch timer

P80 to P83

P90 to P96

EVSS

DSTB/RD

(

P93

)

R/W /WRH

(

P92

)

LBEN/WRL

(

P90

)

RTPTRG

A13 to A15 (P34 to P36)

A1 to A12

(P100 to P107,

P110 to P113

)

SO2

SI2/SDA1

CSI2/I

Note 4

SCK2/SCL1

SO3/TXD1

SI3/RXD1 CSI3/UART1

SCK3/ASCK1

Key return

KR0 to KR7

ROM

correction

VPP

Regulator

REGC

3.3 V

Notes 1.

PD703031A, 703031AY: 128 KB (mask ROM)

PD703033A, 703033AY: 256 KB (mask ROM)

PD703032A, 703032AY: 512 KB (mask ROM)

PD70F3033A, 70F3033AY: 256 KB (flash memory)

PD70F3032A, 70F3032AY: 512 KB (flash memory)

PD703031A, 703031AY: 12 KB

PD703033A, 703033AY, 70F3033A, 70F3033AY: 16 KB

PD703032A, 703032AY, 70F3032A, 70F3032AY: 24 KB

3. SDA0, SDA1, SCL0, and SCL1 pins are available only in the

PD703031AY, 703032AY, 703033AY,

70F3032AY, and 70F3033AY.

4. I2C function is available only in the

PD703031AY, 703032AY, 703033AY, 70F3032AY, and

70F3033AY.

PD70F3032A, 70F3032AY, 70F3033A, 70F3033AY

PD703031A, 703031AY, 703032A, 703032AY, 703033A, 703033AY

CHAPTER 1 INTRODUCTION

User’s Manual U13850EJ6V0UD

(2) Internal units

(a) CPU

The CPU uses five-stage pipeline control to enable single-clock execution of address calculations,

arithmetic logic operations, data transfers, and almost all other instruction processing.

Other dedicated on-chip hardware, such as the multiplier (16 bits × 16 bits → 32 bits) and the barrel

shifter (32 bits) help accelerate processing of complex instructions.

(b) Bus control unit (BCU)

The BCU starts a required external bus cycle based on the physical address obtained by the CPU.

When an instruction is fetched from external memory space and the CPU does not send a bus cycle

start request, the BCU generates a prefetch address and prefetches the instruction code. The

prefetched instruction code is stored in an instruction queue.

This consists of a mask ROM or flash memory mapped to the address space starting at 00000000H.

The ROM capacity varies depending on the product. The ROM capacity of each product is shown

below.

PD703031A, 703031AY: 128 KB (mask ROM)

PD703033A, 703033AY: 256 KB (mask ROM)

PD70F3033A, 70F3033AY: 256 KB (flash memory)

PD703032A, 703032AY: 512 KB (mask ROM)

PD70F3032A, 70F3032AY: 512 KB (flash memory)

ROM can be accessed by the CPU in one clock cycle during instruction fetch.

(d) RAM

The RAM capacity and mapping addresses vary depending on the product. The RAM capacity of each

product is shown below.

PD703031A, 703031AY: 12 KB (mapping starts at FFFFC000H)

PD703033A, 703033AY, 70F3033A, 70F3033AY: 16 KB (mapping starts at FFFFB000H)

PD703032A, 703032AY, 70F3032A, 70F3032AY: 24 KB (mapping starts at FFFF9000H)

RAM can be accessed by the CPU in one clock cycle during data access.

(e) Interrupt controller (INTC)

This controller handles hardware interrupt requests (NMI, INTP0 to INTP6) from on-chip peripheral

hardware and external hardware. Eight levels of interrupt priorities can be specified for these interrupt

requests, and multiplexed servicing control can be performed for interrupt sources.

(f) Clock generator (CG)

The clock generator includes two types of oscillators; each for main clock (fXX) and for subclock (fXT),

generates five types of clocks (fXX, fXX/2, fXX/4, fXX/8, and fXT), and supplies one of them as the operating

clock for the CPU (fCPU).

CHAPTER 1 INTRODUCTION

User’s Manual U13850EJ6V0UD 41

(g) Timer/counter

A two-channel 16-bit timer/event counter, a four-channel 8-bit timer/event counter, and a two-channel 8-

bit interval timer are equipped, enabling measurement of pulse intervals and frequency as well as

programmable pulse output.

The two-channel 8-bit timer/event counter can be connected via a cascade to enable use as a 16-bit

timer.

The two-channel 8-bit interval timer can be connected via a cascade to enable to be used as a 16-bit

timer.

(h) Watch timer

This timer counts the reference time period (0.5 seconds) for counting the clock (the 32.768 kHz

subclock or the main clock). At the same time, the watch timer can be used as an interval timer for the

main clock.

(i) Watchdog timer

A watchdog timer is equipped to detect inadvertent program loops, system abnormalities, etc.

It can also be used as an interval timer.

When used as a watchdog timer, it generates a non-maskable interrupt request (INTWDT) after an

overflow occurs. When used as an interval timer, it generates a maskable interrupt request (INTWDTM)

after an overflow occurs.

(j) Serial interface (SIO)

The V850/SB1 includes three kinds of serial interfaces: asynchronous serial interfaces (UART0,

UART1), clocked serial interfaces (CSI0 to CSI3), and an 8-/16-bit variable-length serial interface (CSI4).

These plus the I2C bus interfaces (I2C0, I2C1) comprise five channels. Two of these channels are

switchable between the UART and CSI and another two switchable between CSI and I2C.

For UART0 and UART1, data is transferred via the TXD0, TXD1, RXD0, and RXD1 pins.

For CSI0 to CSI3, data is transferred via the SO0 to SO3, SI0 to SI3, and SCK0 to SCK3 pins.

For CSI4, data is transferred via the SO4, SI4, and SCK4 pins.

For I2C0 and I2C1, data is transferred via the SDA0, SDA1, SCL0, and SCL1 pins.

I2C0 and I2C1 are equipped only in the

PD703031AY, 703032AY, 703033AY, 70F3032AY, and

70F3033AY.

For UART and CSI4, a dedicated baud rate generator is equipped.

(k) A/D converter

This high-speed, high-resolution 10-bit A/D converter includes 12 analog input pins. Conversion uses

the successive approximation method.

(l) DMA controller

A six-channel DMA controller is equipped. This controller transfers data between the internal RAM and

on-chip peripheral I/O devices in response to interrupt requests sent by on-chip peripheral I/O.

(m) Real-time output port (RTP)

The RTP is a real-time output function that transfers preset 8-bit data to an output latch when an external

trigger signal occurs or when there is a match signal in a timer compare register. It can also be used for

4-bit × 2 channels.

CHAPTER 1 INTRODUCTION

User’s Manual U13850EJ6V0UD

(n) Ports

As shown below, the following ports have general-purpose port functions and control pin functions.

Port I/O Port Function Control Function

Port 0 8-bit I/O NMI, external interrupt, A/D converter trigger, RTP trigger

Port 1 6-bit I/O Serial interface

Port 2 8-bit I/O Serial interface, timer I/O

Port 3 8-bit I/O Timer I/O, external address bus, serial interface

Port 4 8-bit I/O External address/data bus

Port 5 8-bit I/O

Port 6 6-bit I/O External address bus

Port 7 8-bit input A/D converter analog input

Port 8 4-bit input

Port 9 7-bit I/O External bus interface control signal I/O

Port 10 8-bit I/O Real-time output port, external address bus, key return input

Port 11 4-bit I/O

General-

purpose port

Wait control, external address bus

CHAPTER 1 INTRODUCTION

User’s Manual U13850EJ6V0UD 43

1.3 V850/SB1 (B Versions)

1.3.1 Features (V850/SB1 (B versions))

{Number of instructions: 74

{Minimum instruction execution time

50 ns (@ 20 MHz operation, external power supply 5 V, regulator output 3.3 V

operation)

{General-purpose registers 32 bits × 32 registers

{Instruction set Signed multiplication (16 × 16 → 32): 100 ns (@ 20 MHz operation)

(able to execute instructions in parallel continuously without creating any register

hazards).

Saturation operations (overflow and underflow detection functions are included)

32-bit shift instruction: 1 clock

Bit manipulation instructions

Load/store instructions with long/short format

{Memory space 16 MB of linear address space (for programs and data)

External expandability: expandable to 4 MB

Memory block allocation function: 2 MB per block

Programmable wait function

Idle state insertion function

{External bus interface 16-bit data bus (address/data multiplex)

Address bus: separate output enabled

3 V to 5 V interface enabled

Bus hold function

External wait function

{Internal memory

PD703031B, 703031BY (mask ROM: 128 KB/RAM: 8 KB)

PD703033B, 703033BY (mask ROM: 256 KB/RAM: 16 KB)

PD703030B, 703030BY (mask ROM: 384 KB/RAM: 24 KB)

PD703032B, 703032BY (mask ROM: 512 KB/RAM: 24 KB)

PD70F3033B, 70F3033BY (flash memory: 256 KB/RAM: 16 KB)

PD70F3030B, 70F3030BY (flash memory: 384 KB/RAM: 24 KB)

PD70F3032B, 70F3032BY (flash memory: 512 KB/RAM: 24 KB)

{Interrupts and exceptions Non-maskable interrupts: 2 sources

Maskable interrupts: 37 sources (

PD703030B, 703031B, 703032B, 703033B,

70F3030B, 70F3032B, 70F3033B)

38 sources (

PD703030BY, 703031BY, 703032BY,

703033BY, 70F3030BY, 70F3032BY, 70F3033BY)

Software exceptions: 32 sources

Exception trap: 1 source

{I/O lines Total: 83 (12 input ports and 71 I/O ports)

3 V to 5 V interface enabled

{Timer/counter 16-bit timer: 2 channels (PWM output)

8-bit timer: 6 channels (4 PWM outputs, cascade connection enabled)

{Watch timer When operating under subclock or main clock: 1 channel

Operation using the subclock or main clock is also possible in the IDLE mode.

{Watchdog timer 1 channel

CHAPTER 1 INTRODUCTION

User’s Manual U13850EJ6V0UD

{Serial interface (SIO) Asynchronous serial interface (UART)

Clocked serial interface (CSI)

I2C bus interface (I2C) (only for

PD703030BY, 703031BY, 703032BY, 703033BY,

70F3030BY, 70F3032BY, and 70F3033BY)

8-/16-bit variable-length serial interface

CSI/UART: 2 channels

CSI/I2C: 2 channels

CSI (8-/16-bit valuable): 1 channel

Dedicated baud rate generator: 3 channels

{A/D converter 10-bit resolution: 12 channels

{DMA controller Internal RAM ←→ on-chip peripheral I/O: 6 channels

{Real-time output port (RTP) 8 bits × 1 channel or 4 bits × 2 channels

{ROM correction Modifiable 4 points

{Regulator 4.0 V to 5.5 V input → internal 3.3 V

{Key return function 4 to 8 selecting enabled, falling edge fixed

{Clock generator During main clock or subclock operation

5-level CPU clock (including sub operations)

{Power-saving functions HALT/IDLE/STOP modes

{Package 100-pin plastic LQFP (fine pitch, 14 × 14)

100-pin plastic QFP (14 × 20)

{CMOS structure All static circuits

1.3.2 Application fields (V850/SB1 (B versions))

AV equipment

Example: Audio, car audio equipment, VCR, and TV.

CHAPTER 1 INTRODUCTION

User’s Manual U13850EJ6V0UD 45

1.3.3 Ordering information (V850/SB1 (B versions))

Part Number Package Internal ROM

PD703031BGC-xxx-8EU

PD703031BGF-xxx-3BA

PD703031BYGC-xxx-8EU

PD703031BYGF-xxx-3BA

PD703033BGC-xxx-8EU

PD703033BGF-xxx-3BA

PD703033BYGC-xxx-8EU

PD703033BYGF-xxx-3BA

PD703030BGC-xxx-8EU

PD703030BGF-xxx-3BA

PD703030BYGC-xxx-8EU

PD703030BYGF-xxx-3BA

PD703032BGF-xxx-3BA

PD703032BYGF-xxx-3BA

PD70F3033BGC-8EU

PD70F3033BGF-3BA

PD70F3033BYGC-8EU

PD70F3033BYGF-3BA

PD70F3030BGC-8EU

PD70F3030BGF-3BA

PD70F3030BYGC-8EU

PD70F3030BYGF-3BA

PD70F3032BGF-3BA

PD70F3032BYGF-3BA

100-pin plastic LQFP (fine pitch) (14 × 14)

100-pin plastic QFP (14 × 20)

100-pin plastic LQFP (fine pitch) (14 × 14)

100-pin plastic QFP (14 × 20)

100-pin plastic LQFP (fine pitch) (14 × 14)

100-pin plastic QFP (14 × 20)

100-pin plastic LQFP (fine pitch) (14 × 14)

100-pin plastic QFP (14 × 20)

100-pin plastic LQFP (fine pitch) (14 × 14)

100-pin plastic QFP (14 × 20)

100-pin plastic LQFP (fine pitch) (14 × 14)

100-pin plastic QFP (14 × 20)

100-pin plastic LQFP (fine pitch) (14 × 14)

100-pin plastic QFP (14 × 20)

100-pin plastic LQFP (fine pitch) (14 × 14)

100-pin plastic QFP (14 × 20)

100-pin plastic LQFP (fine pitch) (14 × 14)

100-pin plastic QFP (14 × 20)

100-pin plastic LQFP (fine pitch) (14 × 14)

100-pin plastic QFP (14 × 20)

Mask ROM (128 KB)

Mask ROM (256 KB)

Mask ROM (384 KB)

Mask ROM (512 KB)

Flash memory (256 KB)

Flash memory (384 KB)

Flash memory (512 KB)

Remarks 1. ××× indicates ROM code suffix.

2. ROMless devices are not provided.

CHAPTER 1 INTRODUCTION

User’s Manual U13850EJ6V0UD

1.3.4 Pin configuration (top view) (V850/SB1 (B versions))

100-pin plastic LQFP (fine pitch) (14 × 14)

•

PD703030BGC-xxx-8EU •

PD703033BGC-xxx-8EU •

PD70F3033BGC-8EU

•

PD703030BYGC-xxx-8EU •

PD703033BYGC-xxx-8EU •

PD70F3033BYGC-8EU

•

PD703031BGC-xxx-8EU •

PD70F3030BGC-8EU

•

PD703031BYGC-xxx-8EU •

PD70F3030BYGC-8EU

P20/SI2/SDA1

P14/SO1/TXD0

P13/SI1/RXD0

P11/SO0

P10/SI0/SDA0

P07/INTP6

P05/INTP4/ADTRG

P04/INTP3

P03/INTP2

P02/INTP1

P01/INTP0

P00/NMI

P83/ANI11

P82/ANI10

P81/ANI9

P80/ANI8

P77/ANI7

P76/ANI6

P75/ANI5

P74/ANI4

P73/ANI3

P72/ANI2

P107/RTP7/KR7/A12

P110/WAIT/A1

P111/A2

P112/A3

P113/A4

XT1

XT2

REGC

VSS

VDD

P94/ASTB

P40/AD0

P41/AD1

P42/AD2

P43/AD3

100

P21/SO2

P23/RXD1/SI3

P24/TXD1/SO3

EVDD

EVSS

P26/TI2/TO2

P27/TI3/TO3

P30/TI00

P31/TI01

P33/TI11/SO4

P34/TO0/A13/SCK4

P35/TO1/A14

P36/TI4/TO4/A15

P37/TI5/TO5

IC/VPPNote 1

P100/RTP0/KR0/A5

P101/RTP1/KR1/A6

P102/RTP2/KR2/A7

P103/RTP3/KR3/A8

P104/RTP4/KR4/A9

P105/RTP5/KR5/A10

P106/RTP6/KR6/A11

P71/ANI1

P70/ANI0

VSS

VREF

VDD

P65/A21

P64/A20

P63/A19

P62/A18

P61/A17

P60/A16

P57/AD15

P56/AD14

P55/AD13

P54/AD12

P53/AD11

P52/AD10

P51/AD9

P50/AD8

BVSS

BVDD

P47/AD7

P46/AD6

P45/AD5

P44/AD4

P22/SCK2/SCL1Note 2

RESET

CLKOUT

P90/LBEN/WRL

P91/UBEN

P92/R/W/WRH

P93/DSTB/RD

P95/HLDAK

P96/HLDRQ

P15/SCK1/ASCK0

P12/SCK0/SCL0

P25/ASCK1/SCK3

P32/TI10/SI4

P06/INTP5/RTPTRG

Notes 1. IC (

PD703030B, 703030BY, 703031B, 703031BY, 703033B, 703033BY): Connect directly to VSS.

VPP (

PD70F3030B, 70F3030BY, 70F3033B, 70F3033BY): Connect to VSS in normal operation mode.

2. SCL0, SCL1, SDA0, and SDA1 are available only in the 703030BY,

PD703031BY, 703033BY,

70F3030BY, and 70F3033BY.

CHAPTER 1 INTRODUCTION

User’s Manual U13850EJ6V0UD 47

100-pin plastic QFP (14 × 20)

•

PD703030BGF-xxx-3BA •

PD703032BGF-xxx-3BA •

PD70F3030BYGF-3BA

•

PD703030BYGF-xxx-3BA •

PD703032BYGF-xxx-3BA •

PD70F3032BGF-3BA

•

PD703031BGF-xxx-3BA •

PD703033BGF-xxx-3BA •

PD70F3032BYGF-3BA

•

PD703031BYGF-xxx-3BA •

PD703033BYGF-xxx-3BA •

PD70F3033BGF-3BA

•

PD70F3030BGF-3BA •

PD70F3033BYGF-3BA

P13/SI1/RXD0

P11/SO0

P10/SI0/SDA0Note 2

P07/INTP6

P06/INTP5/RTPTRG

P05/INTP4/ADTRG

P04/INTP3

P03/INTP2

P02/INTP1

P01/INTP0

P00/NMI

P83/ANI11

P82/ANI10

P81/ANI9

P80/ANI8

P77/ANI7

P76/ANI6

P75/ANI5

P74/ANI4

P111/A2

P112/A3

P113/A4

XT1

XT2

REGC

VSS

VDD

P94/ASTB

P40/AD0

10031

P21/SO2

P23/RXD1/SI3

P24/TXD1/SO3

EVDD

EVSS

P26/TI2/TO2

P27/TI3/TO3

P30/TI00

P31/TI01

P33/TI11/SO4

P34/TO0/A13/SCK4

P35/TO1/A14

P36/TI4/TO4/A15

P37/TI5/TO5

IC/VPPNote 1

P100/RTP0/KR0/A5

P101/RTP1/KR1/A6

P102/RTP2/KR2/A7

P103/RTP3/KR3/A8

P104/RTP4/KR4/A9

P105/RTP5/KR5/A10

P106/RTP6/KR6/A11

P71/ANI1

P70/ANI0

AVSS

AVREF

AVDD

P65/A21

P64/A20

P63/A19

P62/A18

P61/A17

P60/A16

P57/AD15

P56/AD14

P55/AD13

P54/AD12

P53/AD11

P52/AD10

P51/AD9

P50/AD8

BVSS

BVDD

P47/AD7

P46/AD6

P45/AD5

P44/AD4

P22/SCK2/SCL1Note 2

RESET

CLKOUT

P90/LBEN/WR

P91/UBEN

P92/R/W/WRH

P93/DSTB/RD

P95/HLDAK

P96/HLDRQ

P12/SCK0/SCL0Note 2

P25/ASCK1/SCK3

P32/TI10/SI4

P14/SO1/TXD0

P20/SI2/SDA1Note 2

P107/RTP7/KR7/A12

P110/WAIT/A1

P43/AD3

P42/AD2

P41/AD1

P73/ANI3

P72/ANI2P15/SCK1/ASCK0

Notes 1. IC (

PD703030B, 703030BY, 703031B, 703031BY, 703032B, 703032BY, 703033B, 703033BY):

Connect directly to VSS.

VPP (

PD70F3030B, 70F3030BY, 70F3032B, 70F3032BY, 70F3033B, 70F3033BY):

Connect to VSS in normal operation mode.

2. SCL0, SCL1, SDA0, and SDA1 are available only in the

PD703030BY, 703031BY, 703032BY,

703033BY, 70F3030BY, 70F3032BY, and 70F3033BY.

CHAPTER 1 INTRODUCTION

User’s Manual U13850EJ6V0UD

Pin names (V850/SB1 (B versions))

A1 to A21: Address bus P70 to P77: Port 7

AD0 to AD15: Address/data bus P80 to P83: Port 8

ADTRG: A/D trigger input P90 to P96: Port 9

ANI0 to ANI11: Analog input P100 to P107: Port 10

ASCK0, ASCK1: Asynchronous serial clock P110 to P113: Port 11

ASTB: Address strobe RD: Read

AVDD: Analog VDD REGC: Regulator control

AVREF: Analog reference voltage RESET: Reset

AVSS: Analog VSS RTP0 to RTP7: Real-time output port

BVDD: Power supply for bus interface RTPTRG: RTP trigger

BVSS: Ground for bus interface R/W: Read/write status

CLKOUT: Clock output RXD0, RXD1: Receive data

DSTB: Data strobe SCK0 to SCK4: Serial clock

EVDD: Power supply for port SCL0, SCL1: Serial clock

EVSS: Ground for port SDA0, SDA1: Serial data

HLDAK: Hold acknowledge SI0 to SI4: Serial input

HLDRQ: Hold request SO0 to SO4: Serial output

IC: Internally connected TI00, TI01, TI10,

INTP0 to INTP6: Interrupt request from peripherals TI11, TI2 to TI5: Timer input

KR0 to KR7:Key return TO0 to TO5: Timer output

LBEN: Lower byte enable TXD0,TXD1: Transmit data

NMI: Non-maskable interrupt request UBEN: Upper byte enable

P00 to P07: Port 0 VDD: Power supply

P10 to P15: Port 1 VPP: Programming power supply

P20 to P27: Port 2 VSS: Ground

P30 to P37: Port 3 WAIT: Wait

P40 to P47: Port 4 WRH: Write strobe high level data

P50 to P57: Port 5 WRL: Write strobe low level data

P60 to P65: Port 6 X1, X2: Crystal for main clock

XT1, XT2: Crystal for subclock

CHAPTER 1 INTRODUCTION

User’s Manual U13850EJ6V0UD 49

1.3.5 Function blocks (V850/SB1 (B versions))

(1) Internal block diagram

INTP0 to INTP6

NMI

INTC

TI2/TO2

TI3/TO3

TI4/TO4

TI5/TO5

SIO

SO0

SI0/SDA0

ote

Timer/counter

TI00,TI01,

TI10,TI11

SO1/TXD0

SI1/RXD0

SO4

SI4

CSI0/I

Note 4

CSI1/UART0

Variable

length CSI4

Watchdog

timer

Note

ROM CPU

Note

Multiplier

16 ×16→32

RAM

32-bit barrel

shifter

System

General-purpose

registers

32 bits × 32

Instruction

queue

BCU

STB

(

P94

)

A16 to A21 (P60 to P65)

AD0 to AD15

(P40 to P47, P50 to P57)

A/D

converter

RTP

Ports

CLKOUT

XT1

VDD

VSS

BVDD

BVSS

EVDD

ANI0 to ANI11

AVREF

AVSS

AVDD

ADTRG

RTP0 to RTP7

P110 to P113

P100 to P107

P70 to P77

P60 to P65

P50 to P57

P40 to P47

P30 to P37

P20 to P27

P10 to P15

P00 to P07

SCK0/SCL0

SCK1/ASCK0

SCK4 RESET

XT2

HLDAK

(

P95

)

HLDRQ

(

P96

)

WAIT

(

P110

)

UBEN

(

P91

)

ALU

16-bit timer:

TM0, TM1

8-bit timer:

TM2 to TM7

TO0,TO1

DMAC: 6 ch

Watch timer

P80 to P83

P90 to P96

EVSS

DSTB/RD

(

P93

)

R/W /WRH

(

P92

)

LBEN/WRL

(

P90

)

RTPTRG

A13 to A15 (P34 to P36)

A1 to A12

(P100 to P107,

P110 to P113

)

SO2

SI2/SDA1

CSI2/I

Note 4

SCK2/SCL1

SO3/TXD1

SI3/RXD1 CSI3/UART1

SCK3/ASCK1

Key return

KR0 to KR7

ROM

correction

VPP

Regulator

REGC

3.3 V

Notes 1.

PD703031B, 703031BY: 128 KB (mask ROM)

PD703033B, 703033BY: 256 KB (mask ROM)

PD703030B, 703030BY: 384 K (mask ROM)

PD703032B, 703032BY: 512 K (mask ROM)

PD70F3033B, 70F3033BY: 256 K (flash memory)

PD70F3030B, 70F3030BY: 384 K (flash memory)

PD70F3032B, 70F3032BY: 512 K (flash memory)

PD703031B, 703031BY: 8 KB

PD703033B, 703033BY, 70F3033B, 70F3033BY: 16 KB

PD703030B, 703030BY, 703032B, 703032BY,: 24 KB

70F3030B, 70F3030BY, 70F3032B, 70F3032BY

3. SDA0, SDA1, SCL0, and SCL1 pins are available only in the

PD703030BY, 703031BY, 703032BY,

703033BY, 70F3032BY, 70F3030BY, and 70F3033BY

4. I2C function is available only in the

PD703030BY, 703031BY, 703032BY, 703033BY, 70F3030BY,

70F3032BY, and 70F3033BY

PD70F3030B, 70F3030BY, 70F3032B, 70F3032BY, 70F3033B, 70F3033BY

PD703030B, 703030BY, 703031B, 703031BY, 703032B, 703032BY, 703033B, 703033BY

CHAPTER 1 INTRODUCTION

User’s Manual U13850EJ6V0UD

(2) Internal units

(a) CPU

The CPU uses five-stage pipeline control to enable single-clock execution of address calculations,

arithmetic logic operations, data transfers, and almost all other instruction processing.

Other dedicated on-chip hardware, such as the multiplier (16 bits × 16 bits → 32 bits) and the barrel

shifter (32 bits) help accelerate processing of complex instructions.

(b) Bus control unit (BCU)

The BCU starts a required external bus cycle based on the physical address obtained by the CPU.

When an instruction is fetched from external memory space and the CPU does not send a bus cycle

start request, the BCU generates a prefetch address and prefetches the instruction code. The

prefetched instruction code is stored in an instruction queue.

This consists of a mask ROM or flash memory mapped to the address space starting at 00000000H.

The ROM capacity varies depending on the product. The ROM capacity of each product is shown

below.

PD703031B, 703031BY: 128 KB (mask ROM)

PD703033B, 703033BY: 256 KB (mask ROM)

PD70F3033B, 70F3033BY: 256 KB (flash memory)

PD703030B, 703030BY: 384 KB (mask ROM)

PD70F3030B, 70F3030BY: 384 KB (flash memory)

PD703032B, 703032BY: 512 KB (mask ROM)

PD70F3032B, 70F3032BY: 512 KB (flash memory)

ROM can be accessed by the CPU in one clock cycle during instruction fetch.

(d) RAM

The RAM capacity and mapping addresses vary depending on the product. The RAM capacity of each

product is shown below.

PD703031B, 703031BY: 8 KB (mapping starts at FFFFD000H)

PD703033B, 703033BY, 70F3033B, 70F3033BY: 16 KB (mapping starts at FFFFB000H)

PD703030B, 703030BY, 70F3030B, 70F3030BY,

703032B, 703032BY, 70F3032B, 70F3032BY: 24 KB (mapping starts at FFFF9000H)

RAM can be accessed by the CPU in one clock cycle during data access.

(e) Interrupt controller (INTC)

This controller handles hardware interrupt requests (NMI, INTP0 to INTP6) from on-chip peripheral

hardware and external hardware. Eight levels of interrupt priorities can be specified for these interrupt

requests, and multiplexed servicing control can be performed for interrupt sources.

CHAPTER 1 INTRODUCTION

User’s Manual U13850EJ6V0UD 51