Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1
Rev.  C
05/29/2013
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
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c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
IS62WV12816DALL/DBLL
IS65WV12816DALL/DBLL
 
128K x 16 LOW VOLTAGE, 
ULTRA LOW POWER CMOS STATIC RAM               
FEATURES
• High-speed access time: 35ns, 45ns, 55ns
• CMOS low power operation
– 36 mW (typical) operating
– 9 µW (typical) CMOS standby
• TTL compatible interface levels
• Single power supply
– 1.8V ± 10% Vdd (IS62/65WV12816dALL)
– 2.5V--3.6V Vdd (IS62/65WV12816dBLL)
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial and Autotmovie temperature support
• 2CS Option Available
• Lead-free available
DESCRIPTION
The ISSI IS62/65WV12816DALL/DBLL are high-speed,
2M bit static RAMs organized as 128K words by 16
bits. It is fabricated using ISSI's high-performance
CMOS technology. This highly reliable process coupled
with innovative circuit design techniques, yields high-
performance and low power consumption devices.
When CS1 is HIGH (deselected) or when CS2 is LOW
(deselected) or when CS1 is LOW, CS2 is HIGH and both
LB and UB are HIGH, the device assumes a standby mode
at which the power dissipation can be reduced down with
CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE) controls both writing and reading of the memory. A
data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
The IS62/65WV12816DALL/DBLL are packaged in the
JEDEC standard 48-pin mini BGA (6mm x 8mm) and 44-
Pin TSOP (TYPE II).
FUNCTIONAL BLOCK DIAGRAM
JUNE 2013
A0-A16
CS1
OE
WE
128K x 16
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VDD
I/O
DATA
CIRCUIT
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
UB
LB
CS2
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL 
2 Integrated Silicon Solution, Inc. — www.issi.com
  Rev.  C
05/29/2013
PIN CONFIGURATIONS
48-Pin mini BGA (6mm x 8mm)
(Package Code B)
PIN DESCRIPTIONS
A0-A16 Address Inputs
I/O0-I/O15 Data Inputs/Outputs
CS1, CS2 Chip Enable Input
OE Output Enable Input
WE Write Enable Input
LB Lower-byte Control (I/O0-I/O7)
UB Upper-byte Control (I/O8-I/O15)
NC No Connection
Vdd Power
GND Ground
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A3
A2
A1
A0
CS1
I/O0
I/O1
I/O2
I/O3
VDD
GND
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
VDD
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
1 2 3 4 5 6
A
B
C
D
E
F
G
H
LB OE A0 A1 A2 N/C
I/O8UB A3 A4 CSI I/O0
I/O9I/O10 A5 A6 I/O1I/O2
GND I/O11 NC A7 I/O3VDD
VDD I/O12 NC A16 I/O4GND
I/O14 I/O13 A14 A15 I/O5I/O6
I/O15 NC A12 A13 WE I/O7
NC A8 A9 A10 A11 NC
48-Pin mini BGA (6mm x 8mm)
2 CS Option (Package Code B2)
44-Pin mini TSOP (Type II)
(Package Code T)
1 2 3 4 5 6
A
B
C
D
E
F
G
H
LB OE A0 A1 A2 CS2
I/O
8
UB A3 A4 CS1 I/O
0
I/O
9
I/O
10
A5 A6 I/O
1
I/O
2
GND I/O
11
NC A7 I/O
3
VDD
VDD I/O
12
NC A16 I/O
4
GND
I/O
14
I/O
13
A14 A15 I/O
5
I/O
6
I/O
15
NC A12 A13 WE I/O
7
NC A8 A9 A10 A11 NC
Integrated Silicon Solution, Inc. — www.issi.com 3
Rev.  C
05/29/2013
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL 
TRUTH TABLE
              I/O PIN
  Mode  WE CS1  CS2  OE LB UB  I/O0-I/O7  I/O8-I/O15  VDD Current 
 Not Selected X H X X X X High-Z High-Z ISB1, ISB2
X X L X X X High-Z High-Z ISB1, ISB2
X X X X H H High-Z High-Z ISB1, ISB2
Output Disabled H L H H L X High-Z High-Z Icc
H L H H X L High-Z High-Z Icc
Read H L H L L H dout High-Z Icc
H L H L H L High-Z dout
H L H L L L dout dout
Write L L H X L H dIn High-Z Icc
L L H X H L High-Z dIn
L L H X L L dIn dIn
OPERATING RANGE (VDD)
  Range  Ambient Temperature  IS62WV12816DALL IS62WV12816DBLL
 Commercial 0°C to +70°C 1.8V ± 10% 2.5V - 3.6V
 Industrial –40°C to +85°C 1.8V ± 10% 2.5V - 3.6V
IS65WV12816DALL IS65WV12816DBLL
Automotive -40°C to +125°C 1.8V ± 10% 2.5V - 3.6V
ABSOLUTE MAXIMUM RATINGS(1)
  Symbol  Parameter  Value  Unit
 Vterm Terminal Voltage with Respect to GND –0.2 to Vdd+0.3 V
tStg Storage Temperature –65 to +150 °C
Pt Power Dissipation 1.0 W
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL 
4 Integrated Silicon Solution, Inc. — www.issi.com
  Rev.  C
05/29/2013
CAPACITANCE(1)
  Symbol  Parameter  Conditions  Max.  Unit
 cIn Input Capacitance VIn = 0V 8 pF
cout Input/Output Capacitance Vout = 0V 10 pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
  Symbol  Parameter  Test Conditions  VDD  Min.  Max.  Unit
 VoH Output HIGH Voltage IoH = -0.1 mA 1.8V ± 10% 1.4 — V
IoH = -1 mA 2.5-3.6V 2.2 — V
VoL Output LOW Voltage IoL = 0.1 mA 1.8V ± 10% — 0.2 V
IoL = 1.0 mA 2.5-3.6V — 0.4 V
VIH Input HIGH Voltage 1.8V ± 10% 1.4 Vdd + 0.2 V
2.5-3.6V 2.2 Vdd + 0.3 V
VIL Input LOW Voltage 1.8V ± 10% –0.2 0.4 V
2.5-3.6V –0.2 0.6 V
ILI Input Leakage GND ≤ VIn ≤ Vdd –1 1 µA
ILo Output Leakage GND ≤ Vout ≤ Vdd, Outputs Disabled –1 1 µA
Notes:
For IS62/65WV12816DALL:
VIL (min.) = -1.0V Ac (pluse width < 10ns). Not 100% tested.
VIH (max.) = Vdd + 1.0V Ac; (pluse width < 10ns). Not 100% tested.
For IS62/65WV12816DBLL:
VIL (min.) = -2.0V Ac (pluse width < 10ns). Not 100% tested.
VIH (max.) = Vdd + 2.0V Ac; (pluse width < 10ns). Not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com 5
Rev.  C
05/29/2013
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL 
IS62/65WV12816DALL,   POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol  Parameter  Test Conditions          Max.  Unit
                55
Icc Vdd Dynamic Operating Vdd = Max., Com. 15 mA
Supply Current Iout = 0 mA, f = fmAX Ind. 20
Auto. 25
Icc1 Operating Supply Vdd = Max., Com. 3 mA
Current Iout = 0 mA, f = 0 Ind. 3
Auto. 4
ISB1 TTL Standby Current CS2 = VIL
(TTL Inputs) f = 0Hz Com. 0.3 mA
Ind. 0.3
Auto. 0.5
ISB2 CMOS Standby (1) 0V < CS2 < 0.2V Com. 4 µA
Current (CMOS Inputs) OR Ind. 6
(2) CS1 > VDD - 0.2V,
Auto. 15
cS2 > VDD - 0.2V
OR
(3)
LB
and
UB
> VDD- 0.2V
CS1
<
0.2V,
CS2
>
VDD - 0.2V,
f= 0Hz
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL 
6 Integrated Silicon Solution, Inc. — www.issi.com
  Rev.  C
05/29/2013
IS62/65WV12816DBLL,   POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol  Parameter  Test Conditions      Max  Max.  Max.    Unit
            35  45  55 
Icc Vdd Dynamic Operating Vdd = Max., Com. 22 20 18 mA
Supply Current Iout = 0 mA, f = fmAX Ind. 23 21 19
Auto. 35 30 25
typ.(2) 15 12 10
Icc1 Operating Supply Vdd = Max., Com. 3 3 3 mA
Current Iout = 0 mA, f = 0 Ind. 3 3 3
Auto. 4 4 4
ISB1 TTL Standby Current CS2 = VIL Com. 0.2 0.2 0.2 mA
(TTL Inputs) f = 0Hz Ind. 0.2 0.2 0.2
Auto. 0.3 0.3 0.3
ISB2 CMOS Standby (1) 0V < CS2 < 0.2V Com. 5 5 5 µA
Current (CMOS Inputs) OR Ind. 7 7 7
(2) CS1 > VDD - 0.2V,
Auto. 25 25 25
cS2 > VDD - 0.2V typ.(2) 2 2 2
OR
(3) LB and UB > VDD- 0.2V
           
CS1 < 0.2V,
cS2 > VDD - 0.2V
f= 0Hz
Note:
1. At f = fmAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at Vdd = 3.0V, TA = 25oC and not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com 7
Rev.  C
05/29/2013
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL 
AC TEST CONDITIONS
  Parameter  IS62/65WV12816DALL  IS62/65WV12816DBLL   
    (Unit)  (Unit)
 Input Pulse Level 0.4V to Vdd-0.2V 0.4V to Vdd-0.3V
Input Rise and Fall Times 1V/1ns 1V/1ns
Input and Output Timing Vref Vref
and Reference Level
Output Load See Figures 1 and 2 See Figures 1 and 2
AC TEST LOADS
Figure 1 Figure 2
    1.8V ± 10%   2.5V - 3.6V
 R1(Ω) 3070 3070
  R2(Ω) 3150 3150
VRef 0.9V 1.5V
Vtm 1.8V 2.8V
R1
5 pF
Including
jig and
scope
R2
OUTPUT
VTM
R1
30 pF
Including
jig and
scope
R2
OUTPUT
VTM
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL 
8 Integrated Silicon Solution, Inc. — www.issi.com
  Rev.  C
05/29/2013
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
  35 ns  45 ns  55 ns 
  Symbol  Parameter  Min.  Max.  Min.  Max.  Min.  Max.  Unit
trc Read Cycle Time 35 — 45 — 55 — ns
tAA Address Access Time — 35 — 45 — 55 ns
toHA Output Hold Time 10 — 10 — 10 — ns
tAcS1/tAcS2 CS1/CS2 Access Time — 35 — 45 — 55 ns
tdoe OE Access Time — 15 — 20 — 25 ns
tHzoe(2) OE to High-Z Output — 10 — 15 — 20 ns
tLzoe(2) OE to Low-Z Output 5 — 5 — 5 — ns
tHzcS1/tHzcS2(2) CS1/CS2 to High-Z Output 0 10 0 15 0 20 ns
tLzcS1/tLzcS2(2) CS1/CS2 to Low-Z Output 10 — 10 — 10 — ns
tBA LB, UB Access Time — 35 — 45 — 55 ns
tHzB LB, UB to High-Z Output 0 10 0 15 0 20 ns
tLzB LB, UB to Low-Z Output 0 — 0 — 0 — ns
Notes:
1. Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure 1).
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com 9
Rev.  C
05/29/2013
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL 
DATA VALID
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
DOUT
ADDRESS
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = VIL, CS2 = WE = VIH, UB or LB = VIL)
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE1/
t
ACE2
t
LZCE1/
t
LZCE2
t
HZOE
HIGH-Z DATA VALID
t
HZCS1/
t
HZCS2
ADDRESS
OE
CS1
CS2
DOUT
LB, UB
t
HZB
t
BA
t
LZB
AC WAVEFORMS
READ CYCLE NO. 2(1,3) (CS1, CS2, OE, AND UB/LB Controlled)
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CS1, UB, or LB = VIL. cS2=WE=VIH.
3. Address is valid prior to or coincident with CS1 LOW transition.
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL 
10 Integrated Silicon Solution, Inc. — www.issi.com
  Rev.  C
05/29/2013
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
  35 ns  45 ns  55 ns
  Symbol  Parameter    Min.  Max.   Min.  Max.    Min.  Max.    Unit
tWc Write Cycle Time 35 — 45 — 55 — ns
tScS1/tScS2 CS1/CS2 to Write End 25 — 35 — 45 — ns
tAW Address Setup Time to Write End 25 — 35 — 45 — ns
tHA Address Hold from Write End 0 — 0 — 0 — ns
tSA Address Setup Time 0 — 0 — 0 — ns
tPWB LB, UB Valid to End of Write 30 — 35 — 45 — ns
tPWe WE Pulse Width 30 — 35 — 40 — ns
tSd Data Setup to Write End 15 — 20 — 25 — ns
tHd Data Hold from Write End 0 — 0 — 0 — ns
tHzWe(3) WE LOW to High-Z Output — 20 — 20 — 20 ns
tLzWe(3) WE HIGH to Low-Z Output 5 — 5 — 5 — ns
Notes:
1. Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure 1).
2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in
valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are
referenced to the rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com 11
Rev.  C
05/29/2013
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL 
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CS1 Controlled, OE = HIGH or LOW)
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS1 , CS2 and WE inputs and at
least one of the LB and UB inputs being in the LOW state.
2. WRITE = (CS1) [ (LB) = (UB) ] (WE).
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL 
12 Integrated Silicon Solution, Inc. — www.issi.com
  Rev.  C
05/29/2013
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCS1
t
SCS2
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
OE
CS1
CS2
WE
LB, UB
DOUT
DIN
AC WAVEFORMS
WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)
Integrated Silicon Solution, Inc. — www.issi.com 13
Rev.  C
05/29/2013
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL 
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCS1
t
SCS2
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
OE
CS1
CS2
WE
LB, UB
DOUT
DIN
AC WAVEFORMS
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL 
14 Integrated Silicon Solution, Inc. — www.issi.com
  Rev.  C
05/29/2013
DATA UNDEFINED
t
WC
ADDRESS 1 ADDRESS 2
t
WC
HIGH-Z
t
PBW
WORD 1
LOW
WORD 2
t
HD
t
SA
t
HZWE
ADDRESS
CS1
UB, LB
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
t
PBW
DATA
IN
VALID
t
SD
t
HD
t
SA
t
HA t
HA
UB_CSWR4.eps
HIGH
CS2
AC WAVEFORMS
WRITE CYCLE NO. 4 (UB/LB Controlled)
Integrated Silicon Solution, Inc. — www.issi.com 15
Rev.  C
05/29/2013
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL 
DATA RETENTION SWITCHING CHARACTERISTICS
    Symbol  Parameter  Test Condition      Min.  Max.  Unit
Vdr Vdd for Data Retention See Data Retention Waveform 1.5 3.6 V
Idr Data Retention Current Vdd = Vdr(min), Com. — 4 µA
(1) 0V < CS2 < 0.2V, or Ind. — 6 µA
(2) CS1 ≥ Vdd – 0.2V, CS2 > Vdd - 0.2V or Auto. — 20 µA
(3) LB and UB > Vdd -0.2V, CS1 < 0.2V, CS2 > Vdd - 0.2V typ.(2) 2 µA
tSdr Data Retention Setup Time See Data Retention Waveform 0 — ns
trdr Recovery Time See Data Retention Waveform trc — ns
Note:
1. Typical values are measured at Vdd = Vdr(min), TA = 25oC and not 100% tested.
DATA RETENTION WAVEFORM (CS2 Controlled)
CS2 ≤ 0.2V
tSDR tRDR
VDR
CS2
GND
Data Retention Mode
VDD
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL 
16 Integrated Silicon Solution, Inc. — www.issi.com
  Rev.  C
05/29/2013
DATA RETENTION WAVEFORM (UBand LB Controlled)
VDD
UB and LB > VDD - 0.2V
tSDR tRDR
VDR
UB / LB
GND
Data Retention Mode
Note:
1. CS2 must satisfy either CS2 > Vcc -0.2V or CS2 < 0.2V
2. CS1 must satisfy either CS1 > Vcc -0.2V or CS1 < 0.2V
DATA RETENTION WAVEFORM (CS1Controlled)
VDD
CS1 ≥ VDD
- 0.2V
t
SDR
t
RDR
V
DR
CS1
GND
Data Retention Mode
Note:
1. CS2 must satisfy either CS2 > Vcc -0.2V or CS2 < 0.2V
Integrated Silicon Solution, Inc. — www.issi.com 17
Rev.  C
05/29/2013
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL 
ORDERING INFORMATION: IS62WV12816DALL (1.65V - 2.2V)
Industrial Range: –40°C to +85°C
  Speed (ns)  Order Part No.  Package
55 IS62WV12816DALL-55TI TSOP (Type II)
IS62WV12816DALL-55BI mini BGA (6mm x 8mm)
IS62WV12816DALL-55BLI mini BGA (6mm x 8mm), Lead-free
IS62WV12816DALL-55B2I mini BGA (6mm x 8mm), 2 CS Option
ORDERING INFORMATION: IS62WV12816DBLL (2.5V - 3.6V)
Industrial Range: –40°C to +85°C
  Speed (ns)  Order Part No.  Package
35 IS62WV12816DBLL-35TLI TSOP (Type II), Lead-free
IS62WV12816DBLL-35BLI mini BGA (6mm x 8mm), Lead-free
IS62WV12816DBLL-35B2LI mini BGA (6mm x 8mm), 2 CS Option, Lead-free
45 IS62WV12816DBLL-45TLI TSOP (Type II), Lead-free
IS62WV12816DBLL-45BLI mini BGA (6mm x 8mm), Lead-free
IS62WV12816DBLL-45B2LI mini BGA (6mm x 8mm), 2 CS Option, Lead-free
55 IS62WV12816DBLL-55TI TSOP (Type II)
IS62WV12816DBLL-55TLI TSOP (Type II), Lead-free
IS62WV12816DBLL-55BI mini BGA (6mm x 8mm)
IS62WV12816DBLL-55BLI mini BGA (6mm x 8mm), Lead-free
IS62WV12816DBLL-55B2I mini BGA (6mm x 8mm), 2 CS Option
IS62WV12816DBLL-55B2LI mini BGA (6mm x 8mm), 2 CS Option, Lead-free
ORDERING INFORMATION: IS65WV12816DBLL (2.5V - 3.6V)
Automotive Range (A3): –40°C to +125°C
  Speed (ns)  Order Part No.       Package
45 IS65WV12816DBLL-45CTLA3 TSOP (Type II), Lead-free, Copper Leadframe
IS65WV12816DBLL-45BLA3 mini BGA (6mm x 8mm), Lead-free
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL 
18 Integrated Silicon Solution, Inc. — www.issi.com
  Rev.  C
05/29/2013
2. Reference document : JEDEC MO-207
1. CONTROLLING DIMENSION : MM .
NOTE :
08/12/2008
Package Outline
Integrated Silicon Solution, Inc. — www.issi.com 19
Rev.  C
05/29/2013
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL 
2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION.
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION.
1. CONTROLLING DIMENSION : MM
NOTE :
06/04/2008
Package Outline