Enpirion(R) Power Datasheet ES1020QI Power Sequencing Controller ES1020QI Datasheet The Altera Enpirion ES1020QI is an integrated 4-channel controlled-on/controlled-off power-supply sequencer with supply monitoring, fault protection and a "sequence completed" signal (RESET). For larger systems, more than four supplies can be sequenced by simply connecting a wire between the SYSRESET pins of cascaded ICs. The ES1020QI uses a patented, micropower 7x charge pump to drive four external low-cost NFET switch gates above the supply rail by 5.3V. These ICs can be biased from 5V down to 1.5V by any supply. Features External resistors provide flexible voltage threshold programming of monitored rail voltages. Delay and sequencing are provided by external capacitors for ramp-up and ramp-down. * Glitch Immunity Additional I/O is provided for indicating and driving the RESET state in various configurations. For volume applications, other programmable options and features are available. * Enables Arbitrary Turn-on and Turn-off Sequencing of Up to Four Power Supplies (0.7V to 5V) * Operates From 1.5V to 5V Supply Voltage * Supplies VDD +5.3V of Charge Pumped Gate Drive * Adjustable Voltage Slew Rate for Each Rail * Multiple Sequencers Can be Daisy-Chained to Sequence an Infinite Number of Independent Supplies * Undervoltage Lockout for Each Supply * Low ENABLE Input * QFN Package * Pb-free (RoHS-compliant) Applications * Graphics Cards * FPGA/ASIC/Microprocessor/PowerPC Supply Sequencing * Network Routers * Telecommunications Systems VDD BIAS VDD+5V LOCK OUT Q-PUMP 1A 1A DLY_ONX 1.26V -1A 1A DLY_OFFX 10ms RISING DELAY 1.26V GATEX 30s FILTER FIGURE 1. TYPICAL ES1020QI APPLICATION UVLOX RESET LOGIC 0.633V 150ms RISING DELAY EN SYSRST FIGURE 2. ES1020QI Block Diagram 101 Innovation Drive San Jose, CA 95134 www.altera.com May 2014 (c) 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. ISO 9001:2008 Registered Altera Corporation Subscribe 10041 May 28, 2014 Rev A Page 2 Ordering Information PART NUMBER (Notes 1, 2) PART MARKING S1020 ES1020QI PACKAGE (Pb-free) TEMP. RANGE (C) -40 to +85 PKG. DWG. # 24 Ld 4x4 QFN L24.4x4 NOTES: 1. Add "T" suffix for Tape and Reel. Please refer to Packing and Marking Information: www.altera.com/support/reliability/packing/rel-packing-and-marking.html 2. These Altera Enpirion Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Altera Enpirion Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Pin Configurations RESET VDD SYSRST DLY_ON_A UVLO_A NC ES1020QI (24 LD QFN) TOP VIEW 24 23 22 21 20 19 ENABLE_1 1 GATE_A 2 DLY_OFF_C 3 18 DLY_OFF_A 17 UVLO_C 16 DLY_ON_C EPAD (GND) 15 DLY_ON_D GATE_C 6 13 DLY_OFF_B GATE_D 7 8 9 10 11 12 UVLO_B 14 UVLO_D NC 5 GND GATE_B NC 4 DLY_ON_B DLY_OFF_D ES1020QI Feature Matrix PART NAME EN/EN CMOS/ TTL ES1020QI EN CMOS GATE DRIVE OR OPEN DRAIN OUTPUTS REQUIRED CONDITIONS FOR INITIAL START-UP Gate Drive 4 UVLO 1 EN NUMBER OF NUMBER OF CHANNELS UVLO INPUTS MONITORED THAT TURN OFF WHEN ONE BY EACH UVLO FAULTS RESET 4 UVLO Enpirion Power Datasheet ES1020QI Power Sequencing Controller 10041 May 28, 2014 4 Gates PRESET OR ADJUSTABLE SEQUENCE NUMBER OF UVLO AND PAIRS OF I/O Time Adjustable On and Off 4 Monitors with 1 I/O FEATURES Auto Restart May 2014 Altera Corporation Rev A Page 3 Pin Descriptions PIN NAME May 2014 10041 PIN NUMBER ES1020QI VDD 23 DESCRIPTION Chip Bias. Bias IC from nominal 1.5V to 5V. GND 10 Bias Return. IC ground. ENABLE_1 1 Input to start on/off sequencing. Input to initiate start of programmed sequencing of supplies on or off. Enable functionality disabled for 10ms after UVLO is satisfied. RESET 24 RESET Output. RESET provides low signal 150ms after all GATEs are fully enhanced. Delay is for stabilization of output voltages. RESET asserts low upon UVLO not being satisfied or ENABLE being deasserted. RESET outputs are open-drain, Nchannel FET and are guaranteed to be in correct state for VDD down to 1V and are filtered to ignore fast transients on VDD and UVLO_X. UVLO_A 20 UVLO_B 12 Undervoltage Lockout/Monitoring Input. Provides a programmable UV lockout referenced to an internal 0.633V reference. Filtered to ignore short (<30s) transients below programmed UVLO level. UVLO_C 17 UVLO_D 14 DLY_ON_A 21 DLY_ON_B 8 DLY_ON_C 16 DLY_ON_D 15 DLY_OFF_A 18 DLY_OFF_B 13 DLY_OFF_C 3 DLY_OFF_D 4 GATE_A 2 GATE_B 5 GATE_C 6 GATE_D 7 SYSRST 22 GND EPAD NC 9, 11, 19 Gate On Delay Timer Output. Allows programming of delay and sequence for VOUT turn-on using a capacitor to ground. Each capacitor charged with 1A 10ms after turn-on initiated by ENABLE. Internal current source provides delay to associated FET GATE turn-on. Gate Off Delay Timer Output. Allows programming of delay and sequence for VOUT turn-off through ENABLE via a capacitor to ground. Each capacitor charged with 1A internal current source to an internal reference voltage, causing corresponding gate to be pulled down, thus turning off FET. FET Gate Drive Output. Drives external FETs with 1A current source to soft-start ramp into load. System Reset I/O. As an input, allows for immediate and unconditional latch-off of all GATE outputs when driven low. This input can also be used to initiate programmed sequence with `zero' wait (no 10ms stabilization delay) from input signal on this pin being driven high to first GATE. As an output, when there is a UV condition, this pin pulls low. If common to other SYSRST pins in a multiple IC configuration, it causes immediate and unconditional latch-off of all other GATEs on all other ES1020QI sequencers. Ground. Die Substrate. Can be left floating. No Connect Altera Corporation Enpirion Power Datasheet ES1020QI Power Sequencing Controller May 28, 2014 Rev A Page 4 Absolute Maximum Ratings (Note 5) Thermal Information VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD+6V UVLO, ENABLE, SYSRST. . . . . . . . . . . . . . .-0.3V to VDD + 0.3V RESET, DLY_ON, DLYOFF . . . . . . . . . . . . . .-0.3V to VDD + 0.3V Thermal Resistance (Typical) JA (C/W) JC (C/W) 24 Ld 4x4 QFN Package (Notes 3, 4) 46 8 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . +125C Maximum Storage Temperature Range . . . . . .-65C to +150C Operating Conditions VDD Supply Voltage Range . . . . . . . . . . . . . . . . . . +1.5V to +5.5V Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . -40C to +85C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. 4. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. 5. All voltages are relative to GND, unless otherwise specified. Electrical Specifications VDD = 1.5V to +5V, TA = TJ = -40C to +85C, unless otherwise specified. Boldface limits apply over the operating temperature range, -40C to +85C. PARAMETER SYMBOL TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNIT 619 633 647 mV UVLO Falling Undervoltage Lockout Threshold VUVLOvth TJ = +25C Undervoltage Lockout Threshold Tempco TCUVLOvth 40 V/C Undervoltage Lockout Hysteresis VUVLOhys 10 mV Undervoltage Lockout Threshold Range RUVLOvth Max VUVLOvth- Min VUVLOvth 7 mV Undervoltage Lockout Delay TUVLOdel ENABLE satisfied 10 ms VDD, UVLO, ENABLE glitch filter 30 s Transient Filter Duration tFIL DELAY ON/OFF Delay Charging Current Delay Charging Current Range Delay Charging Current Temperature Coefficient Delay Threshold Voltage Delay Threshold Voltage Temperature Coefficient DLY_ichg DLY_ichg_r VDLY = 0V 0.92 DLY_ichg(max) - DLY_ichg(min) 1 1.08 0.08 TC_DLY_ichg A 0.2 DLY_Vth A 1.238 1.266 nA/C 1.294 V TC_DLY_Vth 0.2 mV/C ENABLE Threshold VENh 0.5 VDD V ENABLE Hysteresis VENh -VENl Measured at VDD = 1.5V 0.2 V ENABLE Lockout Delay tdelEN_LO UVLO satisfied 10 ms ENABLE Input Capacitance Cin_en 5 pF RESET Pull-up Voltage Vpu_rst VDD V ENABLE, RESET AND SYSRST I/O RESET Pull-Down Current RESET Delay after GATE High IRSTpd1 VDD = 1.5V, RST = 0.1V 5 mA IRSTpd3 VDD = 3.3V, RST = 0.1V 13 mA IRSTpd5 VDD = 5V, RST = 0.1V 17 mA TRSTdel GATE = VDD+5V 160 ms Enpirion Power Datasheet ES1020QI Power Sequencing Controller 10041 May 28, 2014 May 2014 Altera Corporation Rev A Page 5 Electrical Specifications VDD = 1.5V to +5V, TA = TJ = -40C to +85C, unless otherwise specified. Boldface limits apply over the operating temperature range, -40C to +85C. (Continued) PARAMETER RESET Output Low SYMBOL VRSTl TEST CONDITIONS MIN (Note 6) TYP Measured at VDD = 5V with 5k pull-up resistors MAX (Note 6) UNIT 0.1 V RESET Output Capacitance COUT_RST 10 pF SYSRST Pull-Up Voltage Vpu_srst VDD V SYSRST Pull-Down Current Ipu_1.5 5 A VDD = 5V 100 A VDD = 1.5V, IOUT = 100A 150 mV 10 pF 40 ns Ipu_5 SYSRST Low Output Voltage Vol_srst SYSRST Output Capacitance Cout_srst SYSRST Low to GATE Turn-Off VDD = 1.5V tdelSYS_G GATE = 80% of VDD + 5V GATE Turn-On Current IGATEon GATE = 0V 0.8 1.1 1.4 A GATE Turn-Off Current IGATEoff_l GATE = VDD, Disabled -1.4 -1.05 -0.8 A 0.35 A GATE GATE Current Range IGATE_range GATE Turn-On/Off Current Temperature Coefficient TC_IGATE GATE Pull-Down High Current IGATEoff_h GATE High Voltage GATE Low Voltage Within IC IGATE max-min GATE = VDD, UVLO = 0V VGATEh VDD < 2V, TJ = +25C VGATEh VDD > 2V VGATEl Gate Low Voltage, VDD = 1V IVDD_5V VDD + 5V 0.2 nA/C 88 mA VDD + 4.9V V VDD + 5.3V V 0 0.1 V VDD = 5V 0.20 0.5 mA IVDD_3.3V VDD = 3.3V 0.14 mA IVDD_1.5V VDD = 1.5V 0.10 mA BIAS IC Supply Current VDD Power-on Reset VDD_POR 1 V NOTE: 6. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. May 2014 10041 Altera Corporation Enpirion Power Datasheet ES1020QI Power Sequencing Controller May 28, 2014 Rev A Page 6 Typical Performance Curves 1.04 634 633 1.03 VDD = 5V DLY CURRENT SOURCE (A) UV THRESHOLD (mV) 632 631 630 VDD = 1.5V 629 628 1.02 1.01 1.00 VDD = 1.5V 0.99 DLY_OFF/ON 627 0.98 626 -40 0.97 -40 VDD = +5V -20 0 20 40 60 80 100 -20 0 20 40 60 80 TEMPERATURE (C) TEMPERATURE (C) FIGURE 3. UVLO THRESHOLD VOLTAGE FIGURE 4. DLY CHARGE CURRENT GATE 5VOUT 3.3VOUT SYSRST 1s/DIV 2V/DIV FIGURE 5. SYSRST LOW TO OUTPUT LATCH-OFF Descriptions and Operation The ES1020QI sequencer is a 4-channel voltage sequencing controller, and is designed for use in multiple-voltage systems requiring power sequencing of various supply voltages. Individual voltage rails are gated on and off by external N-Channel MOSFETs, the gates of which are driven by an internal charge pump to VDD + 5.3V (VQP) in a user-programmed sequence. The 4-channel ES1020QI ENABLE must be asserted low, and all four voltages to be sequenced must be above their respective user-programmed undervoltage lockout (UVLO) levels before programmed output turn-on sequencing can begin. Sequencing order and delay are determined by the choice of external capacitor values on the DLY_ON and DLY_OFF pins. Once all four UVLO inputs and ENABLE are satisfied for 10ms (tdelEN_LO), the four DLY_ON capacitors are simultaneously charged with 1A current sources to the DLY_Vth level of 1.27V. As each DLY_ON pin reaches the DLY_Vth level, its associated GATE turns on, with a 1A source current to the charge pump voltage (VQP) of VDD + 5.3V. Thus, all four GATEs sequentially turn on in the user defined order. Once at DLY_Vth, the DLY_ON pins discharge so they are ready when next needed. After the entire turn-on sequence has been completed and all GATEs have reached the charge pumped voltage (VQP), a 160ms delay (TRSTdel) is started to ensure stability, after which the RESET output is released to go high. Enpirion Power Datasheet ES1020QI Power Sequencing Controller 10041 May 28, 2014 May 2014 Altera Corporation Rev A 100 Page 7 After turn-on, if any input falls below its UVLO point for longer than the glitch filter period (~30s), it is considered a fault. RESET and SYSRST are pulled low, and all GATEs are simultaneously also pulled low. In this mode, the GATEs are pulled low with 88mA. Normal shutdown mode is entered when no UVLO is violated and ENABLE is deasserted. When ENABLE is deasserted, RESET is immediately asserted and pulled low. Next, all four shutdown ramp capacitors on the DLY_OFF pins are charged with a 1A source. When any ramp-capacitor reaches DLY_Vth, a latch is set, and a current is sunk on the respective GATE pin to turn off its external MOSFET. When the GATE voltage is approximately 0.6V, the GATE is pulled down the rest of the way at a higher current level. Each individual external FET is thus turned off, which removes the voltages from the load in the user programmed sequence. Table 1 shows the nominal time delay on the DLY_X pins for various capacitor values, from the start of charging to the 1.27V reference. This table does not include the 10ms of ENABLE lockout delay during a start-up sequence, but it does represent the time from the end of the ENABLE lockout delay to the start of GATE transition. There is no ENABLE lockout delay for a sequence-off, so this table illustrates the delay to GATE transition from a disable signal. TABLE 1. NOMINAL DELAY TO SEQUENCING THRESHOLD DLY PIN CAPACITANCE TIME(s) Open 0.00006 100pF 0.00013 1000pF 0.0013 0.01F 0.013 0.1F 0.13 1F 1.3 10F 13 NOTE: Nom. TDEL_SEQ = Capacitor (F)*1.3M. May 2014 10041 Altera Corporation Enpirion Power Datasheet ES1020QI Power Sequencing Controller May 28, 2014 Rev A Page 8 Figure 6 shows the turn-on and Figure 7 shows the nominal turn-off timing diagram of the ES1020QI. Delay and flexible sequencing possibilities include multiple series, parallel, or adjustable capacitors that can be used to easily fine-tune timing over that offered by standard value capacitors. VUVLOVth <tFIL UVLO_A VUVLOVth UVLO_B VUVLOVth UVLO_C VUVLOVth UVLO_D ENABLE (ES1020QI) tUVLOdel VEN DLY_Vth DLYON_B DLY_Vth DLYON_D DLY_Vth DLYON_A DLY_Vth DLYON_C VQPUMP VQPUMP GATE_B VQPUMP GATE_D VQPUMP VQPUMP-1V GATE_C tRSTdel GATE_A RESET FIGURE 6. ES1020QI TURN-ON AND GLITCH RESPONSE TIMING DIAGRAM Enpirion Power Datasheet ES1020QI Power Sequencing Controller 10041 May 28, 2014 May 2014 Altera Corporation Rev A Page 9 l UVLO_X>VUVLOVth VEN ENABLE (ES1020QI) DLY_Vth DLYOFF_A DLY_Vth DLYOFF_B DLY_Vth DLYOFF_C DLY_Vth DLYOFF_D GATE_C GATE_D GATE_A GATE_B RESET FIGURE 7. ES1020QI TURN-OFF TIMING DIAGRAM Typical Performance Waveforms 5VOUT 5VOUT RESET ENABLE 3.3VOUT 3.3VOUT 2.5VOUT 2.5VOUT 1.5VOUT 1.5VOUT ENABLE 1V/DIV 1V/DIV 40ms/DIV FIGURE 8. ES1020QI SEQUENCED TURN-ON May 2014 10041 20ms/DIV FIGURE 9. ES1020QI SEQUENCED TURN-OFF Altera Corporation Enpirion Power Datasheet ES1020QI Power Sequencing Controller May 28, 2014 Rev A Page 10 l Application Considerations Timing Error Sources In any system there are variance contributors. For the ES1020QI, timing errors are mainly contributed by three sources. Capacitor Timing Mismatch Error Obviously, the absolute capacitor value is an error source; thus, lower-percentage tolerance capacitors help to reduce this error source. Figure 10 illustrates a difference of 0.57ms between two DLY_X outputs ramping to DLY_X threshold voltage. These 5% capacitors were from a common source. In applications where two or more GATEs or LOGIC outputs must have concurrent transitions, it is recommended that a common GATE drive be used to eliminate this timing error. FIGURE 10. CAPACITOR TIMING MISMATCH DLY_X Threshold Voltage and Charging Current Mismatch The two other error sources come from the IC itself and are found across the four DLY_X outputs. These errors are the DLY_X threshold voltage (DLY_Vth) variance when the GATE_X charging and discharging current latches are set, and the DLY_X charging current (DLY_ichg) variances to determine the time to next sequencing event. Both of these parameters are bounded by specification. Figure 11 shows that, with a common capacitor, the typical error contributed by these factors is insignificant, since both DLY_X traces overlay each other. FIGURE 11. DLY_VTH AND DLY_ICHG TIMING MISMATCH Enpirion Power Datasheet ES1020QI Power Sequencing Controller 10041 May 28, 2014 May 2014 Altera Corporation Rev A Page 11 Revision History The table lists the revision history for this document. DATE REVISION May, 2014 1.0 May 2014 10041 CHANGE Initial release. Altera Corporation Enpirion Power Datasheet ES1020QI Power Sequencing Controller May 28, 2014 Rev A Page 12 Package Outline Drawing L24.4x4 24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 10/06 4X 2.5 4.00 A 20X 0.50 B 19 PIN 1 INDEX AREA PIN #1 CORNER (C 0 . 25) 24 1 18 4.00 2 . 10 0 . 15 13 0.15 (4X) 12 7 0.10 M C A B 24X 0 . 23 +- 00 .. 07 05 24X 0 . 4 0 . 1 TOP VIEW 4 BOTTOM VIEW SEE DETAIL "X" 0.10 C C 0 . 90 0 . 1 BASE PLANE ( 3 . 8 TYP ) SEATING PLANE 0.08 C SIDE VIEW ( 2 . 10 ) ( 20X 0 . 5 ) C 0 . 2 REF 5 ( 24X 0 . 25 ) 0 . 00 MIN. 0 . 05 MAX. ( 24X 0 . 6 ) DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. Enpirion Power Datasheet ES1020QI Power Sequencing Controller 10041 May 28, 2014 May 2014 Altera Corporation Rev A