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FDMF6706B - Extra-Small, High-Performance, HighFrequency DrMOS Module Benefits Description Ultra-Compact 6x6 mm PQFN, 72% Space-Saving Compared to Conventional Discrete Solutions Fully Optimized System Efficiency The XSTM DrMOS family is Fairchild's next-generation, fully optimized, ultra-compact, integrated MOSFET plus driver power stage solution for high-current, highfrequency, synchronous buck DC-DC applications. The FDMF6706B integrates a driver IC, two power MOSFETs, and a bootstrap Schottky diode into a thermally enhanced, ultra-compact 6x6 mm PQFN package. Clean Switching Waveforms with Minimal Ringing High-Current Handling Features With an integrated approach, the complete switching power stage is optimized for driver and MOSFET dynamic performance, system inductance, and power MOSFET RDS(ON). XSTM DrMOS uses Fairchild's highperformance PowerTrench(R) MOSFET technology, which dramatically reduces switch ringing, eliminating the snubber circuit in most buck converter applications. Over 93% Peak-Efficiency Driver Output Disable Function (DISB# Pin) Internal Pull-Up and Pull-Down for SMOD# and DISB# Inputs, Respectively A new driver IC with reduced dead times and propagation delays further enhances performance. A thermal warning function warns of potential overtemperature situations. FDMF6706B also incorporates features such as Skip Mode (SMOD) for improved lightload efficiency, along with a Three-state 3.3 V PWM input for compatibility with a wide range of PWM controllers. Fairchild PowerTrench(R) Technology MOSFETs for Clean Voltage Waveforms and Reduced Ringing Applications Fairchild SyncFETTM (Integrated Schottky Diode) Technology in the Low-Side MOSFET High-Performance Gaming Motherboards Integrated Bootstrap Schottky Diode Adaptive Gate Drive Timing for Shoot-Through Protection Desktop Computers, V-Core and Non-V-Core DC-DC Converters Under-Voltage Lockout (UVLO) Workstations Networking and Telecom Microprocessor Voltage Regulators Small Form-Factor Voltage Regulator Modules High-Current Handling of 45 A High-Performance PQFN Copper-Clip Package 3-State 3.3 V PWM Input Driver Skip-Mode SMOD# (Low-Side Gate Turn Off) Input Thermal Warning Flag for Over-Temperature Condition Optimized for Switching Frequencies up to 1MHz Low-Profile SMD Package Fairchild Green Packaging and RoHS Compliance Based on the Intel(R) 4.0 DrMOS Standard Compact Blade Servers, V-Core and Non-V-Core DC-DC Converters High-Current DC-DC Point-of-Load (POL) Converters Ordering Information Part Number Current Rating FDMF6706B 45 A (c) 2011 Fairchild Semiconductor Corporation FDMF6706B * Rev. 1.0.2 Package Top Mark 40-Lead, Clipbond PQFN DrMOS, 6.0 mm x 6.0 mm Package FDMF6706B www.fairchildsemi.com FDMF6706B - Extra-Small, High-Performance, High-Frequency DrMOS Module April 2013 Typical Application Circuit Figure 1. DrMOS Block Diagram VDRV VIN BOOT UVLO VCIN Q1 HS Power MOSFET DBoot DISB# GH Logic GH Level Shift 10A 30k VCIN FDMF6706B - Extra-Small, High-Performance, High-Frequency DrMOS Module Typical Application Circuit PHASE Dead-Time RUP_PWM Input 3-State Logic PWM Control VSWH VDRV RDN_PWM GL GL Logic THWN# VCIN 30k Temp. Sense Q2 LS Power MOSFET 10A CGND Figure 2. (c) 2011 Fairchild Semiconductor Corporation FDMF6706B * Rev. 1.0.2 PGND SMOD# DrMOS Block Diagram www.fairchildsemi.com 2 Figure 3. Bottom View Figure 4. Top View Pin Definitions Pin # 1 2 Name Description When SMOD#=HIGH, the low-side driver is the inverse of PWM input. When SMOD#=LOW, SMOD# the low-side driver is disabled. This pin has a 10 A internal pull-up current source. Do not add a noise filter capacitor. VCIN IC bias supply. Minimum 1 F ceramic capacitor is recommended, from this pin to CGND. 3 VDRV Power for gate driver. Minimum 1 F ceramic capacitor is recommended connected as close as possible from this pin to CGND. 4 BOOT Bootstrap supply input. Provides voltage supply to the high-side MOSFET driver. Connect a bootstrap capacitor from this pin to PHASE. 5, 37, 41 CGND IC ground. Ground return for driver IC. 6 GH 7 FDMF6706B - Extra-Small, High-Performance, High-Frequency DrMOS Module Pin Configuration For manufacturing test only. This pin must float; must not be connected to any pin. PHASE Switch node pin for bootstrap capacitor routing. Electrically shorted to VSWH pin. 8 NC No connect. The pin is not electrically connected internally, but can be connected to VIN for convenience. 9 - 14, 42 VIN Power input. Output stage supply voltage. 15, 29 35, 43 Switch node input. Provides return for high-side bootstrapped driver and acts as a sense point VSWH for the adaptive shoot-through protection. 16 - 28 PGND 36 GL 38 THWN# 39 DISB# Output disable. When LOW, this pin disables the power MOSFET switching (GH and GL are held LOW). This pin has a 10 A internal pull-down current source. Do not add a noise filter capacitor. 40 PWM PWM signal input. This pin accepts a Three-state 3.3 V PWM signal from the controller. Power ground. Output stage ground. Source pin of the low-side MOSFET. For manufacturing test only. This pin must float; must not be connected to any pin. Thermal warning flag, open collector output. When temperature exceeds the trip limit, the output is pulled LOW. THWN# does not disable the module. (c) 2011 Fairchild Semiconductor Corporation FDMF6706B * Rev. 1.0.2 www.fairchildsemi.com 3 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Max. Unit -0.3 6.0 V VCIN Supply Voltage VDRV Drive Voltage Referenced to CGND -0.3 6.0 V VDISB# Output Disable Referenced to CGND -0.3 6.0 V VPWM VSMOD# VGL VTHWN# VIN VBOOT Referenced to CGND Min. PWM Signal Input Referenced to CGND -0.3 6.0 V Skip Mode Input Referenced to CGND -0.3 6.0 V Low Gate Manufacturing Test Pin Referenced to CGND -0.3 6.0 V Thermal Warning Flag Referenced to CGND -0.3 6.0 V Power Input Referenced to PGND, CGND -0.3 25.0 V Referenced to VSWH, PHASE -0.3 6.0 V Referenced to CGND -0.3 25.0 V Referenced to VSWH, PHASE -0.3 6.0 V Bootstrap Supply VGH High Gate Manufacturing Test Pin VPHS PHASE VSWH Switch Node Input Referenced to CGND -0.3 25.0 V Referenced to CGND -0.3 25.0 V Referenced to PGND, CGND (DC Only) -0.3 25.0 V Referenced to PGND, <20 ns -8.0 25.0 V 22 V Referenced to VDRV VBOOT Bootstrap Supply ITHWN# THWN# Sink Current IO(AV) Output Current(1) JPCB Junction-to-PCB Thermal Resistance Referenced to VDRV, <20 ns -0.1 TA Ambient Temperature Range TJ Maximum Junction Temperature TSTG Storage Temperature Range ESD Electrostatic Discharge Protection 25 V 7.0 mA fSW=300 kHz, VIN=12 V, VO=1.0 V 45 fSW=1 MHz, VIN=12 V, VO=1.0 V 40 A 3.5 C/W -40 +125 C +150 C -55 +150 C Human Body Model, JESD22-A114 2000 Charged Device Model, JESD22-C101 1000 FDMF6706B - Extra-Small, High-Performance, High-Frequency DrMOS Module Absolute Maximum Ratings V Note: 1. IO(AV) is rated using Fairchild's DrMOS evaluation board, TA = 25C, natural convection cooling. This rating is limited by the peak DrMOS temperature, TJ = 150C, and varies depending on operating conditions and PCB layout. This rating can be changed with different application settings. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VCIN VDRV VIN Parameter Control Circuit Supply Voltage Min. Typ. Max. Unit 4.5 5.0 5.5 V Gate Drive Circuit Supply Voltage 4.5 5.0 5.5 V Output Stage Supply Voltage 3.0 12.0 15.0(2) V Note: 2. Operating at high VIN can create excessive AC overshoots on the VSWH-to-GND and BOOT-to-GND nodes during MOSFET switching transients. For reliable DrMOS operation, VSWH-to-GND and BOOT-to-GND must remain at or below the Absolute Maximum Ratings shown in the table above. Refer to the "Application Information" and "PCB Layout Guidelines" sections of this datasheet for additional information. (c) 2011 Fairchild Semiconductor Corporation FDMF6706B * Rev. 1.0.2 www.fairchildsemi.com 4 Typical values are VIN = 12 V, VCIN = 5 V, VDRV = 5 V, and TA = +25C unless otherwise noted. Symbol Parameter Condition Min. Typ. Max. Unit Basic Operation Quiescent Current IQ=IVCIN+IVDRV, PWM=LOW or HIGH or Float UVLO IQ UVLO Threshold VCIN Rising UVLO_Hyst UVLO Hysteresis 2.9 3.1 2 mA 3.3 V 0.4 V PWM Input (VCIN = VDRV = 5 V 10%) RUP_PWM Pull-Up Impedance 26 k RDN_PWM Pull-Down Impedance 12 k VIH_PWM PWM High Level Voltage 1.88 2.25 2.61 V VTRI_HI 3-State Upper Threshold 1.84 2.20 2.56 V VTRI_LO 3-State Lower Threshold 0.70 0.95 1.19 V VIL_PWM PWM Low Level Voltage 0.62 0.85 1.13 V 160 200 ns 1.60 1.90 V tD_HOLD-OFF 3-State Shut-off Time VHiZ_PWM 3-State Open Voltage 1.40 PWM Input (VCIN = VDRV = 5 V 5%) RUP_PWM Pull-Up Impedance 26 k RDN_PWM Pull-Down Impedance 12 k VIH_PWM PWM High Level Voltage 2.00 2.25 2.50 V VTRI_HI 3-State Upper Threshold 1.94 2.20 2.46 V VTRI_LO 3-State Lower Threshold 0.75 0.95 1.15 V VIL_PWM PWM Low Level Voltage 0.66 0.85 1.09 V 160 200 ns 1.45 1.60 1.80 V tD_HOLD-OFF 3-State Shut-off Time VHiZ_PWM 3-State Open Voltage DISB# Input VIH_DISB High-Level Input Voltage VIL_DISB Low-Level Input Voltage IPLD 2 V 0.8 Pull-Down Current tPD_DISBL Propagation Delay PWM=GND, Delay Between DISB# from HIGH to LOW to GL from HIGH to LOW tPD_DISBH Propagation Delay PWM=GND, Delay Between DISB# from LOW to HIGH to GL from LOW to HIGH V 10 A 25 ns 25 ns FDMF6706B - Extra-Small, High-Performance, High-Frequency DrMOS Module Electrical Characteristics SMOD# Input VIH_SMOD VIL_SMOD IPLU High-Level Input Voltage 2 V Low-Level Input Voltage 0.8 Pull-Up Current V 10 A tPD_SLGLL Propagation Delay PWM=GND, Delay Between SMOD# from HIGH to LOW to GL from HIGH to LOW 10 ns tPD_SHGLH Propagation Delay PWM=GND, Delay Between SMOD# from LOW to HIGH to GL from LOW to HIGH 10 ns Continued on the following page... (c) 2011 Fairchild Semiconductor Corporation FDMF6706B * Rev. 1.0.2 www.fairchildsemi.com 5 Typical values are VIN = 12 V, VCIN = 5 V, VDRV = 5 V, and TA = +25C unless otherwise noted. Symbol Parameter Condition Min. Typ. Max. Unit Thermal Warning Flag TACT Activation Temperature 150 C TRST Reset Temperature 135 C IPLD=5 mA 30 SW=0 V, Delay Between GH from HIGH to LOW and GL from LOW to HIGH 250 ns 1 RTHWN Pull-Down Resistance 250ns Timeout Circuit tD_TIMEOUT Timeout Delay High-Side Driver RSOURCE_GH Output Impedance, Sourcing Source Current=100 mA RSINK_GH Output Impedance, Sinking Sink Current=100 mA 0.8 tR_GH Rise Time GH=10% to 90%, CLOAD=1.1 nF 6 ns tF_GH Fall Time GH=90% to 10%, CLOAD=1.1 nF 5 ns tD_DEADON LS to HS Deadband Time GL going LOW to GH going HIGH, 1 V GL to 10 % GH 10 ns tPD_PLGHL PWM LOW Propagation Delay PWM going LOW to GH going LOW, VIL_PWM to 90% GH 16 tPD_PHGHH PWM HIGH Propagation Delay (SMOD# Held LOW) PWM going HIGH to GH going HIGH, VIH_PWM to 10% GH (SMOD#=LOW) 30 ns tPD_TSGHH Exiting 3-State Propagation Delay PWM (From 3-State) going HIGH to GH going HIGH, VIH_PWM to 10% GH 30 ns 30 ns Low-Side Driver RSOURCE_GL Output Impedance, Sourcing Source Current=100 mA 1 Output Impedance, Sinking Sink Current=100 mA 0.5 tR_GL Rise Time GL=10% to 90%, CLOAD=4.5 nF 14 ns tF_GL Fall Time GL=90% to 10%, CLOAD=4.5 nF 10 ns SW going LOW to GL going HIGH, 2.2 V SW to 10% GL 12 ns RSINK_GL tD_DEADOFF HS to LS Deadband Time tPD_PHGLL PWM-HIGH Propagation Delay PWM going HIGH to GL going LOW, VIH_PWM to 90% GL 9 tPD_TSGLH Exiting 3-State Propagation Delay PWM (From 3-State) going LOW to GL going HIGH, VIL_PWM to 10% GL 20 ns VF Forward-Voltage Drop IF=10 mA 0.35 V VR Breakdown Voltage IR=1 mA 25 FDMF6706B - Extra-Small, High-Performance, High-Frequency DrMOS Module Electrical Characteristics ns Boot Diode (c) 2011 Fairchild Semiconductor Corporation FDMF6706B * Rev. 1.0.2 22 V www.fairchildsemi.com 6 V IL_PWM PWM 90% GL 1.0V 10% 90% GH to VSWH 10% 1.2V t D_TIMEOUT (250ns Timeout) 2.2V VSWH t PD t PD PHGLL PLGHL tD_DEADOFF t D_DEADON Figure 5. (c) 2011 Fairchild Semiconductor Corporation FDMF6706B * Rev. 1.0.2 PWM Timing Diagram FDMF6706B - Extra-Small, High-Performance, High-Frequency DrMOS Module V IH_PWM www.fairchildsemi.com 7 50 10 45 9 300kHz 8 500kHz Module Power Loss (W) Module Output current, IOUT (A) Test Conditions: VIN=12 V, VOUT=1.0 V, VCIN=5 V, VDRV=5 V, LOUT=320 nH, TA=25C, and natural convection cooling, unless otherwise specified. 40 fSW = 300kHz 35 30 fSW = 1MHz 25 20 15 10 VIN = 12V, VOUT = 1.0V JPCB = 3.5C/W 5 800kHz 7 1MHz 6 5 4 3 2 1 0 0 0 25 50 75 100 125 0 150 5 10 Figure 6. Safe Operating Area Figure 7. 20 25 30 35 40 Module Power Loss vs. Output Current 1.20 1.5 VIN = 12V, IOUT = 30A, fSW = 300kHz Normalized Module Power Loss Normalized Module Power Loss 15 Output Current, IOUT (A) PCB Temperature (C) 1.4 1.3 1.2 1.1 1 0.9 200 300 400 500 600 700 800 900 IOUT = 30A, fSW = 300kHz 1.15 1.10 1.05 1.00 0.95 1000 5 6 7 Module Switching Frequency, fSW (kHz) Figure 8. Power Loss vs. Switching Frequency Figure 9. Normalized Module Power Loss 1.10 1.05 1.00 0.95 10 11 12 13 14 15 Power Loss vs. Input Voltage VIN = 12V, IOUT = 30A, fSW = 300kHz 1.7 1.5 1.3 1.1 0.9 4.75 5.00 5.25 5.50 0.5 1.0 Driver Supply Voltage, VDRV and VCIN (V) Figure 10. 9 1.9 VIN = 12V, IOUT = 30A, fSW = 300kHz 0.90 4.50 8 Module Input Voltage, VIN (V) 1.15 Normalized Module Power Loss VIN = 12V, VOUT = 1V FDMF6706B - Extra-Small, High-Performance, High-Frequency DrMOS Module Typical Performance Characteristics Power Loss vs. Driver Supply Voltage (c) 2011 Fairchild Semiconductor Corporation FDMF6706B * Rev. 1.0.2 1.5 2.0 2.5 3.0 3.5 Output Voltage, VOUT (V) Figure 11. Power Loss vs. Output Voltage www.fairchildsemi.com 8 Test Conditions: VIN=12 V, VOUT=1.0 V, VCIN=5 V, VDRV=5 V, LOUT=320 nH, TA=25C, and natural convection cooling, unless otherwise specified. Driver Supply Current, IVDRV + IVCIN (mA) 1.05 Normalized Module Power Loss VIN = 12V, IOUT = 30A, fSW = 300kHz 1.04 1.03 1.02 1.01 1.00 0.99 0.98 225 275 325 375 42 VIN = 12V, IOUT = 0A, fSW = 300kHz 38 34 30 26 22 18 14 10 6 200 425 400 Power Loss vs. Output Inductance Figure 13. 15 VIN = 12V, IOUT = 0A, fSW = 300kHz 14 13 12 11 4.50 4.75 Figure 14. 5.00 5.25 300kHz 1.08 1MHz 1.06 1.04 1.02 1.00 0.98 0.96 5.50 0 5 10 Driver Supply Current vs. Driver Supply Voltage Figure 15. 20 25 30 35 40 Driver Supply Current vs. Output Current 3.0 TA = 25C VCIN = 5V PWM Threshold Voltage (V) PWM Threshold Voltage (V) 15 Module Output Current, IOUT (A) 3.0 VIH_PWM 2.0 VTRI_HI VHiZ_PWM 1.5 VTRI_LO 1.0 VIL_PWM 0.5 0.0 4.50 1000 Driver Supply Current vs. Frequency Driver Supply Voltage, VDRV & VCIN (V) 2.5 800 1.10 Normalized Driver Supply Current Driver Supply Current, IVDRV + IVCIN (mA) Figure 12. 600 Module Switching Frequency, fSW (kHz) Output Inductance, LOUT (nH) FDMF6706B - Extra-Small, High-Performance, High-Frequency DrMOS Module Typical Performance Characteristics (Continued) 2.5 VIH_PWM 2.0 VTRI_HI 1.5 VTRI_LO 1.0 VIL_PWM 0.5 0.0 4.75 5.00 5.25 5.50 -50 -25 Driver Supply Voltage, VCIN (V) Figure 16. PWM Thresholds vs. Driver Supply Voltage (c) 2011 Fairchild Semiconductor Corporation FDMF6706B * Rev. 1.0.2 0 25 50 75 100 125 150 Driver IC Junction Temperature, TJ (oC) Figure 17. PWM Thresholds vs. Temperature www.fairchildsemi.com 9 Test Conditions: VIN=12 V, VOUT=1.0 V, VCIN=5 V, VDRV=5 V, LOUT=320 nH, TA=25C, and natural convection cooling, unless otherwise specified. 2.2 2.0 VCIN = 5V 1.9 SMOD Threshold Voltage (V) SMOD# Threshold Voltage (V) TA = 25C 2.0 VIH_SMOD 1.8 1.6 VIL_SMOD 1.4 1.8 VIH_SMOD 1.7 1.6 VIL_SMOD 1.5 1.4 1.3 1.2 4.50 4.75 5.00 5.25 -50 5.50 -25 0 Figure 18. SMOD# Thresholds vs. Driver Supply Voltage Figure 19. 75 100 125 150 SMOD# Thresholds vs. Temperature VCIN = 5V DISB Threshold Voltage (V) SMOD# Pull-up Current, IPLU (uA) VCIN = 5V -9.5 -10.0 -10.5 -11.0 -11.5 -12.0 1.90 1.80 VIH_DISB 1.70 1.60 VIL_DISB 1.50 1.40 -50 -25 0 25 50 75 100 125 150 -50 Driver IC Junction Temperature, TJ (oC) Figure 20. -25 0 25 50 75 100 125 150 Driver IC Junction Temperature, TJ (C) SMOD# Pull-Up Current vs. Temperature Figure 21. 2.1 Disable Thresholds vs. Driver Supply Voltage 12.0 TA = 25oC DISB# Pull-down Current, IPLD (uA) DISB# Threshold Voltage (V) 50 2.00 -9.0 2.0 25 Driver IC Junction Temperature (oC) Driver Supply Voltage, VCIN (V) FDMF6706B - Extra-Small, High-Performance, High-Frequency DrMOS Module Typical Performance Characteristics (Continued) VIH_DISB 1.9 1.8 1.7 VIL_DISB 1.6 1.5 1.4 1.3 4.50 4.75 5.00 5.25 5.50 VCIN = 5V 11.5 11.0 10.5 10.0 9.5 9.0 8.5 8.0 -50 -25 Figure 22. Disable Thresholds vs. Temperature (c) 2011 Fairchild Semiconductor Corporation FDMF6706B * Rev. 1.0.2 0 25 50 75 100 125 150 Driver IC Junction Temperature (oC) Driver Supply Voltage, VCIN (V) Figure 23. Disable Pull-Down Current vs. Temperature www.fairchildsemi.com 10 The FDMF6706B is a driver-plus-FET module optimized for the synchronous buck converter topology. A single PWM input signal is all that is required to properly drive the high-side and the low-side MOSFETs. Each part is capable of driving speeds up to 1 MHz. Three-State PWM Input The FDMF6706B incorporates a three-state 3.3 V PWM input gate drive design. The Three-state gate drive has both logic HIGH level and LOW level, along with a 3state shutdown window. When the PWM input signal enters and remains within the three-state window for a defined hold-off time (tD_HOLD-OFF), both GL and GH are pulled LOW. This feature enables the gate drive to shut down both high-and low-side MOSFETs to support features such as phase shedding, a common feature on multi-phase voltage regulators. VCIN and Disable (DISB#) The VCIN pin is monitored by an Under-Voltage Lockout (UVLO) circuit. When VCIN rises above ~3.1 V, the driver is enabled. When VCIN falls below ~2.7 V, the driver is disabled (GH, GL=0). The driver can also be disabled by pulling the DISB# pin LOW (DISB# < VIL_DISB), which holds both GL and GH LOW regardless of the PWM input state. The driver can be enabled by raising the DISB# pin voltage HIGH (DISB# > VIH_DISB). Table 1. Exiting Three-State Condition When exiting a valid three-state condition, the FDMF6706B design follows the PWM input command. If the PWM input goes from three-state to LOW, the lowside MOSFET is turned on. If the PWM input goes from 3-state to HIGH, the high-side MOSFET is turned on, as illustrated in Figure 25. The FDMF6706B design allows for short propagation delays when exiting the three-state window (see Electrical Characteristics). UVLO and Disable Logic UVLO DISB# Driver State 0 X Disabled (GH, GL=0) 1 0 Disabled (GH, GL=0) 1 1 Enabled (See Table 2) 1 Open Disabled (GH, GL=0) Low-Side Driver The low-side driver (GL) is designed to drive a groundreferenced low RDS(ON) N-channel MOSFET. The bias for GL is internally connected between VDRV and CGND. When the driver is enabled, the driver's output is 180 out of phase with the PWM input. When the driver is disabled (DISB#=0 V), GL is held LOW. Note: 3. DISB# internal pull-down current source is 10 A. Thermal Warning Flag (THWN#) The FDMF6706B provides a thermal warning flag (THWN#) to advise of over-temperature conditions. The thermal warning flag uses an open-drain output that pulls to CGND when the activation temperature (150C) is reached. The THWN# output returns to highimpedance state once the temperature falls to the reset temperature (135C). The THWN# output requires a pull-up resistor, which can be connected to VCIN. THWN# does NOT disable the DrMOS module. HIGH THWN# Logic State High-Side Driver The high-side driver is designed to drive a floating Nchannel MOSFET. The bias voltage for the high-side driver is developed by a bootstrap supply circuit consisting of the internal Schottky diode and external bootstrap capacitor (CBOOT). During startup, VSWH is held at PGND, allowing CBOOT to charge to VDRV through the internal diode. When the PWM input goes HIGH, GH begins to charge the gate of the high-side MOSFET (Q1). During this transition, the charge is removed from CBOOT and delivered to the gate of Q1. As Q1 turns on, VSWH rises to VIN, forcing the BOOT pin to VIN + VBOOT, which provides sufficient VGS enhancement for Q1. To complete the switching cycle, Q1 is turned off by pulling GH to VSWH. CBOOT is then recharged to VDRV when VSWH falls to PGND. GH output is in-phase with the PWM input. The high-side gate is held LOW when the driver is disabled or the PWM signal is held within the three-state window for longer than the three-state hold-off time, tD_HOLD-OFF. 135C Reset 150C Temperature Activation Temperature Normal Operation Thermal Warning LOW TJ_driver IC Figure 24. FDMF6706B - Extra-Small, High-Performance, High-Frequency DrMOS Module Functional Description THWN Operation (c) 2011 Fairchild Semiconductor Corporation FDMF6706B * Rev. 1.0.2 www.fairchildsemi.com 11 The driver IC design ensures minimum MOSFET dead time, while eliminating potential shoot-through (crossconduction) currents. It senses the state of the MOSFETs and adjusts the gate drive adaptively to prevent simultaneous conduction. Figure 25 provides the relevant timing waveforms. To prevent overlap during the LOW-toHIGH switching transition (Q2 off to Q1 on), the adaptive circuitry monitors the voltage at the GL pin. When the PWM signal goes HIGH, Q2 turns off after a propagation delay (tPD_PHGLL). Once the GL pin is discharged below ~1 V, Q1 turns on after adaptive delay, tD_DEADON. V IH_PWM To prevent overlap during the HIGH-to-LOW transition (Q1 off to Q2 on), the adaptive circuitry monitors the voltage at the VSWH pin. When the PWM signal goes LOW, Q1 turns off after a propagation delay (tPD_PLGHL). Once the VSWH pin falls below ~2.2 V, Q2 turns on after adaptive delay tD_DEADOFF. Additionally, VGS(Q1) is monitored. When VGS(Q1) is discharged below ~1.2 V, a secondary adaptive delay is initiated that results in Q2 being driven on after tD_TIMEOUT, regardless of VSWH state. This function ensures CBOOT is recharged each switching cycle in the event that the VSWH voltage does not fall below the 2.2 V adaptive threshold. Secondary delay, tD_TIMEOUT is longer than tD_DEADOFF. V IH_PWM V IH_PWM V IH PWM V TRI_HI V TRI_HI V TRI_LO V IL_PWM V IL_PWM tR_GH PWM less than t D_HOLD - OFF GH to VSWH tF_GH 90% tD_HOLD -OFF 10% V IN CCM DCM DCM V OUT 2.2V VSWH GL 90% 90% 1.0V tPD_PHGLL tD_DEADON 10% 10% tPD_PLGHL tR_GL tD_DEADOFF tF_GL Enter 3-State tPD_TSGHH tD_HOLD -OFF Enter 3 -State Exit 3-State tPD_TSGHH Exit 3 State less than t D_HOLD - OFF tD_HOLD-OFF tPD_TSGLH Enter 3 -State FDMF6706B - Extra-Small, High-Performance, High-Frequency DrMOS Module Adaptive Gate Drive Circuit Exit 3-State Notes: Example (tPD_PHGLL - PWM going HIGH to LS VGS (GL) going LOW) tPD_xxx = propagation delay from external signal (PWM, SMOD#, etc.) to IC generated signal. tD_xxx = delay from IC generated signal to IC generated signal. Example (tD_DEADON - LS VGS (GL) LOW to HS VGS (GH) HIGH) PWM tPD_PHGLL = PWM rise to LS VGS fall, VIH_PWM to 90% LS VGS tPD_PLGHL = PWM fall to HS VGS fall, VIL_PWM to 90% HS VGS tPD_PHGHH = PWM rise to HS VGS rise, VIH_PWM to 10% HS VGS (SMOD# held LOW) Exiting 3-state tPD_TSGHH = PWM 3-state to HIGH to HS VGS rise, VIH_PWM to 10% HS VGS tPD_TSGLH = PWM 3-state to LOW to LS VGS rise, VIL_PWM to 10% LS VGS SMOD# tPD_SLGLL = SMOD# fall to LS VGS fall, VIL_SMOD to 90% LS VGS tPD_SHGLH = SMOD# rise to LS VGS rise, VIH_SMOD to 10% LS VGS Dead Times tD_DEADON = LS VGS fall to HS VGS rise, LS-comp trip value (~1.0V GL) to 10% HS VGS tD_DEADOFF = VSWH fall to LS VGS rise, SW-comp trip value (~2.2V VSWH) to 10% LS VGS Figure 25. (c) 2011 Fairchild Semiconductor Corporation FDMF6706B * Rev. 1.0.2 PWM and 3-StateTiming Diagram www.fairchildsemi.com 12 The SMOD function allows higher converter efficiency under light-load conditions. During SMOD, the low-side FET gate signal is disabled (held LOW), preventing discharging of the output capacitors as the filter inductor current attempts reverse current flow - also known as Diode Emulation Mode. Table 2. When the SMOD# pin is pulled HIGH, the synchronous buck converter will work in Synchronous Mode. This mode allows for gating on the low-side FET. When the SMOD# pin is pulled LOW, the low-side FET is gated off. If the SMOD# pin is connected to the PWM controller, the controller can actively enable or disable SMOD when the controller detects light-load condition from output current sensing. This pin is active LOW. See Figure 26 for timing delays. SMOD Logic DISB# PWM SMOD# GH GL 0 X X 0 0 1 3-State X 0 0 1 0 0 0 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 0 Note: 4. The SMOD feature is intended to have low propagation delay between the SMOD signal and the low-side FET VGS response time to control diode emulation on a cycle-by-cycle basis. SMOD# V IH_SMOD V IL_SMOD V IH_PWM V IH_PWM V IL_PWM PWM 90% GH to VSWH 10% 10% DCM V OUT CCM CCM 2.2V VSWH GL 90% 1.0V tPD_PHGLL tD_DEADON 10% FDMF6706B - Extra-Small, High-Performance, High-Frequency DrMOS Module Skip Mode (SMOD) 10% tPD_PLGHL tPD_PHGHH tPD_SLGLL tD_DEADOFF Delay from SMOD# going LOW to LS VGS LOW tPD_SHGLH Delay from SMOD# going HIGH to LS V GS HIGH HS turn -on with SMOD# LOW Figure 26. (c) 2011 Fairchild Semiconductor Corporation FDMF6706B * Rev. 1.0.2 SMOD Timing Diagram www.fairchildsemi.com 13 Supply Capacitor Selection VCIN Filter For the supply inputs (VDRV & VCIN), a local ceramic bypass capacitor is required to reduce noise and to supply peak transient currents during gate drive switching action. It is recommended to use a minimum capacitor value of 1 F X7R or X5R. Keep this capacitor close to the VCIN and VDRV pins and connect it to the GND plane with vias. The VDRV pin provides power to the gate drive of the high-side and low-side power MOSFETs. In most cases, VDRV can be connected directly to VCIN, which supplies power to the logic circuitry of the gate driver. For additional noise immunity, an RC filter can be inserted between VDRV and VCIN. Recommended values of 10 (RVCIN) placed between VDRV and VCIN and 1 F (CVCIN) from VCIN to CGND, Figure 27. Bootstrap Circuit Power Loss and Efficiency The bootstrap circuit uses a charge storage capacitor (CBOOT), as shown in Figure 28. A capacitance of 100 nF X7R or X5R capacitor is typically adequate. A series bootstrap resistor may be needed for specific applications to improve switching noise immunity. The boot resistor (RBOOT) may be required when operating near the maximum rated VIN and is effective at controlling the high-side MOSFET turn-on slew rate and VSHW overshoot. Typical RBOOT values from 0.5 to 2.0 W are effective in reducing VSWH overshoot. A I5V R VCIN C VDRV VDRV DISB DISB# PWM Input PWM A CVCIN VCIN C VIN OpenDrain Output VIN I IN RBOOT BOOT FDMF6706B CBOOT IOUT VSWH SMOD# CGND A LOUT PHASE VOUT COUT THWN# Figure 28. (c) 2011 Fairchild Semiconductor Corporation FDMF6706B * Rev. 1.0.2 (1) (2) (3) (4) (5) (6) (7) VIN OFF ON PIN=(VIN x IIN) + (V5V x I5V) (W) PSW=VSW x IOUT (W) POUT=VOUT x IOUT (W) PLOSS_MODULE=PIN - PSW (W) PLOSS_BOARD=PIN - POUT (W) EFFMODULE=100 x PSW/PIN (%) EFFBOARD=100 x POUT/PIN (%) Block Diagram With VCIN Filter Figure 27. V5V Measurement and Calculation Refer to Figure 28 for power loss testing method. Power loss calculations are: FDMF6706B - Extra-Small, High-Performance, High-Frequency DrMOS Module Application Information V VSW PGND Power Loss Measurement www.fairchildsemi.com 14 boot capacitor (CBOOT) and DrMOS BOOT pin. The BOOT-to-VSWH loop size, including RBOOT and CBOOT, should be as small as possible. The boot resistor may be required when operating near the maximum rated VIN. The boot resistor is effective at controlling the high-side MOSFET turn-on slew rate and VSHW overshoot. RBOOT can improve noise operating margin in synchronous buck designs that may have noise issues due to ground bounce or high positive and negative VSWH ringing. However, inserting a boot resistance lowers the DrMOS efficiency. Efficiency versus noise trade-offs must be considered. RBOOT values from 0.5 to 2.0 are typically effective in reducing VSWH overshoot. Figure 29 provides an example of a proper layout for the FDMF6706B and critical components. All of the highcurrent paths, such as VIN, VSWH, VOUT, and GND copper, should be short and wide for low inductance and resistance. This technique achieves a more stable and evenly distributed current flow, along with enhanced heat radiation and system performance. The following guidelines are recommendations for the PCB designer: 1. Input ceramic bypass capacitors must be placed close to the VIN and PGND pins. This helps reduce the high-current power loop inductance and the input current ripple induced by the power MOSFET switching operation. 2. The VSWH copper trace serves two purposes. In addition to being the high-frequency current path from the DrMOS package to the output inductor, it also serves as a heat sink for the low-side MOSFET in the DrMOS package. The trace should be short and wide enough to present a low-impedance path for the high-frequency, high-current flow between the DrMOS and inductor to minimize losses and temperature rise. Note that the VSWH node is a high-voltage and high-frequency switching node with high noise potential. Care should be taken to minimize coupling to adjacent traces. Since this copper trace also acts as a heat sink for the lower FET, balance using the largest area possible to improve DrMOS cooling while maintaining acceptable noise emission. The VIN and PGND pins handle large current transients with frequency components >100 MHz. If possible, these pins should be connected directly to the VIN and board GND planes. The use of thermal relief traces in series with these pins is discouraged since this adds inductance to the power path. This added inductance in series with either the VIN or PGND pin degrades system noise immunity by increasing positive and negative VSWH ringing. 8. GND pad and PGND pins should be connected to the GND plane copper with multiple vias for stable grounding. Poor grounding can create a noise transient offset voltage level between CGND and PGND. This could lead to faulty operation of the gate driver and MOSFETs. 9. Ringing at the BOOT pin is most effectively controlled by close placement of the boot capacitor. Do not add an additional BOOT to the PGND capacitor. This may lead to excess current flow through the BOOT diode. 3. An output inductor should be located close to the FDMF6706B to minimize the power loss due to the VSWH copper trace. Care should also be taken so the inductor dissipation does not heat the DrMOS. 10. The SMOD# and DISB# pins have weak internal pull-up and pull-down current sources, respectively. These pins should not have any noise filter capacitors. Do not to float these pins unless absolutely necessary. (R) 4. PowerTrench MOSFETs are used in the output stage. The power MOSFETs are effective at minimizing ringing due to fast switching. In most cases, no VSWH snubber is required. If a snubber is used, it should be placed close to the VSWH and PGND pins. The resistor and capacitor need to be of proper size for the power dissipation. 11. Use multiple vias on each copper area to interconnect top, inner, and bottom layers to help distribute current flow and heat conduction. Vias should be relatively large and of reasonably low inductance. Critical high-frequency components, such as RBOOT, CBOOT, the RC snubber, and bypass capacitors should be located as close to the respective DrMOS module pins as possible on the top layer of the PCB. If this is not feasible, they should be connected from the backside through a network of low-inductance vias. 5. VCIN, VDRV, and BOOT capacitors should be placed as close as possible to the VCIN to CGND, VDRV to CGND, and BOOT to PHASE pins to ensure clean and stable power. Routing width and length should be considered. 6. Include a trace from PHASE to VSWH to improve noise margin. Keep the trace as short as possible. 7. The layout should include a place holder to insert a small-value series boot resistor (RBOOT) between the (c) 2011 Fairchild Semiconductor Corporation FDMF6706B * Rev. 1.0.2 FDMF6706B - Extra-Small, High-Performance, High-Frequency DrMOS Module PCB Layout Guidelines www.fairchildsemi.com 15 Bottom View Figure 29. (c) 2011 Fairchild Semiconductor Corporation FDMF6706B * Rev. 1.0.2 PCB Layout Example FDMF6706B - Extra-Small, High-Performance, High-Frequency DrMOS Module Top View www.fairchildsemi.com 16 FDMF6706B - Extra-Small, High-Performance, High-Frequency DrMOS Module Physical Dimensions B 0.10 C PIN#1 INDICATOR 6.00 2X 5.80 A 4.50 30 21 31 6.00 20 0.40 2.50 0.65 0.25 1.60 0.10 C 11 40 2X 1 SEE 0.60 DETAIL 'A' 0.50 TYP TOP VIEW 10 0.35 0.15 2.10 0.40 21 FRONT VIEW 4.400.10 (2.20) 0.10 C A B C 0.05 0.30 30 0.20 (40X) 31 20 0.50 PIN #1 INDICATOR 0.20 MAY APPEAR AS OPTIONAL 2.400.10 (0.70) 1.500.10 11 10 0.40 2.000.10 (0.20) 0.50 (40X) 0.30 40 1 2.000.10 0.50 NOTES: UNLESS OTHERWISE SPECIFIED (0.20) BOTTOM VIEW A) DOES NOT FULLY CONFORM TO JEDEC REGISTRATION MO-220, DATED MAY/2005. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM. D) DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. E) DRAWING FILE NAME: PQFN40AREV3 1.10 0.90 0.10 C 0.08 C 0.30 0.20 2.10 LAND PATTERN RECOMMENDATION 0.05 0.00 DETAIL 'A' C SEATING PLANE SCALE: 2:1 Figure 30. 40-Lead, Clipbond PQFN DrMOS, 6.0x6.0 mm Package Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. (c) 2011 Fairchild Semiconductor Corporation FDMF6706B * Rev. 1.0.2 www.fairchildsemi.com 17 FDMF6706B - Extra-Small, High-Performance, High-Frequency DrMOS Module (c) 2011 Fairchild Semiconductor Corporation FDMF6706B * Rev. 1.0.2 www.fairchildsemi.com 18 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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