ADD8710ARUZREEL - ANALOG DEVICES

To learn more about ON Semiconductor, please visit our website at

www.onsemi.com

Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers

will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor

product management systems do not have the ability to manage part nomenclature that utilizes an underscore

(_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain

device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated

device numbers. The most current and up-to-date ordering information can be found at www.onsemi.com. Please

email any questions regarding the system integration to Fairchild_questions@onsemi.com.

Is Now Part of

ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number

of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right

to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

arising out of the application or use of any product or circuit, and speciﬁcally disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON

Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON

Semiconductor data sheets and/or speciﬁcations can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s

technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA

Class 3 medical devices or medical devices with a same or similar classiﬁcation in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended

or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its ofﬁcers, employees, subsidiaries, afﬁliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out

of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor

is an Equal Opportunity/Afﬁrmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

April 2013

FDMF6706B • Rev. 1.0.2

FDMF6706B - Extra-Small, High-Performance, High-Frequency DrMOS Module

FDMF6706B - Extra-Small, High-Performance, High-

Frequency DrMOS Module

Benefits

 Ultra-Compact 6x6 mm PQFN, 72% Space-Saving

Compared to Conventional Discrete Solutions

 Fully Optimized System Efficiency

 Clean Switching Waveforms with Minimal Ringing

 High-Current Handling

Features

 Over 93% Peak-Efficiency

 High-Current Handling of 45 A

 High-Performance PQFN Copper-Clip Package

 3-State 3.3 V PWM Input Driver

 Skip-Mode SMOD# (Low-Side Gate Turn Off) Input

 Thermal Warning Flag for Over-Temperature

Condition

 Driver Output Disable Function (DISB# Pin)

 Internal Pull-Up and Pull-Down for SMOD# and

DISB# Inputs, Respectively

 Fairchild PowerTrench® Technology MOSFETs for

Clean Voltage Waveforms and Reduced Ringing

 Fairchild SyncFET™ (Integrated Schottky Diode)

Technology in the Low-Side MOSFET

 Integrated Bootstrap Schottky Diode

 Adaptive Gate Drive Timing for Shoot-Through

Protection

 Under-Voltage Lockout (UVLO)

 Optimized for Switching Frequencies up to 1MHz

 Low-Profile SMD Package

 Fairchild Green Packaging and RoHS Compliance

 Based on the Intel® 4.0 DrMOS Standard

Description

The XS™ DrMOS family is Fairchild’s next-generation,

fully optimized, ultra-compact, integrated MOSFET plus

driver power stage solution for high-current, high-

frequency, synchronous buck DC-DC applications. The

FDMF6706B integrates a driver IC, two power MOSFETs,

and a bootstrap Schottky diode into a thermally

enhanced, ultra-compact 6x6 mm PQFN package.

With an integrated approach, the complete switching

power stage is optimized for driver and MOSFET

dynamic performance, system inductance, and power

MOSFET RDS(ON). XS™ DrMOS uses Fairchild's high-

performance PowerTrench® MOSFET technology,

which dramatically reduces switch ringing, eliminating

the snubber circuit in most buck converter applications.

A new driver IC with reduced dead times and

propagation delays further enhances performance. A

thermal warning function warns of potential over-

temperature situations. FDMF6706B also incorporates

features such as Skip Mode (SMOD) for improved light-

load efficiency, along with a Three-state 3.3 V PWM

input for compatibility with a wide range of PWM

controllers.

Applications

 High-Performance Gaming Motherboards

 Compact Blade Servers, V-Core and Non-V-Core

DC-DC Converters

 Desktop Computers, V-Core and Non-V-Core

DC-DC Converters

 Workstations

 High-Current DC-DC Point-of-Load (POL)

Converters

 Networking and Telecom Microprocessor Voltage

Regulators

 Small Form-Factor Voltage Regulator Modules

Ordering Information

Part Number Current Rating Package Top Mark

FDMF6706B 45 A 40-Lead, Clipbond PQFN DrMOS, 6.0 mm x 6.0 mm Package FDMF6706B

FDMF6706B • Rev. 1.0.2 2

FDMF6706B - Extra-Small, High-Performance, High-Frequency DrMOS Module

Typical Application Circuit

Figure 1. Typical Application Circuit

DrMOS Block Diagram

Figure 2. DrMOS Block Diagram

SMOD#

PWM

VCIN

VDRV VIN

PGND

PHASE

DBoot

BOOT

CGND

DISB#

THWN#

HS Power

MOSFET

Input

3- State

Logic

RUP_PWM

VCIN

UVLO

Logic Level Shift

Dead-Time

Control

Temp.

Sense

30kΩ

Logic

10µA

RDN_PWM

LS Power

MOSFET

VSWH

VDRV

FDMF6706B • Rev. 1.0.2 3

FDMF6706B - Extra-Small, High-Performance, High-Frequency DrMOS Module

Pin Configuration

Figure 3. Bottom View Figure 4. Top View

Pin Definitions

Pin # Name Description

1 SMOD#

When SMOD#=HIGH, the low-side driver is the inverse of PWM input. When SMOD#=LOW,

the low-side driver is disabled. This pin has a 10 µA internal pull-up current source. Do not add

a noise filter capacitor.

2 VCIN IC bias supply. Minimum 1 µF ceramic capacitor is recommended, from this pin to CGND.

3 VDRV

Power for gate driver. Minimum 1 µF ceramic capacitor is recommended connected as close as

possible from this pin to CGND.

4 BOOT

Bootstrap supply input. Provides voltage supply to the high-side MOSFET driver. Connect a

bootstrap capacitor from this pin to PHASE.

5, 37, 41 CGND IC ground. Ground return for driver IC.

6 GH For manufacturing test only. This pin must float; must not be connected to any pin.

7 PHASE Switch node pin for bootstrap capacitor routing. Electrically shorted to VSWH pin.

8 NC

No connect. The pin is not electrically connected internally, but can be connected to VIN for

convenience.

9 - 14, 42 VIN Power input. Output stage supply voltage.

15, 29 -

35, 43 VSWH Switch node input. Provides return for high-side bootstrapped driver and acts as a sense point

for the adaptive shoot-through protection.

16 – 28 PGND Power ground. Output stage ground. Source pin of the low-side MOSFET.

36 GL For manufacturing test only. This pin must float; must not be connected to any pin.

38 THWN#

Thermal warning flag, open collector output. When temperature exceeds the trip limit, the

output is pulled LOW. THWN# does not disable the module.

39 DISB#

Output disable. When LOW, this pin disables the power MOSFET switching (GH and GL are

held LOW). This pin has a 10 µA internal pull-down current source. Do not add a noise filter

capacitor.

40 PWM

PWM signal input. This pin accepts a Three-state 3.3 V PWM signal from the controller.

FDMF6706B • Rev. 1.0.2 4

FDMF6706B - Extra-Small, High-Performance, High-Frequency DrMOS Module

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

VCIN Supply Voltage Referenced to CGND -0.3 6.0 V

VDRV Drive Voltage Referenced to CGND -0.3 6.0 V

VDISB# Output Disable Referenced to CGND -0.3 6.0 V

VPWM PWM Signal Input Referenced to CGND -0.3 6.0 V

VSMOD# Skip Mode Input Referenced to CGND -0.3 6.0 V

VGL Low Gate Manufacturing Test Pin Referenced to CGND -0.3 6.0 V

VTHWN# Thermal Warning Flag Referenced to CGND -0.3 6.0 V

VIN Power Input Referenced to PGND, CGND -0.3 25.0 V

VBOOT Bootstrap Supply Referenced to VSWH, PHASE -0.3 6.0 V

Referenced to CGND -0.3 25.0 V

VGH High Gate Manufacturing Test Pin Referenced to VSWH, PHASE -0.3 6.0 V

Referenced to CGND -0.3 25.0 V

VPHS PHASE Referenced to CGND -0.3 25.0 V

VSWH Switch Node Input Referenced to PGND, CGND (DC Only) -0.3 25.0 V

Referenced to PGND, <20 ns -8.0 25.0 V

VBOOT Bootstrap Supply Referenced to VDRV 22 V

Referenced to VDRV, <20 ns 25 V

ITHWN# THWN# Sink Current -0.1 7.0 mA

IO(AV) Output Current(1) fSW=300 kHz, VIN=12 V, VO=1.0 V 45 A

fSW=1 MHz, VIN=12 V, VO=1.0 V 40

θJPCB Junction-to-PCB Thermal Resistance 3.5 °C/W

TA Ambient Temperature Range -40 +125 °C

TJ Maximum Junction Temperature +150 °C

TSTG Storage Temperature Range -55 +150 °C

ESD Electrostatic Discharge Protection Human Body Model, JESD22-A114 2000 V

Charged Device Model, JESD22-C101 1000

Note:

1. IO(AV) is rated using Fairchild’s DrMOS evaluation board, TA = 25°C, natural convection cooling. This rating is limited

by the peak DrMOS temperature, TJ = 150°C, and varies depending on operating conditions and PCB layout. This

rating can be changed with different application settings.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol Parameter Min. Typ. Max. Unit

VCIN Control Circuit Supply Voltage 4.5 5.0 5.5 V

VDRV Gate Drive Circuit Supply Voltage 4.5 5.0 5.5 V

VIN Output Stage Supply Voltage 3.0 12.0 15.0(2) V

Note:

2. Operating at high VIN can create excessive AC overshoots on the VSWH-to-GND and BOOT-to-GND nodes

during MOSFET switching transients. For reliable DrMOS operation, VSWH-to-GND and BOOT-to-GND must

remain at or below the Absolute Maximum Ratings shown in the table above. Refer to the “Application

Information” and “PCB Layout Guidelines” sections of this datasheet for additional infor ma t ion.

FDMF6706B • Rev. 1.0.2 5

FDMF6706B - Extra-Small, High-Performance, High-Frequency DrMOS Module

Electrical Characteristics

Typical values are VIN = 12 V, VCIN = 5 V, VDRV = 5 V, and TA = +25°C unless otherwise noted.

Symbol Parameter Condition Min. Typ. Max. Unit

Basic Operation

IQ Quiescent Current IQ=IVCIN+IVDRV, PWM=LOW or HIGH or Float 2 mA

UVLO UVLO Threshold VCIN Rising 2.9 3.1 3.3 V

UVLO_Hyst UVLO Hysteresis 0.4 V

PWM Input (VCIN = VDRV = 5 V ±10%)

RUP_PWM Pull-Up Impedance 26 kΩ

RDN_PWM Pull-Down Impedance 12 kΩ

VIH_PWM PWM High Level Voltage 1.88 2.25 2.61 V

VTRI_HI 3-State Upper Threshold 1.84 2.20 2.56 V

VTRI_LO 3-State Lower Threshold 0.70 0.95 1.19 V

VIL_PWM PWM Low Level Voltage 0.62 0.85 1.13 V

tD_HOLD-OFF 3-State Shut-off Time 160 200 ns

VHiZ_PWM 3-State Open Voltage 1.40 1.60 1.90 V

PWM Input (VCIN = VDRV = 5 V ±5%)

RUP_PWM Pull-Up Impedance 26 kΩ

RDN_PWM Pull-Down Impedance 12 kΩ

VIH_PWM PWM High Level Voltage 2.00 2.25 2.50 V

VTRI_HI 3-State Upper Threshold 1.94 2.20 2.46 V

VTRI_LO 3-State Lower Threshold 0.75 0.95 1.15 V

VIL_PWM PWM Low Level Voltage 0.66 0.85 1.09 V

tD_HOLD-OFF 3-State Shut-off Time 160 200 ns

VHiZ_PWM 3-State Open Voltage 1.45 1.60 1.80 V

DISB# Input

VIH_DISB High-Level Input Voltage 2 V

VIL_DISB Low-Level Input Voltage 0.8 V

IPLD Pull-Down Current 10 µA

tPD_DISBL Propagation Delay PWM=GND, Delay Between DISB# from

HIGH to LOW to GL from HIGH to LOW 25 ns

tPD_DISBH Propagation Delay PWM=GND, Delay Between DISB# from

LOW to HIGH to GL from LOW to HIGH 25 ns

SMOD# Input

VIH_SMOD High-Level Input Voltage 2 V

VIL_SMOD Low-Level Input Voltage 0.8 V

IPLU Pull-Up Current 10 µA

tPD_SLGLL Propagation Delay PWM=GND, Delay Between SMOD# from

HIGH to LOW to GL from HIGH to LOW 10 ns

tPD_SHGLH Propagation Delay PWM=GND, Delay Between SMOD# from

LOW to HIGH to GL from LOW to HIGH 10 ns

Continued on the following page…

FDMF6706B • Rev. 1.0.2 6

FDMF6706B - Extra-Small, High-Performance, High-Frequency DrMOS Module

Electrical Characteristics

Typical values are VIN = 12 V, VCIN = 5 V, VDRV = 5 V, and TA = +25°C unless otherwise noted.

Symbol Parameter Condition Min. Typ. Max. Unit

Thermal Warning Flag

TACT Activation Temperature 150 °C

TRST Reset Temperature 135 °C

RTHWN Pull-Down Resistance IPLD=5 mA 30 Ω

250ns Timeout Circuit

tD_TIMEOUT Timeout Delay SW=0 V, Delay Between GH from HIGH to

LOW and GL from LOW to HIGH 250 ns

High-Side Driver

RSOURCE_GH Output Impedance, Sourcing Source Current=100 mA 1 Ω

RSINK_GH Output Impedance, Sinking Sink Current=100 mA 0.8 Ω

tR_GH Rise Time GH=10% to 90%, CLOAD=1.1 nF 6 ns

tF_GH Fall Time GH=90% to 10%, CLOAD=1.1 nF 5 ns

tD_DEADON LS to HS Deadband Time GL going LOW to GH going HIGH,

1 V GL to 10 % GH 10 ns

tPD_PLGHL PWM LOW Propagation

Delay

PWM going LOW to GH going LOW,

VIL_PWM to 90% GH 16 30 ns

tPD_PHGHH PWM HIGH Propagation

Delay (SMOD# Held LOW)

PWM going HIGH to GH going HIGH,

VIH_PWM to 10% GH (SMOD#=LOW) 30 ns

tPD_TSGHH Exiting 3-State Propagation

Delay

PWM (From 3-State) going HIGH to GH

going HIGH, VIH_PWM to 10% GH 30 ns

Low-Side Driver

RSOURCE_GL Output Impedance, Sourcing Source Current=100 mA 1 Ω

RSINK_GL Output Impedance, Sinking Sink Current=100 mA 0.5 Ω

tR_GL Rise Time GL=10% to 90%, CLOAD=4.5 nF 14 ns

tF_GL Fall Time GL=90% to 10%, CLOAD=4.5 nF 10 ns

tD_DEADOFF HS to LS Deadband Time SW going LOW to GL going HIGH,

2.2 V SW to 10% GL 12 ns

tPD_PHGLL PWM-HIGH Propagation

Delay

PWM going HIGH to GL going LOW,

VIH_PWM to 90% GL 9 25 ns

tPD_TSGLH Exiting 3-State Propagation

Delay

PWM (From 3-State) going LOW to GL

going HIGH, VIL_PWM to 10% GL 20 ns

Boot Diode

VF Forward-Voltage Drop IF=10 mA 0.35 V

VR Breakdown Voltage IR=1 mA 22 V

FDMF6706B • Rev. 1.0.2 7

FDMF6706B - Extra-Small, High-Performance, High-Frequency DrMOS Module

Figure 5. PWM Timing Diagram

t D_DEADON

PWM

VSWH

tPD PHGLL

tD_DEADOFF

PWM

VIL

PWM

90%

1.0V

10%

tPD PLGHL

2.2V

10%

TIMEOUT

( 250ns Timeout)

1.2V

FDMF6706B • Rev. 1.0.2 8

FDMF6706B - Extra-Small, High-Performance, High-Frequency DrMOS Module

Typical Performance Characteristics

Test Conditions: VIN=12 V, VOUT=1.0 V, VCIN=5 V, VDRV=5 V, LOUT=320 nH, TA=25°C, and natural convection cooling,

unless otherwise specified.

Figure 6. Safe Op erating Area Figure 7. Module Power Loss vs. Output Current

Figure 8. Power Loss vs. Switching Frequency Figure 9. Power Loss vs. Input Voltage

Figure 10. Power Loss vs. Driver Supply Voltage Figure 11. Power Loss vs. Output Voltage

0 25 50 75 100 125 150

Module Output cur rent , I

OUT

(A)

PCB Temper at ure (°C)

= 300kHz

= 1MHz

= 12V, V

OUT

= 1.0V

JPCB

= 3.5°C/W

0 5 10 15 20 25 30 35 40

Module Power Loss (W)

Output Current, I

OUT

(A)

300kHz

500kHz

800kHz

1MHz

= 12V, V

OUT

= 1V

0.9

1.1

1.2

1.3

1.4

1.5

200 300 400 500 600 700 800 900 1000

Normalized Module Power Loss

Module Switc hing Freque ncy, f

(kHz)

= 12V, I

OUT

= 30A, f

= 300kHz

0.95

1.00

1.05

1.10

1.15

1.20

56789101112131415

Nor m a lize d Module P ower Los s

Module Input Voltage , V

(V)

OUT

= 30 A, f

= 300kHz

0.90

0.95

1.00

1.05

1.10

1.15

4.50 4.75 5.00 5.25 5.50

Nor m aliz ed Module Powe r Los s

Driv er S uppl y Vo ltage, V

DRV

and V

CIN

(V)

= 12V, I

OUT

= 30 A, f

= 300kHz

0.9

1.1

1.3

1.5

1.7

1.9

0.5 1.0 1.5 2.0 2.5 3.0 3.5

Nor m aliz ed Module Powe r Los s

Output Voltage, V

OUT

(V)

= 12V, I

OUT

= 30 A, f

= 300kHz

FDMF6706B • Rev. 1.0.2 9

FDMF6706B - Extra-Small, High-Performance, High-Frequency DrMOS Module

Typical Performance Characteristics (Continued)

Test Conditions: VIN=12 V, VOUT=1.0 V, VCIN=5 V, VDRV=5 V, LOUT=320 nH, TA=25°C, and natural convection cooling,

unless otherwise specified.

Figure 12. Power Loss vs. Output Inductance Figure 13. Driver Supply Current vs. Frequency

Figure 14. Driver Supply Current vs. Driver

Supply Voltage Figure 15. Driver Supply Current vs. Output Current

Figure 16. PWM Thresholds vs. Driver Supply Voltage Figure 17. PWM Thresholds vs. Temperature

0.98

0.99

1.00

1.01

1.02

1.03

1.04

1.05

225 275 325 375 425

Nor m a lize d M odule Powe r Los s

Output Inductance, L

OUT

(nH)

= 12V, I

OUT

= 30A, f

= 300kHz

200 400 600 800 1000

Driver Supply Current, I

VDRV

+ I

VCIN

(mA)

Module Switc hing Freque ncy, f

(kHz)

= 12V, I

OUT

= 0A, f

= 300kHz

4.50 4.75 5.00 5.25 5.50

Driver Supp ly Current, I

VDRV

+ I

VCIN

(mA)

Driver Supply Voltage, V

DRV

& V

CIN

(V)

= 12 V, I

OUT

= 0A, f

= 300kHz

0.96

0.98

1.00

1.02

1.04

1.06

1.08

1.10

0 5 10 15 20 25 30 35 4

No r m a liz e d D rive r Supply Cur rent

Module Out put C urre nt, I

OUT

(A)

300kHz

1MHz

0.0

0.5

1.0

1.5

2.0

2.5

3.0

4.50 4.75 5.00 5.25 5.50

PWM Thre shold V olt age (V)

Driver Supply Voltage, V

CIN

(V)

IH_PWM

HiZ_PWM

TRI_HI

TRI_LO

IL_PWM

= 25°C

0.0

0.5

1.0

1.5

2.0

2.5

3.0

-50 -25 0 25 50 75 100 125 150

PWM Thr eshold Voltage (V)

Driver IC Junction Temperature, T

(

CIN

= 5V

IL_PWM

IH_PWM

TRI_HI

TRI_LO

FDMF6706B • Rev. 1.0.2 10

FDMF6706B - Extra-Small, High-Performance, High-Frequency DrMOS Module

Typical Performance Characteristics (Continued)

Test Conditions: VIN=12 V, VOUT=1.0 V, VCIN=5 V, VDRV=5 V, LOUT=320 nH, TA=25°C, and natural convection cooling,

unless otherwise specified.

Figure 18. SMOD# Thresholds vs. Driver

Supply Voltage

Figure 19. SMOD# Thresholds vs. Temperature

Figure 20. SMOD# Pull-Up Current vs. Temperature Figure 21. Disable Thresholds vs. Driver

Supply Voltage

Figure 22. Disable Thresholds vs. Temperature Figure 23. Disable Pull-Down Current vs.

Temperature

1.2

1.4

1.6

1.8

2.0

2.2

4.50 4.75 5.00 5.25 5.50

SM OD# Threshold Vol t a ge (V )

Dr iv e r Supply Voltage , V

CIN

(V)

IH_SMOD

IL_SMOD

25°C

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

-50 -25 0 25 50 75 100 125 150

SMOD Thr e s hold Voltage (V)

Driver IC Junction Temperatu re (

IH_SMOD

CIN

= 5V

IL_SMOD

-12.0

-11.5

-11.0

-10.5

-10.0

-9.5

-9.0

-50 -25 0 25 50 75 100 125 150

SMOD # Pull-up Cur r e nt , I

PLU

(uA)

Driver IC Junction Temperature, T

(

CIN

= 5V

1.40

1.50

1.60

1.70

1.80

1.90

2.00

-50 -25 0 25 50 75 100 125 150

DISB Threshold Voltage (V)

Driver IC Junction Temperature, T

(°C)

IH_DISB

IL_DISB

CIN

= 5V

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

4.50 4.75 5.00 5.25 5.50

DISB# Threshold V oltage (V)

Driver Supply Voltag e , V

CIN

(V)

IH_DISB

= 25

IL_DISB

8.0

8.5

9.0

9.5

10.0

10.5

11.0

11.5

12.0

-50 -25 0 25 50 75 100 125 150

DISB# Pu l l-d o w n Current, I

PLD

(uA)

Driver IC Ju ncti on Temp erat u re (

CIN

= 5V

FDMF6706B • Rev. 1.0.2 11

FDMF6706B - Extra-Small, High-Performance, High-Frequency DrMOS Module

Functional Description

The FDMF6706B is a driver-plus-FET module optimized

for the synchronous buck converter topology. A single

PWM input signal is all that is required to properly drive

the high-side and the low-side MOSFETs. Each part is

capable of driving speeds up to 1 MHz.

VCIN and Disable (DISB#)

The VCIN pin is monitored by an Under-Voltage Lockout

(UVLO) circuit. When VCIN rises above ~3.1 V, the driver

is enabled. When VCIN falls below ~2.7 V, the driver is

disabled (GH, GL=0). The driver can also be disabled by

pulling the DISB# pin LOW (DISB# < VIL_DISB), which

holds both GL and GH LOW regardless of the PWM

input state. The driver can be enabled by raising the

DISB# pin voltage HIGH (DISB# > VIH_DISB).

Table 1. UVLO and Disable Logic

UVLO DISB# Driver State

0 X Disabled (GH, GL=0)

1 0 Disabled (GH, GL=0)

1 1 Enabled (See Table 2)

1 Open Disabled (GH, GL=0)

Note:

3. DISB# internal pull-down current source is 10 µA.

Thermal Warning Flag (THWN#)

The FDMF6706B provides a thermal warning flag

(THWN#) to advise of over-temperature conditions. The

thermal warning flag uses an open-drain output that

pulls to CGND when the activation temperature (150°C)

is reached. The THWN# output returns to high-

impedance state once the temperature falls to the reset

temperature (135°C). The THWN# output requires a

pull-up resistor, which can be connected to VCIN.

THWN# does NOT disable the DrMOS module.

Figure 24. THWN Op eratio n

Three-State PWM Input

The FDMF6706B incorporates a three-state 3.3 V PWM

input gate drive design. The Three-state gate drive has

both logic HIGH level and LOW level, along with a 3-

state shutdown window. When the PWM input signal

enters and remains within the three-state window for a

defined hold-off time (tD_HOLD-OFF), both GL and GH are

pulled LOW. This feature enables the gate drive to shut

down both high-and low-side MOSFETs to support

features such as phase shedding, a common feature on

multi-phase voltage regulators.

Exiting Three-State Condition

When exiting a valid three-state condition, the

FDMF6706B design follows the PWM input command. If

the PWM input goes from three-state to LOW, the low-

side MOSFET is turned on. If the PWM input goes from

3-state to HIGH, the high-side MOSFET is turned on, as

illustrated in Figure 25. The FDMF6706B design allows

for short propagation delays when exiting the three-state

window (see Electrical C haracteristics).

Low-Side Driver

The low-side driver (GL) is designed to drive a ground-

referenced low RDS(ON) N-channel MOSFET. The bias

for GL is internally connected between VDRV and

CGND. When the driver is enabled, the driver's output is

180° out of phase with the PWM input. When the driver

is disabled (DISB#=0 V), GL is held LOW.

High-Side Driver

The high-side driver is designed to drive a floating N-

channel MOSFET. The bias voltage for the high-side

driver is developed by a bootstrap supply circuit

consisting of the internal Schottky diode and external

bootstrap capacitor (CBOOT). During startup, VSWH is

held at PGND, allowing CBOOT to charge to VDRV

through the internal diode. When the PWM input goes

HIGH, GH begins to charge the gate of the high-side

MOSFET (Q1). During this transition, the charge is

removed from CBOOT and delivered to the gate of Q1.

As Q1 turns on, VSWH rises to VIN, forcing the BOOT

pin to VIN + VBOOT, which provides sufficient VGS

enhancement for Q1. To complete the switching cycle,

Q1 is turned off by pulling GH to VSWH. CBOOT is then

recharged to VDRV when VSWH falls to PGND. GH

output is in-phase with the PWM input. The high-side

gate is held LOW when the driver is disabled or the

PWM signal is held within the three-state window for

longer than the three-state hold-off time, tD_HOLD-OFF.

150°C

ctivation

Tem

erature

TJ_driver IC

Thermal

Warning

Normal

Operation

HIGH

LOW

135°C Reset

Temperature

THWN#

Logic

State

FDMF6706B • Rev. 1.0.2 12

FDMF6706B - Extra-Small, High-Performance, High-Frequency DrMOS Module

Adaptive Gate Drive Circuit

The driver IC design ensures minimum MOSFET dead

time, while eliminating potential shoot-through (cross-

conduction) currents. It senses the state of the MOSFETs

and adjusts the gate drive adaptively to prevent

simultaneous conduction. Figure 25 provides the relevant

timing waveforms. To prevent overlap during the LOW-to-

HIGH switching transition (Q2 off to Q1 on), the adaptive

circuitry monitors the voltage at the GL pin. When the

PWM signal goes HIGH, Q2 turns off after a propagation

delay (tPD_PHGLL). Once the GL pin is discharged below

~1 V, Q1 turns on after adaptive delay, tD_DEADON.

To prevent overlap during the HIGH-to-LOW transition

(Q1 off to Q2 on), the adaptive circuitry monitors the

voltage at the VSWH pin. When the PWM signal goes

LOW, Q1 turns off after a propagation delay (tPD_PLGHL).

Once the VSWH pin falls below ~2.2 V, Q2 turns on

after adaptive delay tD_DEADOFF. Additionally, VGS(Q1) is

monitored. When VGS(Q1) is discharged below ~1.2 V, a

secondary adaptive delay is initiated that results in Q2

being driven on after tD_TIMEOUT, regardless of VSWH

state. This function ensures CBOOT is recharged each

switching cycle in the event that the VSWH voltage does

not fall below the 2.2 V adaptive threshold. Secondary

delay, tD_TIMEOUT is longer than tD_DEADOFF.

Figure 25. PWM and 3-StateTiming Diagram

Notes:

tPD_xxx = propagation delay from external signal (PWM, SMOD#, etc.) to IC generated signal. Example (tPD_PHGLL – PWM going HIGH to LS VGS (GL) going LOW)

tD_xxx = delay from IC generated signal to IC generated signal. Example (tD_DEADON – LS VGS (GL) LOW to HS VGS (GH) HIGH)

PWM Exiting 3-state

tPD_PHGLL = PWM rise to LS VGS fall, VIH_PWM to 90% LS VGS t

PD_TSGHH = PWM 3-state to HIGH to HS VGS rise, VIH_PWM to 10% HS VGS

tPD_PLGHL = PWM fall to HS VGS fall, VIL_PWM to 90% HS VGS t

PD_TSGLH = PWM 3-state to LOW to LS VGS rise, VIL_PWM to 10% LS VGS

tPD_PHGHH = PWM rise to HS VGS rise, VIH_PWM to 10% HS VGS (SMOD# held LOW)

SMOD# Dead Times

tPD_SLGLL = SMOD# fall to LS VGS fall, VIL_SMOD to 90% LS VGS t

D_DEADON = LS VGS fall to HS VGS rise, LS-comp trip value (~1.0V GL) to 10% HS VGS

tPD_SHGLH = SMOD# rise to LS VGS rise, VIH_SMOD to 10% LS VGS t

D_DEADOFF = VSWH fall to LS VGS rise, SW-comp trip value (~2.2V VSWH) to 10% LS VGS

tPD_TSGHH

VSWH

PD_PHGLL tD_HOLD -OFF

90%

less than

tD_HOLD -

OFF

Exit

3 S t a t e

1.0V

PWM

VIL_PWM

VIH_PWM VTRI_HI

VIH_PWM VIH_PWM

10%

tR_GL

tD_HOLD -OFF

tPD_TSGLH

less than

tD_HOLD -

OFF

Exit

3-State

IH PWM

VTRI_HI

VTRI_LO

VIL_PWM

PLGHL tPD_TSGHH

DCM

tF_GH

tR_GH

D_HOLD-OFF

10%

CCM DCM

Exit

3-State

90%

10%

90%

Enter

3-State

Enter

3 -State

D_DEADOFF

D_DEADON Enter

3 -State

F_GL

VIN

VOUT

2.2

FDMF6706B • Rev. 1.0.2 13

FDMF6706B - Extra-Small, High-Performance, High-Frequency DrMOS Module

Skip Mode (SMOD)

The SMOD function allows higher converter efficiency

under light-load conditions. During SMOD, the low-side

FET gate signal is disabled (held LOW), preventing

discharging of the output capacitors as the filter inductor

current attempts reverse current flow – also known as

Diode Emulation Mode.

When the SMOD# pin is pulled HIGH, the synchronous

buck converter will work in Synchronous Mode. This

mode allows for gating on the low-side FET. When the

SMOD# pin is pulled LOW, the low-side FET is gated

off. If the SMOD# pin is connected to the PWM

controller, the controller can actively enable or disable

SMOD when the controller detects light-load condition

from output current sensing. This pin is active LOW.

See Figure 26 for timing delays.

Table 2. SMOD Logic

DISB# PWM SMOD# GH GL

0 X X 0 0

1 3-State X 0 0

1 0 0 0 0

1 1 0 1 0

1 0 1 0 1

1 1 1 1 0

Note:

4. The SMOD feature is intended to have low

propagation delay between the SMOD signal and

the low-side FET VGS response time to control

diode emulation on a cycle-by-cycle basis.

Figure 26. SMOD Timing Diagram

tD_DEADON

PWM

SWH

tPD_PHGLL tPD_PLGHL

tD_DEADOFF

VIH_PWM

VIL_PWM

90%

10%

90%

1.0V

2.2V

tPD_PHGHH tPD_SHGLH

Delay from SMOD# going

HIGH to LS VGS HIGH

HS turn -on with SMOD# LOW

SMOD

tPD_SLGLL

Delay from SMOD# going

LOW to LS VGS LOW

DCM

CCM

10%

VIH_PWM

10%

VOUT

VIH_SMOD

VIL_SMOD

10%

FDMF6706B • Rev. 1.0.2 14

FDMF6706B - Extra-Small, High-Performance, High-Frequency DrMOS Module

Application Information

Supply Capacitor Selection

For the supply inputs (VDRV & VCIN), a local ceramic

bypass capacitor is required to reduce noise and to

supply peak transient currents during gate drive

switching action. It is recommended to use a minimum

capacitor value of 1 µF X7R or X5R. Keep this capacitor

close to the VCIN and VDRV pins and connect it to the

GND plane with vias.

Bootstrap Circuit

The bootstrap circuit uses a charge storage capacitor

(CBOOT), as shown in Figure 28. A capacitance of 100 nF

X7R or X5R capacitor is typically adequate. A series

bootstrap resistor may be needed for specific

applications to improve switching noise immunity. The

boot resistor (RBOOT) may be required when operating

near the maximum rated VIN and is effective at

controlling the high-side MOSFET turn-on slew rate and

VSHW overshoot. Typical RBOOT values from 0.5 to

2.0 W are effective in reducing VSWH overshoot.

VCIN Filter

The VDRV pin provides power to the gate drive of the

high-side and low-side power MOSFETs. In most cases,

VDRV can be connected directly to VCIN, which

supplies power to the logic circuitry of the gate driver.

For additional noise immunity, an RC filter can be

inserted between VDRV and VCIN. Recommended

values of 10 Ω (RVCIN) placed between VDRV and VCIN

and 1 µF (CVCIN) from VCIN to CGND, Figure 27.

Power Loss and Efficiency

Measurement and Calculatio n

Refer to Figure 28 for power loss testing method. Power

loss calculations are:

PIN=(VIN x IIN) + (V5V x I5V) (W) (1)

PSW=VSW x IOUT (W) (2)

POUT=VOUT x IOUT (W) (3)

PLOSS_MODULE=PIN - PSW (W) (4)

PLOSS_BOARD=PIN - POUT (W) (5)

EFFMODULE=100 x PSW/PIN (%) (6)

EFFBOARD=100 x POUT/PIN (%) (7)

Figure 27. Block Diagram With VCIN Filter

V5V

DISB

PWM

Input

OFF

CVDRV CVIN

CBOOT

RBOOT

LOUT

COUT

I5V

IIN

IOUT

FDMF6706B

Open-

Drain

Output

VDRV VCIN VIN

PWM

THWN#

BOOT

VSWH

CGND PGND

DISB#

PHASE

VOUT

RVCIN

CVCIN

SMOD#

Figure 28. Power Loss Measurement

FDMF6706B • Rev. 1.0.2 15

FDMF6706B - Extra-Small, High-Performance, High-Frequency DrMOS Module

PCB Layout Guidelines

Figure 29 provides an example of a proper layout for the

FDMF6706B and critical components. All of the high-

current paths, such as VIN, VSWH, VOUT, and GND

copper, should be short and wide for low inductance

and resistance. This technique achieves a more stable

and evenly distributed current flow, along with enhanced

heat radiation and system performance.

The following guidelines are recommendations for the

PCB designer:

1. Input ceramic bypass capacitors must be placed

close to the VIN and PGND pins. This helps reduce

the high-current power loop inductance and the input

current ripple induced by the power MOSFET

switching operation.

2. The VSWH copper trace serves two purposes. In

addition to being the high-frequency current path

from the DrMOS package to the output inductor, it

also serves as a heat sink for the low-side MOSFET

in the DrMOS package. The trace should be short

and wide enough to present a low-impedance path

for the high-frequency, high-current flow between the

DrMOS and inductor to minimize losses and

temperature rise. Note that the VSWH node is a

high-voltage and high-frequency switching node with

high noise potential. Care should be taken to

minimize coupling to adjacent traces. Since this

copper trace also acts as a heat sink for the lower

FET, balance using the largest area possible to

improve DrMOS cooling while maintaining

acceptable noise emission.

3. An output inductor should be located close to the

FDMF6706B to minimize the power loss due to the

VSWH copper trace. Care should also be taken so

the inductor dissipation does not heat the DrMOS.

4. PowerTrench® MOSFETs are used in the output

stage. The power MOSFETs are effective at

minimizing ringing due to fast switching. In most

cases, no VSWH snubber is required. If a snubber is

used, it should be placed close to the VSWH and

PGND pins. The resistor and capacitor need to be of

proper size for the power dissipation.

5. VCIN, VDRV, and BOOT capacitors should be

placed as close as possible to the VCIN to CGND,

VDRV to CGND, and BOOT to PHASE pins to

ensure clean and stable power. Routing width and

length should be considered.

6. Include a trace from PHASE to VSWH to improve

noise margin. Keep the trace as short as possible.

7. The layout should include a place holder to insert a

small-value series boot resistor (RBOOT) between the

boot capacitor (CBOOT) and DrMOS BOOT pin. The

BOOT-to-VSWH loop size, including RBOOT and

CBOOT, should be as small as possible. The boot

resistor may be required when operating near the

maximum rated VIN. The boot resistor is effective at

controlling the high-side MOSFET turn-on slew rate

and VSHW overshoot. RBOOT can improve noise

operating margin in synchronous buck designs that

may have noise issues due to ground bounce or high

positive and negative VSWH ringing. However,

inserting a boot resistance lowers the DrMOS

efficiency. Efficiency versus noise trade-offs must be

considered. RBOOT values from 0.5 to 2.0 Ω are

typically effective in reducing VSWH overshoot.

The VIN and PGND pins handle large current

transients with frequency components >100 MHz. If

possible, these pins should be connected directly to

the VIN and board GND planes. The use of thermal

relief traces in series with these pins is discouraged

since this adds inductance to the power path. This

added inductance in series with either the VIN or

PGND pin degrades system noise immunity by

increasing positive and negative VSWH ringing.

8. GND pad and PGND pins should be connected to

the GND plane copper with multiple vias for stable

grounding. Poor grounding can create a noise

transient offset voltage level between CGND and

PGND. This could lead to faulty operation of the gate

driver and MOSFETs.

9. Ringing at the BOOT pin is most effectively

controlled by close placement of the boot capacitor.

Do not add an additional BOOT to the PGND

capacitor. This may lead to excess current flow

through the BOOT diode.

10. The SMOD# and DISB# pins have weak internal

pull-up and pull-down current sources, respectively.

These pins should not have any noise filter

capacitors. Do not to float these pins unless

absolutely necessary.

11. Use multiple vias on each copper area to

interconnect top, inner, and bottom layers to help

distribute current flow and heat conduction. Vias

should be relatively large and of reasonably low

inductance. Critical high-frequency components,

such as RBOOT, CBOOT, the RC snubber, and bypass

capacitors should be located as close to the

respective DrMOS module pins as possible on the

top layer of the PCB. If this is not feasible, they

should be connected from the backside through a

network of low-inductance vias.

FDMF6706B • Rev. 1.0.2 16

FDMF6706B - Extra-Small, High-Performance, High-Frequency DrMOS Module

Figure 29. PCB Layout Example

Bottom Vie

Top Vie

FDMF6706B • Rev. 1.0.2 17

FDMF6706B - Extra-Small, High-Performance, High-Frequency DrMOS Module

Physical Dimensions

Figure 30. 40-Lead, Clipbond PQFN DrMOS, 6.0x6.0 mm Package

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the mo st recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the

warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

BOTTOM VIEW

LAND PATTERN

RECOMMENDATION

NOTES: UNLESS OTHERWISE SPECIFIED

A) DOES NOT FULLY CONFORM TO JEDEC

REGISTRATION MO-220, DATED

MAY/2005.

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE BURRS

OR MOLD FLASH. MOLD FLASH OR

BURRS DOES NOT EXCEED 0.10MM.

D) DIMENSIONING AND TOLERANCING PER

ASME Y14.5M-1994.

E) DRAWING FILE NAME: PQFN40AREV3

SEE

DETAIL 'A'

SCALE: 2:1

SEATING

PLANE

0.65

0.40

2.10

0.50 TYP

4.50

5.80

2.50

0.25 1.60

0.60

0.15

2.10

0.35

TOP VIEW

FRONT VIEW

0.30

0.20

0.05

0.00

1.10

0.90

0.10 C

0.08 C

2130

0.40

0.50

(0.70)

0.40

2.00±0.10 2.00±0.10

(0.20) (0.20)

1.50±0.10 0.50

0.30 (40X)

0.20

6.00

0.10 C

0.30

0.20 (40X)

4.40±0.10

0.10 CAB

0.05 C

(2.20)

0.50

10 1

PIN#1

INDICATOR

PIN #1 INDICATOR

MAY APPEAR AS

OPTIONAL

2.40±0.10

FDMF6706B • Rev. 1.0.2 18

FDMF6706B - Extra-Small, High-Performance, High-Frequency DrMOS Module

www.onsemi.com

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent

coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.

ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,

regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer

application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not

designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification

in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized

application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and

expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such

claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This

literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5817−1050

www.onsemi.com

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor

19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

For additional information, please contact your local

Sales Representative