ZL50233QCG1 - Microsemi Corp.

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

Features

• Independent multiple channels of echo

cancellation; from 4 channels of 64 ms to 2

channels of 128 ms with the ability to mix

channels at 128 ms or 64 ms in any combination

• Independent Power Down mode for each group of

2 channels for power management

• Fully compliant to ITU-T G.165, G.168 (2000) and

(2002) specifications

• Passed AT&T voice qu ality testing for carrier

grade echo cancellers .

• Compatible to ST-BUS and GCI interfaces with

2 Mbps serial PCM data

• PCM coding, µ/A-Law ITU-T G.711 or sign

magnitude

• Per channel Fax/Modem G.164 2100 Hz or G.165

2100 Hz phase reversal Tone Disable

• Per channel echo canceller parameters control

• Transparent data transfer and mute

• Fast reconvergence on echo path changes

• Fully programmable convergence speeds

• Patented Advanced Non-Linear P rocessor with

high quality subjective perfo rmance

• Protection against narrow band signal divergence

and instability in high echo environments

• +9 dB to -12 dB level adjusters (3 dB steps) at all

signal ports

• Offset nulling of all PCM channels

• 10 MHz or 20 MHz master clock operation

• 3.3 V I/O pads and 1.8 V Logic core operation with

5 V tolerant inputs

• IEEE-1149.1 (JTAG) Test Access Port

• ZL50232, ZL5023 3, ZL50234 and ZL5023 5 have

same pinouts in both LQFP and LBGA packages

Applications

• Voice over IP network gateways

• Voice over ATM, Frame Relay

• T1/E1/J1 multichannel echo canc ellation

• Wireless base stations

• Echo Canceller pools

• DCME, satellite and multiplexer system

March 2006

Ordering Information

ZL50233/QCC 100 Pin LQFP Trays

ZL50233/GDG 208 Ball LBGA Trays, Bake & Drypack

ZL50233QCG1 100 Pin LQFP* Trays, Bake & Drypack

*Pb Free Mat te Tin

-40°C to +85°C

ZL50233

4 Channel Voice Echo Cancellor

Data Sheet

Figure 1 - ZL50233 Device Overview

RESET

Rout

Sout

DS CS R/W A10-A0 DTA D7-D0

DD1 (3.3 V)

TDI TDO TCK TRSTTMS

Rin

IRQ

C4i

F0i

MCLK

ODE

Sin

Fsel

Test PortMicroprocessor Interface

Timing

Unit

Serial

Parallel

Serial

PLL Note:

Refer to Fig u re 4

for Echo Canceller

block diagram

DD2 (1.8 V)

Echo Canceller Pool

Group 0

ECA/ECB

Group 1

ECA/ECB

ZL50233 Data Sheet

Zarlink Semiconductor Inc.

Description

The ZL50233 Voice Echo Canceller implemen ts a cost effective solution for telephony voice-band echo cancellation

conforming to ITU-T G.168 requirements. The ZL50233 archit ecture contains 2 groups of two echo cancellers (ECA

and ECB) which can be configured to provide two channels of 64 milliseconds or one channel of 128 milliseconds

echo cancellation. This provides 4 channels of 64 milliseconds to 2 channels of 128 milliseconds echo cancellation

or any combination of the two configurations. The ZL50233 supports ITU-T G.165 and G.164 tone disable

requirements.

Figure 2 - 100 Pin LQFP

171197252321193 5 13 151

VSS

R/W

DTA

2 4 6 8 1012141618202224

51525354555657585960616263646566676869707172737475

100

VDD1

VDD2

VSS

A10

VSS

VDD2

VDD1

VSS

PLLVSS2

ODE

Sout

Rout

Sin

VSS

C4ib

Foib

Rin

VDD2

Mclk

fsel

PLLVSS1

PLLVDD

VDD1

TMS

TDI

TDO

TCK

VSS

TRSTB

RESETB

IRQB ZL50233 QC

(100 pin LQFP)

VDD1 = 3.3V VDD2 = 1.8V

VDD1

VSS

IC0

ZL50233 Data Sheet

Zarlink Semiconductor Inc.

Figure 3 - 208 Ball LBGA

12345678910111213

- A1 corner is identified by metallized markings.

14 15 16

VDD2

c4i

F0i Rin SinRout ODE

Sout

MCLK

Fsel

TMSTDI

TCK

RESET IRQ DS CSR/W DTA

D0 D1 D2 D4 D5 D6 D7

A10

ZL50233GD

VDD1

IC0

PLLVSS PLLVDD

IC0 IC0 IC0

IC0 IC0

IC0

IC0 IC0

IC0

IC0 VDD1

VSS

TDO TRST

NC NC

NC NC NC

VSS

VSS VSS

VSS

VSS VSS

VSS VSS VSS VSS

VSS

VSS VSS VSS VSS

VSS

VSS VSS

VSS

VSS VSS VSS VSS

VSS

VSS VSS VSS VSS

VSS

VSS VSS

VSS

VSS VSS VSS

VSS

VDD1

VDD1 VDD1

VDD1

VDD1 VDD1

VDD1

VDD1 VDD1

VDD1

VDD1 VDD1

VDD1

VDD1 VDD1

VDD1

VDD2

VDD2 VDD2

VDD2

VDD2 VDD2

VSS

VSS VSS VSS VSS

VDD1

ZL50233 Data Sheet

Zarlink Semiconductor Inc.

Pin Description

Name

Pin #

Description

208-Ball LBGA 100 Pin

LQFP

VSS A1, A3,A7,A11, A13,

A15, A16, B2, B6, B8,

B12, B14, B15, B16, C3,

C5, C7, C9, C11, C12,

C13, C14, C16, D4, D8,

D10, D12, D13, E3, E4,

E14, F13, G3, G4, G7,

G8, G9, G10, H7, H8,

H9, H10, H13, H14, J7,

J8, J9, J10, K7, K8, K9,

K10, K13, K14, L3, L4,

M13, M14, M15, N3, N4,

N5, N7, N9, N11, N13,

P2, P3, P5, P7, P9,P11,

P13, P14, R2, R14,

R15, R16, T1, T3, T7,

T10, T14, T16

5, 18, 32,

42, 56, 69,

81, 98

Ground.

VDD1 A5, A9, B10, C4, C8,

B4, C10, D3, D5, D7,

D9, D11, D14, E13, F3,

F4, F14, H3, H4, J13,

J14, L13, L14, M3, M4,

N6, N8, N10, N14, N15,

P4, P6, P8, P10, P15,

R4, R6, R8, R10, R12,

T5, T12

27, 48, 77,

100 Positive Power Supply VDD1. Nominally 3.3 V.

VDD2 C6, D6, J3, J4, N12,

P12, G13, G14 14, 37, 64,

91 Positive Power Supply VDD2. No minally 1 .8 V.

IC0 E15, F15, A12, A10, A6,

A2, B1, B3, C1 , C2, D 2,

E2, J2, K2, R1

7, 41, 43,

65, 66, 67,

68, 70, 71,

72, 86, 87,

88, 93, 94

Internal Connection. These pins must be connected to VSS for

normal operation.

NC A14, C15, D1, D15, E1,

F1, G1, G15, H1, H15,

J1, J15, K1,

K15,L1,L15,F2,L2

24, 25, 26,

44, 45, 46,

47, 49, 51,

52, 53, 54,

55, 73, 74,

75, 76, 78,

79, 80, 82,

83, 84, 85,

89, 99, 50

No connection. These pins must be left open for normal

operation.

IRQ R9 9 Interrupt Request (Open Drain Output). This output goes low

when an interrupt occurs in any channel. IRQ returns high when

all the interrupts have been read from the Interrupt FIFO

ZL50233 Data Sheet

Zarlink Semiconductor Inc.

DS R11 10 Data Strobe (Input). This active low input works in conjunction

with CS to enable the read and write operations.

CS R13 11 Chip Select (Input). This active low input is used by a

microprocessor to activate the microprocessor port.

R/W R5 12 Read/Write (Input). This input controls the direction of the data

bus lines (D7-D0) during a microprocessor access.

DTA R7 13 Data Transfer Acknowledgment (Open Drain Output). This

active low output indicates that a data bus transfer is completed.

A pull-up resistor (1 K typical) is required at this output.

D0..D7 T2,T4,T6,T8,T9,T11,

T13,T15 15, 16, 17,

19, 20, 21,

22, 23

Data Bus D0 - D7 (Bidirectional). These pins form the 8 bit

bidirectional data bus of the microprocessor port.

A0..A10 P16,N16,M16,L16,K16,

J16,H16,G16,F16,E16,

D16

28, 29, 30,

31, 33, 34,

35, 36, 38,

39, 40

Address A0 to A10 (Input). These inputs provide the A10 - A0

address lines to the internal registers.

ODE B13 57 Output Drive Enable (Input). This input pin is logically AND’d

with the ODE bit-6 of the Main Control Register. When both ODE

bit and ODE input pin are high, the Rout and Sout ST-BUS

outputs are enabled.

When the ODE bit is low or the ODE input pin is low, the Rout

and Sout ST-BUS outputs are high impedance.

Sout A8 58 Send PCM Signal Output (Output). Port 1 TDM data output

streams. Sout pin outputs serial TDM data streams at

2.048 Mb ps with 4 channels per stream.

Rout B9 59 Receive PCM Signal Output (Output). Port 2 TDM data output

streams. Rout pin outputs serial TDM data streams at

2.048 Mb ps with 4 channels per stream.

Sin B11 60 Send PCM Signal Input (Input). Port 2 TDM data input streams.

Sin pin receives serial TDM data streams at 2.048 Mbps with 4

channels per stream.

Rin B7 61 Receive PCM Signal Input (Input). Port 1 TDM data input

streams. Rin pin receives serial TDM data streams at

2.048 Mb ps with 4 channels per stream.

F0i B5 62 Frame Puls e (Input). This input accepts and automatically

identifies frame synchronization signals formatted according to

ST-BUS or GCI interf ace specific ations.

C4i A4 63 Serial Clock (Input). 4.096 MHz serial clock for shifting data

in/out on the serial streams (Rin, Sin, Rout, Sout).

MCLK G2 90 Master Clock (Input). Nominal 10 MHz or 20 MHz Master Clock

input. May be connected to an async hronous (relative to frame

signal) clock source.

Pin Description (continued)

Name

Pin #

Description

208-Ball LBGA 100 Pin

LQFP

ZL50233 Data Sheet

Zarlink Semiconductor Inc.

1.0 Device Overview

The ZL50233 architecture contains 4 echo cancellers divided into 2 groups. Each group has two echo cancellers,

Echo Canceller A and Echo Canceller B. Each group can be configured in Normal, Extended Delay or Back-to-

Back configurations. In Normal configuration, a group of echo cancellers provides two channels of 64 ms echo

cancellation, which run independently on different channels. In Extended Delay configuration, a group of echo

cancellers achieves 128 ms of echo cancellation by cascading the two echo cancellers (A & B). In Back-to-Back

configuration, the two echo cancellers from the same group are positioned to cancel echo coming from both

directions in a single channel, providing full-duplex 64 ms echo cancellation.

Fsel H2 92 Frequency select (Input). This input selects the Master Clock

frequency operation. When Fsel pin is low, nominal 20 MHz

Master Clock input must be applied. When Fsel pin is high,

nominal 10 MHz Master Clock input must be applied.

PLLVss1

PLLVss2 K3 97, 95 PLL Ground. Must be connected to VSS

PLLVDD K4 96 PLL Power Supply. Must be connected to VDD2 = 1.8 V

TMS M2 1 Test Mode Select (3.3 V Input). JTAG signal that controls the

state transitions of the TAP controller. This pin is pulled high by

an internal pull-up when not driven.

TDI M1 2 Test Serial Data In (3.3 V Input). JTAG serial test instructions

and data are shifted in on this pin. This pin is pulled high by an

internal pull-up when not driven.

TDO N1 3 Test Serial Data Out (Output). JTAG serial data is output on this

pin on the falling edge of TCK. This pin is held in high impeda nce

state when JTAG scan is not enabled.

TCK P1 4 Test Clock (3.3 V Input). Provides the clock to the JTAG test

logic.

TRST N2 6 Test Reset (3.3 V Input). Asynchronously initializes the JTAG

TAP controller by putting it in the Test-Logic-Reset state. This pin

should be pulsed low on power-up or held low, to ensure that the

ZL50233 is in the normal functional mode. This pin is pulled by

an internal pull-down when not driven.

RESET R3 8 Device Reset (Schmitt Trigge r Input). An active l ow rese ts the

device and puts the ZL50 233 into a low-power stand-by mode.

When the RESET pin is re turned to logic high and a clock is

applied to the MCLK pin, the device will automatica lly execute

initialization routines, which preset all the Main Control an d

Status Registers to their default power-up values.

Pin Description (continued)

Name

Pin #

Description

208-Ball LBGA 100 Pin

LQFP

ZL50233 Data Sheet

Zarlink Semiconductor Inc.

Each echo canceller con tains the following main elements (see Figure 4).

• Adaptive Filter for estimating the echo channel

• Subtractor for cancelling the echo

• Double-Talk detector for disabling the filter adaptation during periods of doub le-talk

• Path Change detector for fast reconvergence on major echo path changes

• Instability Detector to combat instability in very low ERL environments

• Patented Advanced Non-Linear P rocessor for suppression of resid ual echo, with comfort no ise injection

• Disable To ne Detectors for dete cting valid d isable tones at send and receive path inputs

• Narrow-Band Detector for preventing Adaptive Filter divergence from na rrow-band signals

• Offset Null filters for removing the DC compon ent in PCM channe ls

• +9 to -12 dB level ad justers at all signal ports

• Parallel controller interface compatible with Motorola microcontrollers

• PCM encoder/decoder compatible with µ/A-Law ITU-T G.711 or Sign-Magnitude coding

Each echo canceller in the ZL50233 has four functional states: Mute, Bypass, Disable Adaptation and Enable

Adaptation. These are explained in the section entitled Echo Can celler Functional States.

Figure 4 - Functional Block Diagram

1.1 Adaptive Filter

The adaptive filter a dapts to the e cho path and generates an estimate of th e echo signal. This echo estimate is then

subtracted from Sin. For each group of echo cancellers, the adaptive filter is a 1024 tap FIR adaptive filter which is

divided into two sections. Each section contains 512 taps providing 64 ms of echo estimation. In Normal

configuration, the first section is dedicated to channel A and the second sec tion to channel B. In Extended Delay

configuration, both sections are cascaded to provide 128 ms of echo estimation in channel A. In Back-to Back

configuration, the first section is used in the receive direction and the second section is used in the transmit

direction for the same channel.

Non-Linear

Processor

Offset

Null Linear/

/A-Law

Microprocessor

Interface

Double - Talk

Detector

Control

Narrow-Band

Detector

/A-Law/

Linear

Offset

Null

Echo Canceller (N), where 0 < N < 3

Sout

Rin

Sin

Rout

Programmable Bypass

(channel N)

MuteR

MuteS

+9 to -12 dB

Level Adjust

Linear/

/A-Law +9 to -12 dB

Level Adjust

+9 to -12 dB

Level Adjust

/A-Law/

Linear +9 to -12 dB

Level Adjust

Adaptive

Filter

Disable Tone

Detector

Disabl e To ne

Detector

Path Change

Instability

Detector

ZL50233 Data Sheet

Zarlink Semiconductor Inc.

1.2 Double-Talk Detector

Double-Talk is defined as those periods of time when signal energy is present in both directions simultaneously.

When this happens, it is necessary to disable the filter adaptation to prevent divergence of the Adaptive Filter

coefficients. Note that when double-talk is detected, the adaptation process is halted but the echo canceller

continues to cancel echo using the previous converged echo profile. A double-talk condition exists whenever the

relative signal levels of Rin (Lrin) and Sin (Lsin) meet the following condition:

Lsin > Lrin + 20log10(DTDT)

where DTDT is the Double-Talk Detection Threshold. Lsin and Lrin are signal levels expressed in dBm0.

A different method is used when it is uncertain whether Sin consists of a low level double-talk signal or an echo

return. During these periods, the adaptation process is slowed down but it is not halted. The slow convergence

speed is set using the Slow sub-register in Control Register 4. During slow convergence, the adaptation speed is

reduced by a factor of 2Slow relative to normal convergence for non-zero values of Slow. If Slow equals zero,

adaptation is halted completely.

In the G.168 standard, the echo return loss is expected to be at least 6 dB. This implies that the Double-Talk

Detector Threshold (DTDT) should be set to 0.5 (-6 dB). However, in order to achieve additional guardband, the

DTDT is set internally to 0.5625 (-5 dB).

In some applications the return loss can be higher or lower than 6 dB. The ZL50233 allows the user to change the

detection threshold to suit each application’s need. This threshold can be set by writing the desired threshold value

into the DTDT register.

The DTDT register is 16 bits wide. The register value in hexadecimal can be calculated with the following equation:

DTDT(hex) = hex(DTDT (dec) * 32768)

where 0 < DTDT(dec) < 1

Example:For DTDT = 0.5625 (-5 dB), the

hexadecimal value becomes

hex(0.5625 * 32768) = 4800hex

1.3 Path Change Detector

Integrated into the ZL50233 is a Path Change Detector. This permits fast reconvergence when a major change

occurs in the echo channel. Subtle changes in the echo channel are also tracked automatically once convergence

is achieved, but at a much slower speed.

The Path Change Detector is activated by setting the PathDet bit in Control Register 3 to “1”. An optional path

clearing feature can be enabled by setting the PathClr bit in Control Register 3 to “1”. With path clearing turned on,

the existing echo channel estimate will also be cleared (i.e. the adaptive filter will be filled with zeroes) upon detection

of a major path change.

ZL50233 Data Sheet

Zarlink Semiconductor Inc.

1.4 Non-Linear Processor (NLP)

After echo cancellation, there is always a small amount of residual echo which may still be audible. The ZL50233

uses Zarlink’s patented Advanced NLP to remove residual echo signals which have a level lower than the

Adaptive Suppression Threshold (TSUP in G.168). This threshold depends upon the level of the Rin (Lrin)

reference signal as well as the programmed value of the Non-Linear Processor Threshold register (NLPTHR).

TSUP can be calculated by the following equation:

TSUP = Lrin + 20log10(NLPTHR)

where NLP THR is the N on-Linear Pro cessor Threshold register value and Lrin is the relative pow er level expressed

in dBm0. The NLPTHR register is 16 bits wide. The register value in hexadecimal can be calculated with the

following equation:

NLPTHR(hex) = hex(NLPTHR (dec) * 32768)

where 0 < NLPTHR(dec) < 1

When the level of residual error signal falls below TSUP, the NLP is activated further attenuating the residual signal

by an additional 30 dB. To prevent a perceived decrease in background noise due to the activation of the NLP, a

spectrally-shaped comfort noise, equivalent in power level to the background noise, is injected. This keeps the

perceived noise level constant. Consequently, the user does not hear the activation and de-activation of the NLP.

The NLP processor can be disabled by setting the NLPDis bit to “1” in Control Register 2.

The comfort noise injector can be disabled by setting the INJDis bit to “1” in Control Register 1. It should be noted

that the NLPTHR is valid and the comfort noise injection is active only when the NLP is enabled.

The patented Advanced NLP provides a number of new and improved features over the original NLP found in

previous generation devices. Differences between the Advanced NLP and the original NLP are summarized in

Table 1.

The NLPSel bit in Control Register 3 selects which NLP is used. A “1” will select the Adv a nc e d NLP, “0” selects the

original NLP. (See page 24 for Control Register 3 bit description)

Feature Register or Bit(s) Advanced

NLP Default

Value

Original NLP

Default Value

NLP Selection NLPSel (Control Register 3) 1 0 (feature

not supported)

Reject uncanceled echo as noise NLRun1 (Control Register 3) 1 0 (feature

not supported)

Reject double-talk as noise NLRun2 (Control Register 3) 1 0 (feature

not supported)

Noise level estimator ramping scheme InjCtrl (Control Register 3) 1 0 (feature

not supported)

Noise level ramping rate NLInc (Noise Control) 5(hex) C(hex)

Noise level scaling Noise Scaling 16(hex) 74(hex)

Table 1 - Comparison of NLP Types

ZL50233 Data Sheet

Zarlink Semiconductor Inc.

The Advanced NLP uses a new noise ramping scheme to quickly and more accurately estimate the background

noise level. The noise ramping method of the original NLP can also be used. The InjCtrl bit in Control Register 3

selects the ramping scheme.

The NLInc sub-register in Noise Control is used to set the ramping speed. When InjCtrl = 1 (such as with the

Advanced NLP), a lower value will give faster ramping. When InjCtrl = 0 (such as with the original NLP), a higher

value will give faster ramping. NLInc is a 4-bit value, so only values from 0 to F(hex) are valid.

The Noise Scaling register can be used to adjust the relative volume of the comfort noise. Lowering this value will

scale the injected noise level down, convers ely, raising the value will scale the comfort noise up. Due to dif ference s

in the noise estimator operation, the Advanced NLP requires a diff erent scaling value than the original NLP.

IMPORTANT NOTE: NLInc and the Noise Scaling register have been pre-programmed with G.168 compliant

values. Changing these values may re sult in undesirable comfort noise performance!

The Advanced NLP also contains safeguards to prevent double-talk and uncancelled echo from being mistaken for

background noise. These features were not present in the original NLP. They can be disabled by setting the

NLRun1 and NLRun2 bit s in Control Register 3 to “0”.

1.5 Disable Tone Detect or

The G.165 recommendation defines the disable tone as havin g the following characteris tics: 210 0 Hz ( ±21 Hz) sine

wave, a power level between -6 to -31 dBm0, and a phase reversal of 180 degrees (± 25 degrees) every

450 ms (±25 ms). If the disable tone is present for a minimum of one second with at least one phase reversal, the

Tone Detector will trigger.

The G.164 recommendation defines the disable tone as a 2100 Hz (+21 Hz) sine wave with a power level between

0 to -31 dBm0. If the disable tone is present for a minimum of 400 ms, with or without phase reversal, the Tone

Detector will trigger.

The ZL50233 has two Tone Detectors per channels (for a total of 8) in order to monitor the occurrence of a valid

disable tone on both Rin and Sin. Upon detection of a disable tone, TD bit of the Status Register will indicate logic

high and an interrupt is generated (i.e. IRQ pin low). Refer to Figure 5 and to the Interrupts section.

Figure 5 - Disable Tone Detection

Once a Tone Detector has been triggered, there is no longer a need for a valid disable tone (G.164 or G.165) to

maintain Tone Detector status (i.e. TD bit high). The Tone Detector status will only release (i.e. TD bit low) if the

signals Rin and Sin fall below -30 dBm0, in the frequency range of 390 Hz to 700 Hz, and below -34 dBm0, in the

frequency range of 700 Hz to 3400 Hz, for at least 400 ms. Whenever a Tone Detector releases, an interrupt is

generated (i.e. IRQ pin low).

The selection between G.165 and G.164 tone disable is controlled by the PHDis bit in Control Register 2 on a per

channel basis. When the PHDis bit is set to “1”, G.164 tone disable requirements are selected.

TD bit

Rin

Sin

Echo Canceller A

Tone Detector

Tone Detector Status reg

ECA

TD bit

Rin

Sin

Echo Canceller B

Tone Detector

Tone Detector Status reg

ECB

ZL50233 Data Sheet

Zarlink Semiconductor Inc.

In response to a valid disable tone, the echo canceller must be switched from the Enable Adaptation state to the

Bypass state. This can be done in two ways, automatically or externally. In automatic mode, the Tone Detectors

internally control the switching between Enable Adaptation and Bypass states. The automatic mode is activated by

setting the AutoTD bit in Control Register 2 to high. In ex ternal mod e, an exte rnal controller is needed to service the

interrupts and poll the TD bits in the Status Registers. Following the detection of a disable tone (TD bit high) on a

given channel, the external controller must switch the echo cance ller from Enable Ada ptation to Bypass state.

1.6 Instability Detector

In systems with very low echo channel return loss (ERL), there may be enough feedback in the loop to cause

stability problems in the adaptive filter. This inst ability can result in variable pitched ringing or oscillation. Should this

ringing occur, th e Instability Detector will activate and suppress the oscillations.

The Instability Detector is activated by setting the RingClr bit in Control Register 3 to “1”.

1.7 Narrow Band Signal Detector (NBSD)

Single or dual frequency tones (i.e. DTMF tones) present in the receive input (Rin) of the echo canceller for a

prolonged period of time may cause the Adaptive Filter to diverge. The Narrow Band Signal Detector (NBSD) is

designed to prevent this by detecting single or dual tones of arbitrary fre quency, phase, and amplitude. When narrow

band signals are detected, adaptation is halted but the echo canceller continues to cancel echo.

The NBSD will be active regardless of the Echo Canceller functional state. However the NBSD can be disabled by

setting the NB Dis bit to “1” in Control Register 2.

1.8 Offset Null Filter

Adaptive filters in general do not operate properly when a DC offset is present at any input. To remove the DC

component, the ZL50233 incorporates Offset Null filters in both Rin and Sin inputs.

The offset null filters can be disabled by setting the HPFDis bit to “1” in Control Register 2.

1.9 Adjustable Level Pads

The ZL50233 provides adjustable level pads at Rin, Rout, Sin and Sout. This setup allows signal strength to be

adjusted both inside and outside the echo path. E ach sig nal level may be independe ntly sca led with anywh ere from

+9 dB to -12 dB level, in 3 dB steps. Level values are set using the Gains register.

CAUTION: Gain adjustment can help interface the ZL502 33 to a particular sys tem in order to provide optimum echo

cancellation, but it can also degrade performance if not done carefully. Excessive loss may cause low signal levels

and slow convergence. Exercise great care when adjusting these values. Also, due to internal signal routings in Back

to Back mode, it is not recommended that gain adjustments be used on Rin or Sout in this mode.

The -12 dB PAD bit in Control Register 1 is still supported as a legacy feature. Setting this bit will provide 12 dB of

attenuation at Rin, and override the values in the Gains register.

1.10 ITU-T G.168 Compliance

The ZL50233 has been certified G.168 (1997), (2000) and (2002) compliant in all 64 ms cancellation modes

(i.e. Normal and Back-to-Back configurations) by in-house testing with the DSPG ECT-1 echo canceller tester.

The ZL50233 has also been tested for G.168 compliance and all voice quality tests at AT&T Labs. The ZL50233

was classified as “carrier grade” echo canceller.

ZL50233 Data Sheet

Zarlink Semiconductor Inc.

2.0 Device Configuration

The ZL50233 architecture contains 4 echo cancellers divided into 2 groups. Each group has two echo cancellers

which can be individually controlled (Echo Canceller A (ECA) and Echo Canceller B (ECB)). They can be set in

three distinct configurations: Normal, Back-to-Back, and Extended Delay. See Figures 6, 7, and 8.

2.1 Normal Configuration

In Normal configuration, the two echo cancellers (Echo Canceller A and B) are positioned in parallel, as shown in

Figure 6, providing 64 milliseconds of echo cancellation in two channels simultaneously.

Figure 6 - Normal Device Configuration (64 ms)

2.2 Back-to-Back Config uration

In Back-to-Back configuration, the two echo cancellers from the same group are positioned to cancel echo coming

from both directions in a single channel providing full-duplex 64 ms echo cancellation. See Figure 7. This

configuration uses only one timeslot on PORT1 and PORT2 and the second timeslot nor mally associated with ECB

contains zero code. Back-to-Back configuration allows a no-glue interface for applications where bidirectional echo

cancellation is required.

Figure 7 - Back-to-Back Device Configuration (64 ms)

Rin

Rout

Sout

Sin

echo

path A

echo

path B

channel A

channel B

ECA

ECB

Adaptive

Filter (64 ms)

Adaptive

Filter (64 ms)

PORT1PORT2

ECA

Sin Sout

Rout Rin

ECB

echo echo

path path

Adaptive

Filter (64 ms)

Adaptive

Filter (64 ms)

PORT1PORT2

ZL50233 Data Sheet

Zarlink Semiconductor Inc.

Back-to-Back configuration is selected by writing a “1” into the BBM bit of Control Register 1 for both Echo

Canceller A and Echo Canceller B for a given group of echo canceller. Table 4 shows the 2 groups of 2 cancellers

that can be configured into Back-to-Back.

Examples of Back-to-Back configuration include positioning one group of echo cancellers between a codec and a

transmission device or between two codecs for echo control on analog trunks.

2.3 Extended Delay Configuration

In this configuration, the two echo cancellers from the same group are internally cascaded into one 128

milliseconds echo canceller. See Figure 8. This configuration uses only one timeslot on PORT1 and PORT2 and

the second timeslot normally associated with ECB contains quiet code.

Figure 8 - Extended Delay Configuration (128 ms)

Extended Delay configuration is selected by writing a “1” into the ExtDl bit in Echo Canceller A, Control Register 1.

For a given group, only Echo Canceller A, Control Register 1, has the ExtDl bit. For Echo Canceller B Control

Table 4 shows the 2 groups of 2 cancellers that can each be config ured into 64 ms or 128 ms echo tail capacity.

3.0 Echo Canceller Functional States

Each echo canceller has four functional states: Mute, Bypass, Disable Adaptation and Enable Adaptation.

3.1 Mute

In Normal and in Extended Delay configurations, writing a “1” into the MuteR bit replaces Rin with quiet code which

is applied to both the Adaptive Filter and Rout. Writing a “1” into the MuteS bit replaces the Sout PCM data with

quiet code.

LINEAR

16 bits

2’s complement

SIGN/

MAGNITUDE

µ-Law

A-Law

CCITT (G.711)

µ-Law A-Law

+Zero

(quiet code) 0000hex 80hex FFhex D5hex

Table 2 - Quiet PCM Code As signment

channel A

ECA

Sin Sout

Rout Rin

echo

path A Adaptive Filter

(128 ms)

PORT1PORT2

ZL50233 Data Sheet

Zarlink Semiconductor Inc.

I n B a ck - t o- B ac k c on f iguration, w r i ti n g a “ 1” i nt o t he M ut e R bit of Echo Canceller A, Control Register 2, causes

quiet code to be transmitted on Rout. Writing a “1” into the MuteS bit of Echo Canceller A, Control Register 2,

causes quiet code to be transmitted on Sout.

In Extended Delay and in Back-to-Back configurations, MuteR and Mu teS bit s of Echo Canceller B must always be

“0”. Refer to Figure 4 and to Control Register 2 for bit description.

3.2 Bypass

The Bypass state directly transfers PCM codes from Rin to Rout and from Sin to Sout. When Bypass state is

selected, the Adaptive Filter coefficie nt s a re reset to zero. Byp ass st ate mu st be selected for at lea st one frame

(125 µs) in order to properly clear the filter.

3.3 Disable Adaptation

When the Disable Adaptation state is selected, the Adaptive Filter coefficients are frozen at their current value. The

adaptation process is halted, however, the echo canceller continues to cancel echo.

3.4 Enable Adaptation

In Enable Adaptation state, the Adaptive Filter coefficients are continually updated. This allows the echo canceller

to model the echo return path characteristics in order to cancel echo. This is the normal operating state.

The echo canceller functions are selected in Control Register 1 and Control Register 2 through four control bits:

MuteS, MuteR, Bypas s and AdaptDis. Refer to the Registers Description for details.

4.0 ZL50233 Throughput Delay

The throughput delay of the ZL50233 varies according to the d evice configura tion. For all device configurations , Rin

to Rout has a delay of two frames and Sin to Sout has a delay of three frames. In Bypass st ate, the Rin to Rout and

Sin to Sout paths have a delay of two frames.

5.0 Serial PCM I/O channels

There are two sets of TDM I/O streams, each with channels numbered from 0 to 31. One set of input streams is for

Receive (Rin) channels, and the other set of input streams is for Send (Sin) channels. Likewise, one set of output

streams is for Rout PCM channels, and the other se t is for Sout channels. See Figure 9 for channel allocation.

The arrangement and connection of PCM channels to each e cho canceller is a 2 port I/O configuration for each set

of PCM Send and Receive channels, as illustrated in Figure 9.

5.1 Serial Data Interface Timing

The ZL50233 provides ST-BUS and GCI interface timing. The Serial Interface clock frequency, C4i, is 4.096 MHz.

The input and output data rate of the ST-BUS and GCI bus is 2.048 Mbps.

The 8 KHz input frame pulse can be in either ST-BUS or GCI format. The ZL50233 automatically detects the

presence of an input frame pulse and ident ifi es i t as eit her ST-BUS or GCI. In ST-BUS format, every second falling

edge of the C4i clock marks a bit boundary, and the data is clocked in on the rising edge of C4i, three quarters of

the way into the bit cell (See Figure 13). In GCI format, every second rising edge of the C4i clock marks the bit

boundary, and data is clocked in on the second falling edge of C4i, half the way into the bit cell (see Figure 14).

ZL50233 Data Sheet

Zarlink Semiconductor Inc.

Figure 9 - ST-BUS and GCI Interface Channel Assignment for 2 Mbps Data Streams

Base

Address + Echo Canceller A Base

Address + Echo Canceller B

Byte LS

Byte MS

Byte LS

Byte

- 00h Con trol Reg 1 - 20h Control Reg 1

- 01h Control Reg 2 - 21h Control Reg 2

- 02h Status Reg - 22h Status Reg

- 03h Reserved - 23h Reserved

- 04h Flat Delay Reg - 24h Flat Delay Reg

- 05h Reserved - 25h Reserved

- 06h Decay Step Size Reg - 26h Decay Step Size Reg

- 07h Decay Step Number - 27h Decay Step Number

- 08h Control Reg 3 - 28h Control Reg 3

- 09h Control Reg 4 - 29h Control Reg 4

- 0Ah Noise Scaling - 2Ah Noise Scaling

- 0Bh Noise Control - 2Bh Noise Control

0Dh 0Ch Rin Peak Detect Reg 2Dh 2Ch Rin Peak Detect Reg

0Fh 0Eh Sin Peak Detect Reg 2Fh 2Eh Sin Peak Detect Reg

11h 10h Error Peak Detect Reg 31h 30h Error Peak Detect Reg

13h 12h Reserved 33h 32h Reserved

15h 14h DTDT Reg 35h 34h DTDT Reg

17h 16h Reserved 37h 36h Reserved

19h 18h NLPTHR 39h 38h NLPTHR

1Bh 1Ah Step Size, MU 3Bh 3Ah Step Size, MU

1Dh 1Ch Gains 3Dh 3Ch Gains

1Fh 1Eh Reserved 3Fh 3Eh Reserved

Table 3 - Memory Mapping of Per Cha nnel Control a nd Status Registers

F0i

Rin/Sin

Rout/Sout

125 µsec

ST-BUS

F0i

GCI interface

Note: Refer to Figure 13 and Figure 14 for timing details.

15.625

sec

1230

Active

Disabled Channels with Random Data

Channels

ZL50233 Data Sheet

Zarlink Semiconductor Inc.

6.0 Memory Mapped Control and Status registers

Internal memory and registers are memory mapped into the address sp ace of the HOST interface. The internal dual

ported memory is mapped into segments on a “per channel” basis to monitor and control each individual echo

canceller and associated PCM channels. For example, in Normal configuration, echo canceller #3 makes use of

Echo Canceller B from group 2. It occupies the internal address sp ace from 060 hex to 07Fhex and interfaces to PCM

channel #3 on all serial PCM I/O streams.

As illustrated in Table 3, the “per channel” registers provide independent control and status bits for each echo

canceller. Figure 10 shows the memory map of the control/status register blocks for all echo cancellers.

When Extended Delay or Back-to-Back configuration is selec ted, Control Register 1 of ECA and ECB and Co ntrol

Table 4 is a list of the channels used for the 16 groups of echo cancellers when they are configured as Extended

Delay or Back-to-Back.

6.1 Normal Configuration

For a given group (group 0 to 1), 2 PCM I/O channels are used. For example, group 1 Echo Cancellers A and B,

channels 2 and 3 are active.

6.2 Extended Delay Configuration

For a given group (group 0 or 1), only one PCM I/O channel is active (Echo Canceller A) and the other channel

carries quiet code. For example, group 0, Echo Canceller A (Channel 0) will be active and Echo Canceller B

(Channel 1) will carry quiet code.

6.3 Back-to-Back Config uration

For a given group (group 0 or 1), only one PCM I/O channel is active (Echo Canceller A) and the other channel

carries quiet code. For example, group 1, Echo Canceller A (Channel 2) will be active and Echo Canceller B

(Channel 3) will carry quiet code.

Group Channels

00, 1

12, 3

Table 4 - Group and Channel allocation

ZL50233 Data Sheet

Zarlink Semiconductor Inc.

Figure 10 - Memory Mapping

6.4 Power Up Sequence

On power up, the RESET pin must be held low for 100 µs . Forcing the RESET pin low will put the ZL50233 in power

down state. In this state, all internal clocks are halted, D<7:0>, Sout, Rout, DTA and IRQ pins are tristated. The 8

Main Control Registers, the Interrupt FIFO Register and the Test Register are reset to zero.

When the RESET pin returns to logic high and a valid MCLK is applied, the user must wait 500 µs for the PLL to

lock. C4i and F0i can be active during this period. At this point, the echo canceller must have the internal registers

reset to an initial state. This is accomplished by one of two methods. The user can either issue a second hardware

reset or perform a software reset. A second hardware reset is performed by driving the RESET pin low for at least

500ns and no more than 1500ns before being released. A software reset is accomplished by programming a “1” to

each of the PWUP bits in the Main Control Registers, waiting 250 µs (2 frames) and then programming a “0” to

each of the PWUP bits.

The user must then wait 500 µs for the PLL to relock. Once the PLL has locked, the user can power up the 16

groups of echo cancellers individually by writing a “1” into the PWUP bit in Main Control Register of each echo

canceller group.

For each group of echo cancellers, when the PWUP bit toggles from zero to one, echo cancellers A and B execute

their initialization routine. The initialization routine sets their registers, Base Address+00hex to Base Address+3 Fhex,

to the default Reset Value and clears the Adaptive Filter co efficients. Two frames are necessary for the initialization

routine to execute properly.

Once the initialization routine is executed, the us er c an set the per channel Co ntrol Reg isters, Ba se Address+00hex

to Base Address+3Fhex, for the specific application.

0000h -->

Channel 0, ECA Ctrl/Stat Registers 001Fh

0020h -->

Channel 1, ECB Ctrl/Stat Registers 003Fh

0040h -->

Channel 2, ECA Ctrl/Stat Registers 005Fh

0060h -->

Channel 3, ECB Ctrl/Stat Registers 007Fh

0400h --> 0407h

Main Control Registers <7:0>

Group 0

Echo

Cancellers

Registers

Group 1

Echo

Cancellers

Registers

0410h

Interrupt FIFO Register

0411h

Test Register

0412h ---> FFFFh

Reserved Test Register

ZL50233 Data Sheet

Zarlink Semiconductor Inc.

Figure 11 - Power Up Sequence Flow Diagram

6.5 Power management

Each group of echo cancellers can be placed in Power Down mode by writing a “0” into the PWUP bit in their

respective Main Control Register. When a given group is in Power Down mode, the corresponding PCM data are

bypassed from Rin to Rout and from Sin to Sout with two frames delay. Refer to the Main Control Register section

for description.

The typical power consumption can be calculated with the following equation:

PC = 9 * Nb_of_groups + 3.6, in mW

where 0 ≤ Nb_of_groups ≤ 2.

6.6 Call Initialization

To ensure fast initial convergence on a new call, it is important to clear the Adaptive Filter. This is done by putting

the echo canceller in bypass mode for at least one frame (125 µs) and then enabling adaptation.

Since the Narrow Band De tector is “ON” regardless o f the functiona l st ate of Echo Can celler it is recommended that

the Echo cancellers are reset before any call progress tones are applied.

System Powerup

Delay 100µs

Reset Held Low

Reset High

MCLK Active

Delay 500µs

Reg. Reset Software

Hardware

Reset Low

Delay 1000ns

Reset High

PWUP to “1”

Delay 250µs

PWUP to “0”

Delay 500µs

ECAN Ready

ZL50233 Data Sheet

Zarlink Semiconductor Inc.

6.7 Interrupts

The ZL50233 provides an interrupt pin (IRQ) to indicate to the HOST processor when a G.164 or G.165 Tone

Disable is detected and released.

Although the ZL50233 may be configured to react automatically to tone disable status on any input PCM voice

channels, the user may want for the external HOST processor to respond to Tone Disable information in an

appropriate application-specific manner.

Each echo canceller will generate an interrupt when a Tone Disable occurs and will generate another interrupt

when a Tone Disable releases.

Upon receiving an IRQ, the HOST CPU should read the Interrupt FIFO Register. This register is a FIFO memory

containing the channel number of the echo canceller that has generated the interrupt.

All pending interrupts from any of the echo cancellers and their associated input channel number are stored in this

FIFO memory. The IRQ always returns high after a read access to the Interrupt FIFO Register. The IRQ pin will

toggle low for each pending interrupt.

After the HOST CPU has received the channel number of the interrupt source, the corresponding per channel

Status Register can be read from internal memory to determine the cause of the interrupt (see Table 3 for address

mapping of Status register). The TD bit indicates the presence of a Tone Disable.

The MIRQ bit 5 in the Main Control Register 0 masks interrupts from the ZL50233. To provide more flexibility, the

MTDBI (bit-4) and MTDAI (bit-3) bits in the Main Control Register<3:0> allow Tone Disable to be masked or

unmasked from generating an interrupt on a per channel basis. Refer to the Registers Description section.

7.0 JTAG Support

The ZL50233 JTAG interface conforms to the Boundary-Scan standard IEEE1149.1. This standard specifies a

design-for-testability technique called Boundary-Scan test (BST). The operation of the Boundary Scan circuitry is

controlled by an Test Access Port (TAP) controller. JTAG inputs are 3.3 Volts compliant only.

7.1 Test Access Port (TAP)

The TAP provides access to many test functions of the ZL50233. It consists of four input pins and one output pin.

The following pins are found on the TAP.

• Test Clock Input (TCK)

The TCK provides the clock for the te st logic. The TCK do es not interfere with any on-chip clock and thus

remains independent. The TC K permits shifting of test data into or out of the Boundary-Scan register cells

concurrent with the operation of the devic e and without interfering with the on-ch ip logic.

• Test Mode Se lect Input (TMS)

The logic signals receive d at the TMS in put are interpreted by the TAP Controller to control the test

operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to

VDD1 when it is not driven from an external source.

• Test Data Input (TDI)

Serial input data applied to this port is fed either into the instruction register or into a test data register,

depending on the sequ ence previously applie d to th e TMS input. Both registers are described in a

subsequent section. T he received inp ut data is sampled at the rising edge of TCK pulses. Th is pin is

internally pulled to VDD1 when it is not driven from an exte rnal source.

• Test Data Output (TDO)

Depending on the sequ ence previously applied to th e TMS input, the contents of either the in struction

falling edge of the TCK pulses. When no data is shifted through the Boundary Scan cells, the TDO driver is

set to a high impedance state.

ZL50233 Data Sheet

Zarlink Semiconductor Inc.

• Test Reset (T RST)

This pin is used to reset the JTAG scan structure. This pin is internally pulled to VSS.

7.2 Instruction Register

In accordance with the IEEE 1149.1 standard, the ZL50233 uses public instruction s. The JTAG Interface contains a

3-bit instruction register. Instructions are serially loaded into the instruction register from the TDI when the TAP

Controller is in its shifted-IR state. Subsequently, the instructions are decoded to achieve two basic functions: to

select the test data register th at will operate while the instruction is curren t, and to define the serial test dat a register

path, which is used to shift data between TDI and TDO during data register scanning.

7.3 Test Data Registers

As specified in IEEE 1149.1, the ZL50233 JTAG Interface contains three test data registers:

• Boundary-Scan register

The Boundary-Scan register consists of a series of Boundary-Scan cells arran ged to form a scan path

around the boundary of the ZL50233 core lo gic.

• Bypass Register

The Bypass register is a single stage shift register that provides a one-bit path from TDI to TDO.

• Device Identification register

The Device Identification register provides access to the fo llowing e ncode d in form ation:

device version number, part number and manufacturer's name.

8.0 Register Description

Echo Canceller A (ECA): Control Register 1

Power-up 00hex R/W Address: 00hex + Base Address

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset INJDis BBM PAD Bypass AdpDis 0 ExtDI

Functional Description of Register Bits

Reset When high, the power-up initialization is executed. This presets all register bits including this bit

and clears the Adaptive Filter coefficients.

INJDis When high, the noise injection process is disabled. When low noise injection is enabled.

BBM When high, the Back to Back configuration is enabled. When low, the Normal configuration is

enabled. Note: Do not enable Extended-Delay and BBM configurations at the same time. Always

set both BBM bits of the two echo cancellers (Control Registe r 1) of the same group to the same

logic value to avoid conflict.

PAD When high, 12 dB of attenuation is inserted into the Rin to Rout path. When low, the Gains

Bypass When high, Sin data is by-passed to Sout and Rin data is by-passed to Rout. The Adaptive Filter

coef ficients are set to zero and the filter adaptation is stopped. When low, output data on both

Sout and Rout is a function of the echo canceller algorithm.

AdpDis When high, echo canceller adaptation is disabled. The Voice Processor cancels echo.

When low, the echo canceller dynamically adapts to the echo path characteristics.

0 Bits marked as “1 ” or “0 ” ar e reserved bi ts and sh ou ld be written as indicated .

ExtDl When high, Echo Cancellers A and B of the same group are internally cascaded into one 128 ms

echo canceller. When low, Echo Cancellers A and B of the same group operate independently.

ZL50233 Data Sheet

Zarlink Semiconductor Inc.

Note: In order to correctly write to Control Register 1 and 2 of ECB, it is necessary to write the data twice to the register, one

immediately after another. The two writes must b e separated by at least 350 ns and no mor e than 20 us.

Echo Canceller B (ECB): Control Register 1

Power-up 02hex R/W Address: 20hex + Base Address

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset INJDis BBM PAD Bypass AdpDis 1 0

Functional Description of Register Bits

Reset When high, the power-up initialization is executed which presets all register bits including this bit

and clears the Adaptive Filter coefficients.

INJDis When high, the noise injection process is disabled. When low, noise injection is enabled.

BBM When high, the Back to Back configuration is enabled. When low, the Normal configuration is

enabled. Note: Do not enable Extended-Delay and BBM configuration s at the s ame time. Always

set both BBM bits of the two echo cancellers (Control Reg ister 1) of the sa me group to the s ame

logic value to avoid conflict.

PAD When high, 12 dB of attenuation is inserted into the Rin to Rout path. When low, the Gains

Bypass When high, Sin data is by-passed to Sout and Rin data is by-passed to Rout. The Adaptive Filter

coeffic ie nts are set to zero and the filter adaptation is stopped. When low, output data on both

Sout and Rout is a function of the echo canceller algorithm.

AdpDis When high, echo canceller adaptation is disabled. The Voice Processor cancels echo.

When low, the ech o canceller dynamically adapts to the echo path characteristics.

1 Bits marked as “1” or “0” are reserved bits and should be written as indicated.

0 Control Register 1 (Echo Canceller B) Bit 0 is a reserved bit and should be written “0”.

Power-up

00hex

ECA: Control Register 2 R/W Address:

01hex + Base Address

ECB: Control Register 2 R/W Address:

21hex + Base Address

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TDis PHDis NLPDis AutoTD NBDis HPFDis MuteS MuteR

Functional Description of Register Bits

TDis When high, tone detection is disabled. When low, tone detection is enabled. When both Echo

Cancellers A and B TDis bits are high, Tone Disable processors are disabled entirely and are put

into Power Down mode.

PHDis When high, the tone detectors will trigger upon the presence of a 2100 Hz tone regardless of the

presence/absence of periodic phase reversals. When low, the tone detectors will trigger only upon

the presence of a 2100 Hz tone with periodic phase reversals.

NLPDis When high, the non-linear processor is disabled. When low, the non-linear processors function

normally. Useful for G.165 conformance testing.

AutoTD When high, the echo canceller puts itself in Bypass mode when the tone detectors detect the

presence of 2100 Hz tone. See PHDis for qualification of 2100 Hz tones.

When low, the echo canceller algorithm will remain operational regardless of the state of the

2100 Hz tone detectors.

NBDis When high, the narrow-band detector is disabled. When low, the narrow-band detector is enabled.

HPFDis When high, the offset nulling high pass filters are bypassed in the Rin and Sin paths. When low,

the offset nulling filters are active and will remove DC offsets on PCM input signals.

MuteS When high, data on Sout is muted to quiet code. When low, Sout carries active code.

MuteR When high, data on Rout is muted to quiet code. When low, Rout carries active code.

ZL50233 Data Sheet

Zarlink Semiconductor Inc.

Power-up

00hex

ECA: Status Register Read Address:

02hex + Base Address

ECB: Status Register Read Address:

22hex + Base Address

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reserve TD DTDet Reserve Reserve Reserve TDG NB

Functional Description of Register Bits

Reserve Reserved bit

TD Logic high indicates th e presence of a 2100Hz tone

DTDet Logic high indicates the presence of a double-talk condition

Reserve Reserved bit

TDG Tone detection status bit gated with the AutoTD bit. (Control Register 2)

Logic high indicates that AutoTD has been enabled and the tone detector has detected the

presence of a 2100Hz tone.

NB Logic high indicates the presence of a narrow-band signal on Rin

Power-up

00hex

ECA: Flat Delay Register (FD) R/W Address:

04hex + Base Address

ECB: Flat Delay Register (FD) R/W Address:

24hex + Base Address

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0

Power-up

00hex

ECA: Decay Step Number Register (NS) R/W Address:

07hex + Base Address

ECB: Decay Step Number Register (NS) R/W Address:

27hex+ Base Address

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

NS7 NS6 NS5 NS4 NS3 NS2 NS1 NS0

Power-up

04hex

ECA: Decay Step Size Con trol Register (SSC) R/W Address:

06hex + Base Address

ECB: Decay Step Size Con trol Register (SSC) R/W Address:

26hex + Base Address

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

00000SSC2SSC1SSC0

Note: Bits marked with “0” are reserved bits and should be written “0”

ZL50233 Data Sheet

Zarlink Semiconductor Inc.

Figure 12 - The MU Profile

9.0 Functional Description of Register Bits

The Exponential Decay registers (Deca y Step Number and Decay Step Size) an d Flat De lay register allow the LMS

adaptation step-s ize (MU) to be programmed over the length of the FIR filter. A programmable MU profile allows the

performance of the echo canceller to be optimized for specific applications. For example, if the characteristic of the

echo response is known to have a flat delay of several milliseconds and a roughly exponential decay of the echo

impulse response, then th e MU profile can be prog rammed to approx imate this expected impulse resp onse the reby

improving the convergence characteristics of the Adaptive Filter. Note that in the following register descriptions, one

tap is equivalent to 125 µs (64 ms/512 t aps).

FD7-0 Flat Delay: This register defines the flat delay of the MU profile, (i.e., where the MU value is 2 -16). The dela y

is defined as FD7-0 x 8 taps. For example; If FD7-0 = 5, then MU=2-16 for the first 40 taps of the echo

canceller FIR filter. The valid range of FD7-0 is: 0 ≤ FD7-0 ≤ 64 in normal mode and 0 ≤ FD7-0 ≤ 128 in

extended-delay mode. The default value of FD7-0 is zero.

SSC2-0 Decay Step Size Control: This register controls the step size (SS) to be used during the exponen tial decay

of MU. The decay rate is defined as a decrease of MU by a factor of 2 every SS taps of the FIR filter,

where SS = 4 x2SSC2-0. For example; If SSC2-0 = 4, th en MU is reduce d by a factor of 2 every 64 taps of

the FIR filter. The default va lue of SSC2-0 is 04hex.

NS7-0 Decay Step Number: This register defines the number of steps to be used for the decay of MU where each

step has a period of SS ta ps (see SSC2-0). The start of the exponential decay is defined as: Filter Length

(512 or 1024) - [Decay Step Number (NS7-0) x Step Size (SS)] where SS = 4 x2SSC2-0.

For example; If NS7-0=4 and SSC2-0=4, then the exponential decay start value is 512 - [NS7-0 x SS] =

512 - [4 x (4x24)] = 256 taps for a filter length of 512 taps.

Amplitude of MU

Time

Flat Delay (FD7-0)

Step Size (SS)

1.0

2-16

FIR Filter Length (512 or 1024 taps)

Number of Steps (NS7-0)

ZL50233 Data Sheet

Zarlink Semiconductor Inc.

Power-up

FBhex

ECA: Control Register 3 R/W Address:

08hex + Base Address

ECB: Control Register 3 R/W Address:

28hex + Base Address

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

NLRun2 InjCtrl NLRun1 RingClr Reserve PathClr PathDet NLPSel

Functional Description of Register Bits

NLRun2 When high, the comfort noise level estimator activ ely rejects double-talk as being background

noise. When low, the noise level estimator makes no such distinction.

InjCtrl Selects which noise ramping scheme is used. See Table below.

NLRun1 When high, the comfort noise level estimator actively rejects uncance lled echo as being

background noise. When low, the noise level estimator makes no such distinction.

RingClr When high, the instability detector is activated. When low, the instability detector is disabled.

Reserve Reserved bit. Must always be set to one for normal operation.

PathClr When high, the current echo channel estimate will be cleared and the echo canceller will enter fast

convergence mode upon detection of a path change. When low, the echo canceller will keep the

current path estimate but revert to fast convergence mod e upon detection of a path c hange. Note:

this bit is ignored if PathDet is low.

PathDet When high, the path cha nge detector is activated. When low, th e path change detector is disabled.

NLPSel When high, the Advanced NLP is selected. When low, the original NLP is selected. See Table 1 on

page 9.

Power-up

54hex

ECA: Control Register 4 R/W Address:

09hex + Base Address

ECB: Control Register 4 R/W Address:

29hex + Base Address

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 SD2 SD1 SD0 0 Slow2 Slow1 Slow0

Functional Description of Register Bits

0 Must be set to zero.

SupDec These three bits (SD2,SD1,SD0) control how long the echo canceller remains in a fast

convergence state following a path change, Reset or Bypass operation. A value of zero will keep

the echo canceller in fast convergence indefinitely.

0 Must be set to zero.

Slow Slow converge nce mode sp e ed adjustment.(Bits Slow2, Slow1,Slow0)

For Slow = 1, 2, ..., 7, slow convergence speed is reduced by a factor of 2Slow as compared to

normal adaptation.

For Slow = 0, no adaptation occurs during slow convergence.

ZL50233 Data Sheet

Zarlink Semiconductor Inc.

Power-up

16hex

ECA: Noise Scaling (NS) R/W Address:

0Ahex + Base Address

ECB: Noise Scaling (NS) R/W Address:

2Ahex + Base Address

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

NS7 NS6 NS5 NS4 NS3 NS2 NS1 NS0

Functional Description of Register Bits

This register is used to scale the comfort noise up or down. Larger values will increase the relative level of

comfort noise. The default value of 16hex will provide G.168 compliance with the Advanced NLP. A va lue of 74hex

is recommended if the original NLP is used.

Power-up

45hex

ECA: Noise Control R/W Address:

0Bhex + Base Address

ECB: Noise Control R/W Address:

2Bhex + Base Address

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reserve Reserve Reserve Reserve NLInc3 NLInc2 NLInc1 NLInc0

Functional Description of Register Bits

Reserve Reserved bits. Must be set to 4hex for normal operation.

NLInc Noise level estimator ramping rate. When InjCtrl = 1, a lower value will give faster ramping.

When InjCtrl = 0, a higher value will give faster ramping. The default value of 5hex will provide

G.168 comp liance with InjCtrl = 1. A valu e of Chex is recommended if InjCtrl = 0.

Power-up

N/A

ECA: Rin Peak Detect Register 2 (RP) Read Address:

0Dhex + Base Address

ECB: Rin Peak Detect Register 2 (RP) Read Address:

2Dhex + Base Address

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

RP15 RP14 RP13 RP12 RP11 RP10 RP9 RP8

Power-up

N/A ECA: Rin Peak Detect Register 1 (RP) Read Address:

0Chex + Base Address

ECB: Rin Peak Detect Register 1 (RP) Read Address:

2Chex + Base Address

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

RP7 RP6 RP5 RP4 RP3 RP2 RP1 RP0

Functional Description of Register Bits

These peak detector regis te rs allow the user to monitor the receive in (Rin) peak signal level. The information is

in 16-bit 2’s complement linear coded format presented in two 8 bit registers for each echo canceller. The high

byte is in Register 2 and the low byte is in Register 1.

ZL50233 Data Sheet

Zarlink Semiconductor Inc.

Power-up

N/A

ECA: Sin Peak Detect Register 2 (SP) Read Address:

0Fhex + Base Address

ECB: Sin Peak Detect Register 2 (SP) Read Address:

2Fhex + Base Address

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8

Power-up

N/A ECA: Sin Peak Detect Register 1 (SP) Read Address:

0Ehex + Base Address

ECB: Sin Peak Detect Register 1 (SP) Read Address:

2Ehex + Base Address

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0

Functional Description of Register Bits

These peak detector registers allow the user to monitor the send in (Sin) peak signal level. The information is in

16-bit 2’ s complement linea r coded format presented in two 8 bit registers for each echo canceller. The high byte

is in Register 2 and the low byte is in Register 1.

Power-up

N/A

ECA: Error Peak Detect Register 2 (EP) Read Address:

11hex + Base Address

ECB: Error Peak Detect Register 2 (EP) Read Address:

31hex + Base Address

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

EP15 EP14 EP13 EP12 EP11 EP10 EP9 EP8

Power-up

N/A

ECA: Error Peak Detect Register 1 (EP) R/W Address:

10hex + Base Address

ECB: Error Peak Detect Register 1 (EP) R/W Address:

30hex + Base Address

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0

Functional Description of Register Bits

These peak detector registers allow the use r to monitor the error signal peak level. The information is in 16-bit

2’s complement linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in

ZL50233 Data Sheet

Zarlink Semiconductor Inc.

Power-up

48hex

ECA: Double-Talk Detection Threshold Register 2 R/W Address:

15hex + Base Address

ECB: Double-Talk Detection Threshold Register 2 R/W Address:

35hex + Base Address

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

DTDT15 DTDT14 DTDT13 DTDT12 DTDT11 DTDT10 DTDT9 DTDT8

Power-up

00hex

ECA: Double-Talk Detection Threshold Register 1 R/W Address:

14hex + Base Address

ECB: Double-Talk Detection Threshold Register 1 R/W Address:

34hex + Base Address

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

DTDT7 DTDT6 DTDT5 DTDT4 DTDT3 DTDT2 DTDT1 DTDT0

Functional Description of Register Bits

This register allows the user to program the level of Double-Talk Detection Threshold (DTDT). The 16 bit 2’s

complement linear value defaults to 4800hex= 0.5625 or -5 dB. The maximum value is 7FFFhex = 0.9999 or

0 dB. The high byte is in Register 2 and the low byte is in Register 1.

Power-up

0Chex

ECA: Non-Linear Processor Threshold Register 2

(NLPTHR) R/W Address:

19hex + Base Address

ECB: Non-Linear Processor Threshold Register 2

(NLPTHR) R/W Address:

39hex + Base Address

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

NLP15 NLP14 NLP13 NLP12 NLP11 NLP10 NLP9 NLP8

Power-up

E0hex

ECA: Non-Linear Processor Threshold Register 1

(NLPTHR) R/W Address:

18hex + Base Address

ECB: Non-Linear Processor Threshold Register 1

(NLPTHR) R/W Address:

38hex + Base Address

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

NLP7 NLP6 NLP5 NLP4 NLP3 NLP2 NLP1 NLP0

Functional Description of Register Bits

This register allows the user to program the level of the Non-Linear Processor Threshold (NLPTHR). The 16 bit

2’s complement linear value defaults to 0CE0hex = 0.1 or -20.0 dB. The maximum value is 7FFFhex = 0.9999 or

0 dB. The high byte is in Register 2 and the low byte is in Register 1.

ZL50233 Data Sheet

Zarlink Semiconductor Inc.

Power-up

40hex

ECA: Adaptation Step Size Register 2 (MU) R/W Address:

1Bhex + Base Address

ECB: Adaptation Step Size Register 2 (MU) R/W Address:

3Bhex + Base Address

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MU15 MU14 MU13 MU12 MU11 MU10 MU9 MU8

Power-up

00hex

ECA: Adaptation Step Size Register 1 (MU) R/W Address:

1Ahex + Base Address

ECB: Adaptation Step Size Register 1 (MU) R/W Address:

3Ahex + Base Address

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MU7 MU6 MU5 MU4 MU3 MU2 MU1 MU0

Functional Description of Register Bits

This register allows the user to program the level of MU. MU is a 16 bit 2’ s complement value which defaults to

4000hex = 1.0 The maximum value is 7FFFhex or 1 .9999 decimal. The high byte is in Regis ter 2 and the low byte

is in Register 1.

Power-up

44hex

ECA: Gains Register 2 R/W Address:

1Dhex + Base Address

ECB: Gains Register 2 R/W Address:

3Dhex + Base Address

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 Rin2 Rin1 Rin0 0 Rout2 Rout1 Rout0

Power-up

44hex

ECA: Gains Register 1 R/W Address:

1Chex + Base Address

ECB: Gains Register 1 R/W Address:

3Chex + Base Address

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 Sin2 Sin1 Sin0 0 Sout2 Sout1 Sout0

Functional Description of Register Bits

This register is used to sele ct gain values on RIN, ROU T, SIN and SOUT.

Gains is split into four groups of four bits. Each group maps to a different signal port (as indicated above), and

has three gain bits. The following table indicates how these gain bits are used:

Bit2 Bit1 Bit0 Gain Level

1 1 1 +9 dB

1 1 0 +6 dB)

1 0 1 +3 dB

1 0 0 0 dB (default)

0 1 1 -3 dB

0 1 0 -6 dB

0 0 1 -9 dB

0 0 0 -12 dB

Note that the -12 dB PAD bit in Control Register 1 provides 12 dB of attenuation in the Rin to Rout path, and will

override the settings in Gains.

ZL50233 Data Sheet

Zarlink Semiconductor Inc.

Main Control Register 0 (EC Group 0)

Power-up 00hex R/W Address : 400hex

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

WR_all ODE MIRQ MTDBI MTDAI Format Law PWUP

Functional Description of Register Bits

WR_all Write all control bit: When high, Group 0 and 1 Echo Cancellers Registers are mapped into

0000hex to 0003Fhex which is Group 0 address mapping. Useful to initialize the 2 Groups of Echo

Cancellers as per Group 0. When low, address mapping is per Figure 10. Note: Only the Main

Control Register 0 has the WR_all bit.

ODE Output Data Enable: This contro l bit is logic ally AND’d with the ODE input pin. Wh en both ODE bit

and ODE input pin are high, the Rout and Sout outputs are enabled. When the ODE bit is low or

the ODE input pin is low, the Rout and Sout outputs are high impedance. N ote: Only the Main

Control Register 0 has the ODE bit.

MIRQ Mask Interrupt: When high, all the interrupt s from the Tone Detectors output are masked. The Tone

Detectors operate as specified in their Echo Cancelle r B, Control Register 2.

When low, the Tone Detectors Interrupts are active.

Note: Only the Main Control Register 0 has the MIRQ bit.

MTDBI Mask Tone Detector B Interrupt: When high, the Tone Detector interrupt output fro m Echo

Canceller B is masked. The Tone Detector operates as specified in Echo Canceller B, Control

MTDAI Mask Tone Detector A Interrupt: When high, the Tone Detector interrupt output fro m Echo

Canceller A is masked. The Tone Detector operates as specified in Echo Canceller A, Control

Format ITU-T/Sign Mag: When high, both Echo Cancellers A and B for a given group, accept ITU-T

(G.711) PCM code. When low, both Echo Cancellers A and B for a given group, accept sign-

magnitude PCM code.

Law A/µ Law: When high, both Echo Cancellers A and B for a given group, accept A-Law companded

PCM code. When low, both Echo Cancellers A and B for a give n group, acc ept µ-Law comp ande d

PCM code.

PWUP Power-UP: When high, both Echo Cancellers A and B and Tone Detectors for a given group, are

active. When low, both Echo Canc ellers A an d B a nd Tone Detectors for a given grou p, are placed

in Power Down mode. In this mode, the corresponding PCM data are bypassed from Rin to Rout

an d fr o m S i n t o S out w i t h t wo f r a m es d e l ay. When the PWUP bit toggles from zero to one, the

echo canceller A and B execute their initialization routine which presets their registers, Base

Address+00hex to Base Address+3Fhex, to default power up value and clears the Adaptive Filter

coefficients. Two frames are neces sary for the initialization routine to execute properly. Once the

initialization routine is executed, the user can set the per channel Control Registers for their

specific application.

ZL50233 Data Sheet

Zarlink Semiconductor Inc.

Main Control Register 1 (EC Group 1) R/W Address: 401hex

Power-up 00hex

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Unused Unused Unused MTDBI MTDAI Format Law PWUP

Functional Description of Register Bits

Unused Unused Bits.

MTDBI Mask Tone Detector B Interrupt: When high, the Tone Detector interrupt output from Echo Canc eller

B is masked. The Tone Detector operates as specified in Echo Canceller B, Control Register 2.

When low, the Tone Detector B Interrupt is active.

MTDAI Mask Tone Detector A Interrupt: When high, the Tone Detector interrupt output from Echo Canc eller

A is masked. The Tone Detector operates as specified in Echo Canceller A, Control Register 2.

When low, the Tone Detector A Interrupt is active.

Format ITU-T/Sign Mag: When high, both Echo Cancellers A and B for a given group, select ITU-T (G.711)

PCM code. When low, both Echo Cancellers A and B for a given group , select sign-magnitude PCM

code.

Law A/µ Law: When high, both Echo Cancellers A and B for a given group, select A-Law companded

PCM code. When low, both Echo Cancellers A and B for a given group, select µ-Law companded

PCM code.

PWUP Power-UP: When high, both Echo Cancellers A and B and Tone Detectors for a given group, are

active. When low, both Echo Cancellers A and B and Tone Detectors for a given group, are placed

in Power Down mode. In this mode, the corresponding PCM data are bypassed from Rin to Rout

and from Sin to Sout with two frames delay. When the PWUP bit toggles from zero to one, the

echo cancellers A and B execute their initialization routine which presets their registers, Base

Address+00hex to Base Address+3Fhex, to default Reset Value and clears the Adaptive Filter

coef ficients. Two frames are necessary for the initialization routine to execute properly. Once the

initialization routine is executed, the user can set the per c hannel Control Re gisters for their spec ific

application.

Interrupt FIFO Register

Power-up 00hex R/W Address : 410hex

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

IRQ Unused Unused I4 I3 I2 I1 I0

Functional Description of Register Bits

IRQ Logic high indicates an interrupt has occurred. IRQ bit is cleared af ter the Interrupt FIFO register is

read. Logic Low indicates that no interrupt is pendi ng and the FIFO is empty.

Unused Unused bit.

I<4:0> I<4:0> binary code indicates the channel number at which a Tone Detector state change has

occurred. Note: Whenever a Tone Disable is detected or released, an interrupt is generated.

ZL50233 Data Sheet

Zarlink Semiconductor Inc.

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

† Characteristics are over recommended operating conditions unless otherwise stated.

‡ Typical figures are at 25°C, VDD1 =3.3 V and are for design aid only: not guaranteed and not subject t o production testing .

* Note 1: Maximum leakage on pins (output or I/O pins in high impedance state) is over an app lied voltage (VIN).

Absolute Maximum Ratings*

Parameter Symbol Min. Max. Units

1 I/O Supply Volt age (VDD1)V

DD_IO -0.5 5.0 V

2 Core Supply Voltage (VDD2)V

DD_CORE -0.5 2.5 V

3 Input Voltage VI3 VSS - 0.5 VDD1+0.5 V

4 Input Voltage on any 5 V Tolerant I/O pins VI5 VSS - 0.3 7.0 V

5 Continuous Current at digital output s Io20 mA

6 Package power dissipation PD2W

7 Storage temperature TS-55 150 °C

Recommended Operating Conditions - Voltages are with respect to ground (Vss) unless otherwise stated

Characteristics Sym. Min. Typ.‡Max. Units

1 Operating Temperature TOP -40 +85 °C

2 I/O Supply Voltage (VDD_IO)V

DD1 3.0 3.3 3.6 V

3 Core Supply Voltage (VDD_CORE)V

DD2 1.6 1.8 2.0 V

4 Input High Voltage on 3.3 V tolerant I/O VIH3 0.7VDD1 VDD1 V

5 Input High Voltage on 5 V tolerant I/O pins VIH5 0.7VDD1 5.5 V

6 Input Low Voltage VIL 0.3VDD1 V

DC Electrical Characteristics† - Voltages are with respect to ground (Vss) unless otherwise stated.

Characteristics Sym. Min. Typ.‡Max. Units Test Conditions

Static Supply Current ICC 250 µA RESET = 0

IDD_IO (VDD1 = 3.3 V) IDD_IO 5 mA All 4 channels active

IDD_CORE (VDD2 = 1.8 V) IDD_CORE 13 mA All 4 channels active

2 Power Consumption PC40 mW All 4 channels active

3 Input High Voltage VIH 0.7VDD1 V

4 Inpu t Low Voltage VIL 0.3VDD1 V

5 Input Leakage

Input Leakage on Pullup

Input Leakage on Pulldown

IIH/IIL

ILU

ILD

-30

-55

µA

VIN=VSS to VDD1or 5.5 V

VIN=VSS

VIN=VDD1

See Note 1

6 Input Pin Capacitance CI10 pF

Output High Voltage VOH 0.8VDD1 VI

OH = 12 mA

8 Output Low Voltage VOL 0.4 V IOL = 12 mA

9 High Impedance Leakage IOZ 10 µAV

IN=VSS to 5.5 V

10 Output Pin Capacitance CO10 pF

ZL50233 Data Sheet

Zarlink Semiconductor Inc.

† Characteristics are over recommended operating conditions unless otherwise stated.

‡ Typical figures are at 25°C, VDD1 = 3.3 V and for design aid only: not guaranteed and not subject to production testing.

† Characteristics are over recommended operating conditions unless otherwise stated.

‡ Typical figures are at 25°C, VDD1 = 3.3 V and for design aid only: not guaranteed and not subject to production testing.

* Note1: High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.

AC Electrical Characteristics† - Timing Parameter Measurement Voltage Levels

- Voltages are with respect to ground (Vss) unless otherwise stated.

Characteristics Sym Level Units Conditions

1 CMOS Threshold VTT 0.5VDD1 V

2 CMOS Rise/Fall Threshold Voltage High VHM 0.7VDD1 V

3 CMOS Rise/Fall Threshold Voltage Low VLM 0.3VDD1 V

AC Electrical Characteristics† - Frame Pulse and C4i

Characteristic Sym. Min. Typ.‡Max. Units Notes

1 Frame pulse width (ST-BUS, GCI) tFPW 20 2*

tCP-20 ns

2 Frame Pulse Setup time be fore

C4i falling (ST-BUS or GCI) tFPS 10 122 150 ns

3Frame Pulse Hold Time from C4i

falling (ST-BUS or GCI) tFPH 10 122 150 ns

4C4i Period tCP 190 244 300 ns

5C4i Pulse Width High tCH 85 150 ns

6C4i Pulse Width Low tCL 85 150 ns

7C4i Rise/Fall Time tr, tf10 ns

AC Electrical Characteristics† - Serial Streams for ST-BUS and GCI Backplanes

Characteristic Sym. Min. Typ.‡Max. Units Test Conditions

1 Rin/Sin Set-up Ti me tSIS 10 ns

2 Rin/Sin Hold Time tSIH 10 ns

3 Rout/Sout Dela y

- Active to Acti ve tSOD 60 ns CL=150 pF

4 Output Data Enable (ODE)

Delay tODE 30 ns CL=150 pF, RL=1 K

See Note 1

ZL50233 Data Sheet

Zarlink Semiconductor Inc.

† Characteristics are over recommended operating conditions unless otherwise stated.

‡ Typical figures are at 25°C, VDD1 = 3.3 V and for design aid only: not guaranteed and not subject to production testing.

† Characteristics are over recommended operating conditions unless otherwise stated.

‡ Typical figures are at 25°C, VDD1 = 3. 3V and for design aid only: not guaranteed and not subject to production testing.

AC Electrical Characteristics† - Master Clock - Voltages are with respect to ground (VSS). unless otherwise stated.

Characteristic Sym. Min. Typ.‡Max. Units Notes

1 Master Clock Frequency,

- Fsel = 0

- Fsel = 1 fMCF0

fMCF1 19.0

9.5 20.0

10.0 21.0

10.5 MHz

MHz

2 Master Clock Low tMCL 20 ns

3 Master Clock High tMCH 20 ns

AC Electrical Characteristics† - Motorola Non-Multiplexed Bus Mode

Characteristics Sym Min Typ‡Max Units Test Conditions

1CS setup from DS falling tCSS 0ns

2R/W

setup from DS falling tRWS 0ns

3 Address setup from DS falling tADS 0ns

4CS

hold after DS rising tCSH 0ns

5R/W

hold after DS rising tRWH 0ns

6 Address hold after DS rising tADH 0ns

7 Data delay on read tDDR 79 ns

8 Data hold on read tDHR 315ns

9 Data setup on write tDSW 0ns

10 Data hold on write tDHW 0ns

11 Acknowledgment delay tAKD 80 ns

12 Acknowledgment hold time tAKH 08ns

13 IRQ delay tIRD 20 65 ns

ZL50233 Data Sheet

Zarlink Semiconductor Inc.

Figure 13 - ST-BUS Timing at 2.048 Mbps

Figure 14 - GCI Interface Timing at 2.048 Mbps

Figure 15 - Output Driver Enable (ODE)

F0i

C4i

tFPW

Rout/Sout

Rin/Sin

tFPH

tSOD

tSIH

tCH tCL

tFPS tCP

tSIS

VTT

Bit 7, Channel 0 Bit 6, Channel 0 Bit 5, Channel 0

VHM

VLM

VTT

F0i

C4i

tFPW

Sout/Rout

Sin/Rin

tFPH

tSOD

tSIH

tCH tCL

tFPS tCP

tSIS

VTT

Bit 0, Channel 0 Bit 1, Channel 0 Bit 2, Channel 0

VHM

VLM

VTT

HiZ

Sout/Rout

ODE tODE

tODE

Valid Data

VTT

ZL50233 Data Sheet

Zarlink Semiconductor Inc.

Figure 16 - Master Clock

Figure 17 - Motorola Non-Multiplexed Bus Timing

tMCH

tMCL

VTT

MCLK

A0-A10

D0-D7

READ

WRITE

tCSS tCSH

tADH

tDHR

tRWS

R/W

tADS

tRWH

tDHW

tAKD

tDSW

tDDR

tAKH

DTA

VTT

VALID ADDRESS

VALI D RE A D DATA

VALID WRITE DATA

tIRD

IRQ VTT

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of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other

information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the

capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute

any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and

suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does

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