Industrial Environment Switching Regulators 19" PSL-Family
Edition 2/96 - © Melcher AG 5 - 45
MELCHER
The Power Partners.
5.2
Option -9 Extended Temperature Range
The operational ambient temperature range is extended to
T
A = –40...71°C.
Option P Potentiometer
Option P and the R-function cannot be supported simulta-
neously. The output voltage
U
o can be adjusted with a
screwdriver in the range from 0.92...1.08 of the nominal out-
put voltage
U
o nom.
Ho wever, the minimum differential v oltage ∆
U
io min betw een
input and output voltages as specified in "Electrical Input
and Output Data" should be maintained.
Option U Ambient Temp. Range acc. UL Recognition
Underwriters Laboratories (UL) have approved the PSL
family as recognized components up to an ambient tem-
perature of
T
A max – 10 K given by the upper temperature
limit of the standard PCB material. If the full maximum am-
bient temperature
T
A max is required with UL approval, op-
tion U should be requested. It consists of an alternative
PCB material with a higher maximum temperature specifi-
cation.
The European approval boards have in contrast to UL ac-
cepted the standard PCB material to be operated up to
T
A max = 71°C without any further precautions.
Option L Input filter
Option L is recommended to reduce superimposed inter-
ference voltages, and to prevent oscillations, if input lines
exceed approx. 5 m in total length. The fundamental w ave
(approx. 120 kHz) of the reduced interference voltage be-
tween Vi+ and Gi– has, with an input line inductance of
5µH a maximum magnitude of 4 mVrms.
The input impedance of the switching regulator at 120 kHz
is about 50 mΩ. The harmonics are small in comparison
with the fundamental wave. See also data: RFI.
With option L, the maximum permissible additionally super-
imposed ripple
u
i of the input voltage (rectifier mode) at a
specified input frequency
f
i has the following values:
Input voltage up to 40 V:
u
i max = 12 Vpp at 100 Hz or Vpp = 1200 Hz/
f
i • 1V
Input voltage up to 80 V:
u
i max = 22 Vpp at 100 Hz or Vpp = 2200 Hz/
f
i • 1V
Option C Thyristor Crowbar
This option is recommended to protect the load against
power supply malfunction, but it is not designed to sink ex-
ternal currents.
A fixed-value monitoring circuit checks the output voltage
U
o. When the trigger voltage
U
oc is reached, the thyristor
crowbar tr iggers and disables the output. It may be deacti-
v ated b y removal of the input v oltage . In case of a s witching
transistor defect, an internal fuse prevents excessive cur-
rent.
Note: As a centr al overv oltage protection device, the crow-
bar is usually connected to the e xternal load via distributed
inductance of the lines. For this reason, the overvoltage at
the load can tempor arily e xceed the trigger voltage
U
oc
. De-
pending on the application, further decentralized over-
voltage protection elements may have to be used addition-
ally.
Table 10: Crowbar trigger levels
Characteristics Conditions 5.1 V 12 V 15 V 24 V 36 V Unit
min max min max min max min max min max
U
o c Trigger voltage
U
i min...
U
i max 5.8 6.8 13.5 16 16.5 19 27 31 40 45.5 V
I
o = 0...
I
o nom
t
sDelay time
T
C min...
T
C max 1.5 1.5 1.5 1.5 1.5 µs
Option D (“Save Data”, input undervoltage monitor)
Note: Output instead of input undervoltage monitor is
available on request (option D1).
If the input voltage
U
i is belo w the adjustable threshold v olt-
age
U
t, the control circuit for ter minal D has low impedance.
Terminal D and Go– are connected to a self-conducting
field effect tr ansistor (FET). A 0.5 W Zener diode provides
protection against overvoltages.
The voltage
U
t can be e xternally adjusted with a trim poten-
tiometer by means of a screwdriver. The hysteresis
U
H of
U
t is <2%. Terminal D stays low for a minimum time
t
low min, in order to prevent any oscillation.
U
t can be set to a
value between
U
i min and
U
i max according to fig. 10. It is im-
portant to note that the FET can become conductive again
when
U
D >
U
i – 3V.
Fig. 11
Test circuit with definition of voltage U
D
and current I
D
on
Terminal D.
Fig. 12
Definition of U
t
and U
H
U
D
U
D high
U
D low
U
t
U
i
U
H
Vi +
Gi – Go –
8.2 V
D
U
D
+5 V
100 pF
I
D
10 kΩ
FET
U
t