853011BM www.icst.com/products/hiperclocks.html REV. C NOVEMBER 2, 2005
1
Integrated
Circuit
Systems, Inc.
ICS853011
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS853011 is a low skew, high perfor-
mance 1-to-2 Differential-to-2.5V/3.3V LVPECL/
ECL Fanout Buffer and a member of the
HiPerClockS™ family of High Performance
Clock Solutions from ICS. The ICS853011
is characterized to operate from either a 2.5V or a 3.3V
power supply. Guaranteed output and part-to-part skew
characteristics make the ICS853011 ideal for those
clock distribution applications demanding well defined
performance and repeatability.
FEATURES
•2 differential 2.5V/3.3V LVPECL / ECL outputs
•1 differential PCLK, nPCLK input pair
•PCLK, nPCLK pair can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
•Maximum output frequency: >3GHz
•Translates any single ended input signal to 3.3V
LVPECL levels with resistor bias on nPCLK input
•Output skew: 5ps (typical)
•Part-to-part skew: 130ps (maximum)
•Propagation delay: 390ps (maximum)
•Additive phase jitter, RMS: 0.06ps (typical)
•LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
•ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.8V to -2.375V
•-40°C to 85°C ambient operating temperature
•Available in both Standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM PIN ASSIGNMENT
ICS853011
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
Q0
nQ0
Q1
nQ1
1
2
3
4
HiPerClockS™
ICS
Vcc
PCLK
nPCLK
VEE
8
7
6
5
Q0
nQ0
Q1
nQ1
PCLK
nPCLK
ICS853011
8-Lead TSSOP, 118 mil
3mm x 3mm x 0.95mm package body
G Package
Top View
DATA SHEET
ICS853011
IDT™ / ICS™ LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER ICS853011
1
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V
LVPECL/ECL FANOUT BUFFER
853011BM www.icst.com/products/hiperclocks.html REV. C NOVEMBER 2, 2005
2
Integrated
Circuit
Systems, Inc.
ICS853011
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
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2,10Qn,0QtuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
4,31Qn,1QtuptuO.sleveleca
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5V
EE
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6KLCPntupnI /pulluP
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CC
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7KLCPtupnInwodlluP .slevelecafretniLCEPVL.gnitaolftfelneh
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8V
CC
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upnilanretniotrefer
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R
NWODLLUP
rotsiseRnwodlluPtupnI 57kΩ
R
2/CCV
srotsiseRnwodlluP/pulluP 05kΩ
ICS853011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER TSD
IDT™ / ICS™ LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER ICS853011
2
853011BM www.icst.com/products/hiperclocks.html REV. C NOVEMBER 2, 2005
3
Integrated
Circuit
Systems, Inc.
ICS853011
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 3.8V; VEE = 0V
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
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CC
egatloVylppuSevitisoP 573.23.38.3V
I
EE
tnerruCylppuSrewoP 52Am
ABSOLUTE MAXIMUM RATINGS
TABLE 3B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
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571.2572.283.2522.2592.273.222.2592.2563.2V
V
LO
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504.1545.186.1524.125.1516.144.1535.136.1V
V
PP
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051008002105100800210510080021V
V
RMC
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2.13.32.13.32.13.3V
I
HI
tupnI
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051051051Aµ
I
LI
tupnI
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KLCP
01-01-
01-
Aµ
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051-051-
051-
Aµ
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OCC
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.
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CC
.V3.0+
Supply Voltage, VCC 4.6V (LVPECL mode, VEE = 0)
Negative Supply Voltage, VEE -4.6V (ECL mode, VCC = 0)
Inputs, VI (LVPECL mode) -0.5V to VCC + 0.5V
Inputs, VI (ECL mode) 0.5V to VEE - 0.5V
Outputs, IO
Continuous Current 50mA
Surge Current 100mA
Operating Temperature Range, TA -40°C to +85°C
Storage Temperature, TSTG -65°C to 150°C
Package Thermal Impedance, θJA 112.7°C/W (0 lfpm)
(Junction-to-Ambient) for 8 Lead SOIC
Package Thermal Impedance, θJA 101.7°C/W (0 m/s)
(Junction-to-Ambient) for 8 Lead TSSOP
ICS853011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER TSD
IDT™ / ICS™ LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER ICS853011
3
853011BM www.icst.com/products/hiperclocks.html REV. C NOVEMBER 2, 2005
4
Integrated
Circuit
Systems, Inc.
ICS853011
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 4. AC CHARACTERISTICS, VCC = 0V; VEE = -3.8V TO -2.375V OR VCC = 2.375 TO 3.8V; VEE = 0V
TABLE 3D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -3.8V TO -2.375V
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V
RMC
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V
EE
V2.1+0V
EE
V2.1+0V
EE
V2.1+0V
I
HI
tupnI
tnerruChgiH KLCPn,KLCP
051051051Aµ
I
LI
tupnIKLCP
01-01-01-Aµ
tnerruCwoLKLCPn
051-051-051-Aµ
Vhtiw1:1yravsretemaraptuptuodnatupnI
CC
V.
EE
.V5.0-otV529.0+yravnac
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.
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573.1574.185.1524.1594.175.124.1594.1565.1V
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506.0547.088.0526.027.0518.046.0537.038.0V
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051008002105100800210510080021V
V
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tupnI
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KLCP
01-01-01-Aµ
KLCPn
051-051-051-Aµ
.scitsiretcarahCCDLCEPVLV3.3,B3elbaTevobaeessetonroF
ICS853011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER TSD
IDT™ / ICS™ LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER ICS853011
4
853011BM www.icst.com/products/hiperclocks.html REV. C NOVEMBER 2, 2005
5
Integrated
Circuit
Systems, Inc.
ICS853011
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
ADDITIVE PHASE JITTER
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise . This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
OFFSET FROM CARRIER FREQUENCY (HZ)
SSB PHASE NOISE dBc/HZ
1k 10k 100k 1M 10M 100M
Additive Phase Jitter
155.52MHz@12kHz to 20MHz
= 0.06ps (typical)
ICS853011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER TSD
IDT™ / ICS™ LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER ICS853011
5
853011BM www.icst.com/products/hiperclocks.html REV. C NOVEMBER 2, 2005
6
Integrated
Circuit
Systems, Inc.
ICS853011
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL
OUTPUT SKEW
PART-TO-PART SKEW
OUTPUT RISE/FALL TIME PROPAGATION DELAY
V
CMR
Cross Points
V
PP
VEE
nPCLK
VCC
PCLK
SCOPE
Qx
nQx
LVPECL
2V
-1.8V to -0.375V
tsk(pp)
t
sk(o)
nQx
Qx
nQy
Qy
PAR T 1
PAR T 2
nQx
Qx
nQy
Qy
Clock
Outputs 20%
80% 80%
20%
t
R
t
F
V
SWING
t
PD
nPCLK
Q0, Q1
nQ0, nQ1
PCLK
VCC,
VCCO
V EE
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
t
PW
t
PERIOD
t
PW
t
PERIOD
odc = x 100%
Q0, Q1
nQ0, nQ1
ICS853011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER TSD
IDT™ / ICS™ LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER ICS853011
6
853011BM www.icst.com/products/hiperclocks.html REV. C NOVEMBER 2, 2005
7
Integrated
Circuit
Systems, Inc.
ICS853011
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
APPLICATION INFORMATION
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
VCC
R2
1K
V_REF
C1
0.1u
R1
1K
Single Ended Clock Input
PCLK
nPCLK
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
OUTPUTS:
LVPECL OUTPUT
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
RECOMMENDATIONS FOR UNUSED OUTPUT PINS
ICS853011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER TSD
IDT™ / ICS™ LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER ICS853011
7
853011BM www.icst.com/products/hiperclocks.html REV. C NOVEMBER 2, 2005
8
Integrated
Circuit
Systems, Inc.
ICS853011
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both VSWING and VOH must meet the VPP
and VCMR input requirements. Figures 2A to 2E show inter-
face examples for the HiPerClockS PCLK/nPCLK input driven
by the most common driver types. The input interfaces sug-
gested here are examples only. If the driver is from another
vendor, use their termination recommendation. Please con-
sult with the vendor of the driver component to confirm the
driver termination requirements.
FIGURE 2A. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A CML DRIVER
FIGURE 2B. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY AN SSTL DRIVER
FIGURE 2C. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
PCLK/nPCLK
2.5V
Zo = 60 Ohm
SSTL
HiPerClockS
PCLK
nPCLK
R2
120
3.3V
R3
120
Zo = 60 Ohm
R1
120
R4
120
2.5V
FIGURE 2E. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
HiPerClockS
PCLK
nPCLK
PCLK/nPCLK
3.3V
R2
50
R1
50
3.3V
Zo = 50 Ohm
CML
3.3V
Zo = 50 Ohm
3.3V
HiPerClockS
PCLK
nPCLK
R2
84
R3
125
Input
Zo = 50 Ohm
R4
125
R1
84
LVPECL
3.3V
3.3V
Zo = 50 Ohm
C2
R2
1K
R5
100
Zo = 50 Ohm
3.3V
3.3V
C1
R3
1K
LVDS
R4
1K
HiPerClockS
PCLK
nPCLK
R1
1K
Zo = 50 Ohm
3.3V
PCLK/nPCLK
3.3V
R5
100 - 200
3.3V
3.3V
HiPerClockS
PCLK
nPCLK
R1
125
PCLK/nPCLK
R2
125
R3
84
C1
C2
Zo = 50 Ohm
R4
84
Zo = 50 Ohm
R6
100 - 200
3.3V LVPECL
ICS853011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER TSD
IDT™ / ICS™ LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER ICS853011
8
853011BM www.icst.com/products/hiperclocks.html REV. C NOVEMBER 2, 2005
9
Integrated
Circuit
Systems, Inc.
ICS853011
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
V
CC
- 2V
50Ω50Ω
RTT
Z
o
= 50Ω
Z
o
= 50Ω
FOUT FIN
RTT = Z
o
1
((V
OH
+ V
OL
) / (V
CC
– 2)) – 2
3.3V
125Ω125Ω
84Ω84Ω
Zo = 50Ω
Zo = 50Ω
FOUT FIN
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
designed to drive 50Ω transmission lines. Matched imped-
ance techniques should be used to maximize operating
frequency and minimize signal distortion. Figures 3A and
3B show two different layouts which are recommended only
as guidelines. Other suitable clock layouts may exist and it
would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock
component process variations.
TERMINATION FOR 3.3V LVPECL OUTPUTS
FIGURE 3B. LVPECL OUTPUT T ERMINATIONFIGURE 3A. LVPECL OUTPUT T ERMINATION
ICS853011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER TSD
IDT™ / ICS™ LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER ICS853011
9
853011BM www.icst.com/products/hiperclocks.html REV. C NOVEMBER 2, 2005
10
Integrated
Circuit
Systems, Inc.
ICS853011
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 4A and Figure 4B show examples of termination for
2.5V LVPECL driver. These terminations are equivalent to ter-
minating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very
close to ground level. The R3 in Figure 4B can be eliminated
and the termination is shown in Figure 4C.
FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE
R2
50
Zo = 50 Ohm
VCCO=2.5V
R1
50
Zo = 50 Ohm
+
-
2.5V
2,5V LVPECL
Driver
FIGURE 4B. 2.5V LVPECL DRIVER T ERMINATION EXAMPLE
VCCO=2.5V
R1
50
R2
50
Zo = 50 Ohm
R3
18
2,5V LVPECL
Driver
Zo = 50 Ohm
+
-
2.5V
FIGURE 4A. 2.5V LVPECL DRIVER T ERMINATION EXAMPLE
R2
62.5
2.5V
2,5V LVPECL
Driv er
R3
250
Zo = 50 Ohm
Zo = 50 Ohm
R4
62.5
2.5V
+
-
R1
250
VCCO=2.5V
ICS853011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER TSD
IDT™ / ICS™ LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER ICS853011
10
853011BM www.icst.com/products/hiperclocks.html REV. C NOVEMBER 2, 2005
11
Integrated
Circuit
Systems, Inc.
ICS853011
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853011.
Equations and example calculations are also provided.
1. P ower Dissipation.
The total power dissipation for the ICS853011 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 25mA = 95mW
•Power (outputs)MAX = 30.94mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30.94mW = 61.88mW
Total Power_MAX (3.8V, with all outputs switching) = 95mW + 61.88mW = 156.88mW
2. Junction T emperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA
must be used.
Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W
per Table 5A below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.157W * 103.3°C/W = 101.2°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
θθ
θθ
θJA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 5A. THERMAL RESISTANCE θθ
θθ
θJA FOR 8-PIN SOIC, FORCED CONVECTION
TABLE 5B. THERMAL RESISTANCE θθ
θθ
θJA FOR 8-PIN TSSOP, FORCED CONVECTION
θθ
θθ
θJA by Velocity (Meters per Second)
012
Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W 90.5°C/W 89.8°C/W
ICS853011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER TSD
IDT™ / ICS™ LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER ICS853011
11
853011BM www.icst.com/products/hiperclocks.html REV. C NOVEMBER 2, 2005
12
Integrated
Circuit
Systems, Inc.
ICS853011
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 5.
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V
CC
- 2V.
• For logic high, VOUT = VOH_MAX = VCC_MAX –0.935V
(VCC_MAX - VOH_MAX
) = 0.935V
• For logic low, VOUT = VOL_MAX = VCC_MAX
– 1.67V
(VCC_MAX - VOL_MAX
) = 1.67V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX
– (VCC_MAX
- 2V))/R
L
] * (VCC_MAX
- VOH_MAX) = [(2V - (VCC_MAX - VOH_MAX
))/R
L
] * (VCC_MAX
- VOH_MAX) =
[(2V - 0.935V)/50Ω] * 0.935V = 19.92mW
Pd_L = [(VOL_MAX
– (VCC_MAX
- 2V))/R
L
] * (VCC_MAX
- VOL_MAX) = [(2V - (VCC_MAX - VOL_MAX
))/R
L
] * (VCC_MAX
- VOL_MAX) =
[(2V - 1.67V)/50Ω] * 1.67V = 11.02mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION
VOUT
Q1
VCC - 2V
RL
50
VCC
ICS853011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER TSD
IDT™ / ICS™ LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER ICS853011
12
853011BM www.icst.com/products/hiperclocks.html REV. C NOVEMBER 2, 2005
13
Integrated
Circuit
Systems, Inc.
ICS853011
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS853011 is: 96
Pin compatible with MC100LVEP11 and SY100EP11U
TABLE 6A. θJAVS. AIR FLOW T ABLE FOR 8 LEAD SOIC
θθ
θθ
θJA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 6B. θJAVS. AIR FLOW T ABLE FOR 8 LEAD TSSOP
θθ
θθ
θJA by Velocity (Meters per Second)
012
Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W 90.5°C/W 89.8°C/W
ICS853011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER TSD
IDT™ / ICS™ LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER ICS853011
13
853011BM www.icst.com/products/hiperclocks.html REV. C NOVEMBER 2, 2005
14
Integrated
Circuit
Systems, Inc.
ICS853011
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC
TABLE 7A. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MS-012
LOBMYS sretemilliM
NUMINIMMUMIXAM
N8
A53.157.1
1A01.052.0
B33.015.0
C91.052.0
D08.400.5
E08.300.4
eCISAB72.1
H08.502.6
h52.005.0
L04.07
2.1
α°0°8
PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP
TABLE 7B. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MO-187
LOBMYS sretemilliM
muminiMmumixaM
N8
A--01.1
1A0 51.0
2A97.079.0
b22.083.0
c80.032.0
DCISAB00.3
ECISAB09.4
1ECISAB00.3
eCISAB56.0
1
eCISAB59.1
L04.008.0
α°0°8
aaa--01.0
ICS853011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER TSD
IDT™ / ICS™ LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER ICS853011
14
853011BM www.icst.com/products/hiperclocks.html REV. C NOVEMBER 2, 2005
15
Integrated
Circuit
Systems, Inc.
ICS853011
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 8. ORDERING INFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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ICS853011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER TSD
IDT™ / ICS™ LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER ICS853011
15
853011BM www.icst.com/products/hiperclocks.html REV. C NOVEMBER 2, 2005
16
Integrated
Circuit
Systems, Inc.
ICS853011
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
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ICS853011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER TSD
IDT™ / ICS™ LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER ICS853011
16
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
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