SN54LV165, SN74LV165
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SCES007B – MARCH 1995 – REVISED APRIL 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
EPIC (Enhanced-Performance Implanted
CMOS) 2-µ Process
D
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC, TA = 25°C
D
Typical VOHV (Output VOH Undershoot)
< 2 V at VCC, TA = 25°C
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF , R = 0)
D
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
D
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW),
Ceramic Flat (W) Packages, Chip Carriers
(FK), and (J) 300-mil DIPs
description
The ’LV165 parallel-load, 8-bit shift registers are
designed for 2.7-V to 5.5-V VCC operation.
When the device is clocked, data is shifted toward
the serial output QH. Parallel-in access to each
stage is provided by eight individual direct data
inputs that are enabled by a low level at the SH/LD
input. The ’LV165 feature a clock inhibit function
and a complemented serial output QH.
Clocking is accomplished by a low-to-high
transition of the clock (CLK) input while SH/LD is
held high and clock inhibit (CLK INH) is held low. The functions of the CLK and CLK INH inputs are
interchangeable. Since a low CLK input and a low-to-high transition of CLK INH accomplishes clocking, CLK
INH should be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD is held
high. The parallel inputs to the register are enabled while SH/LD is held low independently of the levels of CLK,
CLK INH, or SER.
The SN54LV165 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74LV165 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OPERATION
SH/LD CLK CLK INH
OPERATION
L X X Parallel load
HHX Q
0
HXH Q
0
H L ↑Shift
H↑L Shift
Copyright 1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
EPIC is a trademark of Texas Instruments Incorporated.
SN54LV165 ...J OR W PACKAGE
SN74LV165 . . . D, DB, OR PW PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
D
C
NC
B
A
E
F
NC
G
H
SN54LV165 . . . FK PACKAGE
(TOP VIEW)
CLK
SH/LD
NC
SER CLK INH
H
GND
NC VCC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SH/LD
CLK
E
F
G
H
QH
GND
VCC
CLK INH
D
C
B
A
SER
QH
Q
H
Q
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54LV165, SN74LV165
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SCES007B – MARCH 1995 – REVISED APRIL 1996
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
S
1D
R
C1 S
1D
R
C1 S
1D
R
C1 S
1D
R
C1 S
1D
R
C1 S
1D
R
C1 S
1D
R
C1 S
1D
R
C1
1
15
2
10
SH/LD
CLK INH
CLK
SER
9
7QH
QH
11 12 13 14 3 4 5 6
ABCDEFGH
Pin numbers shown are for D, DB, J, PW, and W packages.
typical shift, load, and inhibit sequences
Serial ShiftInhibit
Load
E
QH
H
G
C
F
Data
Inputs D
SH/LD
SER
CLK INH
CLK
B
A
QH
L
L
H
L
H
L
H
H
H
H
L
H
L
H
L
H
L
H
L
L
H
L
H
L
H
SN54LV165, SN74LV165
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SCES007B – MARCH 1995 – REVISED APRIL 1996
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC)
"
20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC)
"
50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC)
"
25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND
"
50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at TA = 55°C (in still air) (see Note 3):D package 1.30 W. . . . . . . . . . . . . . . . . . . .
DB package 0.55 W. . . . . . . . . . . . . . . . . . .
PW package 0.5 W. . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 7 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
recommended operating conditions (see Note 4)
SN54LV165 SN74LV165
UNIT
MIN MAX MIN MAX
UNIT
VCC Supply voltage 2.7 5.5 2.7 5.5 V
VIH
High level in
p
ut voltage
VCC = 2.7 V to 3.6 V 2 2
V
V
IH
High
-
le
v
el
inp
u
t
v
oltage
VCC = 4.5 V to 5.5 V 3.15 3.15
V
VIL
Low level in
p
ut voltage
VCC = 2.7 V to 3.6 V 0.8 0.8
V
V
IL
Lo
w-
le
v
el
inp
u
t
v
oltage
VCC = 4.5 V to 5.5 V 1.65 1.65
V
VIInput voltage 0 VCC 0 VCC V
VOOutput voltage 0 VCC 0 VCC V
IOH
High level out
p
ut current
VCC = 2.7 V to 3.6 V –6 –6
mA
I
OH
High
-
le
v
el
o
u
tp
u
t
c
u
rrent
VCC = 4.5 V to 5.5 V –12 –12
mA
IOL
Low level out
p
ut current
VCC = 2.7 V to 3.6 V 6 6
mA
I
OL
Lo
w-
le
v
el
o
u
tp
u
t
c
u
rrent
VCC = 4.5 V to 5.5 V 12 12
mA
∆t/∆vInput transition rise or fall rate 0 100 0 100 ns/V
TAOperating free-air temperature –55 125 –40 85 °C
NOTE 4: Unused inputs must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LV165, SN74LV165
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SCES007B – MARCH 1995 – REVISED APRIL 1996
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
V†
SN54LV165 SN74LV165
UNIT
PARAMETER
TEST
CONDITIONS
V
CC
†
MIN TYP MAX MIN TYP MAX
UNIT
IOH = –100 µAMIN to MAX VCC–0.2 VCC–0.2
VOH IOH = –6 mA 3 V 2.4 2.4 V
IOH = –12 mA 4.5 V 3.6 3.6
IOL = 100 µAMIN to MAX 0.2 0.2
VOL IOL = 6 mA 3 V 0.4 0.4 V
IOL = 12 mA 4.5 V 0.55 0.55
II
VI=V
CC or GND
3.6 V ±1±1
µA
I
I
V
I =
V
CC
or
GND
5.5 V ±1±1µ
A
ICC
VI=V
CC or GND
3.6 V 20 20
µA
I
CC
V
I =
V
CC
or
GND
,
O =
5.5 V 20 20 µ
A
n
ICC One input at VCC – 0.6 V,
Other inputs at VCC or GND 3 V to 3.6 V 500 500 µA
Ci
VI=V
CC or GND
3.3 V 2.5 2.5 p
F
Ci
VI
=
VCC
or
GND
5 V 3 3
F
†For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
SN54LV165
VCC = 5.5 V
± 0.5 V VCC = 3.3 V
± 0.3 V VCC = 2.7 V UNIT
MIN MAX MIN MAX MIN MAX
fclock Clock frequency 0 50 0 40 0 30 MHz
t
Pulse duration
CLK high or low 14 18 22
ns
t
w
P
u
lse
d
u
ration
SH/LD low 14 18 22
ns
SH/LD high before CLK↑10 13 17
t
Setup time
SER before CLK↑811 14
ns
t
su
S
e
t
up
ti
me CLK INH before CLK↑10 12 15
ns
Data before SH/LD↑8 12 17
th
Hold time
SER data after CLK↑665
ns
t
h
Hold
time
Parallel data after SH/LD↑665
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LV165, SN74LV165
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SCES007B – MARCH 1995 – REVISED APRIL 1996
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
SN74LV165
VCC = 5.5 V
± 0.5 V VCC = 3.3 V
± 0.3 V VCC = 2.7 V UNIT
MIN MAX MIN MAX MIN MAX
fclock Clock frequency 0 50 0 40 0 30 MHz
t
Pulse duration
CLK high or low 14 18 22
ns
t
w
P
u
lse
d
u
ration
SH/LD low 14 18 22
ns
SH/LD high before CLK↑10 13 17
t
Setup time
SER before CLK↑811 14
ns
t
su
S
e
t
up
ti
me CLK INH before CLK↑10 12 15
ns
Data before SH/LD↑8 12 17
th
Hold time
SER data after CLK↑665
ns
t
h
Hold
time
Parallel data after SH/LD↑665
ns
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
FROM
TO
SN54LV165
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
VCC = 5.5 V ± 0.5 V VCC = 3.3 V ± 0.3 V VCC = 2.7 V UNIT
(INPUT)
(OUTPUT)
MIN TYP MAX MIN TYP MAX MIN MAX
fmax 50 90 40 75 30 MHz
CLK 20 24 20 38 47
tpd SH/LD QH or QH19 24 19 36 44 ns
H 15 20 15 29 36
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
FROM
TO
SN74LV165
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
VCC = 5.5 V ± 0.5 V VCC = 3.3 V ± 0.3 V VCC = 2.7 V UNIT
(INPUT)
(OUTPUT)
MIN TYP MAX MIN TYP MAX MIN MAX
fmax 50 90 40 75 30 MHz
CLK 20 24 20 38 47
tpd SH/LD QH or QH19 24 19 36 44 ns
H 15 20 15 29 36
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS VCC TYP UNIT
C
p
d
Power dissi
p
ation ca
p
acitance
CL=50
p
F
f=10MHz
3.3 V 33 p
F
Cpd
Power
dissi ation
ca acitance
CL
=
50
F
,
f
=
10
MHz
5 V 57
F
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LV165, SN74LV165
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SCES007B – MARCH 1995 – REVISED APRIL 1996
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Vm
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1 VzOpen
GND
1 kΩ
1 kΩ
Data Input
Timing Input Vm
Vi
0 V
VmVm
Vi
0 V
Vi
0 V
VmVm
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VmVm
Vi
0 V
Vm
Vm
Input
Vm
Output
Control
Output
W aveform 1
S1 at Vz
(see Note B)
Output
W aveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
Vm
Vm
0.5 × Vz
0 V
VmVOL + 0.3 V
VmVOH – 0.3 V
[
0 V
Vi
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
Vz
GND
TEST S1
0.5 ×VCC
VCC
2 ×VCC
1.5 V
2.7 V
6 V
WAVEFORM
CONDITION VCC = 4.5 V
to 5.5 V VCC = 2.7 V
to 3.6 V
Vm
Vi
Vz
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated